SLUS644B - FEBRUARY 2005 - MAY 2005 FEATURES D Supports PCI, PCI-X 1.0 and PCI-X 2.0 Slots D Internal Power Switches for -12 V, 12 V, 3.3 V D D D D D D D D D DESCRIPTION Aux Control for Power FETs for 5 V, 3.3 V, and VIO Overload Protection on All Supplies Current Regulation on 3.3 V, 5 V and VIO Supplies Soft Start to Minimize Inrush Current Programmable Slew Rate for 3.3 V, 5 V, 12 V, VIO and Vaux Supplies Direct Control of All Functions VIO Selection Based on Card Type 80-Lead PowerPadt HTSSOP Package Narrow Package that Fits Between PCI Slots Each TPS2343 contains main supply power control, auxiliary supply power control, power FETs for 12-V, -12-V and auxiliary 3.3-V supplies, VIO control, and digital control for two slots. The main power control circuits start with all supplies off and all outputs are held off until PGOOD is asserted, indicating that system supplies are valid. Then, when power enable is asserted, the control circuit applies constant current to the gates of the power FETs, allowing each FET to ramp load voltage linearly. Each supply can be programmed for a desired ramp rate by selecting the appropriate gate capacitor. The TPS2343 monitors load current and regulates peak current to prevent disturbances to the system power rails. If load current remains regulated for longer than 5 ms, that slot is latched off. APPLICATIONS D Hot Plug Slots in Servers Logic inputs to the TPS2343 access all functions of the TPS2343. All status information from the TPS2343 is available on logic outputs. SIMPLIFIED APPLICATION DIAGRAM PCI-X 2.0 SLOT PCI-X 2.0 SLOT VIO VIO TPS2343 CONTROL LOGIC 3.3VAUX 12V 1.5 V -12V CONTROL 3.3 V 5 V -12V 12V 3.3VAUX 5 V 3.3 V 1.5 V Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPadt is a trademark of Texas Instruments Incorporated. ! " #$%! " &$'(#! )!% )$#!" # ! "&%##!" &% !*% !%" %+" "!$%!" "!)) ,!- )$#! &#%"". )%" ! %#%""(- #($)% !%"!. (( &%!%" Copyright 2005, Texas Instruments Incorporated www.ti.com 1 SLUS644B - FEBRUARY 2005 - MAY 2005 DESCRIPTION (CONT.) Auxiliary power control circuits switch, ramp, and monitor 3.3-V auxiliary power to each slot and control data switches that connect slot power management event (PME) outputs to the main PME bus after auxiliary supply is ramped. PME is disconnected when a board is turned off or a fault occurs on the board's auxiliary power. A fault on auxiliary power also shuts off main power to that board. VIO control consists of gate drivers to select between 3.3 V and 1.5 V in response to command and current limiting circuitry to shut down a slot in the event of over current. Each TPS2343 contains power FETs for 12 V, -12 V, and auxiliary 3.3 V for two slots. These power FETs are short-circuit protected, slew rate controlled, and over-temperature protected. The TPS2343 includes novel current limiting circuitry that limits instantaneous peak current and only shuts off the slot if the current remains out of spec for an extended time. ORDERING INFORMATION TA PACKAGE(1) HTSSOP (DDP) -40C to +85C TPS2343DDP (1) Add suffix R to device type (e.g. TPS2343DDPR) to specify taped and reeled. 2 www.ti.com SLUS644B - FEBRUARY 2005 - MAY 2005 SIMPLIFIED BLOCK DIAGRAM OVERCURRENT SENSE 3VAUXI 3 To Slot B SWA 47 PMEOA 78 + 2.2 V 100 mA MISET 5VGA 22 S Q R Q 3VAUXA + 10 ms Turn-On Delay 2.9 V 2.5 ms Turn-Off Delay I-limit threshold 53 AUXFLTA 1 3VAUXGA 77 PMEA 65 3VIOGA 73 15VIOGA 70 VIOSELA 2 AUX FAULT LATCH OVER- CURRENT SENSE 44 3VGA 76 VIOSA 68 Thermal Shutdown 63 P12VGA 64 P12VINA 62 P12VOA 60 M12VOA 54 FAULTA 61 M12VINA 52 OUTUVA 49 PWROFFA 57 PCIXCAP1A 55 PCIXCAP2A 51 PCIXCAP3A + VIOISA 69 3VSA 74 + 3VISA 75 MAIN FAULT LATCH + 5VSA 66 5VISA 67 S Q R Q + PWRENA 48 PWRLEDA 45 ATTLEDA 46 ALEDENA 43 PLEDENA 42 PCIXCAPA 50 DIGVCC 40 P12VOA 5VISA 3VISA VIOIS OUTPUT UV M12VOA P12VOA 5VISA 3VISA OUTPUTS LOW PCIXCAP Decoder Slot A shown To Logic 23 ANAGND1 59 ANAGND2 10 PWRGND1 71 41 PWRGND2 DIGGND1 25 DIGGND2 56 Slot B is identical DIGGND3 In this drawing, circuits related to many functions are oversimplified. See the Application Section of the data sheet for a more detailed representations of these functions. www.ti.com 3 SLUS644B - FEBRUARY 2005 - MAY 2005 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted){} PARAMETER TPS2343 UNIT Input voltage range, P12VIN -0.5 to 15 M12VIN -15.0 to 0.5 All others -0.5 to 7 Output voltage range, P12VO, 5VG, 3VG, 15VIOG, 3VIOG -0.5 to VP12VIN + 0.5 P12VG -0.5 to 28 M12VO -15 to 0.5 Output current, FAULT, OUTUV, PWROFF 50 Output current pulse, P12VO (dc internally limited) V mA 3 M12VO 0.8 3VAUX 2 A Operating junction temperature range, TJ -40 to 100 Storage temperature range, Tstg -65 to 150 C C Lead temperature soldering 1.6 mm (1/16 inch) from case for 10 seconds 260 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability All voltages are with respect to DIGGND. ELECTROSTATIC DISCHARGE (ESD) PROTECTION TEST METHOD MIN UNIT Human body model (HBM) 2 kV Charged device model (CDM) 1 kV RECOMMENDED OPERATING CONDITIONS PARAMETER Input supply, MIN MAX -10.8 -12 -13.2 P12VINA, P12VINB 10.8 12 13.2 3.0 3.3 3.6 4.75 5.00 5.25 DIGVCC, 3VAUXI V5IN Load current, TYP M12VINA, M12VINB PWRLEDA, PWRLEDB, ATTLEDA, ATTLEDB 0 P12VOA, P12VOB 0 1100 M12VOA, M12VOB 0 -100 3VAUXA, 3VAUXB 0 375 UNIT V 24 mA THERMAL SHUTDOWN PARAMETER TYP UNIT Junction temperature shutdown 150 C Junction temperature - cooldown restart 140 C 4 www.ti.com SLUS644B - FEBRUARY 2005 - MAY 2005 DISSIPATION RATING TABLE PACKAGE TA THERMAL RESISTANCE JUNCTION TO CASE JC THERMAL RESISTANCE JUNCTION TO AMBIENT (NOTE 1) JA THERMAL RESISTANCE JUNCTION TO AMBIENT (NOTE 2) JA HTSSOP-80 (DDP) -40 _C to 85 _C 1.4 _C/W 23 _C/W 32 _C/W Note 1: Thermal resistance measured using an 8-layer PC board following the layout recommendations in TI Publication PowerPAD Thermally Enhanced Package Technical Brief SLMA002. Note 2: Thermal resistance measured using an 8-layer PC board using only top PC board copper to spread the heat. SERIAL MODE PINOUT HTSSOP-80 DDP Package (Top View) 80 PMEB 3VAUXGA 1 3VAUXA 2 79 PMEOB 3VAUXI 3 78 PMEOA 3VAUXGB 4 77 PMEA 3VAUXB 5 76 3VGA 3VGB 6 75 3VISA 3VISB 7 74 3VSA 3VSB 8 73 3VIOGA 3VIOGB 9 72 V5IN PWRGND1 10 71 PWRGND2 70 15VIOGA 15VIOGB 11 VIOISB 12 69 VIOISA VIOSB 13 68 VIOSA 5VISB 14 67 5VISA 5VSB 15 66 5VSA 5VGB 16 65 5VGA P12VINB 17 64 P12VINA P12VGB 18 63 P12VGA P12VOB 19 62 P12VOA M12VINB 20 61 M12VINA M12VOB 21 60 M12VOA 59 ANAGND2 MISET 22 58 PGOOD ANAGND1 23 57 PCIXCAP1A PCIXCAP1B 24 56 DIGGND3 DIGGND2 25 55 PCIXCAP2A PCIXCAP2B 26 54 FAULTA FAULTB 27 AUXFLTB 28 53 AUXFLTA OUTUVB 29 52 OUTUVA PCIXCAP3B 30 51 PCIXCAP3A PCIXCAPB 31 50 PCIXCAPA PWROFFB 32 49 PWROFFA PWRENB 33 48 PWRENA SWB 34 47 SWA ATTLEDB 35 46 ATTLEDA PWRLEDB 36 45 PWRLEDA VIOSELB 37 44 VIOSELA ALEDENB 38 43 ALEDENA PLEDENB 39 42 PLEDENA DIGVCC 40 41 DIGGND1 www.ti.com 5 SLUS644B - FEBRUARY 2005 - MAY 2005 ELECTRICAL CHARACTERISTICS, P12VIN = 12 V, DIGVCC = 3.3 V, M12VIN = -12 V, 3VAUXIN = 3.3 V, V5IN = 5 V, RMISET = 6.04 k, all outputs unloaded, TA = -40_C to 85_C, (unless otherwise noted) (1)(2)(3) 5-V Main Supply PARAMETER TEST CONDITIONS 5VS-5VIS overcurrent threshold (5 V) 5VIS voltage fault threshold MIN TYP MAX UNIT 43 53 63 4.25 4.5 4.75 V 5VS input bias current PWREN = high -100 5VIS input bias current PWREN = high 100 250 5VIS bleed current PWREN = low, 5VIS = 5V 8 60 5VG charge current PWREN = high, 5VG = 5 V -70 -100 -130 A 5VG discharge resistance 0.1 V < V5VG < 0.5 V 1.5 4 15 11 11.5 12 V 2 6 mA 0.075 0.100 0.150 5VG good threshold 100 mV V5IN supply current 5VIS low comparator threshold PWREN = low 400 A A mA V 3.3-V Main Supply PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3VS-3VIS overcurrent threshold (3.3 V) 48 63 76 mV 3VIS voltage fault threshold 2.5 2.7 2.9 V 3VS input bias current PWREN = high -100 3VIS input bias current PWREN = high 100 290 3VIS bleed current PWREN = low, 3VIS = 3.3 V 8 40 3VG charge current PWREN = high, 3VG = 5 V -70 -100 -130 3VG discharge resistance 0.1 V < V3VG < 0.5 V 1.5 4 15 1.2 3 mA 0.100 0.150 DIGVCC supply current 3VIS low comparator threshold 6 PWREN = low www.ti.com 0.075 100 400 A A mA A V SLUS644B - FEBRUARY 2005 - MAY 2005 ELECTRICAL CHARACTERISTICS, P12VIN = 12 V, DIGVCC = 3.3 V, M12VIN = -12 V, 3VAUXIN = 3.3 V, V5IN = 5 V, RMISET = 6.04 k, all outputs unloaded, TA = -40_C to 85_C, (unless otherwise noted) (1)(2)(3) 12-V Main Supply PARAMETER 12-V internal switch on resistance TEST CONDITIONS TYP TA = TJ = 25_C, P12VG > 18 V TA = -40 _C to 85 _C, P12VG > 18 V 12-V overcurrent threshold P12VIN supply current, outputs off MIN 0.18 UNIT 0.30 0.4 1.25 1.50 1.75 1.8 3 17.5 19.0 20.5 9.75 10.15 10.45 PWREN = low P12VG gate good threshold MAX A mA V P12VO fault threshold After P12VG and 5V3VG good P12VG gate charge current PWREN = high -5 -10 -20 A P12VG gate discharge resistance 0.1 V < VP12VG < 0.5V 1.5 4 15 28 55 Turn-on time PWREN = high to P12VO = 11.4 V, CP12VG = 22 nF PWREN = high to P12VO = 11.4 V, CP12VG = 0 nF 0.5 2.0 1.5 3.5 P12VO bleed current PWREN = low to P12VO low comparator trip, CP12VG = 22 nF PWREN = low, P12VO = 12 V P12VO low comparator threshold PWREN = low P12VO turn-on slew rate CP12VG = 0 pF, 10% to 90% measurement Turn-off time ms 8 20 0.075 0.100 s mA 0.150 2 V V/ms -12-V Main Supply PARAMETER -12-V internal switch on-resistance TEST CONDITIONS -12-V overcurrent threshold M12VIN supply current, outputs off M12VO turn-on slew rate(4) MIN TA = TJ = 25_C, steady state TA = -40 _C to 85 _C, steady state TYP 0.50 MAX 0.75 0.9 0.15 PWREN = low 0.20 0.25 A 1000 2000 A V/ms CP12VG = 22 nF, 10% to 90% measurement 0.30 0.68 1.10 Turn-on time CP12VG = 22 nF, PWREN = high to M12VO = -10.4 V, RL = 120 12 18 37 Turn-off time PWREN = low to M12VO low comparator trip 1.5 3.5 M12VO bleed current PWREN = low, M12VO = -12 V M12VO low comparator threshold PWREN = low NOTES: (1). (2) (3) (4) UNIT -8 -20 -0.075 -0.100 ms s mA -0.150 V All voltages are with respect to DIGGND unless otherwise stated. Currents are positive into and negative out of the specified terminal. When references to lines of individual slots are given without the slot identifier, the statement applies to lines on each slot. -12-V main supply turn on is controlled by the +12-V main supply turn on, so the -12-V main supply slew rate is a function of CP12VG. www.ti.com 7 SLUS644B - FEBRUARY 2005 - MAY 2005 ELECTRICAL CHARACTERISTICS, P12VIN = 12 V, DIGVCC = 3.3 V, M12VIN = -12 V, 3VAUXIN = 3.3 V, V5IN = 5 V, RMISET = 6.04 k, all outputs unloaded, TA = -40_C to 85_C, (unless otherwise noted) (1)(2)(3) VIO Supply PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 15VG, 3VIOG output voltage high 11.5 11.9 VIOS - VIOIS overcurrent threshold (1.5 V operation) 20.0 23.5 27.0 mV 10 50 100 -100 20 100 -100 20 200 8 20 0.075 0.100 0.150 1.275 1.325 1.375 0.1 1.0 10 13 15VIOG, 3VIOG turn-off resistance VIOS input bias current PWREN = low, 0.1 V < VVIOG, VVIOG < 0.5 V PWREN = high, VIOSEL = low, test circuit Figure 7 VIOIS input bias current PWREN = high, VIOSEL = low, test circuit Figure 7 VIOIS bleed current PWREN = low, VIOIS =1.5 V VIOIS low comparator threshold PWREN = low VIOIS fault threshold 15VIOG low voltage V A A PWREN = low 15VIOG, 3VIOG gate charge current 7 mA V A Power Fault Response PARAMETER Overcurrent fault detection time TEST CONDITIONS MIN TYP 12 V 2 -12 V, i = 250 mA 4 MAX UNIT 6.5 s 12 Overcurrent response time to regulate 5 V, 3.3 V, Vio 1 3 Overcurrent fault detection time 5 V, 3.3 V, Vio 3 8 ms Overcurrent fault clearing time 5 V, 3.3 V, Vio 50 150 s NOTES: (1) All voltages are with respect to DIGGND unless otherwise stated. (2) Currents are positive into and negative out of the specified terminal. (3) When references to lines of individual slots are given without the slot identifier, the statement applies to lines on each slot. 8 www.ti.com SLUS644B - FEBRUARY 2005 - MAY 2005 ELECTRICAL CHARACTERISTICS, P12VIN = 12 V, DIGVCC = 3.3 V, M12VIN = -12 V, 3VAUXIN = 3.3 V, V5IN = 5 V, RMISET = 6.04 k, all outputs unloaded, TA = -40_C to 85_C, (unless otherwise noted) (1)(2)(3) 3.3 VAUX and PME PARAMETER TEST CONDITIONS 3VAUX overcurrent threshold MIN TYP 0.8 3VAUXI to 3VAUX switch on resistance SW = low, 3VAUXG = 10 V 3VAUXI undervoltage threshold SW = low 3VAUXI supply current, 3VAUX off SW = high 3VAUXG turn-on current SW = low, 3VAUXG = 3.3 V 3VAUXG turn-off resistance SW = high, 0.1 V < 3VAUXG < 0.5 V 3VAUX turn-on time with no gate capacitor C3VAUXG = 0 pF, 10% to 90% measurement 3VAUX turn-on slew rate with gate capacitor C3VAUXG = 22 nF, 10% to 90% measurement 3VAUX bleed current SW = high, 3VAUX = 3.0 V 1.9 -3 MAX UNIT 1.1 1.45 A 300 400 m V 2.2 2.9 1000 2000 -5 -7 8 30 200 350 s 0.13 0.23 0.32 V/ms 8 28 3 mA 3VAUX turn-off time from Fault From SW > 2.0 V to 3VAUX < 0.5 V, C3VAUXG = 22 nF From 3VAUX overcurrent fault PME turn-on time from 3VAUX From 3VAUX > 3.0 V, C3VAUX = 150 F PME turn-off time from SW From SW > 2.0 V 4 PME turn-off time from Fault From 3VAUX overcurrent fault 4 PME switch on resistance SW = low 3VAUX turn-off time from SW 6 1.2 5.0 17 25 s 10 17 ms 10 3VAUX output rising threshold to PME switch closed A A 2.5 ms ss 20 3.0 V DC Logic Characteristics PARAMETER TEST CONDITIONS Input high voltage (all digital inputs) MIN TYP 0.8 Input hysteresis (PGOOD) Output low voltage (ATTLED, PWRLED) Output low voltage (all other outputs) Input pull-up resistor impedance UNIT 2.0 Input low voltage (all digital inputs) Output high voltage (all push-pull outputs) MAX 0.15 IL = 4 mA IL = 8 mA 2.4 0.60 2.8 V 0.5 IL = 24 mA IL = 4 mA For inputs with pull-up resistors (see pin descriptions) 0.4 0.8 0.2 0.5 30 200 PCIXCAP threshold between 33 MHz and 533 MHz 0.3 0.4 0.5 PCIXCAP threshold between 533 MHz and 266 MHz 1.1 1.2 1.3 PCIXCAP threshold between 266 MHz and 66 MHz 1.95 2.05 2.15 PCIXCAP threshold between 66 MHz and 133 MHz 2.8 2.9 3.0 k V NOTES: (1). All voltages are with respect to DIGGND unless otherwise stated. (2) Currents are positive into and negative out of the specified terminal. (3) When references to lines of individual slots are given without the slot identifier, the statement applies to lines on each slot. www.ti.com 9 SLUS644B - FEBRUARY 2005 - MAY 2005 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION 3VAUXGA I/O This pin is connected to the gate of the slot A 3VAUX internal power FET. Connect a capacitor from this pin to PWRGND to program the slot A 3VAUX ramp rate. The recommended capacitor value is 22 nF for 0.23 V/ms ramp rate. 2 3VAUXA O This output supplies 3VAUX power to slot A when enabled and is pulled low by an internal FET when there is a fault on slot A 3VAUX or when SWA is opened. 3 3VAUXI I Connect this power input to 3.3 V power to drive 3VAUX loads. Connect a 0.1-F capacitor from this pin to PWRGND. 4 3VAUXGB I/O This pin is connected to the gate of the slot B 3VAUX internal power FET. Connect a capacitor from this pin to PWRGND to program the slot B 3VAUX ramp rate. The recommended capacitor value is 22 nF for 0.23 V/ms ramp rate. 5 3VAUXB O This output supplies 3VAUX power to slot B when enabled and is pulled low by an internal FET when there is a fault on slot B 3VAUX or when SWB is opened. 6 3VGB I/O Gate drive for the 3-V slot B FET switch. Ramp rate is programmed by an external capacitor in series with a 15-k resistor connected from this pin to PWRGND. A capacitor value of 270 nF sets 0.37 V/ms ramp rate. 7 3VISB I This pin in conjunction with the 3VSB pin senses the current to the 3.3-V slot B. It connects to the load side of the 3.3-V current sense resistor. The recommended current sense resistor value is 6 m. When PWRENB is false or FAULTB is true, this pin is discharged to PWRGND by an internal FET. A 0.01-F capacitor from this pin to ANAGND is recommended. 8 3VSB I This pin in conjunction with the 3VISB pin senses the current to the 3.3-V slot B main power load. Connect to the source of the 3.3-V FET switch. A 0.01-F capacitor from this pin to ANAGND is recommended. 9 3VIOGB I/O 10 PWRGND1 GND 11 15VIOGB I/O NUMBER NAME 1 Ground for high-current paths including discharge current of external gate capacitors. Gate drive for the 1.5-V VIO slot B FET switches. Ramp rate is programmed by the external capacitor connected from 15VIOGB to PWRGND. The recommended capacitor value is 22 nF for a 0.45 V/ms ramp rate. 12 VIOISB I This pin in conjunction with the VIOSB pin senses the current to VIO slot B. It connects to the load side of the VIO current sense resistor. The recommended current sense resistor value is 6 m. When PWRENB is false or FAULTB is true, this pin is discharged to PWRGND by an internal FET. A 0.01-F capacitor from this pin to ANAGND is recommended. 13 VIOSB I This pin in conjunction with the VIOISB pin senses the current to VIO slot B. Connect to the current sense resistor at the Vio FET switch. A 0.01-F capacitor from this pin to ANAGND is recommended. 14 5VISB I This pin in conjunction with the 5VSB pin senses the current to the 5-V slot B main power load. It connects to the load side of the 5-V current sense resistor. The recommended current sense resistor value is 6 m. When PWRENB is false or FAULTB is true, this pin is discharged to PWRGND by an internal FET. A 0.01-F capacitor from this pin to ANAGND is recommended. 15 5VSB I This pin in conjunction with the 5VISB pin senses the current to the 5-V slot B main power load. It connects to the source of the 5-V FET switch. A 0.01-F capacitor from this pin to ANAGND is recommended. 16 5VGB I/O Gate drive for the 5-V slot B FET switch. Ramp rate is programmed by an external capacitor in series with a 15-k resistor connected from this pin to PWRGND. A capacitor value of 270 nF sets 0.37 V/ms ramp rate. 17 P12VINB I 18 10 Gate drive for the 3.3-V VIO slot B FET switches. Ramp rate is programmed by the external capacitor connected from 3VIOGB to PWRGND. The recommended capacitor value is 22 nF for a 0.45 V/ms ramp rate. P12VGB I/O The 12-V power input to slot B. This input must be connected to P12VINA. Connect a 0.1-F capacitor from this pin to PWRGND. This pin is connected to the gate of the slot B 12-V internal power FET. Connect a capacitor from this pin to PWRGND to program the slot B 12-V and -12-V power ramp rate. The recommended capacitor value is 22 nF for 0.45 V/ms ramp rate on 12 V and a 0.68 V/ms ramp rate on -12-V power. www.ti.com SLUS644B - FEBRUARY 2005 - MAY 2005 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NUMBER NAME 19 P12VOB O This output delivers 12-V power to slot B when enabled and is pulled to PWRGND by an internal FET when PWRRNB is false or FAULTB is true. 20 M12VINB I Connect this power input to -12-V power to drive slot B. This input must be connected to M12VINA. Connect a 0.1-F capacitor from this pin to PWRGND. 21 M12VOB O This output delivers -12-V power to slot B when enabled and is pulled to PWRGND by an internal FET when PWRRNB is false or FAULTB is true. Turn-on of -12-V power tracks turn-on of 12-V power and is controlled by the capacitor on P12VGB. 22 MISET I/O This pin programs current limit for 12-V, 5-V, 3.3-V, and -12-V main supplies. MISET does not control 3.3VAUX or VIO current limit. The recommended resistor from MISET to ANAGND is 6.04 k 1%. Increasing the value of this resistor raises the current-limit thresholds for the supplies listed above proportionately. MISET resistor is 12 k maximum. 23 ANAGND1 GND 24 PCIXCAP1B O 25 DIGGND2 GND 26 PCIXCAP2B O This pin indicates bit 2 of the PCIXCAPB state. 27 FAULTB O This is an open-drain output that is low if there is a fault on the main power to slot B. This pin has an internal 100-k pull-up resistor to DIGVCC. 28 AUXFLTB O This open-drain output is low if there is a fault on VAUX power to slot B. This pin has an internal 100-k pull-up resistor to DIGVCC and hysteresis. 29 OUTUVB O This open-drain output is low if slot B outputs are below normal operating range. This pin has an internal 100-k pull-up resistor to DIGVCC. 30 PCIXCAP3B O This pin indicates bit 3 of the PCIXCAPB state. 31 PCIXCAPB I This pin is the input to a 5-level A/D converter that determines the speed and mode of the inserted B slot card based on the impedance from this pin to ANAGND. The operation of this pin meets the specifications of the PCI-X Local Bus Specification, revision 2.0. 32 PWROFFB O This output is low when all of the slot B power outputs are discharged. 33 PWRENB I This pin enables main power for slot B when high. This pin has an internal 100-k pull-up resistor to DIGVCC and hysteresis. When low, FAULTB is clearded and OUTUVB is asserted. 34 SWB I This input enables 3.3-V VAUX power to slot B. When low, AUXFLTB is cleared. This pin has an internal 100-k pull-up resistor to 3VAUXI and hysteresis. 35 ATTLEDB O This output is an open-drain power output that directly drives the slot B attention indicator LED. This pin indicates the slot B LED attention indicator output signal from ALEDENB. This signal pulls low with up to 24 mA of drive when asserted and is pulled high by an on-chip 100-k resistor to V5IN when deasserted. 36 PWRLEDB O This open-drain active-low power output directly drives the slot B power indicator LED. This pin indicates the slot B power LED output from PLEDENB. This signal pulls low with up to 24 mA of drive when asserted and is pulled high by an on-chip 100-k resistor to V5IN when deasserted. 37 VIOSELB I This pin selects 3.3 V VIO for slot B when high, 1.5 V when low. 38 ALEDENB I This pin controls ATTLEDB. When this input is high, the LED is on (low). 39 PLEDENB I This pin controls PWRLEDB. When this input is high, the LED is on (low). 40 DIGVCC I This pin is the 3.3-V main power input to the TPS2343. Bypass this pin to DIGGND with a 0.1-F ceramic capacitor close to the TPS2343. 41 DIGGND1 GND Ground for low-level signals including the current sense circuits and the voltage reference. This pin indicates bit 1 of the PCIXCAPB state. This pin is the ground return for the digital circuits in the TPS2343. This pin is the ground return for the digital circuits in the TPS2343. www.ti.com 11 SLUS644B - FEBRUARY 2005 - MAY 2005 TERMINAL FUNCTIONS TERMINAL 12 I/O DESCRIPTION NUMBER NAME 42 PLEDENA I This pin controls PWRLEDA. When this input is high, the LED is on (low). 43 ALEDENA I This pin controls ATTLEDA. When this input is high, the LED is on (low). 44 VIOSELA I This pin selects 3.3 V VIO for slot A when high, 1.5 V when low. 45 PWRLEDA O This output is an open-drain active-low power output that directly drives the slot A power indicator LED. This pin indicates the slot A power LED output from PLEDENA. This signal pulls low with up to 24 mA of drive when asserted and is pulled high by an on-chip 100-k resistor to V5IN when deasserted. 46 ATTLEDA O This open-drain power output directly drives the slot A attention indicator LED. This pin indicates the slot A LED attention indicator output signal from ALEDENA. This signal pulls low with up to 24 mA of drive when asserted and is pulled high by an on-chip 100-k resistor to V5IN when deasserted. 47 SWA I This input enables 3.3-V Aux power to slot A. When low, AUXFLTA is cleared. This pin has an internal 100-k pull-up resistor to 3VAUXI and hysteresis. 48 PWRENA I This pin enables main power for slot A when high. When low, FAULTA is cleared and OUTUVA is asserted. This pin has an internal 100-k pull-up resistor to DIGVCC and hysteresis. 49 PWROFFA O This output is low when all of the slot A power outputs are discharged. 50 PCIXCAPA I This pin is the input to a 5-level A/D converter that determines the speed and mode of the inserted A slot card based on the impedance from this pin to ANAGND. The operation of this pin meets the specifications of the PCI-X Local Bus Specification, revision 2.0. 51 PCIXCAP3A O This pin indicates bit 3 of the PCIXCAPA state. 52 OUTUVA O This open-drain output is low if slot A main outputs are below normal operating range. This pin has an internal 100-k pull-up resistor to DIGVCC. 53 AUXFLTA O This is an open-drain output that is low if there is a fault on VAUX power to slot A. This pin has an internal 100-k pull-up resistor to DIGVCC. 54 FAULTA O This is an open-drain output that is low if there is a fault on the main power to slot A. This pin has an internal 100-k pull-up resistor to DIGVCC. 55 PCIXCAP2A O This pin indicates bit 2 of the PCIXCAPA state. 56 DIGGND3 GND 57 PCIXCAP1A O This pin indicates bit 1 of the PCIXCAPA state. 58 PGOOD I This input is asserted when power is good in the whole system. This pin has an internal 100-k pull-up resistor to DIGVCC and hysteresis. 59 ANAGND2 GND 60 M12VOA O This output delivers -12-V power to slot A when enabled and is pulled to PWRGND by an internal FET when PWRENA is false or FAULTA is true. Turn-on of -12-V power tracks turn-on of 12-V power and is controlled by the capacitor on P12VGA. 61 M12VINA I Connect this power input to -12-V power to drive slot A. This input must be connected to M12VINB. Connect a 0.1-F capacitor from this pin to PWRGND. 62 P12VOA O This output delivers 12-V power to slot A when enabled and is pulled to PWRGND by an internal FET when PWRENA is false or FAULTA is true. This pin is the ground return for the digital circuits in the TPS2343. Ground for low-level signals including the current sense circuits and the voltage reference. www.ti.com SLUS644B - FEBRUARY 2005 - MAY 2005 TERMINAL FUNCTIONS TERMINAL NUMBER NAME I/O DESCRIPTION This pin is connected to the gate of the slot A 12-V internal power FET. Connect a capacitor from this pin to PWRGND to program the slot A 12-V and -12-V power ramp rate. The recommended capacitor value is 22 nF for 0.45-V/ms ramp rate on 12 V and a 0.68-V/ms ramp rate on -12-V power. 63 P12VGA I/O 64 P12VINA I The 12-V power input to slot A. This input must be connected to P12VINB. Connect a 0.1-F capacitor from this pin to PWRGND. 65 5VGA I/O Gate drive for the 5-V slot A FET switch. Ramp rate is programmed by an external capacitor in series with a 15- resistor connected from this pin to PWRGND. A capacitor value of 270 nF sets 0.37-V/ms ramp rate. 66 5VSA I This pin in conjunction with the 5VISA pin senses the current to the 5-V slot A. It connects to the source of the 5-V FET switch. A 0.01-F capacitor from this pin to ANAGND is recommended. 67 5VISA I This pin in conjunction with the 5VSA pin senses the current to the 5-V slot A. It connects to the load side of the 5-V current sense resistor. The recommended current sense resistor value is 6m. When PWRENA is false or FAULTA is true, this pin is discharged to PWRGND by an internal FET. A 0.01-F capacitor from this pin to ANAGND is recommended. 68 VIOSA I This pin in conjunction with the VIOISA pin senses the current to VIO slot A. Connect to the current sense resistor at the Vio FET switch. A 0.01-F capacitor from this pin to ANAGND is recommended. 69 VIOISA I This pin in conjunction with the VIOSA pin senses the current to VIO slot A. It connects to the load side of the VIO current sense resistor. The recommended current sense resistor value is 6 m. VIO bleed is connected to this pin. A 0.01-F capacitor from this pin to ANAGND is recommended. 70 15VIOGA I/O Gate drive for the 1.5-V VIO slot A FET switches. Ramp rate is programmed by the external capacitor connected from 15VIOGA to PWRGND. The recommended capacitor value is 22 nF for a 0.45-V/ms ramp rate. 71 PWRGND2 GND 72 V5IN I Connect this power input to 5-V power. This input is used to bias analog circuits. Connect a 0.1-F capacitor from this pin to PWRGND. 73 3VIOGA I/O Gate drive for the 3.3-V VIO slot A FET switches. Ramp rate is programmed by the external capacitor connected from 3VIOGA to PWRGND. The recommended capacitor value is 22 nF for a 0.45-V/ ms ramp rate. 74 3VSA I This pin in conjunction with the 3VISA pin senses the current to the 3.3-V slot A main power load. Connect to the source of the 3.3-V FET switch. A 0.01-F capacitor from this pin to ANAGND is recommended. 75 3VISA I This pin in conjunction with the 3VSA pin senses the current to the 3.3-V slot A. It connects to the load side of the 3.3-V current sense resistor. The recommended current sense resistor value is 6 m. When PWRENA is false or FAULTA is true, this pin is discharged to PWRGND by an internal FET. A 0.01-F capacitor from this pin to ANAGND is recommended. 76 3VGA I/O Gate drive for the 3.3-V slot A FET switch. Ramp rate is programmed by an external capacitor in series with a 15-k resistor connected from this pin to PWRGND. A capacitor value of 270 nF sets 0.37-V/ms ramp rate. 77 PMEA I This input connects to the slot A power management event (PME) signal. This pin is internally pulled up to 3VAUXA with a 100-k resistor. 78 PMEOA O This output is connected to PMEA by a bus switch that is closed after slot A 3VAUX voltage is good and opens immediately when there is a fault on slot A 3VAUX or SWA opens. 79 PMEOB O This output is connected to PMEB by a bus switch that is closed after slot B 3VAUX voltage is good and opens immediately when there is a fault on slot B 3VAUX or SWB opens. 80 PMEB I This input connects to the slot B power management event (PME) signal. This pin is internally pulled up to 3VAUXB with a 100-k resistor. Ground for high-current paths including discharge current of external gate capacitors. www.ti.com 13 SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION Turn-On Sequence Main power to the slot turns on when all input supplies are active and power is commanded, by asserting PWRENx. The charge pump combined with the P12VGx capacitor produces a linear voltage ramp on P12VGx, which produces a linear ramping of the 12-V output and the -12-V output. At the same time, a current source on 5VG combined with the 5VG capacitor produces a linear voltage ramp on 5VG and a current source on 3VG combined with the 3VG capacitor produces a linear voltage ramp on 3VG, which produces a linear ramping of the 3.3-V and 5-V main outputs. During this time, if any main slot current exceeds the appropriate over-current threshold for more than the over-current sensitivity time, the slot latches off and remains off until the logic command is turned off and on again. When P12VGx exceeds the 12-V gate good threshold, 5VG exceeds the 5-V good threshold, and 3VG exceeds the 3-V gate good threshold, outputs should be fully ramped and the power MOSFETs should be fully enhanced. +12-V Supply Control The TPS2343 integrates an N-channel power MOSFET for the 12-V supply and a voltage multiplying charge pump to drive the gate of the power MOSFET to 20 V. Inrush current for the 12-V supply is controlled because the slew rate of the 12-V supply is limited. The slew rate for the 12-V supply is set by the capacitor from P12VG to AGND. Slew rate can be estimated as: dV + I GATE dt C P12VGx where CP12VGx is the capacitor from P12VGx to AGND and IGATE is the P12VGx gate charge current. PCI specifications allow for 12-V supply adapter card bulk capacitance of up to 300 F. This load capacitance causes additional inrush current of: I INRUSH + C LOAD dV + 300 mF dt I GATE C P12VGx Using the recommended value for CP12VGx = 0.022 F and the typical value for IGATE = 10 A, average inrush current can be estimated as: I INRUSH + 300 mF 10 mA + 0.136 A 0.022 mF An internal current-sense circuit monitors the 12-V supply. The over-current threshold for the 12-V supply is directly proportional to the resistor from MISET to AGND. Raising the MISET resistor simultaneously raises the current limit threshold for the 12-V, 5-V, 3.3-V and -12-V supplies. For example, to raise the nominal output current from the 12-V supply by 20%, increase the MISET resistor 20%. This resistor can be as high as 12 k if necessary. 14 www.ti.com SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION -12-V Supply Control The TPS2343 integrates an N-channel power MOSFET for the -12-V supply. This switch turns on when PWRENx is asserted and turns off when PWRENx is deasserted or when there is a fault on any main power supply to the slot. Like the 12-V supply, inrush for the -12-V supply is controlled by controlling turn-on slew rate. The -12-V supply tracks the 12-V supply, so the slew rates of these supplies are directly related. To insure that the power MOSFET for the -12-V supply fully enhances, the tracking amplifier has a gain of approximately 1.4, producing a -12-V supply slew rate 40% higher than the 12-V supply slew rate. PCI specifications allow for -12-V supply adapter card bulk capacitance of up to 150 F. This load capacitance causes additional inrush current of: I INRUSH + C LOAD dV + 150 mF dt I GATE C P12VG 1.4 Using the recommended value for CP12VG = 0.022 F and the typical value for IGATE = 10 A, average inrush current can be estimated as: I INRUSH + 150 mF 10 mA 0.022 mF 1.4 + 0.095 A An internal current-sense circuit monitors the -12-V supply. The over-current threshold for the -12-V supply is directly proportional to the resistor from MISET to AGND. Raising the MISET resistor simultaneously raises the current limit threshold for the 12-V, 5-V, 3.3-V and -12-V supplies. For example, to raise the nominal output current from the -12-V supply by 20%, increase the MISET resistor 20%. This resistor can be as high as 12 k if necessary. +5-V Main Supply Control The TPS2343 uses external N-channel power MOSFETs for the 5-V supply. Inrush current for this supply is controlled because the slew rate of the supplies is limited. This slew rate is set by the capacitor from 5VGx to AGND. Slew rate can be estimated as: dV + I GATE dt C 5VG where C5VG is the capacitor from 5VGx to AGND and IGATE is the 5VGx gate charge current. PCI specifications allow for 5-V supply adapter card bulk capacitance of up to 3000 F. This load capacitance causes additional inrush current of: I INRUSH + C LOAD dV + 3000 mF dt I GATE C 5VGx www.ti.com 15 SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION Using the recommended value for C5VGx = 0.27 F and the typical value for IGATE = 100 A, average inrush current can be estimated as: I INRUSH + 3000 mF 100 mA + 1.11 A 0.27 mF An external current-sense resistor monitors the 5-V supply. The calculation of external resistor values is shown in the determining component values section. The over-current thresholds is directly proportional to the resistor from MISET to AGND and inversely proportional to the current-sense resistor. Raising the MISET resistor simultaneously raises the current limit threshold for the 12-V, 5-V, 3.3-V and -12-V supplies. This resistor can be as high as 12 k if necessary. +3.3-V Main Supply Control The TPS2343 uses external N-channel power MOSFETs for the 3.3-V supply. Inrush current for this supply is controlled because the slew rate of the supply is limited. These slew rates are set by the capacitor from 3VGx to AGND. Slew rate can be estimated as: dV + I GATE dt C 3VGx where C3VGx is the capacitor from 3VGx to AGND and IGATE is the 3VGx gate charge current. PCI specifications allow for 3.3-V supply adapter card bulk capacitance of up to 3000 F. This load capacitance causes additional inrush current of: I INRUSH + C LOAD dV + 3000 mF dt I GATE C 3VGx Using the recommended value for C3VGx = 0.27 F and the typical value for IGATE = 100 A, average inrush current can be estimated as: I INRUSH + 3000 mF 100 mA + 1.11 A 0.27 mF An external current-sense resistor monitors the 3.3-V supply. The calculation of external resistor values is shown in the determining component values section.The over-current threshold is directly proportional to the resistor from MISET to AGND and inversely proportional to the current-sense resistor. Raising the MISET resistor simultaneously raises the current limit threshold for the 12-V, 5-V, 3.3-V and -12-V supplies. This resistor can be as high as 12 k if necessary. 16 www.ti.com SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION +1.5-V and +3.3-V VIO Supply Control VIO is frequently used to power VIO for both the slot and the bridge so that there is minimal drop between the slot and the bridge VIO supplies. When calculating the current-limit threshold for VIO, take into account the current consumption of the slot and the bridge. The TPS2343 uses external N-channel power MOSFETs for the 1.5-V and 3.3-V VIO supplies. Inrush current for these supplies is controlled because the slew rate of the supplies are limited. Refer to the VIO Power Selection in the Application Section. Both 1.5-V and 3.3-V VIO slew rates are usually set to the same value capacitor, CVIOGx to AGND and on 3VIOGx to AGND. IGATE is 10 A for both 15VIOGx and 3VIOGx. Slew rate can be estimated as: dV + I GATE dt C VIOGx PCI specifications allow for 1.5-V and 3.3-V VIO supply adapter card bulk capacitance of up to 150 F. This load capacitance causes additional inrush current of: I INRUSH + C LOAD dV + 150 mF dt I GATE C VIOGx Using the recommended value for CVIOGx = 0.022 F and the typical value for IGATE = 5 A, average inrush current can be estimated as: I INRUSH + 150 mF 10 mA + 0.068A 0.022 mF www.ti.com 17 SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION 3VAUX Supply Control The TPS2343 3VAUX supply is completely independent of the main supply. Supply status and faults on main supplies have no effect on 3VAUX and faults on 3VAUX have no effect on main supply operation. The TPS2343 uses internal power MOSFETs for the 3VAUX supply and voltage multiplying charge pumps to drive the gates of the power MOSFETs to 8 V. Inrush current for the 3VAUX supply is controlled because the slew rate of the 3VAUX supply is limited. This slew rate is set by the capacitor from 3VAUXGx to AGND. Slew rate can be estimated as: dV + I GATE dt C 3VAUXGx where C3VAUXGx is the capacitor from 3VAUXGx to AGND and IGATE is the 3VAUXG gate charge current. Inrush current caused by this slewing and any adapter card load capacitance can be estimated as: PCI specifications allow for 3.3VAUX supply adapter card bulk capacitance of up to 150 F. This load capacitance causes additional inrush current of: I INRUSH + C LOAD dV + C LOAD dt 5 mA C 3VAUXGx Using the recommended value for C3VAUXGx = 0.022 F and the typical value for IGATE = 5 A, average inrush current can be estamated as: I RUSH + 150 mF 5 mA + 0.034 A 0.022 mF The 3VAUXx current-sense threshold is internally set and can not be adjusted. When main power is applied to the TPS2343, all gates are actively held low. When main power is removed, leakage current can potentially raise gate voltage, but because main power is not applied, no malfunction occurs. This is noted here as floating gates may be observed during bench testing, but ths is not an application problem. 18 www.ti.com SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION Layout Considerations It is important to use good layout practices regarding device placement and etch routing of the backplane/system board to optimize the performance of the hot plug circuit. Some of the key considerations are listed here: D Decoupling capacitors should be located close to the device. D Any protection devices (e.g. zener clamps) should be located close to the device. D To reduce insertion loss across the hot plug interface, use wide traces for the supply and return current paths. A power plane can be used for the supply return or PWRGND nodes. D Additional copper placed at the land patterns of the sense resistors and pass FETs can significantly reduce the thermal impedance of these devices, reducing temperature rise in the module and improving overall reliability. D Because typical values for current sense resistors can be very low (6 m typical), board trace resistance between elements in the supply current paths becomes significant. To achieve maximum accuracy of the overload thresholds, good Kelvin connections to the resistors should be used for the current sense inputs to the device. The current sense traces should connect symmetrically to the sense resistor land pattern, in close proximity to the element leads, not upstream or downstream from the device. LOAD CURRENT PATH LOAD CURRENT PATH 3VSA 3VISA 3VSA 3VISA SENSE RESISTOR TPS2343 TPS2343 UDG-02154 Figure 1. Connecting the Sense Resistors These recommended layouts provide force-and-sense (Kelvin) connection to the current sense resistor to minimize circuit board trace resistance. www.ti.com 19 SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION Power and Grounding Connect all TPS2343 grounds directly to the digital ground plane on the circuit board through the shortest path possible. Also connect P12VINA, P12VINB, M12VINA and M12VINB directly to the appropriate power plane through the shortest path possible. A 0.1-F decoupling capacitor is recommended on each of these power pins, as close to the pin as possible. Thermal Model The TPS2343 is packaged in the HTSSOP-80 PowerPadt small outline package. The PowerPadt package is a thermally enhanced standard size device package designed to eliminate the use of bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using standard printed circuit board (PCB) assembly techniques, and can be removed and replaced using standard repair procedures. The leadframe die pad is exposed on the bottom of the device. This provides an extremely low thermal resistance between the die and the thermal pad. The thermal pad can be soldered directly to the PCB for heatsinking. In addition, through the use of thermal vias, the thermal pad can be directly connected to a power plane or special heat sink structure designed into the PCB. On the TPS2343, the die substrate is internally connected to the -12-V input supply. Therefore the power plane or heatsink connected to the thermal pad on the bottom of the device must also connect to the -12-V input supply (recommended) or float independent of any supply (acceptable). The thermal performance can be modeled by determining the thermal resistance between the die and the ambient environment. Thermal resistances are measures of how effectively an object dissipates heat. Typically, the larger the device, the more surface area available for power dissipation and the lower the object's thermal resistance. Figure 3 illustrates the thermal path and resistances from the die, TJ through the printed circuit board to the ambient air. Die PD (Watts) Copper Trace TPS2343 80 HTSSOP PowerPadt NN IIIIIIIIIII III II NNNNNNNN II II III NN II II II I II IIIII I II II IIII I II II I II II IIIIIIIIIIIIIIIIIIII Via Thermal Via Solder Die Junction Temperature Die Case Temperature TJ qJC TC qCP PCB Pad Temperature TP qPH PCB Heatsink Temperature TH qHA Heatsink/Copper Plane Ambient Air Temperature TA -12 VIN or Floating UDG-02156 Figure 2. PowerPADt Thermal Model 20 www.ti.com SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION Technical Brief PowerPADt Thermally Enhanced Package (SLMA002) can be used as a guide to model the TPS2343 thermal resistance. DDP PowerPad 80 Pin 4.70 6,20 6,00 5,40 17,10 16,90 NOTE: The pad is centered in both directions with the pins. The tolerance includes both the size and the centering. When mounted to a copper pad with solder on a PCB with two ounce traces, the TPS2343 exhibits thermal resistance from junction to ambient of 29C/W. When the TPS2343 is mounted to a conventional PCB with solder mask under the package and only the lead tips soldered to traces, the TPS2343 exhibits thermal resistance from junction to ambient of 35C/W. Refer to Technical Briefs: PowerPADt Thermally Enhanced Package SLMA003 and PowerPADt Made Easy SLMA004 for more information on using this PowerPadt package. www.ti.com 21 SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION Determining Component Values Load Conditions Table 1. Load Conditions for Determining Component Values SUPPLY DRIVER ILOAD (A) ITRIP (A) CLOAD (F) SR (V/s) +12 V 0.500 +5 V 5.000 1.50 300 250 7.00 3000 +3.3 V 200 7.600 10.0 3000 200 -12 V 0.100 0.20 150 200 +3.3 Vaux 0.375 1.10 150 5000 +1.5 VIO 1.500 4.00 150 200 +3.3-V Supply Overload Trip Point with MISET = 6.04 kW Desired ITRIP (nom) 10 A R SENSE + V RTRIP (nom) I TRIP (nom) I TRIP(min) + I TRIP(max) + + 63 mV + 0.0063 W NChoose 6 mW, 2% sense resistor 10 A V TRIP (min) R SENSE (max) V TRIP (max) R SENSE (min) + 48 mV + 7.84 A 6.12 mW + 76 mV + 12.93 A 5.88 mW +5-V Supply Overload Trip Point with MISET = 6.04 kW Desired ITRIP (nom) 7 A R SENSE + V RTRIP (nom) I TRIP(min) + I TRIP(max) + 22 I TRIP (nom) + 53 mV + 0.00589 W NChoose 6 mW, 2% sense resistor. 7A V TRIP (min) R SENSE (max) V TRIP (max) R SENSE (min) + 43 mV + 7.03 A 6.12 mW + 63 mV + 10.71 A 5.88 mW www.ti.com SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION 3.3 Volt or 1.55 Volt Supply for VIO Overload trip point with MISET = 6.04 kW. Desired ITRIP(nom) = 4 A R SENSE + V TRIP(nom) I TRIP(nom) + 23.5 mV + 0.00598W 4.0 A Choose 0.006 I TRIP(min) + 20 mV + 3.27 A MIN 0.00612 W I TRIP(max) + 27 mV + 4.594 A MIN 0.00588 W Thermal Shutdown Under normal operating consitions, the power dissipation in the TS2343 is low enough that the junction temperature (TJ) is not more than 15C above air temperature (TA). However, in the case of a load that exceeds PCI specifications (but remains under the TPS2343 overcurrent threshold) power dissipation can be higher. To prevent any damage from an out-of-specification load or severe rise in ambient temperature, the TPS2343 contains two independent thermal shutdown circuits, one for each main supply slot. VAUX is not affected by the thermal shutdown. The highest power dissipation in the TPS2343 is from the 12-V power FET so that TPS2343 temperature sense elements are integrated closely with these FETs. These sensors indicate when the temperature at these transistors exceeds approximately 150C, due either to average device power dissipation, 12-V power FET power dissipation, or a combination of both. When excessive junction temperature is detected in one slot, that slot's fault latch is set and remains set until the junction temperature drops by approximately 10C and the slot is then restarted. The other slot is not affected by this event. www.ti.com 23 SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION S6 S3 24 www.ti.com SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION MOSFET Selection All external power MOSFETs are N-channel devices. Gate resistors are not required. Hot plug can cause excessive voltage spikes on the input and output of the FET. During a short circuit, an excessive current spike can occur before current limit turns off the output. Although the duration is usually very small, the energy can be large and cause big voltage fluctuations. The MOSFET will operate at high current and high drain to source voltage which could violate the safe operating area of the device and cause breakdown. To ensure safe operation of the external MOSFET, the drain-to-source voltage rating should be reasonably higher than VIN. A 2-to-1 or 3-to-1 ratio of the VDSS to VIN is recommended. VDSS > 2 x VIN The current rating of the FET at the maximum case temperature (usually 70C - 100C), ID, should be at least 2 x ITRIP(max) (see RSENSE Calculations Section). ID at TC(max) > 2 x ITRIP(max) The gate-to-source voltage rating, VGS of the FET should be at least 10 V because the TPS2343 gate voltages can be as high as 12 V and the source voltage as low as 3.3 V, a difference of 8.7 V. VGS > 10 V Another important parameter in choosing a FET is the on-resistance, RDS(on). The lower the RDS(on), the smaller the power dissipation of the FET and the easier to maintain the PCI recommended bus voltage. The lowest RDS(on) FETs are the most expensive. To calculate the FET RDS(on), note the lower limit for each slot voltage specified in the PCI-X Electrical and Mechanical Addendum. Table 2. SUPPLY VOLTAGE PCI TOLERANCE SUPPLY TOLERANCE MAXIMUM OPERATING CURRENT +5 V 0.25 V 3% 5.0 A +3.3 V 0.3 V 3% 7.6 A VIO = 3.3 0.3 V 3% 3.5 A VIO = 1.5 0.075 V 3% 1.5 A www.ti.com 25 SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION The difference between the lower limit of both the system power supply and the PCI specification slot voltage value is the system voltage budget. System power supplies specified with slightly high output voltage increases the system voltage budget making the FETs RDS(on) less critical. To calculate the RDS(on), sum the voltage drop due to contact resistance of the power input connector, the PCI connector, and the sense resistor. This sum is subtracted from the system voltage budget to give the VRDS(on) and ultimately the RDS(on). V-Power Conn - + V-RDS ON 4 Power Supply + + - V-PCIconn R SENSE 8 R = 0.02 Ohm/pin RDS ON Limits 5 V+/-3% 5.15 V to 4.85 V V-R SENSE PCI Limit 5.25 V to 4.75 V - V-Power Conn - + - + V-PCIconn 4 8 PS Connector R = 0.002 Ohms Slot Figure 3. Terms Terms are defined below referenced by an example calculation. D System voltage budget = PCI lower limit - power supply lower limit D System voltage drop= V power connector + V PCI connector + VRSENSE (For power and ground paths) D VRDS(on) = system voltage budget - system voltage drop D RDS(on) = VRDS(on)/max operating current 26 www.ti.com SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION Example Calculation of RDS(on) for the 5.0 V Main: D D D D D D D D D D D D D D PS low voltage 5.0 V - 3% = 4.85 V PCI spec lowest voltage to add in card = 4.75 V System voltage budget = 4.85 V - 4.75 V = 0.1 V PCI bus has 8 pins for 5.0 A, 5.0 A/8 pins = 0.625 A/pin Contact resistance = 20 m, .625 A x 0.020 = 12.5 mV VPCI connector = 12.5 mV + 12.5 mV (return path) = 25 mV V power connector = 5.0 A/4 pins = 1.25 A/pin Pin contact resistance = 0.002 , V power connector = 1.25A x 0.002 = 2.5 mV, 2.5 mV x 2 = 5 mV VRSENSE = 5.0 A x 0.006 = 30 mV System voltage budget = VPCI connector + V power connector + VRSENSE +VRDS(on) 100 = 25 + 5 + 30 + VRDS(on), VRDS(on) = 40 mV RDS(on) = 0.040 V/5 A = 8 m Systems have different parameters but calculating RDS(on) for the different voltages using these assumptions gives the following results. Table 3. VOLTAGE RDS(on) +5 V 8 m +3.3 V 12 m +3.3 VIO 12 m +1.5 VIO 4 m FET Heatsink Place a layer of copper on the circuit board under the surface mount FET and solder the FET to the board for good thermal connection. Connect the copper to an inner voltage layer at the same potential or if possible, an area of copper on the other side of the board. Decoupling Capacitors Decoupling is required on the power inputs to the TPS2343. Use 0.1-F capacitors on the 12 V, -12 V, 5 V, 3.3 V main and 3.3-VAUX and 1.5-VAUX inputs and keep them close to the TPS2343 voltage input pins. The pin descriptions for the TPS2343 signal outputs recommend 0.01-F decoupling capacitors. These are not required. www.ti.com 27 SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION PCI-X Capability Selection The PCI-X Local Bus 2.0 specification describes how the PCIXCAP pins program board operating mode using resistors on the board. The TPS2343 decodes the resistor values and communicates this to the slot controller using logic signals. Five different operating modes are allowed under PCI-X 2.0. These modes are compatible with the three existing PCI and PCI-X 1.0 modes and add operation at 266 MHz and 533 MHz. The PCI-X 2.0 specification requires that PCIXCAP pins are pulled up to 3.3 V with a 3.3-k, 5% resistor on the backplane or systemboard. This pull-up resistor combined with the resistor on the board creates a voltage divider as shown in Table 4. Table 4. MODE BUS SPEED BOARD CONNECTION ON PCIXCAP PIN PCIXCAP PIN NOMINAL VOLTAGE PCI 2.2 33 MHz/66 MHz ground 0V PCI-X 1.0 66 MHz 10 k 1% to ground 2.481 V PCI-X 1.0 133 MHz open circuit 3.300 V PCI-X 2.0 266 MHz 3.16 k 1% to ground 1.614 V PCI-X 2.0 533 MHz 1.02 k 1% to ground 0.779 V The TPS2343 detects these five different modes using four comparators. These comparators have voltage thresholds between the nominal voltage points, as shown in the electrical characteristics table. These thresholds are proportional to DIGVCC voltage, so any supply variations are compensated by equivalent variation in the voltage thresholds. The voltage thresholds are far from the nominal voltage, so there is noise margin in mode selection. The table below shows these margins with a 3.3-k, 5% pull-up resistor and the voltage threshold ranges shown in the electrical characteristic table. Table 5. MODE WINDOW PCIXCAP VOLTAGE NOISE MARGIN 33 MHz to 533 MHz 0.279 V 533 MHz to 266 MHz 0.314 V 266 MHz to 66 MHz 0.331 V 66 MHz to 133 MHz 0.319 V PCIXCAP Outputs The PCIXCAPxn outputs directly communicate the PCIXCAP resistances according to Table 6. Table 6. MODE BUS SPEED PCIXCAPx1 (PINS 48, 13) PCIXCAPx2 (PINS 46, 15) PCIXCAPx3 (PINS 43, 18) PCI 2.2 33 MHz/66 MHz 0 0 0 PCI-X 1.0 66 MHz 1 0 0 PCI-X 1.0 133 MHz 1 1 0 PCI-X 2.0 266 MHz 0 0 1 PCI-X 2.0 533 MHz 1 0 1 If desired, PCIXCAPx3 can be connected to VIOSEL through an inverter to automatically set VIO based on adapter card type. 28 www.ti.com SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION Power Stage Design Adapter card current is a combination of static adapter card current consumption plus inrush current caused by the supply voltage ramping into the adapter card decoupling capacitance. The TPS2343 implements current limiting on each supply. For the 5-V, 3.3-V and VIO supplies, user-supplied 6-m resistors sense current. For the other supplies, current-sense resistors are integrated into the TPS2343. The current sense thresholds of the 5-V, 3.3-V, 12-V, and -12-V supplies are programmed by one user-supplied resistor connected from MISET to GROUND. The TPS2343 implements slew-rate control using on-chip current sources and user-supplied capacitors. Each supply is controlled by the slew rate capacitor for that supply except for the -12-V supply, which tracks the 12-V supply. Using the recommended current-sense resistors, current-threshold resistor, and slew-rate control capacitors implements a system with slew rates that meet PCI specifications and can deliver power to any adapter card that meets PCI specifications. If a unique adapter card produces premature current limiting with the recommended programming components, current-limit thresholds can be increased by increasing the value of the resistor connected to MISET or inrush current can be reduced by raising the value of the appropriate slew-rate control capacitors. Aux +3.3V In -12V In 73 52 3VAUXI M12VINA +12V In +3.3V In 55 30 +5V In 62 P12VINA DIGVCC IRF7460 or Si4410DY V5IN 5VGA IRF7460 or Si4410DY 65 0.27F 15 k 3VGA 76 5VSA 56 5VISA 57 3VSA 64 3VISA 65 3.3 V to Slot P12VOA 53 12 V to Slot M12VOA 51 -12 V to Slot 3VAUXA 72 3.3V Aux to Slot 0.27F TPS2342 6 m 15 5V to Slot 6 m MISET ANAGND 11 50 PWRGND 61 PWRGND 3VAUXGA 80 71 P12VGA 54 0.022 F 6.04 k 0.022 F Figure 4. Typical TPS2343 Application Showing Power, Slew-Rate Control and Current-Limit Programming Components (one slot shown) www.ti.com 29 SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION Current Regulation and Over Current Protection In the event of excessively high slot current for the 3.3-V main, 5-V main, or VIO supplies, the TPS2343 regulates load current at the maximum specified current for a fixed 5 ms. If the current does not reduce below the maximum in that time, the TPS2343 shuts down main power to that slot. This minimizes the risk of power rail droop on adjacent slots while at the same time allowing marginal cards to continue to function through brief, high-current demands. Control of high-current demand is accomplished using closed-loop regulation of the gate voltage, as shown in the block diagram below. 15VIOGA 70 3VIOGA 73 5VGA 65 3VGA 76 +12V Over Current 3ms Delay -12V Over Current Over Temperature 68 VIOISA 69 3VSA 74 + + VIOSA 23mV + + 3VISA 75 100ms Delay 63mV 66 5VISA 67 S Q R Q 5ms Delay S Q R Q Fault PWREN + + 5VSA Main Fault Latch Regulation Mode Latch 53mV Figure 5. Current Regulation Functional Block Diagram (one slot shown) Once an overload has been detected on one of these three supplies, the regulation mode latch is set, and gate voltage is reduced. At the same time, a 5-ms timer starts. If the timer elapses without the load current reducing, the main fault latch is set, and the slot latchs off until power is shut off and restarted by the host. If the overload reduces for more than 100 s, the regulation mode latch clears and the 5-ms timer resets. For excessively-high slot current on the 12-V main, -12-V main, and 3.3-V auxiliary supplies, the TPS2343 shuts down 3 s after the fault to prevent disturbance to power on the backplane or damage to the TPS2343. 30 www.ti.com SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION VIO Power Selection PCI-X Local Bus specification revision 2.0 requires that VIO be 3.3 V when the slot is operating in 33-MHz, 66-MHz, or 133-MHz modes and 1.5 V when the slot is operating in 266-MHz or 533-MHz modes. The TPS2343 provides signals to drive external power FETs to select between 3.3 V and 1.5 V for VIO. To prevent body-diode conduction from the 3.3-V supply to the 1.5-V supply when 3.3 V is delivered to VIO, the 1.5-V VIO switch uses two power FETs in blocking-series connection. To minimize voltage loss, low on-resistance FETs are required (such as IRF1302S or Si4430DY). It is helpful to anticipate the voltage drop in the FETs and adjust the 1.5-V VIO power source for slightly greater than 1.5 V, for example 1.55 V 25 mV. 1.55V 10 m A IRF1302S or Si4430DY 15VIOG 22 nF 3.3V 10 m A IRF7460 or 3VIOG Si4410DY 22 nF 23mV VIOS + 6mW VIOIS To Slot VIO Figure 6. VIO Application Diagram (one slot shown) When PWREN is asserted, depending on VIOSEL, either 15VIOG or 3VIOG ramps up concurrently with the other main power supplies. When PWREN is deasserted, 15VIOG or 3VIOG ramps down concurrently with the other main power supplies. Gate slewing caps are used on the VIO channels. One cap is used for the 3VIOGx and another for the 15VIOGx in order to set the slew rate properly for a 1.5-V or 3.3-V channel. There is only one charging current on VIO which is set at 10 A and switched between the two pins depending on the VIOSELx input. PCI specifications limit adapter card VIO capacitance to 150 F. It is recommended that the backplane also have between 10 F and 50 F of bypass capacitance on VIO to minimize transients. The capacitance on each gate is 22 nF, producing a gate slew rate of approximately 0.45 V/ms. The averagelimits VIO capacitive inrush current is approximately 68 mA. www.ti.com 31 SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION Digital Communications 3.3V 78 FROM SLOT 47 PMEOA PMEA Vaux SWA AUXFLTA Control PCIXCAP1A 50 PCIXCAPA A/D Converter PCIXCAP2A and Decoder FAULTA PWRENA Main Power OUTUVA Control PWROFFA FROM HOT PLUG 44 VIOSELA 53 57 55 TO HOT PLUG CONTROLLER PCIXCAP3A 48 77 51 54 52 49 V Selection IO and Control 3.3V CONTROLLER 270 43 42 ATTLEDA ALEDENA PLEDENA LED Drivers 46 PWRLEDA 45 Figure 7. Digital Interface Application Diagram (one slot shown) 32 www.ti.com 3.3V 270 SLUS644B - FEBRUARY 2005 - MAY 2005 APPLICATION INFORMATION Power Cycling and PME The PCI power management specification defines a signal called PME (power management event) to allow requests for power state changes to be communicated from the slot back to the system. The TPS2343 provides a slot-specific PMEx input and a gated PMEOx output that can be monitored by the system. The gated PMEOx output is enabled a delay after the SWx slot switch closes (SWx low) as shown in the timing diagram below. The purpose of the delay is to ensure that 3.3-VAUX power is stable to the slot before connecting PMEx the signal. If the PMEx signal was presented to the system while 3.3-VAUX power was still ramping up, a false trigger could result.The 3.3-VAUX circuitry provides over current fault detection. In the event of an over current fault on VAUX, the slot 3.3-VAUX and PME signals are immediately disconnected. The fault state is latched internally in the TPS2343 and is cleared either by opening the SWx slot switch or by removing the 3.3-VAUX power to the TPS2343. 10 ms TYP 2.5 ms TYP 10 ms TYP SWx 3VAUXx PME ENABLE Auxfltx VAUX and PME Gating When SWx is closed (low), 3VAUXx power is immediately applied to the slot with controlled slew rate, minimizing inrush current into 3VAUXx bypass capacitors. After 3VAUXx power completes ramping up, a delay timer starts. At the end of the delay timer cycle, the PMEx enable switches close, allowing connection of the PMEx signal to the PMEOx output. Multiple PMEOx output pins can be connected to the same node, creating a PME bus that can be connected to a master system interrupt input.When SWx is opened (high) or if there is a power fault on slot x, the PMEx enable switch for that slot is immediately opened and the 3VAUXx power for that slot is removed. Although these events happen at approximately the same time, the 3VAUXx power should remain high until the PMEx switch is open so that falling 3VAUXx power does not cause a nuisance PMEx interrupt. To insure that 3VAUXx remains high during a power fault, 3VAUXx should have a bypass capacitance of at least 20 F. If the capacitor is not available on the inserted card, it should be provided on the system board.The PME circuit operates independently of any of the main power supplies. www.ti.com 33 SLUS644B - FEBRUARY 2005 - MAY 2005 TYPICAL CHARACTERISTICS TURN OFF FROM 12 V OVERCURRENT SLOT VOLTAGE TURN ON FROM PWREN 5 V/div. 12 V 5 V/div. 5V +12 3.3 V FAULT OUTUV 12 V PWROFF t - Time - 5 ms/div. t - Time - 5 s/div. Figure 8 Figure 9 5 V TURN OFF FOR 5 V OVERCURRENT 5 V AT COARSE REGULATION ON 5 V OVERCURRENT 5V 5 V/div. 5V 5 V/div. FAULT FAULT OUTUV OUTUV PWROFF PWROFF t - Time - 20 s/div. t - Time - 1 ms/div. Figure 10 34 Figure 11 www.ti.com SLUS644B - FEBRUARY 2005 - MAY 2005 TYPICAL CHARACTERISTICS 12 V TURN OFF FOR 5 V OVERCURRENT 5 V TURN OFF FOR 12 V OVERCURRENT 5 V/div. 5 V/div. 5V 12 V FAULT FAULT OUTUV OUTUV PWROFF PWROFF t - Time - 1 ms/div. t - Time - 5 s/div. Figure 12 Figure 13 1.5 V FOR VIO OVERCURRENT VAUX FOR VAUX OVERCURRENT 2 V/div. 2 V/div. 1.5 VIO VAUX FAULT AUXFLT OUTUV LOAD APPLIED PWROFF t - Time - 1 ms/div. t - Time - 5 s/div. Figure 14 Figure 15 www.ti.com 35 SLUS644B - FEBRUARY 2005 - MAY 2005 TYPICAL CHARACTERISTICS VAUX OFF FROM SW VAUX ON FROM SW 2 V/div. 2 V/div. VAUX VAUX VAUX GATE VAUX GATE SW SW t - Time - 2 ms/div. t - Time - 0.1 ms/div. Figure 17 Figure 16 36 www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS2343DDP ACTIVE HTSSOP DDP 80 28 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS2343DDPG3 ACTIVE HTSSOP DDP 80 28 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS2343DDPR ACTIVE HTSSOP DDP 80 2000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR TPS2343DDPRG3 ACTIVE HTSSOP DDP 80 2000 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS2343DDPR Package Package Pins Type Drawing SPQ HTSSOP 2000 DDP 80 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 8.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 17.3 1.7 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2343DDPR HTSSOP DDP 80 2000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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