Features
• Dual Marked with Device
Part Number and DSCC
Drawing Number
• Manufactured and Tested on
a MIL-PRF-38534 Certified
Line
• QML-38534, Class H and K
• Five Hermetically Sealed
Package Configurations
• Performance Guaranteed
over -55°C to +125°C
• High Speed: 10 M Bit/s
• CMR: > 10,000 V/µs Typical
• 1500 Vdc Withstand Test
Voltage
• 2500 Vdc Withstand Test
Voltage for HCPL-565X
• High Radiation Immunity
• 6N137, HCPL-2601, HCPL-
2630/-31 Function
Compatibility
• Reliability Data
• TTL Circuit Compatibility
Applications
• Military and Space
• High Reliability Systems
• Transportation, Medical, and
Life Critical Systems
• Line Receiver
• Voltage Level Shifting
• Isolated Input Line Receiver
• Isolated Output Line Driver
• Logic Ground Isolation
• Harsh Industrial
Environments
• Isolation for Computer,
Communication, and Test
Equipment Systems
Description
These units are single, dual and
quad channel, hermetically sealed
optocouplers. The products are
capable of operation and storage
over the full military temperature
range and can be purchased as
either standard product or with
full MIL-PRF-38534 Class Level H
or K testing or from the appropri-
ate DSCC Drawing. All devices are
manufactured and tested on a
MIL-PRF-38534 certified line and
are included in the DSCC Quali-
fied Manufacturers List QML-
38534 for Hybrid Microcircuits.
Quad channel devices are
available by special order in the
16 pin DIP through hole
packages.
Truth Table
(Positive Logic)
Multichannel Devices
Input Output
On (H) L
Off (L) H
Functional Diagram
Multiple Channel Devices
Available
Single Channel DIP
Input Enable Output
On (H) H L
Off (L) H H
On (H) L H
Off (L) L H
*See matrix for available extensions.
Hermetically Sealed, High Speed,
High CMR, Logic Gate
Optocouplers
Technical Data
6N134*
81028
HCPL-563X
HCPL-663X
HCPL-565X
5962-98001
HCPL-268K
HCPL-665X
5962-90855
HCPL-560X
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
V
CC
V
OUT
V
E
GND
The connection of a 0.1
µ
F bypass capacitor between VCC and GND is recommended.
2
Selection Guide–Package Styles and Lead Configuration Options
Package 16 Pin DIP 8 Pin DIP 8 Pin DIP 8 Pin DIP 16 Pin Flat Pack 20 Pad LCCC
Lead Style Through Hole Through Hole Through Hole Through Hole Unformed Leads Surface Mount
Channels 2122 4 2
Common Channel VCC, GND None VCC, GND VCC, GND VCC, GND None
Wiring
Withstand Test Voltage 1500 Vdc 1500 Vdc 1500 Vdc 2500 Vdc 1500 Vdc 1500 Vdc
Agilent Part # & Options
Commercial 6N134* HCPL-5600 HCPL-5630 HCPL-5650 HCPL-6650 HCPL-6630
MIL-PRF-38534, Class H 6N134/883B HCPL-5601 HCPL-5631 HCPL-5651 HCPL-6651 HCPL-6631
MIL-PRF-38534, Class K HCPL-268K HCPL-560K HCPL-563K HCPL-665K HCPL-663K
Standard Lead Finish Gold Plate Gold Plate Gold Plate Gold Plate Gold Plate Solder Pads
Solder Dipped Option #200 Option #200 Option #200 Option #200
Butt Cut/Gold Plate Option #100 Option #100 Option #100
Gull Wing/Soldered Option #300 Option #300 Option #300
Class H SMD Part #
Prescript for all below None 5962- None None None None
Either Gold or Solder 8102801EX 9085501HPX 8102802PX 8102805PX 8102804FX 81028032X
Gold Plate 8102801EC 9085501HPC 8102802PC 8102805PC 8102804FC
Solder Dipped 8102801EA 9085501HPA 8102802PA 8102805PA 81028032A
Butt Cut/Gold Plate 8102801UC 9085501HYC 8102802YC
Butt Cut/Soldered 8102801UA 9085501HYA 8102802YA
Gull Wing/Soldered 8102801TA 9085501HXA 8102802ZA
Class K SMD Part #
Prescript for all below 5962- 5962- 5962- 5962- 5962-
Either Gold or Solder 9800101KEX 9085501KPX 9800102KPX 9800104KFX 9800103K2X
Gold Plate 9800101KEC 9085501KPC 9800102KPC 9800104KFC
Solder Dipped 9800101KEA 9085501KPA 9800102KPA 9800103K2A
Butt Cut/Gold Plate 9800101KUC 9085501KYC 9800102KYC
Butt Cut/Soldered 9800101KUA 9085501KYA 9800102KYA
Gull Wing/Soldered 9800101KTA 9085501KXA 9800102KZA
*JEDEC registered part.
Each channel contains a GaAsP
light emitting diode which is
optically coupled to an integrated
high speed photon detector. The
output of the detector is an open
collector Schottky clamped
transistor. Internal shields
provide a guaranteed common
mode transient immunity
specification of 1000 V/µs. For
Isolation Voltage applications
requiring up to 2500 Vdc, the
HCPL-5650 family is also
available. Package styles for
these parts are 8 and 16 pin DIP
through hole (case outlines P and
E respectively), and 16 pin
surface mount DIP flat pack
(case outline F), leadless ceramic
chip carrier (case outline 2).
Devices may be purchased with a
variety of lead bend and plating
options. See Selection Guide
Table for details. Standard
Microcircuit Drawing (SMD)
parts are available for each
package and lead style.
Because the same electrical die
(emitters and detectors) are used
for each channel of each device
listed in this data sheet, absolute
maximum ratings, recommended
operating conditions, electrical
specifications, and performance
characteristics shown in the figures
are identical for all parts.
Occasional exceptions exist due to
package variations and limitations,
and are as noted. Additionally, the
same package assembly processes
and materials are used in all
devices. These similarities give
justification for the use of data
obtained from one part to
represent other parts’ performance
for reliability and certain limited
radiation test results.
3
Outline Drawings
16 Pin DIP Through Hole, 2 Channels
GND
1
V
O2
19
20
2
3
V
O1
87
V
CC2
V
CC1
10
GND
2
15
13
12
Functional Diagrams
16 Pin DIP 8 Pin DIP 8 Pin DIP 16 Pin Flat Pack 20 Pad LCCC
Through Hole Through Hole Through Hole Unformed Leads Surface Mount
2 Channels 1 Channel 2 Channels 4 Channels 2 Channels
Note: All DIP and flat pack devices have common VCC and ground. Single channel DIP has an enable pin 7. LCCC (leadless ceramic
chip carrier) package has isolated channels with separate VCC and ground connections. All diagrams are “top view.”
Leaded Device Marking Leadless Device Marking
5
7
6
8
12
10
11
9
GND
1
3
2
4
16
14
15
13
V
CC
V
O1
V
O2
VCC
VOUT
VE
GND
18
27
36
45
5
7
6
8
12
10
11
9
GND
1
3
2
4
16
14
15
13
V
CC
V
O1
V
O3
V
O2
V
O4
0.20 (0.008)
0.33 (0.013)
4.45 (0.175)
MAX.
20.06 (0.790)
20.83 (0.820)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
0.89 (0.035)
1.65 (0.065)
8.13 (0.320)
MAX.
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
3.81 (0.150)
MIN.
1
3
2
4
8
6
7
5
VCC
GND
VO2
VO1
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
•
50434 COUNTRY OF MFR.
Agilent CAGE CODE*
Agilent DESIGNATOR
DSCC SMD*
PIN ONE/
ESD IDENT
Agilent P/N
DSCC SMD*
* QUALIFIED PARTS ONLY
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
A QYYWWZ
XXXXXX
•
XXXX
XXXXXX
XXX 50434 DSCC SMD*
Agilent CAGE CODE*
Agilent DESIGNATOR
COUNTRY OF MFR.
Agilent P/N
PIN ONE/
ESD IDENT DSCC SMD*
* QUALIFIED PARTS ONLY
4
Outline Drawings (continued)
16 Pin Flat Pack, 4 Channels
8 Pin DIP Through Hole, 2 Channels
2500 Vdc Withstand Test Voltage
20 Terminal LCCC Surface Mount,
2 Channels
8 Pin DIP Through Hole, 1 and 2 Channels
8.13 (0.320)
MAX.
5.23
(0.206)
MAX.
2.29 (0.090)
MAX.
7.24 (0.285)
6.99 (0.275)
1.27 (0.050)
REF.
0.46 (0.018)
0.36 (0.014)
11.13 (0.438)
10.72 (0.422)
2.85 (0.112)
MAX.
0.89 (0.035)
0.69 (0.027)
0.31 (0.012)
0.23 (0.009)
0.88 (0.0345)
MIN.
9.02 (0.355)
8.76 (0.345)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
3.81 (0.150)
MIN.
4.32 (0.170)
MAX.
9.40 (0.370)
9.91 (0.390)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
0.76 (0.030)
1.27 (0.050)
8.13 (0.320)
MAX.
7.36 (0.290)
7.87 (0.310)
0.20 (0.008)
0.33 (0.013)
7.16 (0.282)
7.57 (0.298)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
3.81 (0.150)
MIN.
5.08 (0.200)
MAX.
9.40 (0.370)
9.91 (0.390)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
0.76 (0.030)
1.27 (0.050)
8.13 (0.320)
MAX.
7.36 (0.290)
7.87 (0.310)
0.20 (0.008)
0.33 (0.013)
7.16 (0.282)
7.57 (0.298)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
1.78 (0.070)
2.03 (0.080) 1.02 (0.040) (3 PLCS)
4.95 (0.195)
5.21 (0.205)
8.70 (0.342)
9.10 (0.358)
1.78 (0.070)
2.03 (0.080)
0.51 (0.020)
0.64
(0.025)
(20 PLCS)
1.52 (0.060)
2.03 (0.080)
METALLIZED
CASTILLATIONS (20 PLCS)
2.16 (0.085)
TERMINAL 1 IDENTIFIER
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
SOLDER THICKNESS 0.127 (0.005) MAX.
1.14 (0.045)
1.40 (0.055)
5
Hermetic Optocoupler Options
Option Description
100 Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This
option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below
for details).
200 Lead finish is solder dipped rather than gold plated. This option is available on commercial
and hi-rel product in 8 and 16 pin DIP. DSCC Drawing part numbers contain provisions for
lead finish. All leadless chip carrier devices are delivered with solder dipped terminals as a
standard feature.
300 Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This
option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below
for details). This option has solder dipped leads.
1.14 (0.045)
1.40 (0.055)
4.32 (0.170)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
4.32 (0.170)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
7.36 (0.290)
7.87 (0.310)
0.20 (0.008)
0.33 (0.013)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
1.40 (0.055)
1.65 (0.065)
4.57 (0.180)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MIN.
0.51 (0.020)
MIN.
4.57 (0.180)
MAX.
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
1.40 (0.055)
1.65 (0.065) 9.65 (0.380)
9.91 (0.390)
5° MAX.
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
6
Recommended Operating Conditions
Parameter Symbol Min. Max. Units
Input Current, Low Level, Each Channel IFL 0 250 µA
Input Current, High Level, Each Channel* IFH 10 20 mA
Supply Voltage, Output VCC 4.5 5.5 V
Fan Out (TTL Load) Each Channel N 6
*Meets or exceeds DSCC SMD and JEDEC requirements.
Absolute Maximum Ratings
(No derating required up to +125°C)
Storage Temperature Range, TS...................................-65°C to +150°C
Operating Temperature, TA..........................................-55°C to +125°C
Case Temperature, TC................................................................+170°C
Junction Temperature, TJ...........................................................+175°C
Lead Solder Temperature ............................................... 260°C for 10 s
Peak Forward Input Current, IFPK
, (each channel,
≤1 ms duration) ...................................................................... 40 mA
Average Input Forward Current, IFAVG
(each channel) ................ 20 mA
Input Power Dissipation (each channel) ..................................... 35 mW
Reverse Input Voltage, VR (each channel) ......................................... 5 V
Supply Voltage, VCC (1 minute maximum) ........................................ 7 V
Output Current, IO (each channel) ............................................... 25 mA
Output Power Dissipation (each channel) .................................. 40 mW
Output Voltage, VO (each channel) .................................................. 7 V*
Package Power Dissipation, PD (each channel) ........................ 200 mW
*Selection for higher output voltages up to 20 V is available.
Single Channel Product Only
Emitter Input Voltage, VE............................................................... 5.5 V
Note enable pin 7. An external
0.01 µF to 0.1 µF bypass
capacitor must be connected
between VCC and ground for each
package type.
8 Pin Ceramic DIP Single Channel Schematic
ESD Classification
(MIL-STD-883, Method 3015)
HCPL-5600/01/0K ............................................................... (∆), Class 1
6N134, 6N134/883B, HCPL-5630/31/3K, HCPL-5650/51,
HCPL-6630/31/3K and HCPL-6650/51/5K....................... (Dot), Class 3
7
Electrical Characteristics (TA = -55°C to +125°C, unless otherwise specified)
Group A[13]
Parameter Symbol Test Conditions Subgroups Min. Typ.** Max. Units Fig. Note
High Level IOH*V
CC = 5.5 V, VO = 5.5 V, 1, 2, 3 20 250 µA1 1
Output Current IF = 250 µA
Low Level VOL*V
CC = 5.5 V, IF = 10 mA, 1, 2, 3 0.3 0.6 V 2 1, 9
Output Voltage IOL (Sinking) = 10 mA
Current Transfer hF CTR VO = 0.6 V, IF = 10 mA, 1, 2, 3 100 % 1
Ratio VCC = 5.5 V
Logic Single ICCH*V
CC = 5.5 V, IF = 0 mA 1, 2, 3 9 14 mA 1
High Channel
Dual VCC = 5.5 V, 18 28 mA 6
Channel IF1 = IF2 = 0 mA
Quad VCC = 5.5 V, IF1 = IF2 =2542mA
Channel IF3 = IF4 = 0 mA
Logic Single ICCL*V
CC = 5.5 V, 1, 2, 3 13 18 mA 1
Low Channel IF = 20 mA
Dual VCC = 5.5 V, 26 36 mA 6
Channel IF1 = IF2 = 20 mA
Quad VCC = 5.5 V, IF1 = IF2 =3350mA
Channel IF3 = IF4 = 20 mA
Input Forward VF*I
F
= 20 mA 1, 2, 3 1.5 1.9 V 3 1, 15
1, 2 1.55 1.75 V 3 1, 16
3 1.85
Input Reverse BVR*I
R
= 10 µA 1, 2, 3 5 V 1
Breakdown
Voltage
Input-Output II-O* RH = 45% 1 1.0 µA 2, 8, 17
Leakage Current T
A = 25°C
t = 5 s 1 1.0 µA18
Capacitance CI-O f = 1 MHz, TC = 25°C 4 1.0 4.0 pF 1, 3,
Between Input/ 14
Output
*Identified test parameters for JEDEC registered parts.
**All typical values are at VCC = 5 V, TA = 25°C.
Recommended Operating Conditions (cont’d.)
Single Channel Product Only[10]
Parameter Symbol Min. Max. Units
High Level Enable Voltage VEH 2.0 VCC V
Low Level Enable Voltage VEL 0 0.8 V
Limits
Supply
Current
Supply
Current
Voltage
VI-O = 1500
Vdc
VI-O = 2500
Vdc
8
Electrical Characteristics, (Contd.) TA = -55°C to +125°C unless otherwise specified
Limits
Parameter Symbol Conditions Subgroups Min. Typ.** Max. Units Fig. Note
tPLH* 9 60 100 ns 4, 5, 1, 5
10, 11 140
tPHL* 9 55 100 ns
10, 11 120
Output Rise Time tLH RL = 510 Ω, 9, 10, 11 35 90 ns 1
Output Fall Time tHL 35 40
Common Mode |CMH|V
CM = 50 V (PEAK), 9, 10, 11 1000 >10000 V/µs 7 1, 7,
Transient VCC = 5 V, 14
Immunity at VO (min.) = 2 V,
High Output RL = 510 Ω,
Level IF = 0 mA
Common Mode |CML|V
CM = 50 V (PEAK), 9, 10, 11 1000 >10000 V/µs 7 1, 7,
Transient VCC = 5 V, 14
Immunity at VO (max.) = 0.8 V,
Low Output RL = 510 kΩ,
Level IF = 10 mA
Single Channel Product Only
Low Level IEL VCC = 5.5 V, 1, 2, 3 -1.45 -2.0 mA
Enable Current VE = 0.5 V
High Level VEH 1, 2, 3 2.0 V 10
Enable Voltage
Low Level VEL 1, 2, 3 0.8 V
Enable Voltage
*Identified test parameters for JEDEC registered part.
**All typical values are at VCC = 5 V, TA = 25°C.
Typical Characteristics, TA = 25°C, VCC = 5 V
Parameter Sym. Typ. Units Test Conditions Fig. Note
Input Capacitance CIN 60 pF VF = 0 V, f = 1 MHz 1
Input Diode Temperature ∆VF-1.5 mV/°CI
F
= 20 mA 1
∆TA
Resistance (Input-Output) RI-O 1012 ΩVI-O = 500 V 2
Single Channel Product Only
Propagation Delay Time of tELH 35 ns RL = 510 Ω, CL = 50 pF 8, 9 1, 11
Enable from VEH to VEL IF = 13 mA, VEH = 3 V,
Propagation Delay Time of tEHL 35 ns 1, 12
Enable from VEL to VEH
Dual and Quad Channel Product Only
Input-Input II-I 0.5 nA Relative Humidity = 45% 4
Leakage Current VI-I = 500 V, t = 5 s
Resistance (Input-Input) RI-I 1012 ΩVI-I = 500 V 4
Capacitance (Input-Input) CI-I 0.55 pF f = 1 MHz 4
Propagation Delay
Time to Low
Output Level
6
Propagation Delay
Time to High
Output Level
Group A[13]
Test
VCC = 5 V,
RL = 510 Ω,
CL = 50 pF,
IF = 13 mA
Coefficient
CL = 50 pF,
IF = 13 mA
VEL = 0 V
9
Notes:
1. Each channel.
2. All devices are considered two-terminal devices; II-O is measured between all input leads or terminals shorted together and all
output leads or terminals shorted together.
3. Measured between each input pair shorted together and all output connections for that channel shorted together.
4. Measured between adjacent input pairs shorted together for each multichannel device.
5. tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 V point on the leading
edge of the output pulse. The tPLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the
1.5 V point on the trailing edge of the output pulse.
6. The HCPL-6630, HCPL-6631, and HCPL-663K dual channel parts function as two independent single channel units. Use the single
channel parameter limits for each channel.
7. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state
(V
O < 0.8 V). CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the
logic high state (VO > 2.0 V).
8. This is a momentary withstand test, not an operating condition.
9. It is essential that a bypass capacitor (0.01 to 0.1 µF, ceramic) be connected from VCC to ground. Total lead length between both
ends of this external capacitor and the isolator connections should not exceed 20 mm.
10. No external pull up is required for a high logic state on the enable input.
11. The tELH enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 V
point on the trailing edge of the output pulse.
12. The tEHL enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse to the 1.5 V
point on the leading edge of the output pulse.
13. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and 883B parts receive 100% testing at 25, 125, and
-55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
14. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed
to limits specified for all lots not specifically tested.
15. Not required for 6N134, 6N134/883B, 8102801, HCPL-268K and 5962-9800101 types.
16. Required for 6N134, 6N134/883B, 8102801, HCPL-268K and 5962-9800101 types.
17. Not required for HCPL-5650, HCPL-5651 and 8102805 types.
18. Required for HCPL-5650, HCPL-5651 and 8102805 types only.
Figure 1. High Level Output Current
vs. Temperature. Figure 2. Input-Output
Characteristics. Figure 3. Input Diode Forward
Characteristic.
10
GND
V
CC
I
F
5 V
V
O
D.U.T.
Rm
INPUT
MONITORING
NODE
PULSE
GENERATOR
Z
O
= 50 Ω
t
H
= 5 ns
C
L
*
R
L
* C
L
INCLUDES PROBE AND STRAY WIRING CAPACITANCE.
V
O
0.01 µF
BYPASS
Figure 4. Test Circuit for tPHL and tPLH.*
V
FF
GND
V
CC
I
I
V
CM
510 Ω
+5 V
OUTPUT V
O
MONITORING
NODE
+–
PULSE GEN.
A
BD.U.T.
0.01 µF
BYPASS
Figure 7. Test Circuit for Common Mode Transient Immunity
and Typical Waveforms.
Figure 6. Propagation Delay vs.
Temperature.
Figure 5. Propagation Delay, tPHL and
tPLH vs. Pulse Input Current, IFH.
11
GND
V
CC
+5 V
D.U.T.
I
F
= 13 mA
PULSE
GENERATOR
Z
O
= 50 Ω
t
r
= 5 ns
C
L
*
R
L
* C
L
INCLUDES PROBE AND
STRAY WIRING CAPACITANCE.
V
E
V
OUT
OUTPUT V
E
MONITORING
NODE
OUTPUT V
O
MONITORING
NODE
0.01 µF
BYPASS
GND
V
CC
D.U.T.*
T
A
= +125 °C
* ALL CHANNELS TESTED SIMULTANEOUSLY.
V
OC
CONDITIONS: I
F
= 20 mA
V
CC
V
IN
+–
(EACH OUTPUT)
(EACH INPUT)
I
O
= 25 mA
0.01 µF
200 Ω
5.3 V
(EACH OUTPUT)
+5.5 V
+5.5 V
200 Ω
Figure 10. Operating Circuit for Burn-In and Steady State Life Tests.
Figure 8. Test Circuit for tEHL and tELH.
Figure 9. Enable Propagation Delay
vs. Temperature.
MIL-PRF-38534 Class H,
Class K, and DSCC SMD
Test Program
Agilent’s Hi-Rel Optocouplers are
in compliance with MIL-PRF-
38534 Classes H and K. Class H
and Class K devices are also in
compliance with DSCC drawings
81028, 5962-90855 and 5962-
98001.
Testing consists of 100% screen-
ing and quality conformance
inspection to MIL-PRF-38534.
www.semiconductor.agilent.com
Data subject to change.
Copyright © 1999 Agilent Technologies
Obsoletes 5968-4743E
5968-9407E (10/00)
