BGSA141MN10
BGSA141MN10
Low Resistance Antenna Aperture Switch
Features
•Designed for high-linearity antenna aperture switching
and RF tuning applications
•Multiple selectable switch configurations:
SP4T/SP3T/SPDT/SPST
•Ultra low RON resistance of 1.0 Ωat each port in ON state
•Low COFF capacitance of 270 fF at each port in OFF state
•High max RF voltage OFF state handling
•Low harmonic generation
•MIPI RFFE control interface
•Hardware Pin swapping function to select 2 USID addresses
•Supply voltage range: 2.3 to 3.6 V
•No RF parameter change within supply voltage range
•Small form factor 1.1 mm x 1.5 mm
•RoHS and WEEE compliant package
1.1 x 1.5 mm
2
Application
•Impedance Tuning
•Antenna Tuning
•Inductance Tuning
•Tunable Filters
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC47/20/22
Block diagram
RFC
VDD
VIO
SCLK
SDATA
Voltage
Regulator
Chargepump
GND
Driver
ESD
RF1 RF2 RF3
MIPI
RFFE
RF4
Final Data Sheet
www.infineon.com
Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
Table of Contents
Table of Contents
Table of Contents 1
1 Features 2
2 Maximum Ratings 3
3 DC Characteristics 5
4 RF Small Signal Parameters 6
5 RF large signal parameters 9
6 MIPI RFFE Specification 11
7 Application Information 17
8 Package Information 18
Final Data Sheet 1 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
Features
1 Features
•
Designed for high-linearity antenna aperture switching and RF tuning
applications
•Multiple selectable switch configurations:
SP4T/SP3T/SPDT/SPST
•Ultra low RON resistance of 1.0 Ωat each port in ON state
•Low COFF capacitance of 270 fF at each port in OFF state
•High max RF voltage OFF state handling
•Low harmonic generation
•MIPI RFFE control interface
•Hardware Pin swapping function to select 2 USID addresses
•Supply voltage range: 2.3 to 3.6 V
•No RF parameter change within supply voltage range
•Small form factor 1.1 mm x 1.5 mm
•RoHS and WEEE compliant package
Description
The BGSA141MN10 is a versatile Single-Pole Quad Throw (SP4T) / Single Pole Triple Throw (SP3T) / Single Pole Double
Throw (SPDT) and Single Pole Single Throw (SPST) RF antenna aperture switch optimized for low
Co
as well as low
Ron
enabling applications up to 4.0 GHz. Including a RFFE digital control interface, this switch oers the possibility to adopt a
SP4T, SP3T, SPDT along with SPST topology for a better flexibility in RF Front-End designs.
The BGSA141MN10 includes 4 ultra-low
Ron
ports making it ideal for antenna aperture switching and switchable capacitors
of high values. This single supply chip integrates on-chip CMOS logic driven by a simple, single-pin CMOS or TTL compatible
control input signal. Unlike GaAs technology, the 0.1 dB compression point exceeds the switch maximum input power level,
resulting in linear performance at all signal levels and external DC blocking capacitors at the RF ports are only required if DC
voltage is applied externally. Due to its very high RF voltage ruggedness, it is suited for switching any reactive devices such as
inductors and capacitors in RF matching circuits without significant losses in quality factors.
BGSA141MN10 empower its users with a smart USID selection feature. Default USID is 0b1100 when data signal is routed
to pin 5 and clock signal to pin 6. Default USID is 0b1101 when data signal is routed to pin 6 and clock signal to pin 5. This
Infineon patented feature allows to drive 2 identical BGSA141MN10 parts with the same MIPI RFFE bus opening higher degree
of flexibility and freedom in the PCB design.
Product Name Marking Package
BGSA141MN10 M5 TSNP-10-3
Final Data Sheet 2 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
Maximum Ratings
2 Maximum Ratings
RFC
VDD
VIO
SCLK
SDATA
Voltage
Regulator
Chargepump
GND
ESD
RF1 RF2 RF3 GND
RF IN RF OUT
GND
ISO
RF4
Figure 1: RF operating voltage measurement configuration
Table 1: Maximum Ratings, Table I at TA=25 ◦C, unless otherwise specified
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Frequency Range f0.1 – – GHz 1)
Supply voltage 2) VDD -0.5 – 6 V
only for infrequent and short
duration time periods
Storage temperature range TSTG -55 – 150 ◦C –
RF input power PRF_max – – 39 dBm
Pulsed RF input duty cycle of
25 % and 4620
µ
s in ON-state,
measured per 3GPP TS 45.005
RF voltage VRF_max – – 44 V
Short term peaks (1
µ
s in 0.1%
duty cycle), exceeding typical
linearity, Ron and Co param-
eters, in Isolation mode, test
condition schematic in Fig. 1
ESD capability, CDM 3) VESDCDM -1 – +1 kV
ESD capability, HBM 4) VESDHBM – – Class1B -
ESD capability, system level (RFc port) 5) VESDANT -8 – +8 kV
RFC vs system GND, with 27 nH
shunt inductor
Junction temperature Tj– – 125 ◦C –
1)
Switch has a lowpass response. For higher frequencies, losses have to be considered for their impact on thermal heating. The DC voltage at RF ports
VRFDC
has
to be 0V.
2) Note: Consider potential ripple voltages on top of VDD. Including RF ripple, VDD must not exceed the maximum ratings: VDD =VDC +VRipple .
3) Field-Induced Charged-Device Model JESD22-C101. Simulates charging/discharging events that occur in production equipment and processes. Potential for
CDM ESD events occurs whenever there is metal-to-metal contact in manufacturing.
4) Human Body Model ANSI/ESDA/JEDEC JS-001 (R=1,5 kΩ,C=100 pF).
5) IEC 61000-4-2 (R=330 Ω,C=150 pF), contact discharge.
Final Data Sheet 3 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
Maximum Ratings
Table 2: Maximum Ratings, Table II at TA=25 ◦C, unless otherwise specified
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Maximum DC-voltage on RF-Ports and
RF-Ground
VRFDC 0 – 0 V
No DC voltages allowed on RF-
Ports
RFFE Supply Voltage VIO -0.5 – 3.6 V –
RFFE Control Voltage Levels
V
SCLK
,
VSDATA
-0.7 –
V
IO
+0.7
(max.
3.6)
V –
Warning: Stresses above the max. values listed here may cause permanent damage to the device. Maximum rat-
ings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
Exposure to conditions at or below absolute maximum rating but above the specified maximum operation conditions
may aect device reliability and life time. Functionality of the device might not be given under these conditions.
Final Data Sheet 4 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
DC Characteristics
3 DC Characteristics
Table 3: DC Characteristics at TA=−40 ◦C to 85 ◦C
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Supply Voltage VDD 2.3 2.8 3.6 V –
Supply Current IDD
– 80 150 µA Normal Mode
– 0.1 2 µA Low Power or Default Mode
RFFE supply voltage VIO 1.65 1.8 1.95 V –
RFFE input high voltage1VIH 0.7*VIO – VIO V –
RFFE input low voltage1VIL 0 – 0.3*VIO V –
RFFE output high voltage1VOH 0.8*VIO – VIO V –
RFFE output low voltage1VOL 0 – 0.2*VIO V –
RFFE control input capacitance CCtrl – – 2 pF –
RFFE supply current IVIO – 15 25 µA Idle State
1SCLK and SDATA
Final Data Sheet 5 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
RF Small Signal Parameters
4 RF Small Signal Parameters
Table 4: Parametric specifications using SP4T configuration
Parameter Symbol Values Unit STATE / Notes
Min. Typ. Max.
Frequency range f 0.1 4.0 GHz
VDD = 2.3 −3.6 V,
TA=−40 ◦C... + 85 ◦C,
Z0=50 Ω
RF1, RF2, RF3 or RF4 to RFc
ON resistance
RONSP4T– 1.0 Ω
RF1, RF2, RF3 or RF4 to RFc
OFF capacitance
COFFSP4T– 270 fF
Table 5: Parametric specifications using SP3T configuration
Parameter Symbol Values Unit STATE / Notes
Min. Typ. Max.
Frequency range f 0.1 4.0 GHz
VDD = 2.3 −3.6 V,
TA=−40 ◦C... + 85 ◦C,
Z0=50 Ω
RF1||RF2 or RF3||RF4 to RFc 1)
ON resistance
RONSP3T(1) – 0.5 Ω
RF1||RF2 or RF3||RF4 to RFc 1)
OFF capacitance
COFFSP3T(1) – 540 fF
RF1, RF2, RF3 or RF4 to RFc
ON resistance
RONSP3T(2) – 1.0 Ω
RF1, RF2, RF3 or RF4 to RFc
OFF capacitance
COFFSP3T(2) – 270 fF
1)RF1 and RF2 or RF3 and RF4 connected together on PCB
Table 6: Parametric specifications using SPDT configuration
Parameter Symbol Values Unit STATE / Notes
Min. Typ. Max.
Frequency range f 0.1 4.0 GHz
VDD = 2.3 −3.6 V,
TA=−40 ◦C... + 85 ◦C,
Z0=50 Ω
RF1||RF2 and RF3||RF4 to RFc 1)
ON resistance
RONSPDT – 0.5 Ω
RF1||RF2 and RF3||RF4 to RFc 1)
OFF capacitance
COFFSPDT – 540 fF
1)RF1 and RF2, RF3 and RF4 connected together on PCB
Final Data Sheet 6 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
RF Small Signal Parameters
Table 7: Parametric specifications using SPST configuration
Parameter Symbol Values Unit STATE / Notes
Min. Typ. Max.
Frequency range f 0.1 4.0 GHz
VDD = 2.3 −3.6 V,
TA=−40 ◦C... + 85 ◦C,
Z0=50 Ω
RF1||RF2||RF3||RF4 to RFc 1)
ON resistance
RONSPST – 0.25 Ω
RF1||RF2||RF3||RF4 to RFc 1)
OFF capacitance
COFFSPST – 1.08 pF
1)RF1, RF2, RF3, RF4 connected together on PCB
Table 8: RF electrical parameters
Insertion Loss: RF1 to RFc, RF2 to RFc, RF3 to RFc or RF4 to RFc (SP4T mode) (1,2)
Parameter Symbol Values Unit STATE / Notes
Min. Typ. Max.
698 - 960 MHz
ILSP4T
0.1 0.25 0.4 dB
VDD = 2.3 −3.6 V,Z0=50 Ω,
TA=−40 ◦C... + 85 ◦C
1710 - 1980 MHz 0.35 0.55 0.7 dB
1981 - 2169 MHz 0.45 0.65 1.0 dB
2170 - 2690 MHz 0.5 0.80 1.2 dB
Return Loss: RF1, RF2, RF3 or RF4 (1,2,3)
698 - 960 MHz RLSP4T
16 21 – dB VDD = 2.3 −3.6 V,Z0=50 Ω,
TA=−40 ◦C... + 85 ◦C
1710 - 2690 MHz 12 14 – dB
Isolation: RF1 to RFc, RF2 to RFc, RF3 to RFc or RF4 to RFc (SP4T mode) (1,2,3)
698 - 960 MHz
ISOSP4T
21 25 – dB
VDD = 2.3 −3.6 V,Z0=50 Ω,
TA=−40 ◦C... + 85 ◦C
1710 - 1980 MHz 15 18 – dB
1981 - 2169 MHz 14 17 – dB
2170 - 2690 MHz 13 16 – dB
Isolation: RFc to RFx (Isolation mode)(1,2,3)
698 - 960 MHz
ISOON
17 20 – dB
VDD = 2.3 −3.6 V,Z0=50 Ω,
TA=−40 ◦C... + 85 ◦C
1710 - 1980 MHz 12 14 – dB
1981 - 2169 MHz 11 13 – dB
2170 - 2690 MHz 10 13 – dB
Switching Time
MIPI to RF Time tINT 0.5 5 6 µs
50 % last SCLK falling edge to
90 % RF value settled, Fig. 2
Power Up Settling Time tPUS – 10 25 µs Aer power down mode, Fig. 3
1) Valid for all RF power levels, no compression behavior
2)On application board without any matching components
Final Data Sheet 7 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
RF Small Signal Parameters
90%
SCLK
RF Signal
SDATA
TINT
Figure 2: MIPI to RF Time
SCLK
SDATA
TPUP
VIO
VBAT
b)
SCLK
SDATA
TPUP
VIO
VBAT
a)
Figure 3: Power-Up Settling Time Definition
Power-Up Settling Time Definition:
a)
when the device is already in Active Mode.
b)
when changing from Low Power Mode
to Active Mode.
Aer Power-Up of VIO the device is set to Low Power Mode. An additional MIPI instruction is necessary to set the switch to
Active Mode. This case is covered by b).
Final Data Sheet 8 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
RF large signal parameters
5 RF large signal parameters
Table 9: RF large signal specifications
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
RF operating voltage VRF_peak – – 36 V
In isolation Mode. Test condi-
tions schematic in Fig. 1
Harmonic Generation up to 12.75 GHz(1,2,3)
All RF Ports
Second Order Harmonics
PH2– -105 – dBc 25 dBm, f0= 786 MHz
All RF Ports
Third Order Harmonics
PH3– -115 – dBc 25 dBm, f0= 786 MHz
All RF Ports
Second Order Harmonics
PH2– -93 – dBc 33 dBm, f0= 824 MHz
All RF Ports
Third Order Harmonics
PH3– -94 – dBc 33 dBm,f0= 824 MHz
All RF Ports
Higher Order Harmonics
PHx,x>3– – -105 dBc 25 dBm
Intermodulation Distortion IMD2 (1,2,3)
IIP2, low IIP2,l – 110 – dBm IIP2 conditions, Tab. 10
IIP2, high IIP2,h – 120 – dBm
Intermodulation Distortion IMD3 (1,2,3)
IIP3 IIP3 – 75 – dBm IIP3 conditions, Tab. 11
SV LTE Intermodulation (1,2,3)
IIP3,SVLTE IIP3,SV – 75 – dBm SV-LTE conditions, Tab. 12
1) Terminating Port Impedance: Z0=50 Ω
2) Supply Voltage: VDD = 2.3 −3.6 V
3) On application board without any matching components
Final Data Sheet 9 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
RF large signal parameters
Table 10: IIP2 conditions table
Band In-Band Frequency Blocker Frequency 1 Blocker Power 1 Blocker Frequency 2 Blocker Power 2
[MHz] [MHz] [dBm] [MHz] [dBm]
Band 1 Low 2140 1950 20 190 -15
Band 1 High 2140 1950 20 4090 -15
Band 5 Low 881.5 836.5 20 45 -15
Band 5 High 881.5 836.5 20 1718 -15
Table 11: IIP3 conditions table
Band In-Band Frequency Blocker Frequency 1 Blocker Power 1 Blocker Frequency 2 Blocker Power 2
[MHz] [MHz] [dBm] [MHz] [dBm]
Band 1 2140 1950 20 1760 -15
Band 5 881.5 836.5 20 791.5 -15
Table 12: SV-LTE conditions table
Band In-Band Frequency Blocker Frequency 1 Blocker Power 1 Blocker Frequency 2 Blocker Power 2
[MHz] [MHz] [dBm] [MHz] [dBm]
Band 5 872 827 23 872 14
Band 13 747 786 23 747 14
Band 20 878 833 23 2544 14
Final Data Sheet 10 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
MIPI RFFE Specification
6 MIPI RFFE Specification
All sequences are implemented according to the ’MIPI Alliance Specification for RF Front-End Control Interface’ document version 1.10 - 26.
July 2011.
Table 13: MIPI Features
Feature Supported Comment
Register write command sequence Yes
Register read command sequence Yes
Extended register write command sequence No Up to 4 Bytes
Extented register read command sequence No Up to 4 Bytes
Register 0 write command sequence Yes
Trigger function Yes Trigger assignment to each control register is supported
Programmable USID Yes
3 register command sequence and extended register command
sequence
Status Register Yes Register for debugging
Reset Yes By VIO, Power Mode and RFFE_STATUS
Group SID Yes
USID_Sel pin Yes External pin for changing USID:
1: Pin 5=SDATA and Pin 6=SCLK→1100,
2: Pin 5=SCLK and Pin 6=SDATA→1101
Full speed write Yes
Half speed read Yes
Full speed read Yes
Table 14: Startup Behavior
Feature State Comment
Power status LOW POWER The chip is in low power mode aer startup
Trigger function ENABLED
Trigger function is enabled aer startup. Trigger function can be disabled via
PM_TRIG register.
VTPmax
VTNmin
TSCLKIH TSCLKIL
Figure 4: Received clock signal constraints
Final Data Sheet 11 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
MIPI RFFE Specification
Table 15: MIPI RFFE Operating Timing
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
SCLK Frequency FSCLK 0.032 – 26 MHz Full speed
0.032 – 13 MHz Half speed
SCLK Period TSCLK 0.038 – 32 µs Full speed
0.077 – 32 µs Half speed
SCLK Low Period TSCLKIL 11.25 – – ns Full speed, see Fig. 4
24 – – ns Half speed, see Fig. 4
SCLK High Period TSCLKIH 11.25 – – ns Full speed, see Fig. 4
24 – – ns Half speed, see Fig. 4
SDATA Setup Time TS 1 – – ns Full speed, see Fig. 5
2 – – ns Half speed, see Fig. 5
SDATA Hold Time TH 5 – – ns Full speed, see Fig. 5
5 – – ns Half speed, see Fig. 5
SDATA Release Time TSDATAZ – – 10 ns Full speed, see Fig. 6
– – 18 ns Half speed, see Fig. 6
Time for Data Output TD – – 10.25 ns Full speed, see Fig. 7
– – 22 ns Half speed, see Fig. 7
SDATA Rise/Fall Time TSDATAOTR 2.1 – 6.5 ns Full speed, see Fig. 7
2.1 – 10 ns Half speed, see Fig. 7
VIO Rise Time TVIO-R 10 – 450 µs See Fig. 8
VIO Reset Time TVIO-RST 10 – – µs See Fig. 8
Reset Delay Time TSIGOL 0.12 – – µs See Fig. 8
Final Data Sheet 12 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
MIPI RFFE Specification
VTPmax
VTPmin
VTPmax
VTPmin
TSTHTH
SCLK
SDATA
TS
Figure 5: Bus active data receiver timing requirements
TSDATAZ
SCLK
SDATA
VOHmin
VOLmax
Bus Park Cycle
Signal driven
Signal not driven, pull down only
T is measured from SCLK V level for a device receiving SCLK and driving SDATA lines
SDATAZ TN
VTPmax
VTNmin
Figure 6: Bus park cycle timing
Final Data Sheet 13 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
MIPI RFFE Specification
VOHmin
VOLmax
VTPmax
VTPmin
TD
SCLK
SDATA
TSDATAOTR TSDATAOTR
TD
Figure 7: Bus active data transmission timing specification
Figure 8: Requirements for VIO-initiated reset
Final Data Sheet 14 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
MIPI RFFE Specification
Table 16: Register Mapping
Register
Address
Register Name Data
Bits
Function Description Default Broadcast_ID
Support
Trigger
Support
R/W
0x0000 REGISTER_0 7:0 MODE_CTRL RF Switch Control 00000000 No Yes R/W
0x001D PRODUCT_ID 7:0 PRODUCT_ID This is a read-only register. However, during
the programming of the USID a write com-
mand sequence is performed on this register,
even though the write does not change its
value.
00011100 No No R
0x001E MANUFACTURER_ID 7:0 MANUFACTURER_ID [7:0] This is a read-only register. However, during
the programming of the USID, a write com-
mand sequence is performed on this register,
even though the write does not change its
value.
00011010 No No R
0x001C PM_TRIG 7:6 PWR_MODE 00: Normal operation 10 Yes No R/W
01: Default settings (STARTUP)
10: Low power (LOW POWER)
11: Reserved
5 TRIGGER_MASK_2 If this bit is set, trigger 2 is disabled. When all
triggers disabled, if writing to a register that is
associated to trigger 2, the data goes directly
to the destination register.
0 No
4 TRIGGER_MASK_1 If this bit is set, trigger 1 is disabled. When all
triggers disabled, if writing to a register that is
associated to trigger 1, the data goes directly
to the destination register.
0 No
3 TRIGGER_MASK_0 If this bit is set, trigger 0 is disabled. When all
triggers disabled, if writing to a register that is
associated to trigger 0, the data goes directly
to the destination register.
0 No
2 TRIGGER_2 A write of a one to this bit loads trigger 2’s reg-
isters.
0 Yes
1 TRIGGER_1 A write of a one to this bit loads trigger 1’s reg-
isters.
0 Yes
0 TRIGGER_0 A write of a one to this bit loads trigger 0’s reg-
isters.
0 Yes
0x001F MAN_USID 7:6 SPARE These are read-only bits that are reserved and
yield a value of 0b00 at readback.
00 No No R/W
5:4 MANUFACTURER_ID [9:8] These bits are read-only. However, during the
programming of the USID, a write command
sequence is performed on this register even
though the write does not change its value.
01
3:0 USID Programmable USID. Performing a write to
this register using the described program-
ming sequences will program the USID in de-
vices supporting this feature. These bits store
the USID of the device.
See
Tab. 13
0x001A RFFE_STATUS 7 SOFTWARE RESET 0: Normal operation 0 No No R/W
1: Soware reset
6 COMMAND_FRAME_
PARITY_ERR
Command sequence received with parity er-
ror - discard command.
0 No No R
5 COMMAND_LENGTH_ERR Command length error 0
4 ADDRESS_FRAME_
PARITY_ERR
Address frame parity error = 1 0
3 DATA_FRAME_
PARITY_ERR
Data frame with parity error 0
2 READ_UNUSED_REG Read command to an invalid address 0
1 WRITE_UNUSED_REG Write command to an invalid address 0
0 BID_GID_ERR Read command with a BROADCAST_ID or
GROUP_SID
0
0x001B GROUP_SID 7:4 RESERVED 0000 No No R/W
3:0 GROUP_SID Group slave ID 0000
Final Data Sheet 15 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
MIPI RFFE Specification
Table 17: Switch MIPI Control Combinations (truth table)
REGISTER_0 – Switch control register
State Mode D7 D6 D5 D4 D3 D2 D1 D0
0 Isolation mode (open) 0 0 0 0 0 0 0 0
1 RF1 0 0 0 0 0 0 0 1
2 RF2 0 0 0 0 0 0 1 0
3 RF3 0 0 0 0 0 1 0 0
4 RF4 0 0 0 0 1 0 0 0
5 RF1||RF2 0 0 0 0 0 0 1 1
6 RF1||RF3 0 0 0 0 0 1 0 1
7 RF1||RF4 0 0 0 0 1 0 0 1
8 RF2||RF3 0 0 0 0 0 1 1 0
9 RF2||RF4 0 0 0 0 1 0 1 0
10 RF3||RF4 0 0 0 0 1 1 0 0
11 RF1||RF2||RF3 0 0 0 0 0 1 1 1
12 RF1||RF2||RF4 0 0 0 0 1 0 1 1
13 RF1||RF3||RF4 0 0 0 0 1 1 0 1
14 RF2||RF3||RF4 0 0 0 0 1 1 1 0
15 RF1||RF2||RF3||RF4 0 0 0 0 1 1 1 1
16 RFC short to GND x 1 x x x x x x
Final Data Sheet 16 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
Application Information
7 Application Information
Pin Configuration and Function
RFC
VDD GND
VIO
SCLK
2
3
4
9
8
7
6
1
5SDATA
10
USID
1101
RFC
RF4
RF2
VDD GND
VIO
SDATA
RF1
2
3
4
9
8
7
6
1
5SCLK
10
USID
1100
Default Configuration Swapping Configuration
RF3
RF4
RF2
RF1
RF3
Figure 9: BGSA141MN10 Pin Configuration - USID 1100 and USID 1101 (top view)
Table 18: Pin Definition and Function USID 1100
Pin No. Name Function
1 RF1 RF1 port
2 RF2 RF2 port
3 VDD Power Supply
4 VIO RFFE Power Supply
5 SDATA MIPI RFFE DATA
6 SCLK MIPI RFFE CLOCK
7 GND Ground
8 RF3 RF3 port
9 RF4 RF port
10 RFC Common RF port
Table 19: Pin Definition and Function - USID 1101
Pin No. Name Function
1 RF1 RF1 port
2 RF2 RF2 port
3 VDD Power Supply
4 VIO RFFE Power Supply
5 SCLK MIPI RFFE CLOCK
6 SDATA MIPI RFFE DATA
7 GND Ground
8 RF3 RF3 port
9 RF4 RF port
10 RFC Common RF port
Final Data Sheet 17 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
Package Information
8 Package Information
TSNP-10-3-PO V02
Pin 1 marking
Bottom viewTop view
1.1 ±0.05
0.2 ±0.05
0.375 ±0.025
0.2 ±0.05
1
2
3
4
5
10
9
8
7
6
0.02 MAX.
10x
0.1 B
0.1
10x
A
0.4
0.4
3 x 0.4 = 1.2
0.8
A
1.5±0.05
B
Figure 10: TSNP-10-3 Package Outline (top, side and bottom views)
TSNP-10-3-MK V02
Pin 1 marking
M5
Type code
Date code (YW)
Figure 11: Marking Specification (top view): Date code digits Y and W defined in Table 20/21
Final Data Sheet 18 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
Package Information
Table 20: Year date code marking - digit "Y"
Year "Y" Year "Y" Year "Y"
2000 0 2010 0 2020 0
2001 1 2011 1 2021 1
2002 2 2012 2 2022 2
2003 3 2013 3 2023 3
2004 4 2014 4 2024 4
2005 5 2015 5 2025 5
2006 6 2016 6 2026 6
2007 7 2017 7 2027 7
2008 8 2018 8 2028 8
2009 9 2019 9 2029 9
Table 21: Week date code marking - digit "W"
Week "W" Week "W" Week "W" Week "W" Week "W"
1 A 12 N 23 4 34 h 45 v
2 B 13 P 24 5 35 j 46 x
3 C 14 Q 25 6 36 k 47 y
4 D 15 R 26 7 37 l 48 z
5 E 16 S 27 a 38 n 49 8
6 F 17 T 28 b 39 p 50 9
7 G 18 U 29 c 40 q 51 2
8 H 19 V 30 d 41 r 52 3
9 J 20 W 31 e 42 s
10 K 21 Y 32 f 43 t
11 L 22 Z 33 g 44 u
Final Data Sheet 19 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
Package Information
TSNP-10-3-FP V01
Stencil apertures
Copper Solder mask
0.475
0.4
10x 0.25
10x 0.25
0.4
0.4
10x 0.25
0.2
0.4
0.4
0.4
0.475
Optional solder mask dam
Figure 12: Footprint Recommendation
40.5
Pin 1
marking
1.3
1.7
8
TSNP-10-3-TP V01
Figure 13: TSNP-10-3 Carrier Tape
Final Data Sheet 20 Revision 2.0
2017-06-12
BGSA141MN10
Low Resistance Antenna Aperture Switch
Revision History
Page or Item Subjects (major changes since previous revision)
Revision 2.0, 2017-06-12
Release as final version
Final Data Sheet 21 Revision 2.0
2017-06-12
Trademarks of Infineon Technologies AG
µ
HVIC
TM
,
µ
IPM
TM
,
µ
PFC
TM
, AU-ConvertIR
TM
, AURIX
TM
, C166
TM
, CanPAK
TM
, CIPOS
TM
, CIPURSE
TM
, CoolDP
TM
, CoolGaN
TM
, COOLiR
TM
, CoolMOS
TM
, CoolSET
TM
,
CoolSiC
TM
, DAVE
TM
, DI-POL
TM
, DirectFET
TM
, DrBlade
TM
, EasyPIM
TM
, EconoBRIDGE
TM
, EconoDUAL
TM
, EconoPACK
TM
, EconoPIM
TM
, EiceDRIVER
TM
, eupec
TM
,
FCOS
TM
, GaNpowIR
TM
, HEXFET
TM
, HITFET
TM
, HybridPACK
TM
, iMOTION
TM
, IRAM
TM
, ISOFACE
TM
, IsoPACK
TM
, LEDrivIR
TM
, LITIX
TM
, MIPAQ
TM
, ModSTACK
TM
,
my-d
TM
, NovalithIC
TM
, OPTIGA
TM
, OptiMOS
TM
, ORIGA
TM
, PowIRaudio
TM
, PowIRStage
TM
, PrimePACK
TM
, PrimeSTACK
TM
, PROFET
TM
, PRO-SIL
TM
, RASIC
TM
,
REAL3TM, SmartLEWISTM, SOLID FLASHTM, SPOCTM, StrongIRFETTM, SupIRBuckTM, TEMPFETTM, TRENCHSTOPTM, TriCoreTM, UHVICTM, XHPTM, XMCTM.
Trademarks updated November 2015
Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2017-06-12
Published by
Infineon Technologies AG
81726 Munich, Germany
c
2017 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
IMPORTANT NOTICE
The information given in this document shall in no event
be regarded as a guarantee of conditions or characteris-
tics ("Beschaenheitsgarantie"). With respect to any ex-
amples, hints or any typical values stated herein and/or
any information regarding the application of the prod-
uct, Infineon Technologies hereby disclaims any and
all warranties and liabilities of any kind, including with-
out limitation warranties of non-infringement of intel-
lectual property rights of any third party. In addition,
any information given in this document is subject to
customer’s compliance with its obligations stated in
this document and any applicable legal requirements,
norms and standards concerning customer’s products
and any use of the product of Infineon Technologies
in customer’s applications. The data contained in this
document is exclusively intended for technically trained
sta. It is the responsibility of customer’s technical de-
partments to evaluate the suitability of the product for
the intended application and the completeness of the
product information given in this document with re-
spect to such application.
For further information on technology, delivery terms
and conditions and prices, please contact the nearest
Infineon Technologies Oice (www.infineon.com).
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon Tech-
nologies oice.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by autho-
rized representatives of Infineon Technologies, Infineon
Technologies products may not be used in any appli-
cations where a failure of the product or any conse-
quences of the use thereof can reasonably be expected
to result in personal injury.