LMC6024IM - Texas Instruments High-Performance Analog

LMC6024

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SNOS621D –AUGUST 2000–REVISED MARCH 2013

LMC6024 Low Power CMOS Quad Operational Amplifier

Check for Samples: LMC6024

1FEATURES DESCRIPTION

The LMC6024 is a CMOS quad operational amplifier

2• Specified for 100 kΩand 5 kΩLoads which can operate from either a single supply or dual

• High Voltage Gain 120 dB supplies. Its performance features include an input

• Low Offset Voltage Drift 2.5 μV/°C common-mode range that reaches V−, low input bias

current and voltage gain (into 100 kΩand 5 kΩloads)

• Ultra Low Input Bias Vurrent 40 fA that is equal to or better than widely accepted bipolar

• Input Common-mode Range Includes V−equivalents, while the power supply requirement is

• Operating Range from +5V to +15V Supply less than 1 mW.

• Low Distortion 0.01% at 1 kHz This chip is built with Texas Instrument's advanced

• Slew Rate 0.11 V/μsDouble-Poly Silicon-Gate CMOS process.

• Micropower Operation 1 mW See the LMC6022 datasheet for a CMOS dual

operational amplifier with these same features.

APPLICATIONS

• High-impedance Buffer or Preamplifier

• Current-to-voltage Converter

• Long-term Integrator

• Sample-and-hold Circuit

• Peak Detector

• Medical Instrumentation

• Industrial Controls

Connection Diagram

Top View

Figure 1. 14-Pin DIP and SOIC Package

See Package Number D0014A

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LMC6024

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Absolute Maximum Ratings (1)(2)

Differential Input Voltage ±Supply Voltage

Supply Voltage (V+−V−) 16V

Lead Temperature Soldering, 10 sec. 260°C

Storage Temperature Range −65°C to +150°C

Voltage at Output/Input Pin (V+) + 0.3V, (V−)−0.3V

Current at Input Pin ±5 mA

Current at Output Pin ±18 mA

Current at Power Supply Pin 35 mA

Output Short Circuit to V+See(3)

Output Short Circuit to V−See(4)

Junction Temperature 150°C

ESD Tolerance(5) 1000V

Power Dissipation See(6)

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings indicate conditions for

which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test

conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) Do not connect output to V+when V+is greater than 13V or reliability may be adversely affected.

(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or

multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30

mA over long term may adversly affect reliability.

(5) Human body model, 100 pF discharge through a 1.5 kΩresistor.

(6) The maximum power dissipation is a function of TJ(max),θJA, and TA. The maximum allowable power dissipation at any ambient

temperature is PD= (TJ(max) −TA)/θJA.

Operating Ratings

Temperature Range −40°C ≤TJ≤+85°C

Supply Voltage Range 4.75V to 15.5V

Power Dissipation See(1)

Thermal Resistance (θJA)(2) 14-Pin DIP 85°C/W

14-Pin SOIC 115°C/W

(1) For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD= (TJ−TA)/θJA.

(2) All numbers apply for packages soldered directly into a PC board.

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DC Electrical Characteristics

The following specifications apply for V+= 5V, V−= 0V, VCM = 1.5V, VO= 2.5V, and RL= 1M unless otherwise noted.

Boldface limits apply at the temperature extremes; all other limits TJ= 25°C. LMC6024I

Parameter Test Conditions Typical(1) Units

Limit(2)

VOS Input Offset Voltage 1 9 mV

11 Max

ΔVOS/ΔT Input Offset Voltage Average 2.5 μV/°C

Drift

IBInput Bias Current 0.04 pA

200 Max

IOS Input Offset Current 0.01 pA

100 Max

RIN Input Resistance >1 TeraΩ

CMRR Common Mode Rejection 0V ≤VCM ≤12V 83 63 dB

Ratio Min

V+= 15V 61

+PSRR Positive Power Supply 5V ≤V+≤15V 83 63 dB

Rejection Ratio Min

−PSRR Negative Power Supply 0V ≤V−≤ −10V 94 74 dB

Rejection Ratio Min

VCM Input Common-Mode Voltage V+= 5V and 15V −0.4 −0.1 V

Range For CMRR ≥50 DB Max

V+−1.9 V+−2.3 V

Min

V+−2.5

AVLarge Signal Voltage Gain RL= 100 kΩ(3) Sourcing 1000 200 V/mV

Min

100

Sinking 500 90 V/mV

Min

RL= 5 kΩ(3) Sourcing 1000 100 V/mV

Min

Sinking 250 50 V/mV

Min

VOOutput Voltage Swing V+= 5V 4.987 4.40 V

RL= 100 kΩto 2.5V Min

4.43

0.004 0.06 V

Max

0.09

V+= 5V 4.940 4.20 V

RL= 5 kΩto 2.5V Min

4.00

0.040 0.25 V

Max

0.35

V+= 15V 14.970 14.00 V

RL= 100 kΩto 7.5V Min

13.90

0.007 0.06 V

Max

0.09

V+= 15V 14.840 13.70 V

RL= 5 kΩto 7.5V Min

13.50

0.110 0.32 V

Max

0.40

(1) Typical values represent the most likely parametric norm.

(2) All limits are guaranteed by testing or correlation.

(3) V+= 15V, VCM = 7.5V, and RLconnected to 7.5V. For Sourcing tests, 7.5V ≤VO≤11.5V. For Sinking tests, 2.5V ≤VO≤7.5V.

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DC Electrical Characteristics (continued)

The following specifications apply for V+= 5V, V−= 0V, VCM = 1.5V, VO= 2.5V, and RL= 1M unless otherwise noted.

Boldface limits apply at the temperature extremes; all other limits TJ= 25°C. LMC6024I

Parameter Test Conditions Typical(1) Units

Limit(2)

IOOutput Current V+= 5V 22 13 mA

Sourcing, VO= 0V Min

Sinking VO= 5V (4) 21 13 mA

Min

V+= 15V 40 23 mA

Sourcing, VO= 0V Min

Sinking, VO= 13V (5) 39 23 mA

Min

ISSupply Current All Four Amplifiers 160 240 μA

VO= 1.5V Max

280

(4) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or

multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30

mA over long term may adversly affect reliability.

(5) Do not connect output to V+when V+is greater than 13V or reliability may be adversely affected.

AC Electrical Characteristics

The following specifications apply for V+= 5V, V−= 0V, VCM = 1.5V, VO= 2.5V, and RL= 1M unless otherwise noted.

Boldface limits apply at the temperature extremes; all other limits TJ= 25°C. LMC6024I

Parameter Test Conditions Typical(1) Units

Limit(2)

SR Slew Rate See(3) 0.11 0.05 V/μs

Min

0.03

GBW Gain-Bandwidth Product 0.35 MHz

θMPhase Margin 50 Deg

GMGain Margin 17 dB

Amp-to-Amp Isolation See(4) 130 dB

enInput-Referred Voltage Noise F = 1 kHz 42 nV/√Hz

inInput-Referred Current Noise F = 1 kHz 0.0002 pA/√Hz

(1) Typical values represent the most likely parametric norm.

(2) All limits are guaranteed by testing or correlation.

(3) V+= 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.

(4) Input referred, V+= 15V and RL= 100 kΩconnected to 7.5V. Each amp excited in turn with 1 kHz to produce VO= 13 VPP.

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Typical Performance Characteristics

VS= ±7.5V, TA= 25°C unless otherwise specified

Supply Current Input Bias Current

vs Supply Voltage vs Temperature

Figure 2. Figure 3.

Common-Mode Voltage

Range

vs Output Characteristics

Temperature Current Sinking

Figure 4. Figure 5.

Output Characteristics Input Voltage Noise

Current Sourcing vs Frequency

Figure 6. Figure 7.

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Typical Performance Characteristics (continued)

VS= ±7.5V, TA= 25°C unless otherwise specified CMRR

Crosstalk Rejection vs

vs Frequency Frequency

Figure 8. Figure 9.

Power Supply Rejection

CMRR Ratio

vs vs

Temperature Frequency

Figure 10. Figure 11.

Open-Loop Voltage

Gain

vs Open-Loop

Temperature Frequency Response

Figure 12. Figure 13.

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Typical Performance Characteristics (continued)

VS= ±7.5V, TA= 25°C unless otherwise specified Gain and Phase

Responses

Gain and Phase Responses vs

vs Load Capacitance Temperature

Figure 14. Figure 15.

Gain Error

(VOS

vs Non-Inverting Slew Rate

VOUT) vs Temperature

Figure 16. Figure 17.

Large-Signal Pulse

Inverting Slew Rate Non-Inverting Response

vs Temperature (AV= +1)

Figure 18. Figure 19.

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Typical Performance Characteristics (continued)

VS= ±7.5V, TA= 25°C unless otherwise specified

Non-Inverting Small

Signal Pulse Response Inverting Large-Signal

(AV= +1) Pulse Response

Figure 20. Figure 21.

Stability

Inverting Small-Signal vs

Pulse Response Capacitive Load

Avoid resistive loads of less than 500Ω, as they may cause instability.

Figure 22. Figure 23.

Stability

Capacitive Load

Figure 24.

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APPLICATION HINTS

AMPLIFIER TOPOLOGY

The topology chosen for the LMC6024 is unconventional (compared to general-purpose op amps) in that the

traditional unity-gain buffer output stage is not used; instead, the output is taken directly from the output of the

integrator, to allow rail-to-rail output swing. Since the buffer traditionally delivers the power to the load, while

maintaining high op amp gain and stability, and must withstand shorts to either rail, these tasks now fall to the

integrator.

As a result of these demands, the integrator is a compound affair with an embedded gain stage that is doubly fed

forward (via Cfand Cff) by a dedicated unity-gain compensation driver. In addition, the output portion of the

integrator is a push-pull configuration for delivering heavy loads. While sinking current the whole amplifier path

consists of three gain stages with one stage fed forward, whereas while sourcing the path contains four gain

stages with two fed forward.

Figure 25. LMC6024 Circuit Topology (Each Amplifier)

The large signal voltage gain while sourcing is comparable to traditional bipolar op amps, for load resistance of at

least 5 kΩ. The gain while sinking is higher than most CMOS op amps, due to the additional gain stage;

however, when driving load resistance of 5 kΩor less, the gain will be reduced as indicated in the Electrical

Characterisitics. The op amp can drive load resistance as low as 500Ωwithout instability.

COMPENSATING INPUT CAPACITANCE

Refer to the LMC660 or LMC662 datasheets to determine whether or not a feedback capacitor will be necessary

for compensation and what the value of that capacitor would be.

CAPACITIVE LOAD TOLERANCE

Like many other op amps, the LMC6024 may oscillate when its applied load appears capacitive. The threshold of

oscillation varies both with load and circuit gain. The configuration most sensitive to oscillation is a unity-gain

follower. See the Typical Performance Characteristics.

The load capacitance interacts with the op amp's output resistance to create an additional pole. If this pole

frequency is sufficiently low, it will degrade the op amp's phase margin so that the amplifier is no longer stable at

low gains. The addition of a small resistor (50Ωto 100Ω) in series with the op amp's output, and a capacitor (5

pF to 10 pF) from inverting input to output pins, returns the phase margin to a safe value without interfering with

lower-frequency circuit operation. Thus, larger values of capacitance can be tolerated without oscillation. Note

that in all cases, the output will ring heavily when the load capcitance is near the threshold for oscillation.

Figure 26. Rx, Cx Improve Capacitive Load Tolerance

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Capacitive load driving capability is enhanced by using a pull up resistor to V+(Figure 27). Typically a pull up

resistor conducting 50 μA or more will significantly improve capacitive load responses. The value of the pull up

resistor must be determined based on the current sinking capability of the amplifier with respect to the desired

output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see DC Electrical

Characteristics).

Figure 27. Compensating for Large

Capacitive Loads with a Pull Up Resistor

PRINTED-CIRCUIT-BOARD LAYOUT

FOR HIGH-IMPEDANCE WORK

It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires

special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the

LMC6024, typically less than 0.04 pA, it is essential to have an excellent layout. Fortunately, the techniques for

obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board,

even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or

contamination, the surface leakage will be appreciable.

To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6024's inputs

and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp's

inputs. See Figure 28. To have a significant effect, guard rings should be placed on both the top and bottom of

the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier

inputs, since no leakage current can flow between two points at the same potential. For example, a PC board

trace-to-pad resistance of 1012 ohms, which is normally considered a very large resistance, could leak 5 pA if the

trace were a 5V bus adjacent to the pad of an input. This would cause a 100 times degradation from the

LMC6024's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a

resistance of 1011 ohms would cause only 0.05 pA of leakage current, or perhaps a minor (2:1) degradation of

the amplifier's performance. See Figure 28,Figure 30, and Figure 31 for typical connections of guard rings for

standard op-amp configurations. If both inputs are active and at high impedance, the guard can be tied to ground

and still provide some protection; see Figure 32.

Figure 28. Example of Guard Ring in P.C. Board Layout (Using the LMC6024)

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Guard Ring Connections

Figure 29. Inverting Amplifier Guard Ring Figure 30. Non-Inverting Amplifier Guard Ring

Connections Connections

Figure 31. Follower Guard Ring Connections Figure 32. Howland Current Pump Guard Ring

Connections

The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few

circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the

amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an

excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but

the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 33.

(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.)

Figure 33. Air Wiring

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BIAS CURRENT TESTING

The test method of Figure 34 is appropriate for bench-testing bias current with reasonable accuracy. To

understand its operation, first close switch S2 momentarily. When S2 is opened, then

(1)

Figure 34. Simple Input Bias Current Test Circuit

A suitable capacitor for C2 would be a 5 pF or 10 pF silver mica, NPO ceramic, or air-dielectric. When

determining the magnitude of I−, the leakage of the capacitor and socket must be taken into account. Switch S2

should be left shorted most of the time, or else the dielectric absorption of the capacitor C2 could cause errors.

Similarly, if S1 is shorted momentarily (while leaving S2 shorted)

(2)

where Cxis the stray capacitance at the +input.

Typical Single-Supply Applications

(V+= 5.0 VDC)

A 5V bias on the photodiode can cut its capacitance by a factor of 2 or 3, leading to improved response and lower

noise. However, this bias on the photodiode will cause photodiode leakage (also known as its dark current).

Figure 35. Photodiode Current-to-Voltage Converter

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(V+= 5.0 VDC)

Figure 36.

(Upper limit of output range dictated by input common-mode range; lower limit dictated by minimum current

requirement of LM385.)

Figure 37. Micropower Current Source

Figure 38. Low-Leakage Sample-and-Hold

If R1 = R5, R3 = R6, and R4 = R7;

Then

∴AV≈100 for circuit shown.

For good CMRR over temperature, low drift resistors should be used. Matching of R3 to R6 and R4 to R7 affects

CMRR. Gain may be adjusted through R2. CMRR may be adjusted through R7.

Figure 39. Instrumentation Amplifier

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(V+= 5.0 VDC)

fO= 10 Hz

Q = 2.1

Gain = −8.8

Figure 40. 10 Hz Bandpass Filter

fc= 10 Hz

d = 0.895

Gain = 1

Figure 41. 10 Hz High-Pass Filter (2 dB Dip)

Figure 42. 1 Hz Low-Pass Filter (Maximally Flat, Dual Supply Only)

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(V+= 5.0 VDC)

Gain = −46.8

Output offset voltage reduced to the

level of the input offset voltage of

the bottom amplifier (typically 1 mV),

referred to VBIAS.

Figure 43. High Gain Amplifier with Offset Voltage Reduction

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REVISION HISTORY

Changes from Revision C (March 2013) to Revision D Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 15

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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMC6024IM/NOPB ACTIVE SOIC D 14 55 Green (RoHS

& no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 85 LMC6024IM

LMC6024IMX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 85 LMC6024IM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

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Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMC6024IMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMC6024IMX/NOPB SOIC D 14 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

Pack Materials-Page 2

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