IDT5962-8866507ZA - Integrated Device Technology, Inc.

JUNE 2000

DSC 2746/11

HIGH SPEED

2K X 16 DUAL-PORT

SRAM

IDT7133SA/LA

IDT7143SA/LA

Features

◆◆

◆High-speed access

– Military: 25/35/45/55/70/90ns (max.)

– Industrial: 25/35/55ns (max.)

– Commercial: 20/25/35/45/55/70/90ns (max.)

◆◆

◆Low-power operation

– IDT7133/43SA

Active: 1150mW (typ.)

Standby: 5mW (typ.)

– IDT7133/43LA

Active: 1050mW (typ.)

Standby: 1mW (typ.)

◆◆

◆Versatile control for write: separate write control for lower

and upper byte of each port

◆◆

◆MASTER IDT7133 easily expands data bus width to 32 bits

or more using SLAVE IDT7143

◆◆

◆On-chip port arbitration logic (IDT7133 only)

Functional Block Diagram

NOTE:

1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor.

IDT7143 (SLAVE): BUSY is input.

◆◆

◆BUSY output flag on IDT7133; BUSY input on IDT7143

◆◆

◆Fully asynchronous operation from either port

◆◆

◆Battery backup operation–2V data retention

◆◆

◆TTL-compatible; single 5V (±10%) power supply

◆◆

◆Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-

pin TQFP

◆◆

◆Military product compliant to MIL-PRF-38535 QML

◆◆

◆Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Description

The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs.

The IDT7133 is designed to be used as a stand-alone 16-bit Dual-Port

RAM or as a “MASTER” Dual-Port RAM together with the IDT7143

“SLAVE” Dual-Port in 32-bit-or-more word width systems. Using the

IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider

I/O

CONTROL

MEMORY

ARRAY

ARBITRATION

LOGIC

(IDT7133 ONLY)

R/WLUB

CEL

R/WLLB

OEL

I/O0L - I/O7L

BUSYL

A0L

CEL

R/WRUB

CER

R/WRLB

OER

I/O8R -I/O

15R

I/O0R -I/O7R

BUSYR(1)

A0R

CER

2746 drw 01

A10L ADDRESS

DECODER

A10R

I/O

CONTROL

ADDRESS

DECODER

11 11

(1)

I/O8L -I/O

15L

6.42

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges

2746 drw 02

16 IDT7133/43

J68-1 / F68-1(4)

68-Pin PLCC/Flatpack

Top View(5)

INDEX

98765432

68 67 66 65 64 63 62 61

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

A6L

A5L

A4L

A3L

A2L

A1L

A0L

A0R

A1R

A2R

A3R

A4R

A5R

BUSYL

BUSYR

CEL

CER

I/O

10L

I/O

11L

I/O

13L

I/O

14L

I/O

15L

(1)

I/O

(1)

10L

R/W

LLB

I/O

10R

I/O

12R

I/O

13R

I/O

14R

I/O

15R

I/O

10R

GND

(2)

R/W

RLB

R/W

RUB

I/O

11R

I/O

12L

GND

(2)

R/W

LUB

Pin Configurations(1,2,3)

memory system applications results in full-speed, error-free operation

without the need for additional discrete logic.

Both devices provide two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access

for reads or writes to any location in memory. An automatic power

down feature, controlled by CE, permits the on-chip circuitry of each

port to enter a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology, these

devices typically operate on only 1,150mW of power. Low-power (LA)

versions offer battery backup data retention capability, with each port

typically consuming 200µW for a 2V battery.

The IDT7133/7143 devices have identical pinouts. Each is packed

in a 68-pin ceramic PGA, 68-pin flatpack, 68-pin PLCC and 100-pin

TQFP. Military grade product is manufactured in compliance with the

latest revision of MIL-PRF-38535 QML, making it ideally suited to

military temperature applications demanding the highest level of

performance and reliability.

NOTES:

1. Both VCC pins must be connected to the power supply to ensure reliable

operation.

2. Both GND pins must be connected to the ground supply to ensure reliable

operation.

3. J68-Package body is approximately 0.95 in x 0.95 in x 0.17 in.

F68-Package body is approximately 1.18 in x 1.18 in x 0.16 in.

PN100-Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

Index

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100999897969594939291908988878685848382818079787776

IDT7133/43PF

PN100-1(4)

100-Pin TQFP

Top View(5)

N/C

I/O10L

I/O11L

I/O12L

I/O13L

GND

I/O14L

I/O15L

VCC

GND

I/O0R

I/O1R

I/O2R

I/O3R

VCC

I/O4R

I/O5R

I/O6R

N/C

2746 drw 03

N/C

A5L

A4L

A3L

A2L

A1L

A0L

N/C

GND

N/C

BUSYR

N/C

A0R

N/C

BUSYL

A1R

A2R

A3R

A4R

I/O9L

I/O8L

I/O7L

I/O6L

I/O5L

I/O4L

I/O3L

I/O2L

GND

I/O1L

I/O0L

OEL

VCC

R/W

LLB

CEL

R/W

LUB

N/C

A10L

A9L

A8L

A7L

A6L

I/O7R

I/O8R

I/O9R

I/O10R

I/O11R

I/O12R

I/O13R

I/O14R

GND

I/O15R

R/W

RLB

GND

N/C

A10R

A9R

A8R

A7R

A6R

A5R

N/C

N/CN/C

R/W

RUB

6.42

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges

Pin Configurations(1,2,3) (con't.)

NOTES:

1. Both V CC pins must be connected to the power supply to ensure reliable operation.

2. Both GND pins must be connected to the ground supply to ensure reliable operation.

3. Package body is approximately 1.18 in x 1.18 in x 0.16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

Pin Names

2746drw04

I/O0L

VCC(1)

A10L A9L

A8L A7L

A6L A5L

A4L

A3L

I/O1L

I/O2L

I/O3L

I/O4L

I/O5L

I/O6L

I/O7L

I/O8L I/O9L

I/O10L

I/O11L

I/O12L

I/O13L

I/O14L

I/O15L

VCC(1)

GND(2)

I/O0R

I/O1R

I/O2R

I/O3R

I/O4R

I/O5R

I/O6R I/O7R

I/O8R I/O9R

I/O10R I/O11R

I/O12R I/O13R

I/O14R I/O15R

A2L

A1L

A0L

R/WLUB

R/WLLB OEL

A2R

A3R

A4R

A5R A6R

A7R

A8R

A9R

A10R

R/WRLB

R/WRUB

OER

GND(2)

BUSYL

BUSYR

CEL

CER

50 48 46 44 42 40 38 36

A0R

A1R

52 49 47 45 43 41 39 37 3553 34

5455

5657

5859

6061

6263

6465

6667

168

20 21

22 23

24 25

26 27

28 29

30 31

32 33

IDT7133/43G

GU68-1(4)

68-Pin PGA

Top View(5)

Pin 1

Designator ABCDEFGHJKL

Left Port Right Port Names

LCE

RChip Enab le

R/WLUB R/WRUB Up p er B y te Re ad / Wri te E nabl e

R/WLLB R/WRLB Lo we r B yte Re ad /Write Enab le

OELOEROutput Enable

A0L - A10L A0R - A10R Address

I/O0L - I/ O15L I/O0R - I/O15R Data Input/ Outp ut

BUSYLBUSYRBusy Flag

VCC Power

GND Ground

2746 tbl 01

6.42

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges

Capacitance (TA = +25°C, f = 1.0mhz)

Recommended DC Operating

Conditions

Maximum Operating

Temperature and Supply Voltage(1,2)

Absolute Maximum Ratings(1)

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (Either port, VCC = 5.0V ± 10%)

NOTE:

1. At Vcc < 2.0V, input leakages are undefined.

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.

NOTES:

1. This parameter is determined by device characterization but is not production

tested.

2. 3dV references the interpolated capacitance when the input and output switch from

0V to 3V or from 3V to 0V.

NOTES:

1. This is the parameter TA. This is the "instant on" case temperature.

NOTES:

1. VIL (min.) = -1.5V for pulse width less than 10ns.

2. VTERM must not exceed Vcc + 10%.

Symbol Rating Commercial

& I ndustrial Military Unit

VTERM(2) Terminal Voltage

with Res pe c t

to GND

-0.5 to +7.0 -0.5 to +7.0 V

TBIAS Temperature

Under Bias -55 to +125 -65 to +135 oC

TSTG Storage

Temperature -65 to +150 -65 to +150 oC

PT(3) Power

Dissipation 2.0 2.0 W

IOUT DC O ut p ut

Current 50 50 mA

2746 tbl 02

Grade Ambient

Temperature GND Vcc

Military -55OC to +125OC0V 5.0V

+ 10%

Commercial 0OC to +70OC0V5.0V

+ 10%

Industrial -40OC to +85OC0V 5.0V

+ 10%

2746 tbl 04

Symbol Parameter(1) Conditions(2) Max. Unit

CIN Input Capac itance VIN = 3dV 11 pF

COUT Outp ut Cap aci tance VOUT = 3dV 11 pF

2746 tbl 03

Symbol Parameter Min. Typ. Max. Unit

VCC Sup ply Voltage 4.5 5.0 5.5 V

GND Ground 0 0 0 V

VIH Input High Voltage 2.2 ____ 6.0(2) V

VIL Inp ut Lo w Vo ltag e -0.5(1) ____ 0.8 V

2 7 46 tb l 05

Symbol Parameter Test Conditions

7133SA

7143SA 7133LA

7143LA

UnitMin. Max. Min. Max.

|ILI| Inp ut Leak ag e Curre nt(1) VCC = 5. 5V, VIN = 0V to VCC ___ 10 ___ 5µA

|ILO| Outp ut Le akag e Current CE = VIH, VOUT = 0V to VCC ___ 10 ___ 5µA

VOL Outp ut Lo w Vo ltag e (I/ O0-I/O15)I

OL = 4mA ___ 0.4 ___ 0.4 V

VOL Op en Drain Outp ut Low Vo ltage

(BUSY

)IOL = 16mA ___ 0.5 ___ 0.5 V

VOH Outp ut Hig h Vo ltag e IOH = -4mA 2.4 ___ 2.4 ___ V

2746 tbl 06

6.42

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges

NOTES:

1. VCC = 5V, TA = +25°C for Typ., and are not production tested. ICCDC = 180mA (typ.)

2. 'X' in part number indicates power rating (SA or LA)

3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions" of input levels of

GND to 3V.

4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

DC Electrical Characteristics Operating

Temperature and Supply Voltage Range(2) (VCC = 5.0V ± 10%)

7133X20

7143X20

Com'l Only

7133X25

7143X25

Com'l, Ind

& Mili tary

7133X35

7143X35

Com'l, Ind

& Mili tary

Sym bol Parameter Test Condi tion Versi on Typ. (1) Max. Typ.(1) Max. Typ.(1) Max. Unit

ICC Dy na mi c Op e rating

Current

(Both Ports Active )

CE = VIL, Outp uts Disab led

f = fMAX(3)

COM'L S

L250

230 310

280 250

230 300

270 240

210 295

250 mA

MIL &

IND S

L____

____

____ 250

230 330

300 240

220 325

295

ISB1 Standby Current

(Bo th Po rts - TTL

Le vel Inputs)

L and CER = VIH

f = fMAX(3)

COM'L S

L25

25 80

70 25

25 80

70 25

25 70

60 mA

MIL &

IND S

L____

____

____ 25

25 90

80 25

25 75

ISB2 Standby Current

(One Po rt - TTL

Le vel Inputs)

"A" = VIL and CE"B" = VIH(4)

f=fMAX(3)

Active Port Outputs Disabled

COM'L S

L140

120 200

180 140

100 200

170 120

100 180

160 mA

MIL &

IND S

L____

____

____ 140

100 230

190 120

100 200

180

ISB3 Full Stand by Curre nt

(Bo th Po rts -

CM OS L e v e l Inp u ts )

Bo th Ports CEL and

R > VCC - 0.2V

VIN > VCC - 0.2V o r

VIN < 0.2 V, f = 0 (4)

COM'L S

L1.0

0.2 15

51.0

0.2 15

41.0

0.2 15

4mA

MIL &

IND S

L____

____

____ 1.0

0.2 30

10 1.0

0.2 30

ISB4 Full Stand by Curre nt

(One Po rt -

CM OS L e v e l Inp u ts )

"A" < 0.2V and

"B" > VCC - 0.2V(5)

VIN > VCC - 0.2V o r V IN < 0.2V

Active Port Outputs Disabled

f = fMAX(3)

COM'L S

L140

120 190

170 140

120 190

170 120

100 170

150 mA

MIL &

IND S

L____

____

____ 140

120 220

200 120

100 190

170

2 746 tbl 07 a

7133X45

7143X45

Co m' l &

Military

7133X55

7143X55

Com'l, Ind

& Mili tary

7133X70/90

7143X70/90

Co m' l &

Military

Sym bol Parameter Test Condi ti on Versi on Typ. (1) Max. Typ.(1) Max. Typ.(1) Max. Unit

ICC Dy nam ic Op e r atin g

Current

(Bo th Po rts Ac tiv e )

CE = VIL, Outputs Disabled

f = fMAX(3)

COM'L S

L230

210 290

250 230

210 285

250 230

210 280

250 mA

MIL &

IND S

L230

210 320

290 230

210 315

285 230

210 310

280

ISB1 Stand by Curre nt

(Bo th Po rts - TTL

Le vel Inp uts)

CEL and CER = VIH

f = fMAX(3)

COM'L S

L25

25 75

65 25

25 70

60 25

25 70

60 mA

MIL &

IND S

L25

25 80

70 25

25 80

70 25

25 75

ISB2 S tand b y Current

(One Po rt - TTL

Le vel Inp uts)

CE"A" = VIL and CE"B" = VIH(4)

f=fMAX(3)

Active Port Outputs Disabled

COM'L S

L120

100 190

170 120

100 180

160 120

100 180

160 mA

MIL &

IND S

L120

100 210

190 120

100 210

190 120

100 200

180

ISB3 Full Stand by Current

(Bo th Po rts -

CMOS Lev e l Inp uts)

Bo th Ports CEL and

CER > VCC - 0.2V

VIN > VCC - 0.2V o r

VIN < 0.2 V, f = 0(4)

COM'L S

L1.0

0.2 15

41.0

0.2 15

41.0

0.2 15

4mA

MIL &

IND S

L1.0

0.2 30

10 1.0

0.2 30

10 1.0

0.2 30

ISB4 Full Stand by Current

(One Po rt -

CMOS Lev e l Inp uts)

CE"A" < 0.2V and

CE"B" > VCC - 0.2V(5)

VIN > VCC - 0.2V or V IN < 0.2V

Active Port Outputs Disabled

f = fMAX(3)

COM'L S

L120

100 180

160 120

100 170

150 120

100 170

150 mA

MIL &

IND S

L120

100 200

180 120

100 200

180 120

100 190

170

2746 tbl 07b

6.42

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges

2746 drw 06

DATAOUT

775Ω

1250Ω

30pF

DATAOUT

775Ω

1250Ω

5pF*

BUSY

270Ω

30pF

Data Retention Waveform

AC Test Conditions

Data Retention Characteristics

(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V

NOTES:

1. Vcc = 2V, TA = +25°C, and are not production tested.

2. tRC = Read Cycle Time

3. This parameter is guaranteed by device characterization but is not production tested.

Figure 2. Output Load

(for tLZ, tHZ, tWZ, tOW)

*Including scope and jig

Figure 1. AC Output Test Load

Figure 3. BUSY Output Load

(IDT7133 only)

7133LA/7143LA

Symbol Parameter Test Condition Min. Typ. (1) Max. Unit

VDR VCC fo r Data Re te nti o n V CC = 2V 2.0 ___ ___ V

ICCDR Data Rete ntio n Curre nt CE

> VHC

VIN > VHC or < VLC

MIL. & IND. ___ 100 4000 µA

COM'L. ___ 100 1500

tCDR(3) Chip Dese lect to Data Re tention Time 0 ___ ___ V

tR(3) Operation Recovery Time tRC(2) ___ ___ V

2746 tbl 08

Inp ut P ul se Le v e l s

Inp ut Ris e/Fall Time s

Inp ut Timing Re fe rence Lev els

Outp ut Refe re nce Le vels

Outp ut Lo ad

GND to 3.0V

5ns M ax .

1.5V

Fi gures 1, 2 and 3

2746 tbl 09

2746 drw 05

tCDR tR

VCC

DATA RETENTION MODE

VDR

VDR >2V4.5V 4.5V

VIH

6.42

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage(3)

NOTES:

1. Transition is measured 0mV fromLow or High-impedance voltage with load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. 'X' in part number indicates power rating (SA or LA).

7133X20

7143X20

Com'l Only

7133X25

7143X25

Com'l, I nd

& Mi litary

7133X35

7143X35

Com'l, I nd

& Mi litary

UnitSymbol Parameter Min.Max.Min.Max.Min.Max.

READ CYCLE

tRC Read Cycle Time 20 ____ 25 ____ 35 ____ ns

tAA Address Access Time ____ 20 ____ 25 ____ 35 ns

tACE Chip Enable Acce ss Time ____ 20 ____ 25 ____ 35 ns

tAOE Outp ut Enab le Acc es s Time ____ 12 ____ 15 ____ 20 ns

tOH Output Ho ld fro m Address Change 0 ____ 0____ 0____ ns

tLZ Outp ut Lo w-Z Tim e(1,2) 0____ 0____ 0____ ns

tHZ Outp ut Hig h-Z Tim e (1,2) ____ 12 ____ 15 ____ 20 ns

tPU Chip En able to Power Up Time(2) 0____ 0____ 0____ ns

tPD Chi p Di s ab le to P o we r Do wn Ti me(2) ____ 20 ____ 50 ____ 50 ns

2 746 tb l 10 a

7133X45

7143X45

Com'l &

Military

7133X55

7143X55

Com'l, Ind

& Mi litary

7133X70/90

7143X70/90

Com'l &

Military

UnitSymbol Parameter Min.Max.Min.Max.Min.Max.

READ CYCLE

tRC Read Cycle Time 45 ____ 55 ____ 70/90 ____ ns

tAA Address Access Time ____ 45 ____ 55 ____ 70/90 ns

tACE Chip Enable Acce ss Time ____ 45 ____ 55 ____ 70/90 ns

tAOE Outp ut Enab le Acc es s Time ____ 25 ____ 30 ____ 40/40 ns

tOH Output Ho ld fro m Address Change 0 ____ 0____ 0/0 ____ ns

tLZ Outp ut Lo w-Z Tim e(1,2) 0____ 5____ 5/5 ____ ns

tHZ Outp ut Hig h-Z Tim e (1,2) ____ 20 ____ 20 ____ 25/25 ns

tPU Chip En able to Power Up Time(2) 0____ 0____ 0/0 ____ ns

tPD Chi p Di s ab le to P o we r Do wn Ti me(2) ____ 50 ____ 50 ____ 50/50 ns

2746 tbl 10b

6.42

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges

TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(5)

TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(5)

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is deasserted first, OE or CE.

3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has no

relationship to valid output data.

4. Start of valid data depends on which timing becomes effective last, t AOE, tACE, tAA, or tBDD.

5. R/W = VIH, and the address is valid prior to or coincidental with CE transition LOW.

2746 drw 07

tAA

tOH tOH

DATAOUT

ADDRESS

tRC

DATA VALIDPREVIOUS DATA VALID

BUSYOUT

tBDD(3,4)

2746 drw 08

tAOE

tLZ tHZ

DATAOUT

tACE

VALID DATA

CURRENT ICC

ISB

tPU

50%

tLZ tPD

50%

tHZ

(1)

(4)

(1)

(4)

(2)

6.42

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage(5)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage from the Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization but not production tested.

3. For MASTER/SLAVE combination, t WC = tBAA + tWR + tWP, since R/W = VIL must occur after tBAA.

4. The specification for tDH must be met by the device supplying write data to the RAM under all operation conditions. Although tDH and tOW values will very over voltage and

temperature, the actual tDH will always be smaller than the actual tOW.

5. 'X' in part number indicates power rating (SA or LA).

Symbol Parameter

7133X20

7143X20

Co m'l On ly

7133X25

7143X25

Com'l, Ind

& Military

7133X35

7143X35

Com'l, Ind

& Military

UnitMin. Max. Min. Max. Min. Max.

WRI T E CYC L E

tWC Write Cycle Time(3) 20 ____ 25 ____ 35 ____ ns

tEW Chip Enable to End -o f-Write 15 ____ 20 ____ 25 ____ ns

tAW Address Valid to End-of-Write 15 ____ 20 ____ 25 ____ ns

tAS Address Set-up Time 0 ____ 0____ 0____ ns

tWP Write Pulse Width 15 ____ 20 ____ 25 ____ ns

tWR Write Re covery Time 0 ____ 0____ 0____ ns

tDW Data Valid to End-of-Write 15 ____ 15 ____ 20 ____ ns

tHZ Output High-Z Time (1,2) ____ 12 ____ 15 ____ 20 ns

tDH Data Ho ld Time (4) 0____ 0____ 0____ ns

tWZ Write Enable to Outp ut in High-Z(1,2) ____ 12 ____ 15 ____ 20 ns

tOW Outp u t Ac ti v e from E nd - o f-Wri te (1,2,4) 0____ 0____ 0____ ns

2746 tb l 11 a

Symbol Parameter

7133X45

7143X45

Com'l &

Military

7133X55

7143X55

Com'l, Ind

& Military

7133X70/90

7143X70/90

Com'l &

Military

UnitMin. Max. Min. Max. Min. Max.

WRI T E CYC L E

tWC Write Cycle Time(3) 45 ____ 55 ____ 70/90 ____ ns

tEW Chip Enable to End -o f-Write 30 ____ 40 ____ 50/50 ____ ns

tAW Address Valid to End-of-Write 30 ____ 40 ____ 50/50 ____ ns

tAS Address Set-up Time 0 ____ 0____ 0/0 ____ ns

tWP Write Pulse Width 30 ____ 40 ____ 50/50 ____ ns

tWR Write Re covery Time 0 ____ 0____ 0/0 ____ ns

tDW Data Valid to End-of-Write 20 ____ 25 ____ 30/30 ____ ns

tHZ Output High-Z Time (1,2) ____ 20 ____ 20 ____ 25/25 ns

tDH Data Ho ld Time (4) 5____ 5____ 5/5 ____ ns

tWZ Write Enable to Outp ut in High-Z(1,2) ____ 20 ____ 20 ____ 25/25 ns

tOW Outp u t Ac ti v e from E nd - o f-Wri te (1,2,4) 5____ 5____ 5/5 ____ ns

2746 tb l 11b

6.42

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage(6)

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and Busy".

2. tBDD is calculated parameter and is greater of 0, tWDD - tWP (actual) or tDDD - tDW (actual).

3. To ensure that the earlier of the two ports wins.

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. 'X' in part number indicates power rating (SA or LA).

7133X20

7143X20

Com ' l On ly

7133X25

7143X25

Com'l, Ind

& Military

7133X35

7143X35

Com'l, Ind

& Military

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

BUSY TIMING (For MASTER 71V33)

tBAA BUSY Access Time from Addre ss ____ 20 ____ 20 ____ 30 ns

tBDA BUSY Disable Time from Address ____ 20 ____ 20 ____ 30 ns

tBAC BUSY Access Time from Chip Enable ____ 20 ____ 20 ____ 25 ns

tBDC BUSY Disable Time from Chip Enable ____ 17 ____ 20 ____ 25 ns

tWDD Write Pulse to Data Delay(1) ____ 40 ____ 50 ____ 60 ns

tDDD Write Data Valid to Re ad Data Delay (1) ____ 30 ____ 35 ____ 45 ns

tBDD BUSY Disable to Valid Data(2) ____ 25 ____ 30 ____ 35 ns

tAPS Arb itratio n Priority Se t-up Time (3) 5____ 5____ 5____ ns

tWH Write Hold After BUSY(5) 20 ____ 20 ____ 25 ____ ns

BUSY INPUT TIM ING (For SLAVE 71V43)

tWB BUSY In p ut to Write (4) 0____ 0____ 0____ ns

tWH Write Hold After BUSY(5) 20 ____ 20 ____ 25 ____ ns

tWDD Write Pulse to Data Delay(1) ____ 40 ____ 50 ____ 60 ns

tDDD Write Data Valid to Re ad Data Delay (1) ____ 30 ____ 35 ____ 45 ns

2746 tbl 12a

7133X45

7143X45

Com ' l &

Military

7133X55

7143X55

Com'l, Ind

& Military

7133X70/90

7143X70/90

Com ' l &

Military

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

BUSY TIMING (For MASTER 71V33)

tBAA BUSY Access Time from Addre ss ____ 40 ____ 40 ____ 45/45 ns

tBDA BUSY Disable Time from Address ____ 40 ____ 40 ____ 45/45 ns

tBAC BUSY Access Time from Chip Enable ____ 30 ____ 35 ____ 35/35 ns

tBDC BUSY Disable Time from Chip Enable ____ 25 ____ 30 ____ 30/30 ns

tWDD Write Pulse to Data Delay(1) ____ 80 ____ 80 ____ 90/90 ns

tDDD Write Data Valid to Re ad Data Delay (1) ____ 55 ____ 55 ____ 70/70 ns

tBDD BUSY Disable to Valid Data(2) ____ 40 ____ 40 ____ 40/40 ns

tAPS Arb itratio n Priority Se t-up Time (3) 5____ 5____ 5/5 ____ ns

tWH Write Hold After BUSY(5) 30 ____ 30 ____ 30/30 ____ ns

BUSY INP UT TI MING (For S LAVE 71V43)

tWB BUSY In p ut to Write (4) 0____ 0____ 0/0 ____ ns

tWH Write Hold After BUSY(5) 30 ____ 30 ____ 30/30 ____ ns

tWDD Write Pulse to Data Delay(1) ____ 80 ____ 80 ____ 90/90 ns

tDDD Write Data Valid to Re ad Data Delay (1) ____ 55 ____ 55 ____ 70/70 ns

2746 t b l 12b

6.42

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL.

3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.

4. During this period, the I/O pins are in the output state, and input signals must not be applied.

5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal ( CE or R/W) is asserted last.

7. Timing depends on which enable signal is de-asserted first, CE or OE.

8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed

on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified tWP.

9. R/W for either upper or lower byte.

Write Cycle No. 2 (CE Controlled Timing)(1,5)

Timing Waveform of Write Cycle No. 1 (R/W Controlled Timing)(1,5,8)

2746 drw 09

tAW

tAS

tWR

tDW

DATAIN

ADDRESS

tWC

R/W

tWP

tDH

DATAOUT

tWZ(7)

(4)

(2)

tOW

(9)

tLZ

(7)

tHZ

(6)

(3)

(4)

(7)

tHZ

2746 drw 10

tAW

tAS tWR

tDW

DATAIN

ADDRESS

tWC

R/W

tEW

tDH

(9)

(6) (2)

6.42

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges

2746 drw 11

tDW

tAPS

ADDR"A"

tWC

MATCH

tWP

R/W"A"

DATAIN"A"

ADDR"B"

tDH

VALID

(1)

MATCH

BUSY"B"

tBDA

VALID

tBDD

tDDD(4)

tWDD

DATAOUT "B"

Timing Waveform of Write with Port-to-Port Read and BUSY(1,2,3)

Timing Waveform of Write with BUSY(3)

NOTES:

1. tWH must be met for both BUSY input (IDT7143, slave) and output (IDT7133, master).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

NOTES:

1. To ensure that the earlier of the two ports wins, tAPS is ignored for Slave (IDT7143).

2. CEL = CER = VIL

3. OE = VIL for the reading port.

4. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

2746 drw 12

R/W"A"

BUSY"B"

tWP

tWB

R/W"B"

tWH(1)

(2)

6.42

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges

Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)

Timing Waveform of BUSY Arbitration Controlled by Addresses(1)

NOTES:

1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port " A".

2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted

(IDT7133 only).

tAPS(2)

2746 drw 13

ADDR"A" AND "B" ADDRESSES MATCH

CE"B"

BUSY"B"

tBAC tBDC

CE"A"

tRC

2746 drw 14

ADDR"A" ADDRESSES MATCH

ADDR"B"

BUSY "B"

ADDRESSES DO NOT MATCH

tWC

tAPS

tBAA tBDA

(2)

6.42

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges

Functional Description

The IDT7133/43 provides two ports with separate control, address

and I/O pins that permit independent access for reads or writes to any

location in memory. The IDT7133/43 has an automatic power down

feature controlled by CE. The CE controls on-chip power down circuitry

that permits the respective port to go into a standby mode when not

selected (CE HIGH). When a port is enabled, access to the entire

memory array is permitted. Non-contention READ/WRITE conditions

are illustrated in Truth Table 1.

Busy Logic

Busy Logic provides a hardware indication that both ports of the

RAM have accessed the same location at the same time. It also allows

one of the two accesses to proceed and signals the other side that the

RAM is “busy”. The BUSY pin can then be used to stall the access until

the operation on the other side is completed. If a write operation has

been attempted from the side that receives a BUSY indication, the

write signal is gated internally to prevent the write from proceeding.

The use of BUSY logic is not required or desirable for all applica-

tions. In some cases it may be useful to logically OR the BUSY outputs

together and use any BUSY indication as an interrupt source to flag the

event of an illegal or illogical operation. If the write inhibit function of

BUSY logic is not desirable, the BUSY logic can be disabled by using

the IDT7143 (SLAVE). In the IDT7143, the BUSY pin operates solely

as a write inhibit input pin. Normal operation can be programmed by

tying the BUSY pins HIGH. If desired, unintended write operations can

be prevented to a port by tying the BUSY pin for that port LOW. The

BUSY outputs on the IDT 7133 RAM are open drain and require pull-

up resistors.

Width Expansion with Busy Logic

Master/Slave Arrays

When expanding an IDT7133/43 RAM array in width while using

BUSY logic, one master part is used to decide which side of the RAM

array will receive a BUSY indication, and to output that indication. Any

number of slaves to be addressed in the same address range as the

master, use the BUSY signal as a write inhibit signal. Thus on the

IDT7133 RAM the BUSY pin is an output and on the IDT7143 RAM, the

BUSY pin is an input (see Figure 3).

Expanding the data bus width to 32 bits or more in a Dual-Port RAM

system implies that several chips will be active at the same time. If each

chip includes a hardware arbitrator, and the addresses for each chip

arrive at the same time, it is possible that one will activate its BUSYL

while another activates its BUSYR signal. Both sides are now BUSY

and the CPUs will await indefinitely for their port to become free.

To avoid the “Busy Lock-Out” problem, IDT has developed a

MASTER/SLAVE approach where only one hardware arbitrator, in the

MASTER, is used. The SLAVE has BUSY inputs which allow an

interface to the MASTER with no external components and with a

speed advantage over other systems.

When expanding Dual-Port RAMs in width, the writing of the SLAVE

RAMs must be delayed until after the BUSY input has settled.

Otherwise, the SLAVE chip may begin a write cycle during a contention

situation. Conversely, the write pulse must extend a hold time past

BUSY to ensure that a write cycle takes place after the contention is

resolved. This timing is inherent in all Dual-Port memory systems where

more than one chip is active at the same time.

The write pulse to the SLAVE should be delayed by the maximum

arbitration time of the MASTER. If, then, a contention occurs, the write

to the SLAVE will be inhibited due to BUSY from the MASTER.

Figure 4. Busy and chip enable routing for both width and depth expansion

with the IDT7133 (MASTER) and the IDT7143 (SLAVE).

VCC

R/W

BUSY

R/W

BUSY

IDT7133

MASTER

VCC

R/W

BUSY

R/W

BUSY

R/W

BUSY

R/W

BUSY

LEFT RIGHT

2746drw 15

IDT7143

SLAVE

270Ω270Ω

6.42

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges

Truth Table I  Non-Contention Read/Write Control(4)

Truth Table II  Address BUSY

Arbitration

NOTES:

1. Pins BUSYL and BUSYR are both outputs on the IDT7133 (MASTER). Both are

inputs on the IDT7143 (SLAVE). On Slaves the BUSY input internally inhibits

writes.

2. "L" if the inputs to the opposite port were stable prior to the address and enable

inputs of this port. “H” if the inputs to the opposite port became stable after the

address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR

= VIL will result BUSYL and BUSYR outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW

regardless of actual logic level on the pin. Writes to the right port are internally

ignored when BUSYR outputs are driving LOW regardless of actual logic level on

the pin.

NOTES:

1. A0L - A10L≠A0R - A10R

2. If BUSY = LOW, data is not written.

3. If BUSY = LOW, data may not be valid, see tWDD and tDDD timing.

4. "H" = HIGH, "L" = LOW, "X" = Don ’t Care, "Z" = High-Impedance, "LB" = Lower Byte, "UB" = Upper Byte

LEFT OR RIGHT PORT(1)

FunctionR/WLB R/WUB CE OE I/O0-7 I/O8-15

X X H X Z Z Port Disable d and in Power Down Mo de, ISB2, ISB4

XXHX Z ZCE

R = CEL = VIH, Po we r Do wn Mo d e , ISB1 or ISB3

LLLXDATA

IN DATAIN Data on Lower Byte and Upper Byte Written into Memory(2)

LHLL

DATAIN DATAOUT Da ta o n Lowe r B yte Wri tte n into M e mo ry(2), Data in Memory Output on

Upper Byte(3)

HLLL

DATAOUT DATAIN Data i n Me mo ry Output o n Lower Byte (3), Data o n Up pe r By te Written into

Memory(2)

LHLHDATA

IN Z Data o n Lo we r Byte Written into Memory (2)

HLLH Z DATA

IN Da ta o n Up p e r B y te Wri tte n i nto M e mory(2)

HHLLDATA

OUT DATAOUT Data i n Me mo ry Output on Lo wer By te and Upp er Byte

H H L H Z Z High Impedance Outputs

2746 tbl 13

Inputs Outputs

Function

CELCERA0L-A10L

A0R-A10R BUSYL(1) BUSYR(1)

XXNO MATCHHHNormal

HXMATCHHHNormal

XHMATCHHHNormal

L L MATCH (2) (2) Write Inhib it(3)

2 7 46 tb l 14

6.42

IDT7133SA/LA, IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges

Ordering Information

Power

Speed

Package

Process/

Temperature

Range

Blank

Commercial (0°Cto+70

°C)

Industrial (-40°Cto+85

°C)

Military (-55°Cto+125

°C)

Compliant to MIL-PRF-38535 QML

68-pin PLCC (J68-1)

68-pin PGA (GU68-1)

68-pin Flatplack (F68-1)

100-pin TQFP (PN100-1)

XXXX

Device

Type

IDT

Speed in nanoseconds

2746 drw 16

SA Low Power

Standard Power

7133

7143 32K (2K x 16-Bit) MASTER Dual-Port RAM

32K (2K x 16-Bit) SLAVE Dual-Port RAM

Commercial Only

Commercial, Industrial & Military

Commercial & Military

Commercial, Industrial & Military

Commercial & Military

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 831-754-4613

Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Datasheet Document History

12/18/98: Initiated datasheet document history

Converted to new format

Cosmetic and typographical corrections

Added additional notes to pin configurations

Page 2 corrected PN100 pinout

2/17/99: Corrected PF ordering code

3/9/99: Cosmetic and typographical corrections

6/9/99: Changed drawing format

10/1/99: Added Industrial Temperature Ranges and removed corresponding notes

11/10/99: Replaced IDT logo

4/1/00: Changed ±500mV to 0mV in notes

Page 2 Fixed overbar in pinout

6/26/00: Page 4 Increased storage temperature parameters

Clarified TA parameter

Page 5 DC Electrical parameters–changed wording from "open" to "disabled"