HUF75307T3ST - Intersil Corporation

File Number 4364.4

HUF75307T3ST

2.6A, 55V, 0.090 Ohm, N-Channel UltraFET

Power MOSFET

This N-Channel power MOSFET is

manufactured using the innovative

UltraFET™process.Thisadvanced

process technology achieves the

lowest possible on-resistance per silicon area, resulting in

outstanding performance. This device is capable of

withstanding high energy in the avalanche mode and the

diode exhibits very low reverse recovery time and stored

charge. It was designed for use in applications where power

efﬁciency is important, such as switching regulators,

switching converters, motor drivers, relay drivers, low-

voltage bus switches, and power management in portable

and battery-operated products.

Formerly developmental type TA75307.

Features

• 2.6A, 55V

• Ultra Low On-Resistance, rDS(ON) = 0.090Ω

• Diode Exhibits Both High Speed and Soft Recovery

• Temperature Compensating PSPICE™ Model

• Thermal Impedance SPICE Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

Packaging

SOT-223

Ordering Information

PART NUMBER PACKAGE BRAND

HUF75307T3ST SOT-223 5307

NOTE: HUF75307T3ST is available only in tape and reel.

DRAIN

SOURCE

GATE

DRAIN

(FLANGE)

Data Sheet October 1999

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a trademark of MicroSim Corporation.

Absolute Maximum Ratings TA= 25oC, Unless Otherwise Specified UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 55 V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 55 V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20V V

Drain Current

Continuous (Figure 2) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 2.6

Figure 5 A

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Figures 6, 14, 15

Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1

9.09 W

mW/oC

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG -55 to 150 oC

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL

Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300

260

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. TJ = 25oC to 125oC.

Electrical Speciﬁcations TA = 25oC, Unless Otherwise Speciﬁed

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) 55 - - V

Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V

Zero Gate Voltage Drain Current IDSS VDS = 50V, VGS = 0V - - 1 µA

VDS = 45V, VGS = 0V, TA = 150oC - - 250 µA

Gate to Source Leakage Current IGSS VGS = ±20V - - 100 nA

Drain to Source On Resistance rDS(ON) ID = 2.6A, VGS = 10V) (Figure 9) - 0.070 0.090 Ω

Turn-On Time tON VDD = 30V, ID≅ 2.6A,

RL = 11.5Ω, VGS =10V,

RGS = 25Ω

- - 55 ns

Turn-On Delay Time td(ON) -5-ns

Rise Time tr-30-ns

Turn-Off Delay Time td(OFF) -35-ns

Fall Time tf-25-ns

Turn-Off Time tOFF - - 90 ns

Total Gate Charge Qg(TOT) VGS = 0V to 20V VDD = 30V,

ID≅ 2.6A,

RL = 11.5Ω

Ig(REF) = 1.0mA

(Figure 13)

-1417nC

Gate Charge at 10V Qg(10) VGS = 0V to 10V - 8.3 10 nC

Threshold Gate Charge Qg(TH) VGS = 0V to 2V - 0.6 0.8 nC

Gate to Source Gate Charge Qgs - 1.00 - nC

Gate to Drain “Miller” Charge Qgd - 4.00 - nC

Input Capacitance CISS VDS = 25V, VGS = 0V,

f = 1MHz

(Figure 12)

- 250 - pF

Output Capacitance COSS - 115 - pF

Reverse Transfer Capacitance CRSS -30-pF

Thermal Resistance Junction to Ambient RθJA Pad Area = 0.171 in2 (see note 2) - - 110 oC/W

Pad Area = 0.068 in2- - 128 oC/W

Pad Area = 0.026 in2- - 147 oC/W

Source to Drain Diode Speciﬁcations

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage VSD ISD = 2.6A - - 1.25 V

Reverse Recovery Time trr ISD = 2.6A, dISD/dt = 100A/µs--40ns

Reverse Recovered Charge QRR ISD = 2.6A, dISD/dt = 100A/µs--50nC

NOTE:

2. 110 oC/W measured using FR-4 board with 0.171in2 footprint for 1000s.

HUF75307T3ST

Typical Performance Curves

FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT

TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

AMBIENT TEMPERATURE

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY

0 50 100 150

TA, AMBIENT TEMPERATURE (oC)

POWER DISSIPATION MULTIPLIER

0.2

0.4

0.6

0.8

1.0

1.2

ID, DRAIN CURRENT (A)

TA, AMBIENT TEMPERATURE (oC)

1.0

1.5

2.0

2.5

3.0

25 50 75 100 125 150

0.5

RθJA = 110oC/W

0.001

0.01

0.1

10-5 10-4 10-3 10-2 10-1 100101102103

ZθJA, NORMALIZED

THERMAL IMPEDANCE

SINGLE PULSE NOTES:

DUTY FACTOR: D = t1/t2

PEAK TJ = PDM x ZθJA x RθJA + TA

PDM

t1t2

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

0.05

0.01

0.02

t, RECTANGULAR PULSE DURATION (s)

RθJA = 110oC/W

0.01

0.1

100

1 10 100 200

VDS, DRAIN TO SOURCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

TJ = MAX RATED

TA = 25oC

100µs

10ms

1ms

VDSS(MAX) = 55V

LIMITED BY rDS(ON)

AREA MAY BE

OPERATION IN THIS

RθJA = 110oC/W

103

102

101

100

10-1

10-2

10-3

t, PULSE WIDTH (s)

IDM, PEAK CURRENT (A)

I = I25 150 - TA

125

FOR TEMPERATURES

ABOVE 25oC DERATE PEAK

CURRENT AS FOLLOWS:

TA = 25oC

RθJA = 110oC/W

HUF75307T3ST

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS

FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

Typical Performance Curves (Continued)

0.01 0.1 1 10

IAS, AVALANCHE CURRENT (A)

tAV, TIME IN AVALANCHE (ms)

tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)

If R = 0

If R ≠ 0

tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]

STARTING TJ = 25oC

STARTING TJ = 150oC

012345

ID, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 6V

VGS = 10V

VGS = 20V

PULSE DURATION = 80µs

TA = 25oC

VGS = 5V

VGS = 7V

DUTY CYCLE = 0.5% MAX

0 1.5 3.0 4.5 6.0 7.5

ID, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VDD = 15V

150oC

25oC

-55oC

0.5

1.0

1.5

2.0

2.5

-80 -40 0 40 80 120 160

NORMALIZED DRAIN TO SOURCE

TJ, JUNCTION TEMPERATURE (oC)

ON RESISTANCE

PULSE DURATION = 80µs

VGS = 10V, ID = 2.6A

DUTY CYCLE = 0.5% MAX

NORMALIZED GATE

TJ, JUNCTION TEMPERATURE (oC)

THRESHOLD VOLTAGE

0.4

0.6

0.8

1.0

1.2

-80 -40 0 40 80 120 160

VGS = VDS, ID = 250µA

BREAKDOWN VOLTAGE

0.8

0.9

1.0

1.1

1.2

-80 -40 0 40 80 120 160

TJ, JUNCTION TEMPERATURE (oC)

NORMALIZED DRAIN TO SOURCE

ID = 250µA

HUF75307T3ST

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT

GATE CURRENT

Typical Performance Curves (Continued)

100

200

300

400

500

0 102030405060

C, CAPACITANCE (pF)

VDS, DRAIN TO SOURCE VOLTAGE (V)

CISS

COSS

CRSS

VGS = 0V, f = 1MHz

CISS = CGS + CGD

CRSS = CGD

COSS = CDS + CGD

02468

VGS, GATE TO SOURCE VOLTAGE (V)

VDD = 30V

Qg, GATE CHARGE (nC)

ID = 2.6A

ID = 1.5A

ID = 0.5A

WAVEFORMS IN

DESCENDING ORDER:

Test Circuits and Waveforms

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM

VGS

0.01Ω

IAS

VDS

VDD

DUT

VARY tP TO OBTAIN

REQUIRED PEAK IAS

VDD

VDS

BVDSS

IAS

tAV

VGS +

VDS

VDD

DUT

Ig(REF)

VDD

Qg(TH)

VGS = 2V

Qg(10)

VGS = 10V

Qg(TOT)

VGS = 20V

VDS

VGS

Ig(REF)

HUF75307T3ST

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJ(MAX), and the

thermal resistance of the heat dissipating path determines

the maximum allowable device power dissipation, PD(MAX),

in an application. Therefore the application’s ambient

temperature, TA (oC), and thermal resistance RθJA (oC/W)

must be reviewed to ensure that TJ(MAX) is never exceeded.

Equation 1 mathematically represents the relationship and

serves as the basis for establishing the rating of the part.

In using surface mount devices such as the SOT-223

package, the environment in which it is applied will have a

signiﬁcant inﬂuence on the part’s current and maximum

power dissipation ratings. Precise determination of the

PD(MAX) is complex and inﬂuenced by many factors:

1. Mounting pad area onto which the device is attached and

whether there is copper on one side or both sides of the

board.

2. The number of copper layers and the thickness of the

board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air ﬂow and board orientation.

6. For non steady state applications, the pulse width, the

duty cycle and the transient thermal response of the part,

the board and the environment they are in.

Intersil provides thermal information to assist the designer’s

preliminary application evaluation. Figure 20 deﬁnes the

RθJA for the device as a function of the top copper

(component side) area. This is for a horizontally positioned

FR-4 board with 1oz copper after 1000 seconds of steady

state power with no air ﬂow. This graph provides the

necessary information for calculation of the steady state

junction temperature or power dissipation. Pulse

applications can be evaluated using the Intersil device Spice

thermal model or manually utilizing the normalized maximum

transient thermal impedance curve.

Displayed on the curve are the three RθJA values listed in

the Electrical Speciﬁcations table. The three points were

chosen to depict the compromise between the copper board

area, the thermal resistance and ultimately the power

dissipation, PD(MAX). Thermal resistances corresponding to

other component side copper areas can be obtained from

Figure 20 or by calculation using Equation 2. The area, in

square inches is the top copper area including the gate and

source pads.

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS

Test Circuits and Waveforms (Continued)

VGS

RGS DUT

-VDD

VDS

VGS

tON

td(ON)

90%

10%

VDS 90%

10%

td(OFF)

tOFF

90%

50%

10% PULSE WIDTH

VGS

(EQ. 1)

PDMAX()

TJMAX()

–()

RθJA

--------------------------------------------=

FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD

AREA

100

150

200

0.01 0.1 1.0

147oC/W - 0.026in2

RθJA = 75.9 -19.3 ln(AREA)

AREA, TOP COPPER AREA (in2)

RθJA (oC/W)

128oC/W - 0.068in2

110oC/W - 0.171in2

(EQ. 2)

RθJA 75.9 19.3 Area()ln×–=

HUF75307T3ST

PSPICE Electrical Model

.SUBCKT HUF75307T3ST 2 1 3 ; rev 7/25/97

CA 12 8 3.5e-10

CB 15 14 3.7e-10

CIN 6 8 2.26e-10

DBODY 7 5 DBODYMOD

DBREAK 5 11 DBREAKMOD

DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 57.4

EDS 14 8 5 8 1

EGS 13 8 6 8 1

ESG 6 10 6 8 1

EVTHRES 6 21 19 8 1

EVTEMP 20 6 18 22 1

IT 8 17 1

LDRAIN 2 5 1e-9

LGATE 1 9 1.4e-9

LSOURCE 3 7 3.1e-10

K1 LGATE LSOURCE 0.131

MMED 16 6 8 8 MMEDMOD

MSTRO 16 6 8 8 MSTROMOD

MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1

RDRAIN 50 16 RDRAINMOD 7.0e-3

RGATE 9 20 1.9

RLDRAIN 2 5 10

RLGATE 1 9 14

RLSOURCE 3 7 3

RSLC1 5 51 RSLCMOD 1e-6

RSLC2 5 50 1e3

RSOURCE 8 7 RSOURCEMOD 5.6e-2

RVTHRES 22 8 RVTHRESMOD 1

RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD

S1B 13 12 13 8 S1BMOD

S2A 6 15 14 13 S2AMOD

S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*50),3))}

.MODEL DBODYMOD D (IS = 2.6e-13 RS = 2.34e-2 IKF = 5.5 N = 0.995 TRS1 = 2.8e-3 TRS2 = 1.1e-5 CJO = 3.7e-10 TT = 3.5e-8 M = 0.46

+ XTI = 5.5)

.MODEL DBREAKMOD D (RS = 0.5 IKF = 0.1 N = 1 TRS1 = 3e-3 TRS2 = -5e-5)

.MODEL DPLCAPMOD D (CJO = 5.6e-10 IS = 1e-30 N = 10 M = 0.92)

.MODEL MMEDMOD NMOS (VTO = 3.25 KP = 1.8 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.9)

.MODEL MSTROMOD NMOS (VTO = 3.68 KP = 13.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)

.MODEL MWEAKMOD NMOS (VTO = 2.83 KP = 0.03 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 19 RS = 0.1)

.MODEL RBREAKMOD RES (TC1 = 1.08e-3 TC2 = 5e-7)

.MODEL RDRAINMOD RES (TC1 = 1.7e-2 TC2 = 1e-4)

.MODEL RSLCMOD RES (TC1 = 1e-9 TC2 = 1e-4)

.MODEL RSOURCEMOD RES (TC1 = 3.3e-3 TC2 = 1e-9)

.MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -4e-6)

.MODEL RVTEMPMOD RES (TC1 = -2.9e-3 TC2 = 2.2e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -7.1 VOFF= -4)

.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4 VOFF= -7.1)

.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.01 VOFF= 1.9)

.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.9 VOFF= 0.01)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK DBODY

RSOURCE

SOURCE

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ESLC

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

HUF75307T3ST

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

SPICE Thermal Model

REV 15 Nov 97

HUF75307T3ST

CTHERM1 7 6 7.5e-5

CTHERM2 6 5 3.5e-4

CTHERM3 5 4 1.2e-3

CTHERM4 4 3 1.5e-2

CTHERM5 3 2 6.9e-2

CTHERM6 2 1 4.5e-1

RTHERM1 7 6 7.5e-2

RTHERM2 6 5 2.0e-1

RTHERM3 5 4 1.2

RTHERM4 4 3 3.3

RTHERM5 3 2 28

RTHERM6 2 1 90

RTHERM4

RTHERM6

RTHERM5

RTHERM3

RTHERM2

RTHERM1

CTHERM4

CTHERM6

CTHERM5

CTHERM3

CTHERM2

CTHERM1

7JUNCTION

CASE

HUF75307T3ST