Rev 0.1 / Feb. 2006 3
11Preliminary
Mobile DDR Memory 256Mbit (16Mx16bit)
HY5MS5B6ALF(P)-xE Series
DESCRIPTION
The Hynix Mobile DDR SDRAMs is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G
cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs.
The Hynix HY5MS5B6ALF(P)-xE Series is 268,435,456-bit CMOS Low Power Double Data Rate Synchronous
DRAM(Mobile DDR), ideally suited for the main memory applications which requires large memory density and high
bandwidth. It is organized as 4banks of 4,194,304x16.
The HYNIX HY5MS5B6ALF(P)-xE Low power Double Data Rate SDRAM(Mobile DDR) uses a double-data-rate architec-
ture to achieve high-speed operation. The address lines are multiplexed with the Data Input/ Output signals on a mul-
tiplexed x16 Input/ Output bus. The double data rate architecture is essentially a 2
n
prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. This interface reduces the pin count and
makes it possible to migrate to other densities without changing the footprint.
The Hynix HY5MS5B6ALF(P)-xE Serises Low power DDR SDRAMs(Mobile DDR) offer fully synchronous operations ref-
erenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising
edges of the CK (The Mobile DDR operates from a differential clock
: the crossing of CK going HIGH and CK going LOW
is referred to as the positive edge of CK
), Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it (
Input data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK
). The data paths are internally pipelined and 2-bit prefetched to achieve very high
bandwidth. All input and output voltage levels are compatible with Interface of Low Power DDR SDRAM(Mobile DDR)
Device.
Read and write accesses to the Low Power DDR SDRAMs(Mobile DDR) are burst oriented;
accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.
The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be
accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and
the starting column location for the burst access.
The Low Power DDR SDRAMs(Mobile DDR) provides for programmable read or write bursts of 2, 4 or 8 locations. An
AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst access.
As with standard SDRAMs, the pipe lined, multibank architecture of Low Power DDR SDRAMs(Mobile DDR) allows for
concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation times.
And the Low Power DDR SDRAMs(Mobile DDR) also provides for special programmable options including Partial Array
Self Refresh of a quarter bank, a half bank or all banks, Temperature Compensated Self Refresh of 45 or 85 degrees
oC. A burst of Read or Write cycles in progress can be terminated by a burst terminate command or can be interrupted
and replaced by a new burst Read or Write command on any cycle(This pipelined design is not restricted by a 2N rule).