FUJITSU SEMICONDUCTOR DATA SHEET DS07-16202-1E 32-bit Proprietary Microcontroller CMOS FR Family MB91191 Series MB91191/MB91F191A/MB91191R DESCRIPTION The MB91191 is a single-chip microcontroller using a 32-bit RISC-CPU (FR series) as its core. It contains peripheral I/O resources suitable for software servo control in applications such as VTRs that require high-speed CPU processing. FEATURES CPU * 32-bit RISC (FR series) , load/store architecture, 5-stage pipeline * General-purpose registers : 16 x 32-bit * 16-bit fixed-length instructions (basic instructions) , 1 instruction per cycle * Includes memory-to-memory transfer, bit manipulation, and barrel shift instructions : Optimized for embedded applications * Includes function entry/exit instructions and multiple-register load/store instructions : Instruction set supports high level languages * Register interlock function : For efficient assembly language coding * Branch instructions with delay slots : Reduced overhead for branch operations * Internal multiplier unit is supported at instruction level Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles * Interrupts (PC and PS saving) : 6 cycles, 16 priority levels (Continued) PACKAGE Plastic, LQFP, 120-pin (FPT-120P-M05) MB91191 Series (Continued) Bus Interface * 16-bit address output, 8/16-bit data input and output * Basic bus cycle : 2 clock cycles * Supports interfaces for various types of memory * Multiplexed data/address input/output * Automatic wait cycles : Between 0 and 7 wait cycles can be specified independently for each memory area * Unused data/address pins can be configured as input/output ports * Supports little endian mode Bit Search Module * Searches, starting from the MSB, for the position of the first 1/0 bit transition in a word. The operation is performed in one cycle. Serial I/O * 3 channels with internal buffer RAM (automatic transfer of up to 128 bytes) * Independent send and receive buffer mode (automatic transfer of up to 64 bytes) A/D Converter (Successive Approximation Type) * 10-bit x 16 channels * Uses successive approximation conversion method (conversion time : 8.4 s @ 20 MHz) * Channel scan function * Hardware and software conversion start functions * Internal FIFO (Software conversion : 6 stages, Hardware conversion : 6 stages) Timers * 16-bit x 4 channels * 16-bit timer/counter x 1 channel (with square wave output) * 8/16-bit timer/counter x 1 channel (with square wave output) FG input unit * Incorporates capstan, drum, and reel input circuits Capture unit * Internal 24-bit free-run counter (Minimum resolution = 50 ns @ 20 MHz) * Internal FIFO (Data : 21-bit x 8, Detection : 8-bit x 8) Programmable pattern generator * Internal RAM buffer (PPG0 : 256 bytes, PPG1 : 64 bytes) * Output timing resolution : 800 ns @ 20 MHz * Includes an A/D converter hardware start function Realtime timing generator * RTG : 3 circuits * Output timing resolution : 400 ns or 800 ns selectable * Timing output ports : 5 ports PWM * 12-bit PWM x 6 channels (rate, multi-type) * Base frequency = 78.1 kHz or 39.0 kHz (@ 20 MHz) selectable (Continued) 2 MB91191 Series (Continued) PWC * 8-bit PWC x 1 channel (with mask input) * Measurement resolution : 400ns @ 20 MHz General-purpose prescaler * 10-bit prescaler x 1 channel (with square wave and pulse outputs) * Dedicated internal oscillator circuit * Includes load function driven by PPG output Interrupt control * External interrupts : 3 inputs * Key input interrupt : 8 inputs 3 MB91191 Series PIN ASSIGNMENT 65 70 75 80 85 60 95 55 100 50 105 45 110 40 115 30 25 20 15 10 120 5 35 P93/PPG02 P94/PPG03 P80/PPG04 P81/PPG05 P82/PPG06 P83/PPG07 P84/PPG08 P85/PPG09 P86/PPG10 P87/PPG11 P40/PPG12 P41/PPG13 P42/PPG14 P43/PPG15 P44/PPG16 P45/PPG17 P46/PPG18 P47 A15 P57 P57 A14 P56 P56 A13 P55 P55 A12 P54 P54 A11 P53 P53 A10 P52 P52 A09 P51 P51 A08 P50 P50 VSS D31/A07 D31/A15 P37 D30/A06 D30/A14 P36 D29/A05 D29/A13 P35 ALE P62 WR0 RD P20 P21 P22 P23 P24 P25 P26 P27 A00/D24 A01/D25 A02/D26 A03/D27 A04/D28 ALE WR1 WR0 RD A00/D16 A01/D17 A02/D18 A03/D19 A04/D20 A05/D21 A06/D22 A07/D23 A08/D24 A09/D25 A10/D26 A11/D27 A12/D28 X0 X1 VSS MD2 MD1 MD0 RST P70/XOUT P67/T40 P66/T501 P65 P64 P63 P62 P61 P60 P20 P21 P22 P23 P24 P25 P26 P27 VDD P30 P31 P32 P33 P34 PA0/AN-8/KEY0 PB7/AN-7 PB6/AN-6 PB5/AN-5 PB4/AN-4 PB3/AN-3 PB2/AN-2 PB1/AN-1 PB0/AN-0 AVDD AVRH AVSS VSS P17/RTG4 P16/RTG3 P15/RTG2 P14/RTG1 P13/RTG0 P12/EC5/INT1 P11/EC4/INT0 P10/PMSK P07/EXI2/PMI P06/EXI1 P05/EXI0 P04/CFG P03/DFG P02/DPG P01/RFG0 P00/RFG1 VDD 90 PA1/AN-9/KEY1 PA2/AN-A/KEY2 PA3/AN-B/KEY3 PA4/AN-C/KEY4 PA5/AN-D/KEY5 PA6/AN-E/KEY6 PA7/AN-F/KEY7 PD0/SI2 PD1/SO2 PD2/SCK2 PD3/SI1/INT2 PD4/SO1 PD5/SCK1 PD6/SCS0 PD7/SI0 PC0/SO0 PC1/SCK0 PC2/PWM5/SCS1 PC3/PWM4/SCS2 PC4/PWM3 PC5/PWM2 PC6/PWM1 PC7/PWM0 VSS OSCI/PCK OSCO VDD P90/P0 P91/PPG00 P92/PPG01 (TOP VIEW) (FPT-120P-M05) 4 8-bit MPX mode 16-bit MPX mode MB91191 Series PIN DESCRIPTIONS Pin No. Pin Name 1 X0 (I) 2 X1 (O) 3 VSS 4 MD2 5 MD1 6 MD0 7 Circuit Type Function A Crystal oscillator pins VSS pin B Operation mode setting pins CMOS Schmidt inputs RST B Reset input pin. CMOS Schmidt input. 8 P70/XOUT C Shared pin with clock output (X0/2, PCK/2) . CMOS input. 9 P67/T40 Shared pin with timer 4 square wave output. CMOS input. 10 P66/T501 Shared pin with timer 5 square wave output. CMOS input. 11 P65 General-purpose I/O port. CMOS input. 12 P64 13 P63/ALE/ALE 14 P62/P62/WR1 Shared pin with write strobe output 1. CMOS input. 15 P61/WR0/WR0 Shared pin with write strobe output 0. CMOS input. 16 P60/RD/RD Shared pin with read strobe output. CMOS input. 17 P20/P20/D16 : A00 18 P21/P21/D17 : A01 19 P22/P22/D18 : A02 20 P23/P23/D19 : A03 21 P24/P24/D20 : A04 22 P25/P25/D21 : A05 23 P26/P26/D22 : A06 24 P27/P27/D23 : A07 25 VDD 26 P30/D24 : A00/D24 : A08 27 P31/D25 : A01/D25 : A09 28 P32/D26 : A02/D26 : A10 29 P33/D27 : A03/D27 : A11 30 P34/D28 : A04/D28 : A12 31 P35/D29 : A05/D29 : A13 32 P36/D30 : A06/D30 : A14 33 P37/D31 : A07/D31 : A15 34 VSS C General-purpose I/O port. CMOS input. Shared pin with address strobe output. CMOS input. C General-purpose I/O ports. CMOS inputs. Power supply pin C Shared external bus pins and high-current I/O ports. CMOS inputs. VSS pin (Continued) 5 MB91191 Series Pin No. Pin Name 35 P50/A08/P50 36 P51/A09/P51 37 P52/A10/P52 38 P53/A11/P53 39 P54/A12/P54 40 P55/A13/P55 41 P56/A14/P56 42 P57/A15/P57 43 P47 44 P46/PPG18 45 P45/PPG17 46 P44/PPG16 47 P43/PPG15 48 P42/PPG14 49 P41/PPG13 50 P40/PPG12 51 P87/PPG11 52 P86/PPG10 53 P85/PPG09 54 P84/PPG08 55 P83/PPG07 56 P82/PPG06 57 P81/PPG05 58 P80/PPG04 59 P94/PPG03 60 P93/PPG02 61 P92/PPG01 62 P91/PPG00 63 P90/P0 64 VDD 65 OSCO 66 OSCI/PCK 67 VSS Circuit Type C Function Shared external bus pins and high-current I/O ports. CMOS inputs. General-purpose I/O port. CMOS input. C Shared pins with PPG outputs. CMOS inputs. C Shared pins with PPG outputs. CMOS inputs. C Shared pins with PPG outputs. CMOS inputs. C Shared pins with PPG outputs. CMOS inputs. Shared pin with general-purpose prescaler output. CMOS input. (O) (I) Power supply pin A Crystal oscillator pins for dedicated general-purpose prescaler oscillation. VSS pin (Continued) 6 MB91191 Series Pin No. Pin Name Circuit Type Function 68 PC7/PWM0 69 PC6/PWM1 70 PC5/PWM2 71 PC4/PWM3 72 PC3/PWM4/SCS2 73 PC2/PWM5/SCS1 74 PC1/SCK0 75 PC0/SO0 76 PD7/SI0 77 PD6/SCS0 78 PD5/SCK1 79 PD4/SO1 80 PD3/SI1/INT2 81 PD2/SCK2 82 PD1/SO2 C Shared pin with serial 2 serial output. CMOS input. 83 PD0/SI2 F Shared pin with serial 2 serial input. CMOS Schmidt input. 84 PA7/AN-F/KEY7 85 PA6/AN-E/KEY6 86 PA5/AN-D/KEY5 87 PA4/AN-C/KEY4 88 PA3/AN-B/KEY3 E Shared pins with analog inputs and key inputs. CMOS Schmidt inputs 89 PA2/AN-A/KEY2 90 PA1/AN-9/KEY1 91 PA0/AN-8/KEY0 C Shared pins with PWM outputs. CMOS inputs. Shared pin with PWM output and serial 2 chip select. CMOS Schmidt input. F Shared pin with PWM output and serial 1 chip select. CMOS Schmidt input. Shared pin with serial 0 shift clock. CMOS Schmidt input. C Shared pin with serial 0 serial output. CMOS input. Shared pin with serial 0 serial input. CMOS Schmidt input. F Shared pin with serial 0 chip select input. CMOS Schmidt input. Shared pin with serial 1 shift clock. CMOS Schmidt input. C F Shared pin with serial 1 serial output. CMOS input. Shared pin with serial 1 serial input and external interrupt 2. CMOS Schmidt input. Shared pin with serial 2 shift clock. CMOS Schmidt input. (Continued) 7 MB91191 Series (Continued) Pin No. 8 Pin Name 92 PB7/AN-7 93 PB6/AN-6 94 PB5/AN-5 95 PB4/AN-4 96 PB3/AN-3 97 PB2/AN-2 98 PB1/AN-1 99 PB0/AN-0 100 Circuit Type Function D Shared pins with analog inputs. CMOS Schmidt inputs. AVDD A/D converter power supply pin 101 AVRH A/D converter reference power supply pin 102 AVSS A/D converter VSS pin 103 VSS VSS pin 104 P17/RTG4 105 P16/RTG3 106 P15/RTG2 C Shared pins with RTG outputs. CMOS inputs. 107 P14/RTG1 108 P13/RTG0 109 P12/EC5/INT1 110 P11/EC4/INT0 111 P10/PMSK Shared pin with PWC mask input. CMOS Schmidt input. 112 P07/EXI2/PMI Shared pin with external capture input and PWC input. CMOS Schmidt input. 113 P06/EXI1 114 P05/EXI0 115 P04/CFG 116 P03/DFG Shared pin with drum FG input. CMOS Schmidt input. 117 P02/DPG Shared pin with drum pulse input. CMOS Schmidt input. 118 P01/RFG0 119 P00/RFG1 Shared pins with reel FG inputs. CMOS Schmidt inputs. 120 VDD Shared pin with timer 5 clock input and external interrupt input. CMOS Schmidt input. F Shared pin with timer 4 clock input and external interrupt input. CMOS Schmidt input. Shared pin with external capture input. CMOS Schmidt input. F Shared pin with capstan FG input. CMOS Schmidt input. Power supply pin MB91191 Series I/O CIRCUITS Type Circuit Remarks * Oscillation feedback resistor : 1 M approx. X0,OSCI Clock input A Standby control signal X1,OSCO * CMOS Schmidt input B Input Output data DC test * CMOS level output * CMOS input No standby control DC test C Input Standby control signal = 1 (fixed) Output data DC test * CMOS level output * CMOS input with input control * Analog input DC test D Analog input CH selection Digital input Input control (Continued) 9 MB91191 Series (Continued) Type Circuit Remarks Input data DC test * CMOS level output * CMOS Schmidt input with input control * Analog input DC test E Analog input CH selection Digital input Input control Output data DC test * CMOS level output * CMOS Schmidt input No standby control DC test F Input Standby control signal = 1 (fixed) Output data DC test H DC test Input 10 * CMOS level output * CMOS Schmidt input No standby control MB91191 Series BLOCK DIAGRAM RAM 256 byte PPG0 P37/D31 FR20 CPU core I-bus D-bus I-bus D-bus C-bus Port 6 Port 5 RAM 6 KB RAM 2 KB D-bus ROM 254 KB RAM 128 byte Serial ch 0 RAM 128 byte Serial ch 1 RAM 128 byte Serial ch 2 12-bit PWM00-02 16-bit timers 0 to 3 12-bit PWM10-12 P11/EC4/INT0 8/16-bit timer Interrupt controller External interrupts 16-bit timer 4 24-bit FRC RFG1 X0 X1 OSC C-unit OSCI OSCO OSC 10-bit programmable prescaler PD0/SI2 PD1/SO2 PD2/SCK2 PD3/SI1/INT2 PD4/SO1 PD5/SCK1 PD6/SCS0 PD7/SI0 PC0/S00 PC1/SCK0 PC2/PWM5/SCS1 PC3/PWM4/SCS2 PC4/PWM3 PC5/PWM2 PC6/PWM1 PC7/PWM0 INT2 - INT0 (from port 1, D) External interrupts (key inputs) RFG0 P00/RFG1 P87/PPG11 P86/PPG10 P85/PPG09 P84/PPG08 P83/PPG07 P82/PPG06 P81/PPG05 P80/PPG04 P94/PPG03 P93/PPG02 P92/PPG01 P91/PPG00 P90/P0 16-bit RTG0-2 CFG DFG P47 P46/PPG18 P45/PPG17 P44/PPG16 P43/PPG15 P42/PPG14 P41/PPG13 P40/PPG12 RTG4 - RTG0 (to port 1) 8-bit PWC Port 0 P10/PMSK P07/EXI2/PMI P06/EXI1 P05/EXI0 P04/CFG P03/DFG P02/DPG P01/RFG0 R-bus 10-bit A/DC FIFO 29-bit x 8 FIFO FIFO (software) (hardware) Port A/B P17/RTG4 P16/RTG3 P15/RTG2 P14/RTG1 P13/RTG0 P12/EC5/INT1 Port 1 P70/XOUT Port 7 External bus control Port 8/9 Bit search P20/D16 P57/A15 P50/A08 P60/RD P61/WR0 P62/WR1 P63/ALE P64 P65 P66/T501 P67/T40 RAM 64 byte PPG1 Port C/D Port 2/3 P30/D24 P27/D23 Port 4 Mode control MD0 MD1 MD2 RST PA7/AN-F/KEY7 PA6/AN-E/KEY6 PA5/AN-D/KEY5 PA4/AN-C/KEY4 PA3/AN-B/KEY3 PA2/AN-A/KEY2 PA1/AN-9/KEY1 PA0/AN-8/KEY0 PB7/AN-7 PB6/AN-6 PB5/AN-5 PB4/AN-4 PB3/AN-3 PB2/AN-2 PB1/AN-1 PB0/AN-0 11 MB91191 Series (Bus names) * I bus : 16-bit bus for internal instructions. As the FR family of CPUs use the Harvard architecture, instructions and data use separate buses. A bus converter is connected to the I bus. * D bus : Internal 32-bit data bus. The internal peripherals are connected to the D bus. * C bus : Internal multiplexed bus. Connected to the I and D buses via a switch. An external interface module is connected to the C bus. Data and instructions are multiplexed on the external data bus. * R bus : Internal 16-bit data bus. The R bus connects to the D bus via an adapter. The I/O, clock oscillator, and interrupt controller are connected to the R bus. As the R bus is only 16 bits wide, address and data are multiplexed on the bus and therefore multiple cycles are required when the CPU accesses these resources. 12 MB91191 Series ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter (VSS = AVSS = 0 V) Symbol Rating Unit Remarks Min. Max. VDD VSS - 0.3 VSS + 3.5 V Analog power supply voltage AVDD VSS - 0.3 VSS + 3.5 V *1 Analog reference voltage AVRH VSS - 0.3 VSS + 3.5 V *1 Input voltage VI VSS - 0.3 VSS + 3.5 V *2 Output voltage VO VSS - 0.3 VSS + 3.5 V *2 "L" level maximum output current IOL 10 mA *3 "L" level average output current IOLAV 8 mA *4 "L" level total maximum output current IOL 100 mA IOLAV 50 mA *5 IOH -10 mA *3 "H" level average output current IOHAV -4 mA *4 "H" level total maximum output current IOH -50 mA "H" level total average output current IOHAV -20 mA Power consumption PD 500 mW Operating temperature TA -20 +70 C Tstg -55 +150 C Power supply voltage "L" level total average output current "H" level maximum output current Storage temperature *5 *1 : Ensure that these do not exceed VDD + 0.3 V. Also ensure that AVDD does not exceed VDD, including at power-on. *2 : VI and VO may not exceed VDD + 0.3 V. *3 : The maximum output current is the peak value for a single pin. *4 : The average output current is the average current for a single pin over a period of 100 ms. *5 : The total average output current is the average current for all pins over a period of 100 ms. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 13 MB91191 Series 2. Recommended Operating Conditions Parameter Power supply voltage Symbol VDD (VSS = AVSS = 0 V) Value Min. Max. 2.7 3.3 2.0 3.3 Unit Normal operation V Analog power supply voltage AVDD VSS - 0.3 VDD + 0.2 V Analog reference voltage AVRH AVSS AVDD V TA -20 70 C Operating temperature Remarks Maintaining RAM state in stop mode WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 14 MB91191 Series 3. DC Characteristics Parameter Sym bol 0.7 VDD VDD + 0.3 V VDD - 0.4 VDD + 0.3 V 0.8 VDD VDD + 0.3 V VDD VDD + 0.3 V *3 VSS - 0.3 0.2 VDD V *1 VSS - 0.3 VSS + 0.4 V VSS - 0.3 0.2 VDD V VSS - 0.3 VSS V VOH1 *4 VDD = 3.0 V, IOH = -4.0 mA 2.4 V 2.4 V MB91191/R VOH2 *5, *6 VDD = 3.0 V, IOH = -8.0 mA 2.4 V MB91F191A 2.4 V MB91191/R VDD = 3.0 V, IOL = 4.0 mA VDD = 3.0 V, IOL = 8.0 mA VDD = 3.0 V, IOL = 1.0 mA 0.6 V 0.6 V 0.3 V VDD = 3.0 V, VSS < VI < VDD 1 5 A 8 20 A 50.1 60 mA MB91F191A 16 25 mA MB91191/R 24 36 mA MB91F191A 13 18 mA MB91191/R 1 240 A MB91F191A 10 300 A MB91191/R VIH "H" level input voltage Pin Name VIHS *3 *1 *2 VIHM MD2 to MD0 VIL "L" level input voltage VILS *2 VILM MD2 to MD0 "H" level output voltage VOL1 *4 "L" level output voltage VOL2 *5, *6 VOL3 *4, *5, *6 Input leak current Power supply current (VDD = 3.0 V 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value Condition Unit Remarks Min. Typ. Max. ILI1 *2 ILIX X0, OSCI IDD VDD = 3.0 V, *7 IDDS VDD VDD = 3.0 V, *8 IDDH VDD = 3.0 V, TA = 25 C, *9 MB91F191A MB91191/R Input 10 pF CIN Other than VDD, VSS, AVDD, AVSS, and AVRH capacitance *1 : X0, X1, OSCI, OSCO *2 : XRST, PC3 to PC1, PD6, PD5, PD3, PD2, PA7 to PA0, P12 to P10, P07 to P00, PD7, PD0 *3 : Inputs other than *1, *2, MD2 to MD0 *4 : P07 to P00, P17 to P10, P27 to P20, P47 to P40, P67 to P60, P70, P87 to P80, P94 to P90, PA7 to PA0, PB7 to PB0, PC7 to PC2, PD7, PD6, PD3, PD0 *5 : P37 to P30, P57 to P50 *6 : PD5, PD4, PD2, PD1, PC1, PC0 *7 : Operating current for X0 = 20 MHz, OSCI = VSS (fixed) , all port outputs = low, gear selection : CPU = 10 MHz, peripherals = 20 MHz *8 : Operating current in sleep mode for X0 = 20 MHz, OSCI = VSS (fixed), all port outputs = low, gear selection : CPU = 10 MHz, peripherals = 20 MHz *9 : Operating current in stop mode for X0 = 20 MHz, OSCI = VSS (fixed) , all port outputs = low, gear selection : CPU = 10 MHz, peripherals = 20 MHz 15 MB91191 Series 4. AC Characteristics (1) Clock Timings Parameter (VDD = 3.0 V 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value Condition Unit Remarks Min. Max. Symbol Clock frequency Clock cycle time 1 Frequency fluctuation* (PLL locked) fC 10 20 MHz tC 50 100 ns r 10 % 20*2 ns 8 ns 5 20 MHz 10 20 MHz 50 200 ns 50 100 ns PWH Input clock pulse width PWL tCR Input clock rise/fall time tCF Internal operating clock CPU frequency Peripherals Internal operating clock CPU cycle time Peripherals fCP When wait controller set to 1 wait cycle fCPP tCP tCPP *1 : The frequency fluctuation value is the maximum percentage deviation from the preset center frequency when using the multiplier (when PLL is locked) . *2 : Values are for minimum clock frequency (10 MHz) input to X0, oscillator circuit = 1/2, and gear ratio = 1/8. + || f = f0 x 100 (%) + Center frequency f0 - - tc PWH PWL Power supply voltage (V) tcf 3.3 Guaranteed operation range fcpp 2.7 fcp 10 M 20 M Frequency (Hz) 16 tcr MB91191 Series The figure below shows the relationship between the X0 input and the internal clock based on the GCR (Gear Control Register) CHC, CCK1, and CCK0 bit settings. X0 input Source oscillation x 1 (CHC bit in GCR = 0) (a) gear x 1 Internal clock tCYC CCK1/0:00 (b) gear x 1/2 Internal clock tCYC CCK1/0:01 (c) gear x 1/4 tCYC Internal clock CCK1/0:10 (d) gear x 1/8 tCYC Internal clock CCK1/0:11 Source oscillation x 1/2 (CHC bit in GCR = 1) (a) gear x 1 Internal clock tCYC CCK1/0:00 (b) gear x 1/2 Internal clock tCYC CCK1/0:01 (c) gear x 1/4 Internal clock tCYC CCK1/0:10 (d) gear x 1/8 Internal clock tCYC CCK1/0:11 Where tCYCH is the H level width of the internal clock and tCYCL is the L level width. For example, when set to source oscillation x 1/2, gear x 1/4 and X0 input frequency = 20 MHz : tCYC = 400 ns, tCYCH = 350 ns, tCYCL = 50 ns 17 MB91191 Series (2) Multiplex Bus Read/Write Operation Parameter Symbol (VDD = +3.0 V 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value CondiRePin Name Unit tion marks Min. Typ. Max. ALE pulse width tEHEL ALE Address delay time tEHAV Address clear time tEHAX A15 to A0 D31 to D16 Data delay time tELDV D31-D16 RD delay time tELRL RD pulse width tRLRH WR0, WR1 delay time tELWL WR0, WR1 pulse width tWLWH Data setup RDX time tDSRH RDX Data hold time tRHDX RD WR0, WR1 RD D31 to D16 tCYC - 10 ns tCYCH - 15 tCYCH tCYCH + 15 ns *2 tCYCL - 2 tCYCL tCYCL + 10 ns *2 tCYCL + 26 ns *2 tCYC - 11 tCYC tCYC + 11 ns tCYC - 11 tCYC tCYC + 11 ns tCYC - 11 tCYC tCYC + 11 ns tCYC - 11 tCYC tCYC + 11 ns 15 ns 0 ns *1 *1 *1 : When the bus is delayed by automatic wait insertion, add (tCYC x number of wait cycles) to this value. *2 : This value is for gear setting = x1 For the value for gear settings 1/2, 1/4, and 1/8, substitute 1/2, 1/4, and 1/8 respectively for n in the formula below. Formula : tCYCH = (1 - n / 2) x tCYC tCYCL = (n / 2) x tCYC Internal clock tEHEL ALE tEHAV tELAX tDSRH tRHDX Read time D31 - D16 MPX bus RD tELRL Write time D31 - D16 MPX bus tRLRH tWHDX tELDV WR0 , WR1 tELWL A15 - A08 When not multiplexed 18 tWLWH MB91191 Series (3) Reset Input Ratings Parameter Reset input time Symbol Pin Name tRSTL RST (VDD = 3.0 V 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value Unit Remarks Min. Max. 5 tCP ns tRSTL RST 0.2 VDD (4) Power-On Reset Paramete (VDD = 3.0 V 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value Pin Name Unit Remarks Min. Max. Symbol Power supply rise time tR Power supply cutoff time tOFF Oscillation stabilization delay time tOSC VDD 20 ms 2 ms 221 tc ns tOFF tR 2.7 V VDD 0.2 V Sudden changes in the power supply voltage may cause a power-on reset. The recommended practice if you wish to change the power supply voltage while the device is operating is to raise the voltage smoothly. 3.0 V VDD 2.0 V Maintain RAM data Recommended rate of voltage rise is 50 mV/ms or less. VSS VDD tOSC (Oscillation stabilization delay time) RST tRSTL When turning on the power, start with the RST pin in the "L" level state and allow a time of tRST Lafter reaching the VDD power supply level before changing the pin to the "H" level. 19 MB91191 Series (5) Serial I/O (CH0 to 2) Symbol Parameter (VDD = +3.0 V 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value Condition Unit Remarks Min. Max. 8 tCPP ns -10 50 ns 50 ns tSHIX 50 ns Serial clock "H" pulse width tSHSL 4 tCPP - 10 ns Serial clock "L" pulse width tSLSH 4 tCPP - 10 ns SCK SO delay time tSLOV 0 50 ns Valid SI SCK tIVSH 50 ns SCK valid SI hold time tSHIX 50 ns Serial busy time tBUSY 6 tCPP ns SCS SCK, SO delay time tCLZO 50 ns SCS SCK input mask time tCLSL 3 tCPP ns SCS SCK, SO Hi-Z time tCHOZ 50 ns Serial clock cycle time tSCYC SCK SO delay time tSLOV Valid SI SCK tIVSH SCK valid SI hold time Internal clock External clock * Internal shift clock mode tSCYC SCK tSLOV SO SI tIVSH tSHIX * External shift clock mode tSLSH tCLZO tSHSL SCK tSLOV SO SI tIVSH tSHIX SCS tCLSL 20 tBUSY tCHOZ MB91191 Series (6) FG Pulse Input Parameter (VDD = 3.0 V 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value Pin Name Unit Remarks Min. Max. Symbol Servo input "H" pulse width tSPWH Servo input "L" pulse width tSPWL CFG, DFG, DPG, RFG0 to 1, EXI0 to 2 tC + 50 ns tC + 50 ns Note : tC is the clock cycle time of the X0 and X1 pin oscillation. CFG DFG, DPG RFG0 to 1 EXI0 to 2 tSPWH tSPWL tf (7) Timer External Clock Input Parameter Symbol Timer 4 input "H" pulse width tECWH Timer 4 input "L" pulse width tECWL Timer 5 input "H" pulse width tECWH Timer 5 input "L" pulse width tECWL EC4, EC5 tr (VDD = +3.0 V 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value Pin Name Unit Remarks Min. Max. EC4 EC5 tECWH 4 tC + 50 ns 4 tC + 50 ns 4 tCPP ns 4 tCPP ns tECWL tf tr 21 MB91191 Series (8) General-Purpose Prescaler Parameter Symbol PCK input clock frequency fCP PCK input "H" pulse width tSPWH PCK input "L" pulse width tSPWL PCK input Fall time tf Rise time tr PO output delay time (VDD = 3.0 V 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value Pin Name Unit Remarks Min. Max. tPOPI 12 MHz 33 ns 33 ns PCK 100 ns PO 80 ns PCK tSPWH tf tSPWL PCK tPOPI PO 22 tr MB91191 Series 5. Electrical Characteristics for the A/D Converter (VDD = 3.0 V + 0.3 V, VSS = AVSS = 0 V, TA = -20 C to +70 C) Value Condition Unit Remarks Min. Typ. Max. Sym bol Pin Name Resolution 10 bit Conversion time 8.4 s Total error 4.0 LSB Linearity error 3.5 LSB Differential linearity error 2.0 LSB Zero transition error VOT AVSS - 1.5 AVSS + 0.5 AVSS + 2.5 LSB AVRH - 5.5 AVRH - 1.5 AVRH + 0.5 LSB Parameter Full-scale transition error VFST VDD = AVDD = 3.0 V, AVRH = 3.0 V AN-0 to AN-F VDD = AVDD = 3.0 V, AN-0 to AVRH = 3.0 V AN-F Analog input current IAIN AN-0 to AN-F 0.1 10 A Analog input voltage VAIN AN-0 to AN-F AVSS AVRH V Reference voltage AVRH AVRH AVDD V 3.0 mA 5.0 A 100 A 10 A 4 LSB Power supply current Reference voltage supply current During conversion IA Conversion halted IAH During conversion IR Conversion halted IRH Variation between channels AVDD AVRH AN-0 to AN-F VDD = AVDD = 3.0 V VDD = AVDD = 3.0 V, AVRH = 3.0 V Notes : * The relative error increases as |AVRH| becomes smaller. * Ensure that the output impedance of the external circuit connected to the analog input meets the following condition : Output impedance of external circuit < 7 k (approx.) If the output impedance of the external circuit is too high, the analog voltage sampling time may be too short. (Sampling time = 6.4 s for a 20 MHz machine clock) 23 MB91191 Series 6. A/D Converter Glossary * Resolution : The change in analog voltage that can be recognized by the A/D converter. * Linearity error The deviation between the actual conversion characteristics and the line linking the zero transition point ("00 0000 0000B" "00 0000 0001B") and the full scale transition point ("11 1111 1110B" "11 1111 1111B") . * Differential linearity error The variation from the ideal input voltage required to change the output code by 1 LSB. * Total error The total error is the difference between the actual value and the theoretical value. Includes the zero transition error, full-scale transition error and linearity error. Total Error 3FF 3FE Digital Output 3FD 1.5 LSB' Actual conversion characteristic {1 LSB' x (N - 1) + 0.5 LSB'} 004 VNT (Measured value) 003 Actual conversion characteristic 002 Theoretical characteristic 001 0.5 LSB' AVSS Analog Input AVRH - AVSS [V] 1024 Total error for digital output N = VNT - {1 LSB' x (N - 1) + 0.5 LSB'} 1 LSB' 1 LSB' (Theoretical) = VOT' (Theoretical) = AVSS + 0.5 LSB' [V] VFST' (Theoretical) = AVRH - 1.5 LSB' [V] VNT : Voltage at which digital output changes from (N + 1) to N 24 AVRH MB91191 Series Differential Linearity Error Linearity Error 3FF Actual conversion characteristic N+1 {1 LSB x (N - 1) + VoT'} VFST (Measured value) Digital Output 3FD 004 VNT (Measured value) 003 002 Digital Output 3FE Actual conversion characteristic Theoretical characteristic N N-1 Actual conversion characteristic Theoretical characteristic N-2 001 VOT (Measured value) AVSS Analog Input AVSS AVRH Linearity error for VNT - {1 LSB x (N - 1) + VOT} = digital output N 1 LSB' VFST (Measured VNT value) (Measured value) Actual conversion characteristic Analog Input AVRH [LSB] Differential linearity error V (N+1) T - VNT = - 1 LSB [LSB] for digital output N 1 LSB' VOT' (Theoretical) = VFST - VOT 1022 [V] VOT : Voltage at which digital output changes from (000) H to (001) H. VFST : Voltage at which digital output changes from (3FE) H to (3FF) H. 25 MB91191 Series ORDERING INFOMATION Part No. MB91191PFF 26 Package Plastic LQFP, 120-pin (FPT-120P-M05) Remarks MB91191 Series PACKAGE DIMENSION Plastic LQFP, 120-pin (FPT-120P-M05) +0.20 16.000.20(.630.008)SQ 14.000.10(.551.004)SQ 90 1.50 0.10 +.008 .059 .004 61 (Mounting height) 0.100.10 (STAND OFF) (.004.004) 91 60 Details of "A" part 11.60 (.457) REF 0.15(.006) 0.10(.004)MAX 0.36(.014)MAX 1 PIN INDEX 120 31 "A" LEAD No. 15.00 (.591) NOM 0.15(.006) Details of "B" part 1 0.40(.0157)TYP 30 +0.08 0.14 0.03 +.003 .006 .001 0.065(.003) +0.05 0.127 0.02 +.002 .005 .001 M 0 "B" 0.10(.004) C 10 0.500.20 (.020.008) 1995 FUJITSU LIMITED F120006S-2C-3 Dimensions in mm (inches). 27 MB91191 Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 F0107 FUJITSU LIMITED Printed in Japan All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.