DS07-16202-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
32-bit Proprietary Microcontroller
CMOS
FR Family MB91191 Series
MB91191/MB91F191A/MB91191R
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■■
■DESCRIPTION
The MB91191 is a single-chip microcontroller using a 32-bit RISC-CPU (FR series) as its core. It contains
peripheral I/O resources suitable f or softw are serv o control in applications such as VTRs that require high-speed
CPU processing.
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■■
■FEATURES
CPU
• 32-bit RISC (FR series) , load/store architecture, 5-stage pipeline
• General-purpose registers : 16 × 32-bit
• 16-bit fixed-length instructions (basic instructions) , 1 instruction per cycle
• Includes memory-to-memory transfer, bit manipulation, and barrel shift instructions :
Optimized for embedded applications
• Includes function entry/exit instructions and multiple-register load/store instructions :
Instruction set supports high le vel languages
• Register interlock function : For efficient assembly language coding
• Branch instructions with delay slots : Reduced overhead for branch operations
• Internal multiplier unit is supported at instruction level
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
• Interrupts (PC and PS saving) : 6 cycles, 16 priority levels
(Continued)
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■PACKAGE
Plastic, LQFP, 120-pin
(FPT-120P-M05)
MB91191 Series
2
(Continued)
Bus Interface
• 16-bit address output, 8/16-bit data input and output
• Basic bus cycle : 2 clock cycles
• Supports interfaces for various types of memory
• Multiplexed data/address input/output
• Automatic wait cycles : Between 0 and 7 wait cycles can be specified independently for each memory area
• Unused data/address pins can be configured as input/output ports
• Supports little endian mode
Bit Search Module
• Searches, starting from the MSB, for the position of the first 1/0 bit transition in a word. The operation is
performed in one cycle.
Serial I/O
• 3 channels with internal buffer RAM (automatic transfer of up to 128 bytes)
• Independent send and receive buffer mode (automatic transfer of up to 64 bytes)
A/D Converter (Successive Approximation Type)
• 10-bit × 16 channels
• Uses successive approximation conversion method (conversion time : 8.4 µs @ 20 MHz)
• Channel scan function
• Hardware and software conversion start functions
• Internal FIFO (Software conversion : 6 stages, Hardware conversion : 6 stages)
Timers
• 16-bit × 4 channels
• 16-bit timer/counter × 1 channel (with square wave output)
• 8/16-bit timer/counter × 1 channel (with square wave output)
FG input unit
• Incorporates capstan, drum, and reel input circuits
Capture unit
• Internal 24-bit free-run counter (Minimum resolution = 50 ns @ 20 MHz)
• Internal FIFO (Data : 21-bit × 8, Detection : 8-bit × 8)
Programmable pattern generator
• Inter nal RAM buffer (PPG0 : 256 bytes, PPG1 : 64 bytes)
• Output timing resolution : 800 ns @ 20 MHz
• Includes an A/D converter hardware start function
Realtime timing generator
• RTG : 3 circuits
• Output timing resolution : 400 ns or 800 ns selectable
• Timing output ports : 5 ports
PWM
• 12-bit PWM × 6 channels (rate, mu lti-type)
• Base frequency = 78.1 kHz or 39.0 kHz (@ 20 MHz) selectable
(Continued)
MB91191 Series
3
(Continued)
PWC
•8-bit PWC × 1 channel (with mask input)
• Measurement resolution : 400ns @ 20 MHz
General-purpose prescaler
• 10-bit prescaler × 1 channel (with square wave and pulse outputs)
• Dedicated inter nal oscillator circuit
• Includes load function driven by PPG output
Interrupt control
• External interrupts : 3 inputs
• Key input interrupt : 8 inputs
MB91191 Series
4
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■PIN ASSIGNMENT
PA0/AN-8/KEY0
PB7/AN-7
PB6/AN-6
PB5/AN-5
PB4/AN-4
PB3/AN-3
PB2/AN-2
PB1/AN-1
PB0/AN-0
AVDD
AVRH
AVSS
VSS
P17/RTG4
P16/RTG3
P15/RTG2
P14/RTG1
P13/RTG0
P12/EC5/INT1
P11/EC4/INT0
P10/PMSK
P07/EXI2/PMI
P06/EXI1
P05/EXI0
P04/CFG
P03/DFG
P02/DPG
P01/RFG0
P00/RFG1
VDD
P93/PPG02
P94/PPG03
P80/PPG04
P81/PPG05
P82/PPG06
P83/PPG07
P84/PPG08
P85/PPG09
P86/PPG10
P87/PPG11
P40/PPG12
P41/PPG13
P42/PPG14
P43/PPG15
P44/PPG16
P45/PPG17
P46/PPG18
P47
P57
P56
P55
P54
P53
P52
P51
P50
VSS
P37
P36
P35
A15
A14
A13
A12
A11
A10
A09
A08
D31/A07
D30/A06
D29/A05
P57
P56
P55
P54
P53
P52
P51
P50
D31/A15
D30/A14
D29/A13
PA1/AN-9/KEY1
PA2/AN-A/KEY2
PA3/AN-B/KEY3
PA4/AN-C/KEY4
PA5/AN-D/KEY5
PA6/AN-E/KEY6
PA7/AN-F/KEY7
PD0/SI2
PD1/SO2
PD2/SCK2
PD3/SI1/INT2
PD4/SO1
PD5/SCK1
PD6/SCS0
PD7/SI0
PC0/SO0
PC1/SCK0
PC2/PWM5/SCS1
PC3/PWM4/SCS2
PC4/PWM3
PC5/PWM2
PC6/PWM1
PC7/PWM0
VSS
OSCI/PCK
OSCO
VDD
P90/P0
P91/PPG00
P92/PPG01
ALE
WR1
WR0
RD
A00/D16
A01/D17
A02/D18
A03/D19
A04/D20
A05/D21
A06/D22
A07/D23
A08/D24
A09/D25
A10/D26
A11/D27
A12/D28
ALE
P62
WR0
RD
P20
P21
P22
P23
P24
P25
P26
P27
A00/D24
A01/D25
A02/D26
A03/D27
A04/D28
X0
X1
VSS
MD2
MD1
MD0
RST
P70/XOUT
P67/T40
P66/T501
P65
P64
P63
P62
P61
P60
P20
P21
P22
P23
P24
P25
P26
P27
VDD
P30
P31
P32
P33
P34
16-bit MPX mode
8-bit MPX mode
95
100
105
110
115
120
90
85
80
75
70
65
5
10
15
20
25
30
60
55
50
45
40
35
(TOP VIEW)
(FPT-120P-M05)
MB91191 Series
5
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■PIN DESCRIPTIONS
(Continued)
Pin No. Pin Name Circuit
Type Function
1 X0 (I) A Crystal oscillator pins
2 X1 (O)
3V
SS VSS pin
4MD2
BOperation mode setting pins
CMOS Schmidt inputs
5MD1
6MD0
7RST B Reset input pin. CMOS Schmidt input.
8 P70/XOUT C Shared pin with clock output (X0/2, PCK/2) . CMOS input.
9 P67/T40
C
Shared pin with timer 4 square wave output. CMOS input.
10 P66/T501 Shared pin with timer 5 square wave output. CMOS input.
11 P65 General-purpose I/O port. CMOS input.
12 P64 General-purpose I/O port. CMOS input.
13 P63/ALE/ALE Shared pin with address strobe output. CMOS input.
14 P62/P62/WR1 Shared pin with write strobe output 1. CMOS input.
15 P61/WR0/WR0 Shared pin with write strobe output 0. CMOS input.
16 P60/RD/RD Shared pin with read strobe output. CMOS input.
17 P20/P20/D16 : A00
CGeneral-purpose I/O ports.
CMOS inputs.
18 P21/P21/D17 : A01
19 P22/P22/D18 : A02
20 P23/P23/D19 : A03
21 P24/P24/D20 : A04
22 P25/P25/D21 : A05
23 P26/P26/D22 : A06
24 P27/P27/D23 : A07
25 VDD Power supply pin
26 P30/D24 : A00/D24 : A08
CShared external bus pins and high-current I/O ports.
CMOS inputs.
27 P31/D25 : A01/D25 : A09
28 P32/D26 : A02/D26 : A10
29 P33/D27 : A03/D27 : A11
30 P34/D28 : A04/D28 : A12
31 P35/D29 : A05/D29 : A13
32 P36/D30 : A06/D30 : A14
33 P37/D31 : A07/D31 : A15
34 VSS VSS pin
MB91191 Series
6
(Continued)
Pin No. Pin Name Circuit
Type Function
35 P50/A08/P50
CShared external bus pins and high-current I/O ports.
CMOS inputs.
36 P51/A09/P51
37 P52/A10/P52
38 P53/A11/P53
39 P54/A12/P54
40 P55/A13/P55
41 P56/A14/P56
42 P57/A15/P57
43 P47
C
General-purpose I/O port. CMOS input.
44 P46/PPG18
Shared pins with PPG outputs.
CMOS inputs.
45 P45/PPG17
46 P44/PPG16
47 P43/PPG15
48 P42/PPG14
49 P41/PPG13
50 P40/PPG12
51 P87/PPG11
CShared pins with PPG outputs.
CMOS inputs.
52 P86/PPG10
53 P85/PPG09
54 P84/PPG08
55 P83/PPG07
56 P82/PPG06
57 P81/PPG05
58 P80/PPG04
59 P94/PPG03 CShared pins with PPG outputs.
CMOS inputs.
60 P93/PPG02
61 P92/PPG01
CShared pins with PPG outputs.
CMOS inputs.
62 P91/PPG00
63 P90/P0 Shared pin with general-purpose prescaler output. CMOS input.
64 VDD Power supply pin
65 OSCO (O) ACrystal oscillator pins for dedicated general-purpose prescaler oscil-
lation.
66 OSCI/PCK (I)
67 VSS VSS pin
MB91191 Series
7
(Continued)
Pin No. Pin Name Circuit
Type Function
68 PC7/PWM0
CShared pins with PWM outputs.
CMOS inputs.
69 PC6/PWM1
70 PC5/PWM2
71 PC4/PWM3
72 PC3/PWM4/SCS2
F
Shared pin with PWM output and serial 2 chip select.
CMOS Schmidt input.
73 PC2/PWM5/SCS1 Shared pin with PWM output and serial 1 chip select.
CMOS Schmidt input.
74 PC1/SCK0 Shared pin with serial 0 shift clock.
CMOS Schmidt input.
75 PC0/SO0 C Shared pin with serial 0 serial output. CMOS input.
76 PD7/SI0
F
Shared pin with serial 0 serial input.
CMOS Schmidt input.
77 PD6/SCS0 Shared pin with serial 0 chip select input.
CMOS Schmidt input.
78 PD5/SCK1 Shared pin with serial 1 shift clock.
CMOS Schmidt input.
79 PD4/SO1 C Shared pin with serial 1 serial output. CMOS input.
80 PD3/SI1/INT2 F
Shared pin with serial 1 serial input and external interrupt 2.
CMOS Schmidt input.
81 PD2/SCK2 Shared pin with serial 2 shift clock.
CMOS Schmidt input.
82 PD1/SO2 C Shared pin with serial 2 serial output. CMOS input.
83 PD0/SI2 F Shared pin with serial 2 serial input.
CMOS Schmidt input.
84 PA7/AN-F/KEY7
EShared pins with analog inputs and key inputs.
CMOS Schmidt inputs
85 PA6/AN-E/KEY6
86 PA5/AN-D/KEY5
87 PA4/AN-C/KEY4
88 PA3/AN-B/KEY3
89 PA2/AN-A/KEY2
90 PA1/AN-9/KEY1
91 PA0/AN-8/KEY0
MB91191 Series
8
(Continued)
Pin No. Pin Name Circuit
Type Function
92 PB7/AN-7
DShared pins with analog inputs.
CMOS Schmidt inputs.
93 PB6/AN-6
94 PB5/AN-5
95 PB4/AN-4
96 PB3/AN-3
97 PB2/AN-2
98 PB1/AN-1
99 PB0/AN-0
100 AVDD A/D converter power supply pin
101 AVRH A/D converter reference power supply pin
102 AVSS A/D converter VSS pin
103 VSS VSS pin
104 P17/RTG4
CShared pins with RTG outputs.
CMOS inputs.
105 P16/RTG3
106 P15/RTG2
107 P14/RTG1
108 P13/RTG0
109 P12/EC5/INT1
F
Shared pin with timer 5 clock input and external interrupt input.
CMOS Schmidt input.
110 P11/EC4/INT0 Shared pin with timer 4 clock input and external interrupt input.
CMOS Schmidt input.
111 P10/PMSK Shared pin with PWC mask input. CMOS Schmidt input.
112 P07/EXI2/PMI
F
Shared pin with external capture input and PWC input.
CMOS Schmidt input.
113 P06/EXI1 Shared pin with external capture input.
CMOS Schmidt input.
114 P05/EXI0
115 P04/CFG Shared pin with capstan FG input. CMOS Schmidt input.
116 P03/DFG Shared pin with drum FG input. CMOS Schmidt input.
117 P02/DPG Shared pin with drum pulse input. CMOS Schmidt input.
118 P01/RFG0 Shared pins with reel FG inputs.
CMOS Schmidt inputs.
119 P00/RFG1
120 VDD Power supply pin
MB91191 Series
9
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■I/O CIRCUITS
(Continued)
Type Circuit Remarks
A
• Oscillation feedback
resistor : 1 MΩ approx.
B
• CMOS Schmidt input
C
• CMOS level output
• CMOS input
No standby control
D
• CMOS level output
• CMOS input
with input control
• Analog input
X0,OSCI
X1,OSCO
Clock input
Standby control signal
Input
Standby control signal = 1 (fixed)
Output data
Input
DC test
DC test
Input control
Output data
DC test
DC test
Analog input
CH selection
Digital input
MB91191 Series
10
(Continued)
Type Circuit Remarks
E
• CMOS level output
• CMOS Schmidt input
with input control
• Analog input
F
• CMOS level output
• CMOS Schmidt input
No standby control
H
• CMOS level output
• CMOS Schmidt input
No standby control
Input control
Input data
DC test
DC test
Analog input
CH selection
Digital input
Standby control signal = 1 (fixed)
Output data
Input
DC test
DC test
Output data
Input
DC test
DC test
MB91191 Series
11
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■BLOCK DIAGRAM
P47
P46/PPG18
P45/PPG17
P44/PPG16
P43/PPG15
P42/PPG14
P41/PPG13
P40/PPG12
P87/PPG11
P86/PPG10
P85/PPG09
P84/PPG08
P83/PPG07
P82/PPG06
P81/PPG05
P80/PPG04
P94/PPG03
P93/PPG02
P92/PPG01
P91/PPG00
P90/P0
PD0/SI2
PD1/SO2
PD2/SCK2
PD3/SI1/INT2
PD4/SO1
PD5/SCK1
PD6/SCS0
PD7/SI0
PC0/S00
PC1/SCK0
PC2/PWM5/SCS1
PC3/PWM4/SCS2
PC4/PWM3
PC5/PWM2
PC6/PWM1
PC7/PWM0
PA7/AN-F/KEY7
PA6/AN-E/KEY6
PA5/AN-D/KEY5
PA4/AN-C/KEY4
PA3/AN-B/KEY3
PA2/AN-A/KEY2
PA1/AN-9/KEY1
PA0/AN-8/KEY0
PB7/AN-7
PB6/AN-6
PB5/AN-5
PB4/AN-4
PB3/AN-3
PB2/AN-2
PB1/AN-1
PB0/AN-0
MD0
MD1
MD2
RST
P37/D31
P30/D24
P27/D23
P20/D16
P57/A15
P50/A08
P60/RD
P61/WR0
P62/WR1
P63/ALE
P64
P65
P66/T501
P67/T40
P17/RTG4
P16/RTG3
P15/RTG2
P14/RTG1
P13/RTG0
P12/EC5/INT1
P11/EC4/INT0
P10/PMSK
P07/EXI2/PMI
P06/EXI1
P05/EXI0
P04/CFG
P03/DFG
P02/DPG
P01/RFG0
P00/RFG1
P70/XOUT
X0
X1
OSCI
OSCO
Mode control
Port 2/3
Port 5
Port 6
Port 7
Port 1
Port 0
OSC
OSC
FR20 CPU core
I-bus
I-bus
D-bus
D-bus
D-bus
C-bus
RAM 2 KB
ROM 254 KB
External bus control
16-bit timers 0 to 3
8/16-bit timer
16-bit timer 4
8-bit PWC
Interrupt
controller
CFG
DFG
RFG0
RFG1
C-unit
10-bit programmable
prescaler
24-bit
FRC
FIFO
29-bit × 8
RAM 256 byte PPG0
PPG1
RAM 64 byte
Bit search
RAM 6 KB
R-bus
RAM
128 byte Serial
ch 0
RAM
128 byte Serial
ch 1
RAM
128 byte Serial
ch 2
12-bit PWM00-02
12-bit PWM10-12
External interrupts
16-bit RTG0-2
External interrupts
(key inputs)
10-bit A/DC
FIFO
(software) FIFO
(hardware)
Port 4
Port 8/9Port C/DPort A/B
INT2 - INT0 (from port 1, D)
RTG4 - RTG0 (to port 1)
MB91191 Series
12
(Bus names)
• I b us : 16-bit b us f or internal instructions. As the FR f amily of CPUs use the Harvard architecture, instructions
and data use separate buses. A bus converter is connected to the I bus.
• D bus : Internal 32-bit data bus. The internal peripherals are connected to the D bu s.
• C bus : Inter nal multiplexed bus. Connected to the I and D bu ses via a switch. An external interface module
is connected to the C bus. Data and instructions are multiplexed on the external data bus.
• R b us : Internal 16-bit data bus . The R bus connects to the D b us via an adapter. The I/O, clock oscillator, and
interrupt controller are connected to the R bus. As the R bus is only 16 bits wide, address and data
are multiplexed on the bus and therefore multiple cycles are required when the CPU accesses these
resources.
MB91191 Series
13
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■ELECTRICAL CHARACTERISTICS
1. Absolute Maximu m Ratings (VSS = AVSS = 0 V)
*1 : Ensure that these do not exceed VDD + 0.3 V.
Also ensure that AVDD does not exceed VDD, including at power-on.
*2 : VI and VO may not exceed VDD + 0.3 V.
*3 : The maximum output current is the peak value for a single pin.
*4 : The average output current is the average current for a single pin over a period of 100 ms.
*5 : The total average output current is the average current for all pins over a period of 100 ms.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Rating Unit Remarks
Min. Max.
Power supply voltage VDD VSS − 0.3 VSS + 3.5 V
Analog power supply voltage AVDD VSS − 0.3 VSS + 3.5 V *1
Analog reference voltage AVRH VSS − 0.3 VSS + 3.5 V *1
Input voltage VIVSS − 0.3 VSS + 3.5 V *2
Output voltage VOVSS − 0.3 VSS + 3.5 V *2
“L” level maximum output current IOL 10 mA *3
“L” level average output current IOLAV 8mA*4
“L” level total maximum output current ΣIOL 100 mA
“L” level total average output current ΣIOLAV 50 mA *5
“H” level maximum output current IOH −10 mA *3
“H” level average output current IOHAV −4mA*4
“H” level total maximum output current ΣIOH −50 mA
“H” level total average output current ΣIOHAV −20 mA *5
Power consumption PD500 mW
Operating temperature TA−20 +70 °C
Storage temperature Tstg −55 +150 °C
MB91191 Series
14
2. Recommended Operating Conditions (VSS = AVSS = 0 V)
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Value Unit Remarks
Min. Max.
Power supply voltage VDD
2.7 3.3 VNormal operation
2.0 3.3 Maintaining RAM state in
stop mode
Analog power supply voltage AVDD VSS − 0.3 VDD + 0.2 V
Analog reference voltage AVRH AVSS AVDD V
Operating temperature TA−20 70 °C
MB91191 Series
15
3. DC Characteristics (VDD = 3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
*1 : X0, X1, OSCI, OSCO
*2 : XRST, PC3 to PC1, PD6, PD5, PD3, PD2, PA7 to PA0, P12 to P10, P07 to P00, PD7, PD0
*3 : Inputs other than *1, *2, MD2 to MD0
*4 : P07 to P00, P17 to P10, P27 to P20, P47 to P40, P67 to P60, P70, P87 to P80, P94 to P90, PA7 to PA0, PB7
to PB0, PC7 to PC2, PD7, PD6, PD3, PD0
*5 : P37 to P30, P57 to P50
*6 : PD5, PD4, PD2, PD1, PC1, PC0
*7 : Operating current for X0 = 20 MHz, OSCI = VSS (fix ed) , all port outputs = low, gear selection : CPU = 10 MHz,
peripherals = 20 MHz
*8 : Operating current in sleep mode for X0 = 20 MHz, OSCI = VSS (fixed), all port outputs = low, gear selection :
CPU = 10 MHz, peripherals = 20 MHz
*9 : Operating current in stop mode for X0 = 20 MHz, OSCI = VSS (fixed) , all port outputs = low, gear selection :
CPU = 10 MHz, peripherals = 20 MHz
Parameter Sym
bol Pin Name Condition Value Unit Remarks
Min. Typ. Max.
“H” level input
voltage
VIH *3 0.7 VDD VDD + 0.3 V
VIHS *1 VDD − 0.4 VDD + 0.3 V
*2 0.8 VDD VDD + 0.3 V
VIHM MD2 to MD0 VDD VDD + 0.3 V
“L” level input
voltage
VIL *3 VSS − 0.3 0.2 VDD V
VILS *1 VSS − 0.3 VSS + 0.4 V
*2 VSS − 0.3 0.2 VDD V
VILM MD2 to MD0 VSS − 0.3 VSS V
“H” level output
voltage
VOH1 *4 VDD = 3.0 V,
IOH = −4.0 mA 2.4 V MB91F191A
2.4 V MB91191/R
VOH2 *5, *6 VDD = 3.0 V,
IOH = −8.0 mA 2.4 V MB91F191A
2.4 V MB91191/R
“L” level output
voltage
VOL1 *4 VDD = 3.0 V,
IOL = 4.0 mA 0.6 V
VOL2 *5, *6 VDD = 3.0 V,
IOL = 8.0 mA 0.6 V
VOL3 *4, *5, *6 VDD = 3.0 V,
IOL = 1.0 mA 0.3 V MB91191/R
Input leak
current ILI1 *2 VDD = 3.0 V,
VSS < VI < VDD
±1±5µA
ILIX X0, OSCI ±8±20 µA
Power supply
current
IDD
VDD
VDD = 3.0 V, *7 50.1 60 mA MB91F191A
16 25 mA MB91191/R
IDDS VDD = 3.0 V, *8 24 36 mA MB91F191A
13 18 mA MB91191/R
IDDH VDD = 3.0 V,
TA = 25 °C, *9 1 240 µA MB91F191A
10 300 µA MB91191/R
Input
capacitance CIN Other than VDD, VSS,
AVDD, AVSS, and AVRH 10 pF
MB91191 Series
16
4. AC Characteristics
(1) Clock Timings (VDD = 3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
*1 : The frequency fluctuation v alue is the maxim um percentage deviation from the preset center frequency when
using the multiplier (when PLL is locked) .
*2 : Values are for minimum clock frequency (10 MHz) input to X0, oscillator circuit = 1/2, and gear ratio = 1/8.
Parameter Symbol Condition Value Unit Remarks
Min. Max.
Clock frequency fC10 20 MHz
Clock cycle time tC50 100 ns
Frequency fluctuation*1 (PLL locked) ∆r10 %
Input clock pulse width PWH 20*2ns
PWL
Input clock rise/fall time tCR 8ns
tCF
Internal operating clock
frequency CPU fCP When wait
controller set to
1 wait cycle
520MHz
Peripherals fCPP 10 20 MHz
Internal operating clock
cycle time CPU tCP 50 200 ns
Peripherals tCPP 50 100 ns
∆f =Center frequency f0
+α
−α
+
−
| α |
f0× 100 (%)
tc
PWH
tcf
PWL
tcr
Frequency (Hz)
Power supply voltage (V)
3.3
2.7
Guaranteed operation range
fcp
fcpp
10 M 20 M
MB91191 Series
17
The figure below shows the relationship between the X0 input and the inter nal clock based on the GCR (Gear
Control Register) CHC, CCK1, and CCK0 bit settings.
Where tCYCH is the H level width of the internal clock and tCYCL is the L level width.
For example, when set to source oscillation × 1/2, gear × 1/4 and X0 input frequency = 20 MHz : tCYC = 400 ns,
tCYCH = 350 ns, tCYCL = 50 ns
CCK1/0:11
X0 input
Source oscillation × 1
(CHC bit in GCR = 0)
(a) gear × 1 Internal clock
CCK1/0:00
tCYC
tCYC
tCYC
tCYC
tCYC
tCYC
tCYC
tCYC
(b) gear × 1/2 Internal clock
Internal clock
Internal clock
CCK1/0:01
(c) gear × 1/4
Internal clock
CCK1/0:10
(d) gear × 1/8
CCK1/0:11
Source oscillation × 1/2
(CHC bit in GCR = 1)
(a) gear x 1 Internal clock
CCK1/0:00
(b) gear x 1/2
CCK1/0:01
(c) gear x 1/4 Internal clock
CCK1/0:10
(d) gear x 1/8 Internal clock
MB91191 Series
18
(2) Multiplex Bus Read/Write Operation (VDD = +3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
*1 : When the bus is delayed by automatic wait insertion, add (tCYC × number of wait cycles) to this value.
*2 : This value is for gear setting = ×1
For the value for gear settings 1/2, 1/4, and 1/8, substitute 1/2, 1/4, and 1/8 respectively f or n in the formula below .
Formula : tCYCH = (1 − n / 2) × tCYC
tCYCL = (n / 2) × tCYC
Parameter Symbol Pin Name Condi-
tion Value Unit Re-
marks
Min. Typ. Max.
ALE pulse width tEHEL ALE tCYC − 10 ns
Address delay time tEHAV A15 to A0
D31 to D16 tCYCH − 15 tCYCHtCYCH + 15 ns *2
Address clear time tEHAX tCYCL − 2tCYCLtCYCL + 10 ns *2
Data delay time tELDV D31-D16 tCYCL + 26 ns *2
RD delay time tELRL RD tCYC − 11 tCYC tCYC + 11 ns
RD pulse width tRLRH tCYC − 11 tCYC tCYC + 11 ns *1
WR0, WR1 delay time tELWL WR0, WR1 tCYC − 11 tCYC tCYC + 11 ns
WR0, WR1 pulse width tWLWH tCYC − 11 tCYC tCYC + 11 ns *1
Data setup → RDX ↑ time tDSRH RD
D31 to D16 15 ns
RDX ↑→ Data hold time tRHDX 0ns
tWLWH
Internal
clock
ALE
Read time
D31 - D16
MPX bus
RD
Write time
D31 - D16
MPX bus
WR0 , WR1
A15 - A08
When not
multiplexed
tEHEL
tEHAV tELAX tDSRH tRHDX
tELRL tRLRH
tELDV tWHDX
tELWL
MB91191 Series
19
(3) Reset Input Ratings (VDD = 3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
(4) Power-On Reset (VDD = 3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Parameter Symbol Pin Name Value Unit Remarks
Min. Max.
Reset input time tRSTL RST 5 tCP ns
Paramete Symbol Pin Name Value Unit Remarks
Min. Max.
Power supply rise time tRVDD 20 ms
Power supply cutoff time tOFF 2ms
Oscillation stabilization
delay time tOSC 221 tcns
0.2 VDD
RST
tRSTL
VDD
tR
2.7 V
0.2 V
tOFF
When turning on the power, start with
the RST pin in the "L" level state and
allow a time of tRST Lafter reaching
the VDD power supply level before
changing the pin to the "H" level.
VDD 3.0 V
2.0 V
VSS
VDD
RST
Maintain RAM data
tRSTL
Recommended rate of voltage
rise is 50 mV/ms or less.
tOSC
(Oscillation stabilization delay time)
Sudden changes in the power supply voltage may cause a power-on reset.
The recommended practice if you wish to change the power supply voltage while the device is operating
is to raise the voltage smoothly.
MB91191 Series
20
(5) Serial I/O (CH0 to 2) (VDD = +3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Parameter Sym-
bol Condition Value Unit Remarks
Min. Max.
Serial clock cycle time tSCYC
Internal clock
8 tCPP ns
SCK ↓ → SO delay time tSLOV −10 50 ns
Valid SI → SCK ↑tIVSH 50 ns
SCK ↑ → valid SI hold time tSHIX 50 ns
Serial clock “H” pulse width tSHSL
External clock
4 tCPP − 10 ns
Serial clock “L” pulse width tSLSH 4 tCPP − 10 ns
SCK ↓ → SO delay time tSLOV 050ns
Valid SI → SCK ↑tIVSH 50 ns
SCK ↑ → valid SI hold time tSHIX 50 ns
Serial busy time tBUSY 6 tCPP ns
SCS ↓ → SCK, SO delay time tCLZO 50 ns
SCS ↓ → SCK input mask time tCLSL 3 tCPP ns
SCS ↓ → SCK, SO Hi-Z time tCHOZ 50 ns
tSCYC
SCK
tSLOV
SO
SI
tIVSH tSHIX
tCLSL
tCLZO tSLSH
tSLOV
tSHSL tBUSY tCHOZ
SCK
SO
SI
tIVSH tSHIX
SCS
• Internal shift clock mode
• External shift clock mode
MB91191 Series
21
(6) FG Pulse Input (VDD = 3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Note : tC is the clock cycle time of the X0 and X1 pin oscillation.
(7) Timer External Clock Input (VDD = +3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Parameter Symbol Pin Name Value Unit Remarks
Min. Max.
Servo input “H” pulse width tSPWH CFG, DFG, DPG,
RFG0 to 1, EXI0 to 2 tC + 50 ns
Servo input “L” pulse width tSPWL tC + 50 ns
Parameter Symbol Pin Name Value Unit Remarks
Min. Max.
Timer 4 input “H” pulse width tECWH EC4 4 tC + 50 ns
Timer 4 input “L” pulse width tECWL 4 tC + 50 ns
Timer 5 input “H” pulse width tECWH EC5 4 tCPP ns
Timer 5 input “L” pulse width tECWL 4 tCPP ns
CFG
DFG, DPG
RFG0 to 1
EXI0 to 2 tSPWH
tf
tSPWL
tr
EC4,
EC5
tr
tECWH
tf
tECWL
MB91191 Series
22
(8) General-Purpose Prescaler (VDD = 3.0 V ± 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Parameter Symbol Pin Name Value Unit Remarks
Min. Max.
PCK input clock frequency fCP
PCK
12 MHz
PCK input “H” pulse width tSPWH 33 ns
PCK input “L” pulse width tSPWL 33 ns
PCK input Fall time tfPCK 100 ns
Rise time tr
PO output delay time tPOPI PO 80 ns
PCK
PO
tSPWH tftSPWL tr
tPOPI
MB91191 Series
23
5. Electrical Characteristics for the A/D Converter
(VDD = 3.0 V + 0.3 V, VSS = AVSS = 0 V, TA = −20 °C to +70 °C)
Notes : • The relative error increases as |AVRH| becomes smaller.
• Ensure that the output impedance of the external circuit connected to the analog input meets the following
condition :
Output impedance of external circuit < 7 kΩ (approx.)
If the output impedance of the external circuit is too high, the analog voltage sampling time may be too
short. (Sampling time = 6.4 µs for a 20 MHz machine clock)
Parameter Sym
bol Pin
Name Condition Value Unit Remarks
Min. Typ. Max.
Resolution 10 bit
Conversion time 8.4 µs
Total error
VDD = AVDD = 3.0 V,
AVRH = 3.0 V
±4.0 LSB
Linearity error ±3.5 LSB
Differential linearity error ±2.0 LSB
Zero transition error VOT AN-0 to
AN-F VDD = AVDD = 3.0 V,
AVRH = 3.0 V
AVSS −
1.5 AVSS +
0.5 AVSS +
2.5 LSB
Full-scale transition error VFST AN-0 to
AN-F AVRH −
5.5 AVRH −
1.5 AVRH +
0.5 LSB
Analog input current IAIN AN-0 to
AN-F 0.1 10 µA
Analog input voltage VAIN AN-0 to
AN-F AVSS AVRH V
Reference voltage AVRH AVRH AVDD V
Power
supply
current
During
conversion IAAVDD VDD = AVDD = 3.0 V 3.0 mA
Conversion
halted IAH 5.0 µA
Reference
voltage
supply
current
During
conversion IRAVRH VDD = AVDD = 3.0 V,
AVRH = 3.0 V
100 µA
Conversion
halted IRH 10 µA
Variation between
channels AN-0 to
AN-F 4LSB
MB91191 Series
24
6. A/D Converter Glossary
• Resolution : The change in analog voltage that can be recognized by the A/D converter.
• Linearity error
The deviation between the actual conversion characteristics and the line linking the zero transition point
(“00 0000 0000B” ←→ “00 0000 0001B”) and the full scale transition point (“11 1111 1110B” ←→ “11 1111
1111B”) .
• Differential linearity error
The variation from the ideal input voltage required to change the output code by 1 LSB.
• Total error
The total error is the difference between the actual value and the theoretical value.
Includes the zero transition error, full-scale transition error and linearity error.
1 LSB’ (Theoretical) = [V]
Total error for digital output N =
VOT’ (Theoretical) = AVSS + 0.5 LSB’ [V]
VFST’ (Theoretical) = AVRH − 1.5 LSB’ [V]
VNT : Voltage at which digital output changes from (N + 1) to N
AVRH − AVSS
1024
VNT − {1 LSB’ × (N − 1) + 0.5 LSB’}
1 LSB’
1.5 LSB’
Digital Output
3FF
3FE
3FD
004
003
002
001
AVSS
0.5 LSB’
Theoretical characteristic
Actual conversion
characteristic
{1 LSB’ × (N − 1) + 0.5 LSB’}
Actual conversion
characteristic
Total Error
AVRH
Analog Input
VNT
(Measured value)
MB91191 Series
25
= [LSB]
VOT’ (Theoretical) = [V]
VOT : Voltage at which digital output changes from (000) H to (001) H.
VFST : Voltage at which digital output changes from (3FE) H to (3FF) H.
VFST − VOT
1022
= − 1 LSB [LSB]
V (N+1) T − VNT
1 LSB’
Differential linearity error
for digital output N
VNT − {1 LSB × (N − 1) + VOT}
1 LSB’
Linearity error for
digital output N
Digital Output
Digital Output
Analog Input
Linearity Error
AVSS AVRH Analog Input
AVSS AVRH
VOT (Measured value)
Theoretical characteristic
Actual conversion
characteristic
VNT
(Measured
value)
{1 LSB × (N − 1) + VoT’}
Actual conversion characteristic
3FF
3FE
3FD
004
003
002
001
Differential Linearity Error
Actual conversion characteristic
V
NT
(Measured value)
Actual conversion characteristic
Theoretical characteristic
N + 1
N
N − 1
N − 2
VFST
(Measured
value)
V
FST
(Measured
value)
MB91191 Series
26
■
■■
■ORDERING INFOMATION
Part No. Package Remarks
MB91191PFF Plastic LQFP, 120-pin
(FPT-120P-M05)
MB91191 Series
27
■
■■
■PACKAGE DIMENSION
Plastic LQFP, 120-pin
(FPT-120P-M05)
Dimensions in mm (inches).
C
1995 FUJITSU LIMITED F120006S-2C-3
0.065(.003)
M
0.10(.004)
1 PIN INDEX
.059
.004
+.008
0.10
+0.20
1.5016.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
0.127
+0.05
0.02
+.002
.001
.005
15.00
(.591)
NOM
.006
.001
+.003
0.03
+0.08
0.140.40(.0157)TYP
11.60
(.457)
REF
"B"
0 10˚
(.020±.008)
0.50±0.20
Details of "B" part
Details of "A" part
0.36(.014)MAX
0.10(.004)MAX
0.15(.006)
0.15(.006)
130
31
6091
120
6190
0.10±0.10
(.004±.004) (STAND OFF)
(Mounting height)
LEAD No.
"A"
MB91191 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
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Electronic Devices
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F0107
FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, and
manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use,
and household use, but are not designed, developed and
manufactured as contemplated (1) for use accompanying fatal risks
or dangers that, unless extremely high safety is secured, could have
a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
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You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
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