NCV5230DR2G - ON SEMICONDUCTOR - Datasheet.Directory

August, 2010 − Rev. 5

1Publication Order Number:

NE5230/D

NE5230, SA5230, SE5230

Low Voltage Operational

Amplifier

The NE5230 is a very low voltage operational amplifier that can

perform with a voltage supply as low as 1.8 V or as high as 15 V.

In addition, split or single supplies can be used, and the output will

swing to ground when applying the latter. There is a bias adjusting pin

which controls the supply current required by the device and thereby

controls its power consumption. If the part is operated at ±0.9 V

supply voltages, the current required is only 110 mA when the current

control pin is left open. Even with this low power consumption, the

device obtains a typical unity gain bandwidth of 250 kHz. When the

bias adjusting pin is connected to the negative supply, the unity gain

bandwidth is typically 600 kHz while the supply current is increased

to 600 mA. In this mode, the part will supply full power output beyond

the audio range.

The NE5230 also has a unique input stage that allows the

common−mode input range to go above the positive and below the

negative supply voltages by 250 mV. This provides for the largest

possible input voltages for low voltage applications. The part is also

internally−compensated to reduce external component count.

The NE5230 has a low input bias current of typically ±40 nA, and a

large open−loop gain of 125 dB. These two specifications are

beneficial when using the device in transducer applications. The large

open−loop gain gives very accurate signal processing because of the

large “excess” loop gain in a closed−loop system.

The output stage is a class AB type that can swing to within 100 mV

of the supply voltages for the largest dynamic range that is needed in

many applications. The NE5230 is ideal for portable audio equipment

and remote transducers because of its low power consumption, unity

gain bandwidth, and 30 nV/√Hz noise specification.

Features

•Works Down to 1.8 V Supply Voltages

•Adjustable Supply Current

•Low Noise

•Common−mode Includes Both Rails

•VOUT Within 100 mV of Both Rails

•These are Pb−Free Devices

Applications

•Portable Precision Instruments

•Remote Transducer Amplifier

•Portable Audio Equipment

•Rail−to−Rail Comparators

•Half−wave Rectification without Diodes

•Remote Temperature Transducer with 4.0 to 20 mA Output

Transmission

http://onsemi.com

PIN CONNECTIONS

See detailed ordering and shipping information in the package

dimensions section on page 16 of this data sheet.

ORDERING INFORMATION

(Top View)

PDIP−8

N SUFFIX

CASE 626

SOIC−8

D SUFFIX

CASE 751

−IN

+IN OUTPUT

BIAS ADJ.

VEE

VCC

−

N, D Packages

See general marking information in the device marking

section on page 16 of this data sheet.

DEVICE MARKING INFORMATION

NE5230, SA5230, SE5230

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MAXIMUM RATINGS

Rating Symbol Value Unit

Single Supply Voltage VCC 18 V

Dual Supply Voltage VS±9 V

Input Voltage (Note 1) VIN ±9 (18) V

Differential Input Voltage (Note 1) ±VSV

Common−Mode Voltage (Positive) VCM VCC + 0.5 V

Common−Mode Voltage (Negative) VCM VEE − 0.5 V

Power Dissipation (Note 2) PD500 mW

Thermal Resistance, Junction−to−Ambient

N Package

D Package

RqJA 130

182

°C/W

Operating Junction Temperature (Note 2) TJ150 °C

Operating Temperature Range

TA0 to 70

−40 to 85

−40 to 125

°C

80 Output Short−Circuit Duration to Either Power Supply Pin (Notes 2 and 3) Indefinite s

Storage Temperature Tstg −65 to 150 °C

Lead Soldering Temperature (10 sec max) Tsld 230 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. Can exceed the supply voltages when VS ≤±7.5 V (15 V).

2. The maximum operating junction temperature is 150°C. At elevated temperatures, devices must be derated according to the package thermal

resistance and device mounting conditions.

Derate above 25°C at the following rates:

N package at 7.7 mW/°C

D package at 5.5 mW/°C.

3. Momentary shorts to either supply are permitted in accordance to transient thermal impedance limitations determined by the package and

device mounting conditions.

RECOMMENDED OPERATING CONDITIONS

Characteristic Value Unit

Single Supply Voltage 1.8 to 15 V

Dual Supply Voltage ±0.9 to ±7.5 V

Common−Mode Voltage (Positive) VCC + 0.25 V

Common−Mode Voltage (Negative) VEE − 0.25 V

Temperature NE Grade

SA Grade

SE Grade

0 to +70

−40 to +85

−40 to +125

°C

NE5230, SA5230, SE5230

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DC AND AC ELECTRICAL CHARACTERISTIC Unless otherwise specified, ±0.9V ≤ Vs ≤ ±7.5 V or equivalent single supply,

RL = 10 kW, full input common−mode range, over full operating temperature range.

Characteristic Symbol Test Conditions Bias Min Typ Max Unit

NE5230, SA5230

Offset Voltage VOS TA = 25°C Any 0.4 3.0 mV

TA = Tlow to Thigh Any 3.0 4.0

Drift VOS Any 2.0 5.0 mV/°C

Offset Current IOS TA = 25°C

High 3.0 50 nA

Low 3.0 30

TA = Tlow to Thigh

High 100

Low 60

Drift IOS High 0.5 1.4 nA/°C

Low 0.3 1.4

Bias Current IBTA = 25°C

High 40 150 nA

Low 20 60

TA = Tlow to Thigh

High 200

Low 150

Drift IBHigh 2.0 4.0 nA/°C

Low 2.0 4.0

Supply Current IS

VS = ±0.9 V

TA = 25°C

Low 110 160 mA

High 600 750

TA = Tlow to Thigh

Low 250

High 800

VS = ±7.5 V

TA = 25°C

Low 320 550 mA

High 1100 1600

TA = Tlow to Thigh

Low 600

High 1700

Common−Mode Input Range VCM VOS ≤6 mV, TA = 25°CAny V−− 0.25 V++ 0.25 V

VOS ≤6 mV, TA = Tlow to Thigh Any V−V+

Common−Mode Rejection Ratio CMRR

VS = ±7.5 V

RS = 10 kW; VCM = ±7.5 V;

TA = 25°C

Any 85 95 dB

RS = 10 kW; VCM = ±7.5 V;

TA = Tlow to Thigh

Any 80

Power Supply Rejection Ratio PSRR

TA = 25°C

High 90 105 dB

Low 85 95

VOS v 6 mV, TA = Tlow to Thigh

High 75

Low 80

Load Current Source ILVS = ±0.9 V; TA = 25°C High 4.0 6 mA

Sink VS = ±0.9 V; TA = 25°C High 5.0 7

Source VS = ±7.5 V; TA = 25°C High 16

Sink VS = ±7.5 V; TA = 25°C High 32

Source VS = ±0.9 V; TA = Tlow to Thigh Any 1.0 5

Sink VS = ±0.9 V; TA = Tlow to Thigh Any 2.0 6

Source VS = ±7.5 V; TA = Tlow to Thigh Any 4.0 10

Sink VS = ±7.5 V; TA = Tlow to Thigh Any 5.0 15

For NE5230 devices, Tlow = 0°C and Thigh = +70°C. For SA5230 devices, Tlow = −40°C and Thigh = +85°C.

NE5230, SA5230, SE5230

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DC AND AC ELECTRICAL CHARACTERISTIC Unless otherwise specified, ±0.9V ≤ Vs ≤ ±7.5 V or equivalent single supply,

RL = 10 kW, full input common−mode range, over full operating temperature range.

Characteristic UnitMaxTypMinBiasTest ConditionsSymbol

SE5230

Offset Voltage VOS TA = 25°C Any 0.4 3.0 mV

TA = Tlow to Thigh Any 3.0 4.0

Drift VOS Any 2.0 5.0 mV/°C

Offset Current IOS TA = 25°C

High 3.0 50 nA

Low 3.0 30

TA = Tlow to Thigh

High 100

Low 60

Drift IOS High 0.5 1.4 nA/°C

Low 0.3 1.4

Bias Current IBTA = 25°C

High 40 150 nA

Low 20 60

TA = Tlow to Thigh

High 300

Low 300

Drift IBHigh 2.0 4.0 nA/°C

Low 2.0 4.0

Supply Current IS

VS = ±0.9 V

TA = 25°C

Low 110 160 mA

High 600 750

TA = Tlow to Thigh

Low 275

High 850

VS = ±7.5 V

TA = 25°C

Low 320 550 mA

High 1100 1600

TA = Tlow to Thigh

Low 600

High 1700

Common−Mode Input Range VCM VOS ≤6 mV, TA = 25°CAny V−− 0.25 V++ 0.25 V

VOS ≤ 20 mV, TA = Tlow to Thigh Any V−V+

Common−Mode Rejection Ratio CMRR

VS = ±7.5 V

RS = 10 kW; VCM = ±7.5 V;

TA = 25°C

Any 85 95 dB

RS = 10 kW; VCM = ±7.5 V;

TA = Tlow to Thigh

Any 80

Power Supply Rejection Ratio PSRR

TA = 25°C

High 90 105 dB

Low 85 95

TA = Tlow to Thigh

High 75

Low 80

Load Current Source ILVS = ±0.9 V; TA = 25°C High 4.0 6 mA

Sink VS = ±0.9 V; TA = 25°C High 5.0 7

Source VS = ±7.5 V; TA = 25°C High 16

Sink VS = ±7.5 V; TA = 25°C High 32

Source VS = ±0.9 V; TA = Tlow to Thigh Any 1.0 5

Sink VS = ±0.9 V; TA = Tlow to Thigh Any 2.0 6

Source VS = ±7.5 V; TA = Tlow to Thigh Any 4.0 10

Sink VS = ±7.5 V; TA = Tlow to Thigh Any 5.0 15

For SE5230 devices, Tlow = −40°C and Thigh = +125°C.

NE5230, SA5230, SE5230

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DC AND AC ELECTRICAL CHARACTERISTIC Unless otherwise specified, ±0.9V ≤ Vs ≤ ±7.5 V or equivalent single supply,

RL = 10 kW, full input common−mode range, over full operating temperature range.

Characteristic UnitMaxTypMinBiasTest ConditionsSymbol

NE5230, SA5230, SE5230

Large−Signal Open−Loop Gain AVOL VS = ±7.5 V

RL = 10 kW; TA = 25°C

High 120 2000 V/mV

Low 60 750

TA = Tlow to Thigh

High 100

Low 50

Output Voltage Swing VOUT

VS = ±0.9 V

TA = 25°C +SW Any 750 800 mV

TA = 25°C −SW Any 750 800

TA = Tlow to Thigh; +SW Any 700

TA = Tlow to Thigh; −SW Any 700

VS = ±7.5 V

TA = 25°C +SW Any 7.30 7.35 V

TA = 25°C −SW Any −7.32 −7.35

TA = Tlow to Thigh; +SW Any 7.25 7.30

TA = Tlow to Thigh; −SW Any −7.30 −7.35

Slew Rate SR

TA = 25°C

High 0.25 V/ms

Low 0.09 V/ms

Inverting Unity Gain Bandwidth BW

CL = 100 pF; TA = 25°C

High 0.6 MHz

Low 0.25 MHz

Phase Margin qMCL = 100 pF; TA = 25°C Any 70 °

Settling Time tSCL = 100 pF, 0.1%

High 2.0 ms

Low 5.0 ms

Input Noise VINN RS = 0 W; f = 1.0 kHz

High 30 nV/√Hz

Low 60 nV/√Hz

Total Harmonic Distortion THD VS = ±7.5 V

AV = 1; VIN = 500 mV; f = 1.0 kHz High 0.003 %

VS = ±0.9 V

AV = 1, VIN = 500 mV; f = 1.0 kHz High 0.002 %

For NE5230 devices, Tlow = 0°C and Thigh = +70°C. For SA5230 devices, Tlow = −40°C and Thigh = +85°C.

For SE5230 devices, Tlow = −40°C and Thigh = +125°C.

NE5230, SA5230, SE5230

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THEORY OF OPERATION

Input Stage

Operational amplifiers which are able to function at

minimum supply voltages should have input and output

stage swings capable of reaching both supply voltages

within a few millivolts in order to achieve ease of quiescent

biasing and to have maximum input/output signal handling

capability. The input stage of the NE5230 has a

common−mode voltage range that not only includes the

entire supply voltage range, but also allows either supply to

be exceeded by 250 mV without increasing the input offset

voltage by more than 6.0 mV. This is unequalled by any

other operational amplifier today.

In order to accomplish the feat of rail−to−rail input

common−mode range, two emitter−coupled differential

pairs are placed in parallel so that the common−mode

voltage of one can reach the positive supply rail and the other

can reach the negative supply rail. The simplified schematic

of Figure 1 shows how the complementary emitter−coupler

transistors are configured to form the basic input stage cell.

Common−mode input signal voltages in the range from

0.8 V above VEE to VCC are handled completely by the NPN

pair, Q3 and Q4, while common−mode input signal voltages

in the range of VEE to 0.8 V above VEE are processed only

by the PNP pair, Q1 and Q2. The intermediate range of input

voltages requires that both the NPN and PNP pairs are

operating. The collector currents of the input transistors are

summed by the current combiner circuit composed of

transistors Q8 through Q11 into one output current.

Transistor Q8 is connected as a diode to ensure that the

outputs of Q2 and Q4 are properly subtracted from those of

Q1 and Q3.

The input stage was designed to overcome two important

problems for rail−to−rail capability. As the common−mode

voltage moves from the range where only the NPN pair was

operating to where both of the input pairs were operating, the

effective transconductance would change by a factor of two.

Frequency compensation for the ranges where one input pair

was operating would, of course, not be optimal for the range

where both pairs were operating. Secondly, fast changes in

the common−mode voltage would abruptly saturate and

restore the emitter current sources, causing transient

distortion. These problems were overcome by assuring that

only the input transistor pair which is able to function

properly is active. The NPN pair is normally activated by the

current source IB1 through Q5 and the current mirror Q6 and

Q7, assuming the PNP pair is non−conducting. When the

common−mode input voltage passes below the reference

voltage, VB1 − 0.8 V at the base of Q5, the emitter current is

gradually steered toward the PNP pair, away from the NPN

pair. The transfer of the emitter currents between the

complementary input pairs occurs in a voltage range of

about 120 mV around the reference voltage VB1. In this way

the sum of the emitter currents for each of the NPN and PNP

transistor pairs is kept constant; this ensures that the

transconductance of the parallel combination will be

constant, since the transconductance of bipolar transistors is

proportional to their emitter currents.

An essential requirement of this kind of input stage is to

minimize the changes in input offset voltage between that of

the NPN and PNP transistor pair which occurs when the

input common−mode voltage crosses the internal reference

voltage, VB1. Careful circuit layout with a cross−coupled

quad for each input pair has yielded a typical input offset

voltage of less than 0.3 mV and a change in the input offset

voltage of less than 0.1 mV.

R10 R11

R8 R9

Q3 Q1 Q2 Q4

Q10 Q11

Q6 Q7

Q8 Q9

VEE

VCC

IOUT

Vb2

+Vb1

VIN−VIN+

Ib1

Figure 1. Input Stage

NE5230, SA5230, SE5230

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Output Stage

Processing output voltage swings that nominally reach to

less than 100 mV of either supply voltage can only be

achieved by a pair of complementary common−emitter

connected transistors. Normally, such a configuration

causes complex feed−forward signal paths that develop by

combining biasing and driving which can be found in

previous low supply voltage designs. The unique output

stage of the NE5230 separates the functions of driving and

biasing, as shown in the simplified schematic of Figure 2 and

has the advantage of a shorter signal path which leads to

increasing the effective bandwidth.

This output stage consists of two parts: the Darlington

output transistors and the class AB control regulator. The

output transistor Q3 connected with the Darlington

transistors Q4 and Q5 can source up to 10 mA to an output

load. The output of NPN Darlington connected transistors

Q1 and Q2 together are able to sink an output current of

10 mA. Accurate and efficient class AB control is necessary

to insure that none of the output transistors are ever

completely cut off. This is accomplished by the differential

amplifier (formed by Q8 and Q9) which controls the biasing

of the output transistors. The differential amplifier compares

the summed voltages across two diodes, D1 and D2, at the

base of Q8 with the summed voltages across the

base−emitter diodes of the output transistors Q1 and Q3. The

base−emitter voltage of Q3 is converted into a current by Q6

and R6 and reconverted into a voltage across the

base−emitter diode of Q7 and R7. The summed voltage

across the base−emitter diodes of the output transistors Q3

and Q1 is proportional to the logarithm of the product of the

push and pull currents IOP and ION, respectively. The

combined voltages across diodes D1 and D2 are

proportional to the logarithm of the square of the reference

current IB1. When the diode characteristics and

temperatures of the pairs Q1, D1 and Q3, Q2 are equal, the

relation IOP ×ION − IB1 ×IB1 is satisfied.

Separating the functions of biasing and driving prevents

the driving signals from becoming delayed by the biasing

circuit. The output Darlington transistors are directly

accessible for in−phase driving signals on the bases of Q5

and Q2. This is very important for simple high−frequency

compensation. The output transistors can be high−frequency

compensated by Miller capacitors CM1A and CM1B

connected from the collectors to the bases of the output

Darlington transistors.

A general−purpose op amp of this type must have enough

open−loop gain for applications when the output is driving

a low resistance load. The NE5230 accomplishes this by

inserting an intermediate common−emitter stage between

the input and output stages. The three stages provide a very

large gain, but the op amp now has three natural dominant

poles − one at the output of each common−emitter stage.

Frequency compensation is implemented with a simple

scheme of nested, pole−splitting Miller integrators. The

Miller capacitors CM1A and CM1B are the first part of the

nested structure, and provide compensation for the output

and intermediate stages. A second pair of Miller integrators

provide pole−splitting compensation for the pole from the

input stage and the pole resulting from the compensated

combination of poles from the intermediate and output

stages. The result is a stable, internally−compensated op

amp with a phase margin of 70°.

Ib1 Ib2 Ib3

Ib5

Ib4

Q8 Q9

CM1B

CM1A

Vb2

Vb5

VCC

VEE

VOUT

IOP

ION

Figure 2. Output Stage

NE5230, SA5230, SE5230

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THERMAL CONSIDERATIONS

When using the NE5230, the internal power dissipation

capabilities of each package should be considered.

ON Semiconductor does not recommend operation at die

temperatures above 110°C in the SO package because of its

inherently smaller package mass. Die temperatures of

150°C can be tolerated in all the other packages. With this

in mind, the following equation can be used to estimate the

die temperature:

Tj+Tamb )(PD qJA)(eq. 1)

Where

Tamb= Ambient Temperature

Tj= Die Temperature

PD= Power Dissipation

= (ICC x VCC)

qJA = Package Thermal Resistance

= 270°C/W for SO−8 in PC Board Mounting

See the packaging section for information regarding other

methods of mounting.

qJA − 100°C/W for the plastic DIP.

The maximum supply voltage for the part is 15 V and the

typical supply current is 1.1 mA (1.6 mA max). For

operation at supply voltages other than the maximum, see

the data sheet for ICC versus VCC curves. The supply current

is somewhat proportional to temperature and varies no more

than 100 mA between 25°C and either temperature extreme.

Operation at higher junction temperatures than that

recommended is possible but will result in lower Mean Time

Between Failures (MTBF). This should be considered

before operating beyond recommended die temperature

because of the overall reliability degradation.

DESIGN TECHNIQUES AND APPLICATIONS

The NE5230 is a very user−friendly amplifier for an

engineer to design into any type of system. The supply

current adjust pin (Pin 5) can be left open or tied through a

pot or fixed resistor to the most negative supply (i.e., ground

for single supply or to the negative supply for split supplies).

The minimum supply current is achieved by leaving this pin

open. In this state it will also decrease the bandwidth and

slew rate. When tied directly to the most negative supply, the

device has full bandwidth, slew rate and ICC. The

programming of the current−control pin depends on the

trade−offs which can be made in the designer’s application.

The graphs in Figures 3 and 4 will help by showing

bandwidth versus ICC. As can be seen, the supply current can

be varied anywhere over the range of 100 mA to 600 mA for

a supply voltage of 1.8 V. An external resistor can be

inserted between the current control pin and the most

negative supply. The resistor can be selected between 1.0 W

to 100 kW to provide any required supply current over the

indicated range. In addition, a small varying voltage on the

bias current control pin could be used for such exotic things

as changing the gain−bandwidth for voltage controlled low

pass filters or amplitude modulation. Furthermore, control

over the slew rate and the rise time of the amplifier can be

obtained in the same manner. This control over the slew rate

also changes the settling time and overshoot in pulse

response applications. The settling time to 0.1% changes

from 5.0 ms at low bias to 2.0 ms at high bias. The supply

current control can also be utilized for wave−shaping

applications such as for pulse or triangular waveforms. The

gain−bandwidth can be varied from between 250 kHz at low

bias to 600 kHz at high bias current. The slew rate range is

0.08 V/ms at low bias and 0.25 V/ms at high bias.

Figure 3. Unity Gain Bandwidth vs. Power Supply

Current for VCC = ±0.9 V

Figure 4. ICC Current vs. Bias Current Adjusting

Resistor for Several Supply Voltages

800

700

600

500

400

300

200

100

100 200 300 400 500 600700

UNITY GAIN BANDWIDTH (kHz)

TA − 25°CVCC − 15V

VCC − 12V

VCC − 9V

VCC − 6V

VCC − 3V

VCC − 2V

VCC − 1.8V

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

100101102103104105

RADJ (W)

POWER SUPPLY CURRENT (mA)

ICC CURRENT (mA)

NE5230, SA5230, SE5230

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The full output power bandwidth range for VCC equals

2.0 V, is above 40 kHz for the maximum bias current setting

and greater than 10 kHz at the minimum bias current setting.

If extremely low signal distortion (<0.05%) is required at

low supply voltages, exclude the common−mode crossover

point (VB1) from the common−mode signal range. This can

be accomplished by proper bias selection or by using an

inverting amplifier configuration.

Most single supply designs necessitate that the inputs to

the op amp be biased between VCC and ground. This is to

assure that the input signal swing is within the working

common−mode range of the amplifier. This leads to another

helpful and unique property of the NE5230 that other CMOS

and bipolar low voltage parts cannot achieve. It is the simple

fact that the input common−mode voltage can go beyond

either the positive or negative supply voltages. This benefit

is made very clear in a non−inverting voltage−follower

configuration. This is shown in Figure 5 where the input sine

wave allows an undistorted output sine wave which will

swing less than 100 mV of either supply voltage. Many

competitive parts will show severe clipping caused by input

common−mode limitations. The NE5230 in this

configuration offers more freedom for quiescent biasing of

the inputs close to the positive supply rail where similar op

amps would not allow signal processing.

There are not as many considerations when designing

with the NE5230 as with other devices. Since the NE5230

is internally−compensated and has a unity gain−bandwidth

of 600 kHz, board layout is not so stringent as for very high

frequency devices such as the NE5205. The output

capability of the NE5230 allows it to drive relatively high

capacitive loads and small resistive loads. The power supply

pins should be decoupled with a low−pass RC network as

close to the supply pins as possible to eliminate 60 Hz and

other external power line noise, although the power supply

rejection ratio (PSRR) for the part is very high. The pinout

for the NE5230 is the same as the standard single op amp

pinout with the exception of the bias current adjusting pin.

V+

V−

−

NE5230

OTHER

PARTS

V+

V−

V+

V−

V+

V−

Figure 5. In a non−inverting voltage−follower configuration, the NE5230 will give full rail−to−rail swing.

Other low voltage amplifiers will not because they are limited by their input common−mode

range and output swing capability.

NE5230, SA5230, SE5230

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REMOTE TRANSDUCER WITH CURRENT

TRANSMISSION

There are many ways to transmit information along two

wires, but current transmission is the most beneficial when

the sensing of remote signals is the aim. It is further

enhanced in the form of 4.0 to 20 mA information which is

used in many control−type systems. This method of

transmission provides immunity from line voltage drops,

large load resistance variations, and voltage noise pickup.

The zero reference of 4mA not only can show if there is a

break in the line when no current is flowing, but also can

power the transducer at the remote location. Usually the

transducer itself is not equipped to provide for the current

transmission. The unique features of the NE5230 can

provide high output current capability coupled with low

power consumption. It can be remotely connected to the

transducer to create a current loop with minimal external

components. The circuits for this are shown in Figures 6

and 7. Here, the part is configured as a voltage−to−current,

or transconductance amplifier. This is a novel circuit that

takes advantage of the NE5230’s large open−loop gain. In

AC applications, the load current will decrease as the

open−loop gain rolls off in magnitude. The low offset

voltage and current sinking capabilities of the NE5230 must

also be considered in this application.

The NE5230 circuit shown in Figure 6 is a pseudo

transistor configuration. The inverting input is equivalent to

the “base,” the point where VEE and the non−inverting input

meet is the “emitter,” and the connection after the output

diode meets the VCC pin is the collector. The output diode

is essential to keep the output from saturating in this

configuration. From here it can be seen that the base and

emitter form a voltage−follower and the voltage present at

RC must equal the input voltage present at the inverting

input. Also, the emitter and collector form a

current−follower and the current flowing through RC is

equivalent to the current through RL and the amplifier. This

sets up the current loop. Therefore, the following equation

can be formulated for the working current transmission line.

The load current is:

IL+VIN

(eq. 2)

and proportional to the input voltage for a set RC. Also, the

current is constant no matter what load resistance is used

while within the operating bandwidth range of the op amp.

When the NE5230’s supply voltage falls past a certain point,

the current cannot remain constant. This is the “voltage

compliance” and is very good for this application because of

the near rail output voltage. The equation that determines the

voltage compliance as well as the largest possible load

resistor for the NE5230 is as follows:

RLmax +ƪVremote supply *VCC min *VIN maxƫ

(eq. 3)

Where VCC min is the worst−case power supply voltage

(approximately 1.8 V) that will still keep the part

operational. As an example, when using a 15 V remote

power supply, a current sensing resistor of 1.0 W, and an

input voltage (VIN) of 20 mV, the output current (IL) is

20 mA. Furthermore, a load resistance of zero to

approximately 650 W can be inserted in the loop without any

change in current when the bias current−control pin is tied

to the negative supply pin. The voltage drop across the load

and line resistance will not affect the NE5230 because it will

operate down to 1.8 V. With a 15 V remote supply, the

voltage available at the amplifier is still enough to power it

with the maximum 20 mA output into the 650 W load.

Figure 6. The NE5230 as a Remote Transducer

Transconductance Amp with 4.0 − 20 mA Current

Transmission Output Capability

VREMOTE

POWER

SUPPLY

NE5230

VCC

VEE

VIN

IOUT

245

−

NOTES:

1. IOUT = VIN/RC

2. RL MAX ≈VREMOTE *1.8V *VINMAX

IOUT

For RC = 1.0 W

IOUT

4mA

VIN

4mV

20mA 20mV

Figure 7. The Same Type of Circuit as Figure 6, but

for Sourcing Current to the Load

VCC

NE5230

−

VEE + IOUT

−

VIN

VCC

−

NE5230, SA5230, SE5230

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What this means is that several instruments, such as a chart

recorder, a meter, or a controller, as well as a long cable, can

be connected in series on the loop and still obtain accurate

readings if the total resistance does not exceed 650 W.

Furthermore, any variation of resistance in this range will

not change the output current.

Any voltage output type transducer can be used, but one

that does not need external DC voltage or current excitation

to limit the maximum possible load resistance is preferable.

Even this problem can be surmounted if the supply power

needed by the transducer is compatible with the NE5230.

The power goes up the line to the transducer and amplifier

while the transducer signal is sent back via the current output

of the NE5230 transconductance configuration.

The voltage range on the input can be changed for

transducers that produce a large output by simply increasing

the current sense resistor to get the corresponding 4.0 to

20 mA output current. If a very long line is used which

causes high line resistance, a current repeater could be

inserted into the line. The same configuration of Figure 7 can

be used with exception of a resistor across the input and line

ground to convert the current back to voltage. Again, the

current sensing resistor will set up the transconductance and

the part will receive power from the line.

TEMPERATURE TRANSDUCER

A variation on the previous circuit makes use of the supply

current control pin. The voltage present at this pin is

proportional to absolute temperature (PTAT) because it is

produced by the amplifier bias current through an internal

resistor divider in a PTAT cell. If the control pin is connected

to the input pin, the NE5230 itself can be used as a

temperature transducer. If the center tap of a resistive pot is

connected to the control pin with one side to ground and the

other to the inverting input, the voltage can be changed to

give different temperature versus output current conditions

(Figure 8). For additional control, the output current is still

proportional to the input voltage differential divided by the

current sense resistor.

When using the NE5230 as a temperature transducer, the

thermal considerations in the previous section must be kept

in mind.

VREMOTE

POWER

SUPPLY

NE5230

VCC

VEE

IOUT

−

NOTES:

1. IOUT = VIN/RC

2. RL MAX ≈VREMOTE *1.8V *VINMAX

IOUT

For RC = 1W

IOUT

4mA

20mA

VIN

4mV

20mV

200

Figure 8. NE5230 remote temperature transducer utilizing 4.0 − 20 mA current transmission. This application

shows the use of the accessibility of the PTAT cell in the device to make the part, itself, a transducer.

10W

NE5230, SA5230, SE5230

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HALF−WAVE RECTIFIER WITH

RAIL−TO−GROUND OUTPUT SWING

Since the NE5230 input common−mode range includes

both positive and negative supply rails and the output can

also swing to either supply, achieving half−wave rectifier

functions in either direction becomes a simple task. All that

is needed are two external resistors; there is no need for

diodes or matched resistors. Moreover, it can have either

positive− or negative−going outputs, depending on the way

the bias is arranged. In Figure 9, the circuit is biased to

ground, while circuit (Figure 10) is biased to the positive

supply. This rather unusual biasing does not cause any

problems with the NE5230 because of the unique internal

saturation detectors incorporated into the part to keep the

PNP and NPN output transistors out of “hard” saturation. It

is therefore relatively quick to recover from a saturated

output condition. Furthermore, the device does not have

parasitic current draw when the output is biased to either rail.

This makes it possible to bias the NE5230 into “saturation”

and obtain half−wave rectification with good recovery. The

simplicity of biasing and the rail−to−ground half−sine wave

swing are unique to this device. The circuit gain can be

changed by the standard op amp gain equations for an

inverting configuration.

It can be seen in these configurations that the op amp

cannot respond to one−half of the incoming waveform. It

cannot respond because the waveform forces the amplifier

to swing the output beyond either ground or the positive

supply rail, depending on the biasing, and, also, the output

cannot disengage during this half cycle. During the other

half cycle, however, the amplifier achieves a half−wave that

can have a peak equal to the total supply voltage. The

photographs in Figure 11 show the effect of the different

biasing schemes, as well as the wide bandwidth (it works

over the full audio range), that the NE5230 can achieve in

this configuration.

VCC

Figure 9. Rail−to−Ground Output Swing Referenced to Ground

Figure 10. Negative−Going Output Referenced to VCC

VIN

VCC

−

VCC

VOUT

VCC

VIN

VOUT

VCC

−

Half−Wave Rectifier With Positive−Going Output Swings

10W

NE5230, SA5230, SE5230

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500 mV/Div 200mS /Div

Biased to Ground

500 mV/Div 20 mS/Div

Biased to Ground

500 mV/Div 20 mS/Div

Biased to Positive Rail

Figure 11. Performance Waveforms for the Circuits in Figures 9 and 10.

Good response is shown at 1.0 and 10 kHz for both circuits under full swing with a 2.0 V supply.

NE5230, SA5230, SE5230

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By adding another NE5230 in an inverting summer

configuration at the output of the half−wave rectifier, a

full−wave can be realized. The values for the input and

feedback resistors must be chosen so that each peak will

have equal amplitudes. A table for calculating values is

included in Figure 12. The summing network combines the

input signal at the half−wave and adds it to double the

half−wave’s output, resulting in the full−wave. The output

waveform can be referenced to the supply or ground,

depending on the half−wave configuration. Again, no

diodes are needed to achieve the rectification.

This circuit could be used in conjunction with the remote

transducer to convert a received AC output signal into a DC

level at the full−wave output for meters or chart recorders

that need DC levels.

HALF-WAVE

+VIN

−VIN

+VIN

−VIN

+VIN

+VBFULL-WAVE

−2VIN

VEE

VCC

+VB

245

R3 R5

R4 2

345

−

INPUT

HALF-WAVE

OUTPUT

FULL-WAVE

OUTPUT

500mV 500mV

500mV

520ms

NOTES:

R2 = 2 R1

R4 = R5 = R3

+VB will vary output reference.

For single supply operation VEE

can be grounded on A2.

Figure 12. Adding an Inverting Summer to the Input and Output of the Half−Wave will Result in Full−Wave

NE5230, SA5230, SE5230

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CONCLUSION

The NE5230 is a versatile op amp in its own right. The part

was designed to give low voltage and low power operation

without the limitations of previously available amplifiers

that had a multitude of problems. The previous application

examples are unique to this amplifier and save the user

money by excluding various passive components that would

have been needed if not for the NE5230’s special input and

output stages.

The NE5230 has a combination of novel specifications

which allows the designer to implement it easily into

existing low−supply voltage designs and to enhance their

performance. It also offers the engineer the freedom to

achieve greater amplifier system design goals. The low input

referenced noise voltage eases the restrictions on designs

where S/N ratios are important. The wide full−power

bandwidth and output load handling capability allow it to fit

into portable audio applications. The truly ample open−loop

gain and low power consumption easily lend themselves to

the requirements of remote transducer applications. The

low, untrimmed typical offset voltage and low offset

currents help to reduce errors in signal processing designs.

The amplifier is well isolated from changes on the supply

lines by its typical power supply rejection ratio of 105 dB.

REFERENCES

1. Johan H. Huijsing, Multi−stage Amplifier with

Capacitive Nesting for Frequency Compensation,

U.S. Patent Application Serial No. 602.234, filed

April 19, 1984.

2. Bob Blauschild, Differential Amplifier with

Rail−to−Rail Capability, U.S. Patent Application

Serial No. 525.181, filed August 23, 1983.

3. Operational Amplifiers − Characteristics and

Applications, Robert G. Irvine, Prentice−Hall, Inc.,

Englewood Cliffs, NJ 07632, 1981.

4. Transducer Interface Handbook − A Guide to

Analog Signal Conditioning, Edited by Daniel H.

Sheingold, Analog Devices, Inc., Norwood, MA

02062, 1981.

NE5230, SA5230, SE5230

http://onsemi.com

NE5230N

AWL

YYWWG

SA5230N

AWL

YYWWG

PDIP−8

N SUFFIX

CASE 626

SOIC−8

D SUFFIX

CASE 751

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or G= Pb−Free Package

MARKING DIAGRAMS

N5230

ALYW

S5230

ALYW

S5230

ALYWE

ORDERING INFORMATION

Device Description Temperature Range Shipping†

NE5230DG 8−Pin Plastic Small Outline (SO−8) Package

(Pb−Free) 0°C to +70°C98 Units / Rail

NE5230DR2G 8−Pin Plastic Small Outline (SO−8) Package

(Pb−Free) 0°C to +70°C2500 / Tape & Reel

NE5230NG 8−Pin Plastic Dual In−Line Package (PDIP−8)

(Pb−Free) 0°C to +70°C50 Units / Rail

SA5230DG 8−Pin Plastic Small Outline (SO−8) Package

(Pb−Free) −40°C to +85°C98 Units / Rail

SA5230DR2G 8−Pin Plastic Small Outline (SO−8) Package

(Pb−Free) −40°C to +85°C2500 / Tape & Reel

SA5230NG 8−Pin Plastic Dual In−Line Package (PDIP−8)

(Pb−Free) −40°C to +85°C50 Units / Rail

SE5230DG 8−Pin Plastic Small Outline (SO−8) Package

(Pb−Free) −40°C to +125°C98 Units / Rail

SE5230DR2G 8−Pin Plastic Small Outline (SO−8) Package

(Pb−Free) −40°C to +125°C2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

NE5230, SA5230, SE5230

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PACKAGE DIMENSIONS

PDIP−8

CASE 626−05

ISSUE M

NOTE 5

TOP VIEW

CSEATING

PLANE

0.010 CA

SIDE VIEW

END VIEW

NOTE 3

DIM MIN NOM MAX

INCHES

A−−−− −−−− 0.210

A1 0.015 −−−− −−−−

b0.014 0.018 0.022

C0.008 0.010 0.014

D0.355 0.365 0.400

D1 0.005 −−−− −−−−

e0.100 BSC

E0.300 0.310 0.325

L0.115 0.130 0.150

−−−− −−−− 5.33

0.38 −−−− −−−−

0.35 0.46 0.56

0.20 0.25 0.36

9.02 9.27 10.02

0.13 −−−− −−−−

2.54 BSC

7.62 7.87 8.26

2.92 3.30 3.81

MIN NOM MAX

MILLIMETERS

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. DIMENSION E IS MEASURED WITH THE LEADS RE-

STRAINED PARALLEL AT WIDTH E2.

4. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

E1 0.240 0.250 0.280 6.10 6.35 7.11

E3 −−−− −−−− 0.430 −−−− −−−− 10.92

0.300 BSC 7.62 BSC

e/2

NE5230, SA5230, SE5230

http://onsemi.com

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AJ

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer

purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

NE5230/D

PUBLICATION ORDERING INFORMATION

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USA/Canada

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Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

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Email: orderlit@onsemi.com

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For additional information, please contact your local

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