PRELIMINARY DATA
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without noti ce.
January 2006 Rev. 1 1/41
1
M25P128
128 Mbit (Multilevel), Low Voltage, Serial Flash Memory
With 50MHz SPI Bus Interface
Feature summary
■128 Mbit of Flash Memory
■Page Program (up to 256 Bytes) in 2.5ms
(typical)
■Sector Erase (2Mbit)
■Bulk Erase (128Mbit)
■2.7 to 3.6V Single Supply Voltage
■SPI Bus Compatible Serial Interface
■50MHz Clock Rate (maximum)
■Electronic Signature
– JEDEC Standard Two-Byte Signature
(2018h)
■More than 10000 Erase/Program Cycles per
Sector
■More than 20-Year Data Retention
■Packages
– ECOPACK® (RoHS compliant)
VDFPN8 (ME)
8x6mm (MLP8)
SO16 (MF)
300 mils width
www.st.com
Contents M25P128
2/41 Rev. 1
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 10
4.4 Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4.3 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.5 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
M25P128 Contents
Rev. 1 3/41
6.6 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.7 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 24
6.8 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.9 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.10 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
List of tables M25P128
4/41 Rev. 1
List of tables
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Protected Area Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Read Identification (RDID) Data-Out Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Status Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Power-Up Timing and VWI Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 9. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 10. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 11. AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 13. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 14. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 15. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8x6mm,
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 16. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width. . . . . . . . . . . . . . . . . . . . 38
Table 17. Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
M25P128 List of figures
Rev. 1 5/41
List of figures
Figure 1. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. VDFPN Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Bus Master and Memory Devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. SPI Modes Supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Hold Condition Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Write Enable (WREN) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Write Disable (WRDI) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Read Identification (RDID) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . . 18
Figure 11. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence . . . . . . . . . 20
Figure 12. Write Status Register (WRSR) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence. . . . . . . . . . . . . 23
Figure 14. Read Data Bytes at Higher Speed (FAST_READ) Instruction and Data-Out Sequence . . 24
Figure 15. Page Program (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16. Sector Erase (SE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17. Bulk Erase (BE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 18. Power-up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19. AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20. Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 21. Write Protect Setup and Hold Timing during WRSR when SRWD=1. . . . . . . . . . . . . . . . . 35
Figure 22. Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 23. Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 24. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Outline 37
Figure 25. SO16 wide – 16 lead Plastic Small Outline, 300 mils body width. . . . . . . . . . . . . . . . . . . . 38
Summary description M25P128
6/41 Rev. 1
1 Summary description
The M25P128 is a mult ile ve l 128Mbit (16Mbit x 8) Serial Flash Memory, with adv anced write
protection mechanisms, accessed by a high speed SPI-compatible b us.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program
instruction.
The memory is organized as 64 sector s, each containing 1024 pages. Each page is 256
bytes wide. Thus, the whole memory can be viewed as co nsisting of 65536 pages, or
16777216 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,
using the Sector Erase instruction.
In order to meet environmental requirements, ST offers these devices in ECOPACK®
pac kages. ECOPACK® packages are Lead-f ree and RoHS compliant. ECOPACK is an ST
tradema rk. ECOPACK specifications are available at: www.st.com.
Figure 1. Logic Diagram
Table 1. Signal Names
C Serial Clock
D Serial Data In put
Q Serial Data Output
SChip Select
WWrite Protect
HOLD Hold
VCC Supply Voltage
VSS Ground
AI11313
S
VCC
M25P128
HOLD
VSS
W
Q
C
D
M25P128 Summary description
Rev. 1 7/41
Figure 2. VDFPN Connections
1. There is an exposed die paddle on the underside of the MLP8 package. This is pulled, internally, to VSS,
and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See Package mechanical section for package dimensions, and how to identify pin-1.
Figure 3. SO Connections
1. DU = Don’t Use
2. See Package mechanical section for package dimensions, and how to identify pin-1.
1
AI11314
2
3
4
8
7
6
5DVSS C
HOLDQ
SV
CC
W
M25P128
1
AI11315
2
3
4
16
15
14
13
DU
DU DU
DU
VCC
HOLD
DUDU
M25P128
5
6
7
8
12
11
10
9WQ VSS
DU
DU
S
D
C
Signal description M25P128
8/41 Rev. 1
2 Signal description
2.1 Serial data output (Q)
This output signal is used to tr ansf er data serially out of the de vice . Data is shifted out on the
falling edge of Serial Clock (C).
2.2 Serial data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
2.3 Serial clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latc hed on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
When this input signal is High, the de vice is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Program, Erase or Write Status Register cycle is in progr ess,
the device will be in the Standby Power mode. Driving Chip Select (S) Low selects the
device, placing it in the Active Power mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any se rial communications with the de vice without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impe da nc e, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
2.6 Write Protect (W)
The main purpose of this inp ut sig na l is to freeze the size of the area of mem ory that is
protected against pro g ram or erase inst ructions (as specified by the values in the BP2, BP1
and BP0 bits of the Status Re gister).
M25P128 SPI modes
Rev. 1 9/41
3 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two follo wing modes:
●CPOL=0, CPHA=0
●CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between t he t w o mod es, as sho w n in Figure 5, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●C remains at 0 for (CPOL=0, CPHA=0)
●C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. Bus Master and Memory Devices on the SPI Bus
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 5. SPI Modes Supported
AI03746e
Bus Master
(ST6, ST7, ST9,
ST10, Others) SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3 CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
WHOLD WHOLD WHOLD
R(2) R(2) R(2)
VCC
VCC VCC VCC
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
Operating features M25P128
10/41 Rev. 1
4 Operating features
4.1 Page programming
To progra m one data byte , two instructions are required: Write Enab le (WREN), which is one
byte, and a Page Program (PP) sequence, which consists of four bytes plus da ta. This is
followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted Bytes in a single sequence versus using several Page
Progr am (PP) sequences with each containing only a few Bytes (see Section 6.8: Page
Program (PP) and Table 14: AC Characteristics).
4.2 Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be
achie v ed either a se ctor at a time, using the Sector Erase (SE) instruction, or throughout the
entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of
duration tSE or tBE).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
4.3 Polling during a write, program or erase cycle
A further impro vement in the time to Write Status Register (WRSR), Prog r am (PP) or Erase
(SE or BE) can be achieved b y no t waiting for the worst case delay (tW, tPP
, tSE, or tBE). The
Write In Progress (WIP) bit is pro vided in the Status Register so t hat the application progr am
can monitor its v alue , polling it to establish when the pre v ious Write cycle , Prog ram cycle or
Erase cycle is complete.
4.4 Active power and standby power modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the de vice is deselected, b ut could remain in the Activ e Power
mode until all internal cycles have completed (Program, Erase, Write Status Register). The
device then goes in to the Standby Power mode. The device consumption drops to I CC1.
M25P128 Operating features
Rev. 1 11/41
4.5 Status Register
The Status Regist er conta ins a n umber o f stat us and cont rol bit s that can be rea d or set (a s
appropriate) by specific instructions. See Section 6.4: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
4.6 Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat t his, the
M25P128 features the following data protection mechanisms:
●P ow er On Reset and an internal timer (tPUW) can pr ovide protectio n against inadv ertant
changes while the power supply is outside the operating specification.
●Progr am, Er ase and Write Status Regist er instructions are chec ked that the y consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
●All instructions that modify data m ust be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset stat e
by the following events:
–Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction completion
– Page Program (PP) instruction completion
– Sector Erase ( SE) instruction co mpletion
– Bulk Erase (BE) instruction completion
●The Block Protect (BP2, BP1, BP0) bits allow part of the me m ory to be configured as
read-only. This is the Software Protected Mode (SPM).
●The Write Protect (W) signal allows the Block Protect (BP2, BP1, BP0) bits and Status
Register Write Disable (SRW D) bit to be protected. This is the Hardware Protected
Mode (HPM).
Table 2. Protected Area Sizes
Status Register Content Memory Content
BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area
0 0 0 none All Sectors (Sectors 0 to 63)(1)
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
0 0 1 Upper 64th (1 Sector, 2Mb) Sectors 0 to 62
0 1 0 Upper 32nd (2 Sectors, 4Mb) Sectors 0 to 61
0 1 1 Upper 16nd (4 Sectors, 8Mb) Sectors 0 to 59
1 0 0 Upper 8nd (8 Sectors, 16Mb) Sectors 0 to 55
1 0 1 Upper Quarter (16 Sectors, 32Mb) Lower 3 Quarters (Sectors 0 to 47)
1 1 0 Upper Half (32 Sectors, 64Mb) Lower Half (Sectors 0 to 31)
1 1 1 All sectors (64 Sectors, 128Mb) none
Operating features M25P128
12/41 Rev. 1
4.7 Hold condition
The Hold (HOLD) signal is used to pause any se rial communications with the de vice without
resetting the clocking sequence. However, taking this signal Low does not terminate any
Write Status Register, Progr am or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low (as shown in Figure 6).
The Hold condition ends on the rising edge of the Hold (HOLD) si gnal, provided that this
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low. (This is shown in Figure 6).
During the Hold condition, the Serial Data Output (Q) is high impe da nc e, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
Normally, the de vice is kept selected, with Chip Select (S) driv en Lo w, for the whole dur ation
of the Hold conditi on. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
Figure 6. Hold Condition Activation
AI02029D
HOLD
C
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
M25P128 Memory Organization
Rev. 1 13/41
5 Memory Organization
The memory is organized as:
●16777216 bytes (8 bits each)
●64 sectors (2Mbits, 262144 bytes each)
●65536 pages (256 bytes each).
Each page can be individually pro grammed (bits are prog rammed from 1 to 0). The de vice is
Sector or Bulk Er asable (bits are erased from 0 t o 1) but not Page Erasable.
Figure 7. Block Diagram
AI11316
HOLD
S
W Control Logic High Voltage
Generator
I/O Shift Register
Address Register
and Counter 256 Byte
Data Buffer
256 Bytes (Page Size)
X Decoder
Y Decoder
Size of the
read-only
memory area
C
D
Q
Status
Register
00000h
FFFFFFh
000FFh
Memory Organization M25P128
14/41 Rev. 1
Table 3. Memory Organization
Sector Address Range
63 FC0000h FFFFFFh
62 F80000h FBFFFFh
61 F40000h F7FFFFh
60 F00000h F3FFFFh
59 EC0000h EFFFFFh
58 E80000h EBFFFFh
57 E40000h E7FFFFh
56 E00000h E3FFFFh
55 DC0000h DFFFFFh
54 D80000h DBFFFFh
53 D40000h D7FFFFh
52 D00000h D3FFFFh
51 CC0000h CFFFFFh
50 C80000h CBFFFFh
49 C40000h C7FFFFh
48 C00000h C3FFFFh
47 BC0000h BFFFFFh
46 B80000h BBFFFFh
45 B40000h B7FFFFh
44 B00000h B3FFFFh
43 AC0000h AFFFFFh
42 A80000h ABFFFFh
41 A40000h A7FFFFh
40 A00000h A3FFFFh
39 9C0000h 9FFFFFh
38 980000h 9BFFFFh
37 940000h 97FFFFh
36 900000h 93FFFFh
35 8C0000h 8FFFFFh
34 880000h 8BFFFFh
33 840000h 87FFFFh
32 800000h 83FFFFh
31 7C0000h 7FFFFFh
30 780000h 7BFFFFh
29 740000h 77FFFFh
M25P128 Memory Organization
Rev. 1 15/41
28 700000h 73FFFFh
27 6C0000h 6FFFFFh
26 680000h 6BFFFFh
25 640000h 67FFFFh
24 600000h 63FFFFh
23 5C0000h 5FFFFFh
22 580000h 5BFFFFh
21 540000h 57FFFFh
20 500000h 53FFFFh
19 4C0000h 4FFFFFh
18 480000h 4BFFFFh
17 440000h 47FFFFh
16 400000h 43FFFFh
15 3C0000h 3FFFFFh
14 380000h 3BFFFFh
13 340000h 37FFFFh
12 300000h 33FFFFh
11 2C0000h 2FFFFFh
10 280000h 2BFFFFh
9 240000h 27FFFFh
8 200000h 23FFFFh
7 1C0000h 1FFFFFh
6 180000h 1BFFFFh
5 140000h 17FFFFh
4 100000h 13FFFFh
3 0C0000h 0FFFFFh
2 080000h 0BFFFFh
1 040000h 07FFFFh
0 000000h 03FFFFh
Table 3. Memory Orga nization (continued)
Sector Address Range
Instructions M25P128
16/41 Rev. 1
6 Instructions
All instruct ion s, addresses and dat a are shifted in and out of the device, most significant bit
first.
Serial Data Input (D) is sampled on the first rising edge of Serial Cloc k (C) after Chip Select
(S) is drive n L ow. Then, the on e-byte instruction code must be shifte d in to t he device, most
significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed in Table 4.
Every instruction sequence starts with a one- byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ) , Read Data Bytes at Higher Speed (Fast_Read),
Read Status Register (RDSR) or Read Identification (RDID) instruction, the shifted-in
instruction sequence is f ollo wed b y a data-out sequence . Chip Select (S) can be driven High
after any bit of the data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status
Register (WRSR), Write Enable (WREN) or Write Disable (WRDI), Chip Select (S) must be
driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not
executed. That is, Chip Select (S) must driven High when the number of clock pulses after
Chip Select (S) being driven Low is an exact multiple of eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
Table 4. Instruction Set
Instruction Description One-byte Instruction
Code Address
Bytes Dummy
Bytes Data
Bytes
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disable 0000 0100 04h 0 0 0
RDID Read Identification 1001 1111 9Fh 0 0 1 to 3
RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞
WRSR Write Status Register 0000 0001 01h 0 0 1
READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞
FAST_READ Read Data Bytes at Higher
Speed 0000 1011 0Bh 3 1 1 to ∞
PP Page Program 0000 0010 02h 3 0 1 to 256
SE Sector Erase 1101 1000 D8h 3 0 0
BE Bulk Erase 1100 0111 C7h 0 0 0
M25P128 Instructions
Rev. 1 17/41
6.1 Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP) , Sector
Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered b y d riving Chip Select (S) Lo w, sending the
instruction code, an d then driving Chip Select (S) High.
Figure 8. Write Enable (WREN) Instruction Sequence
6.2 Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, an d then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
●Power-up
●Write Disable (WRDI) instruction completion
●Write Status Register (WRSR) instruction completion
●Page Program (PP) instruction completion
●Sector Erase (SE) instruction completion
●Bulk Erase (BE) instruction completion
Figure 9. Write Disable (WRDI) Instruction Seq u ence
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
Instructions M25P128
18/41 Rev. 1
6.3 Read Identification (RDID)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be
read, followed by two bytes of device identification. The manufacturer identification is
assigned b y JEDEC, and has the v alue 20h f or STMicroe lectronics. T he de vice identification
is assigned b y the device manufacturer, and indicates the memory type in the first byte
(20h), and the memory capacity of the device in the second byte (18h).
Any Read Id entification (RDID) instruction while an Erase or Pr ogram cycle is in progress , is
not decoded, and has no effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in. This is followed by the 24-bit device identification, stored in
the memory, being shifted out on Serial Data Output (Q), each bit being shifted out during
the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 10.
The Read Identification (RDID) instruction is terminated by driving Chip Select (S ) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standb y Power mode , the de vi ce waits to be selected, so that it can r eceive , decode a nd
execute instructions.
Figure 10. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
Table 5. Read Identification (RDID) Data-Out Sequence
Manufacturer Identification Device Identification
Memory Type Memory Capacity
20h 20h 18h
C
D
S
21 3456789101112131415
Instruction
0
AI06809b
Q
Manufacturer Identification
High Impedance
MSB
15 1413 3210
Device Identification
MSB
16 17 18 28 29 30 31
M25P128 Instructions
Rev. 1 19/41
6.4 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress . When one of these cycles is in progress , it is recommended to
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is
also possible to read the Status Register continuously, as shown in Figure 11.
The status and control bits of the Status Register are as follows:
6.4.1 WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to
0 no such cycle is in progress.
6.4.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the inte rnal Write Enable Latch is set, when set to 0 t he internal Write Enable
Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
6.4.3 BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes
protected against P age Program (PP) and Sector Erase (SE) instructions. The Block Protect
(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,
BP1, BP0) bits are 0.
6.4.4 SRWD bit
The Status Register Write Disable (SR W D) bit is operated in conj unction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Prot ect (W ) is driv en Lo w). In this mode, the
non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and
the Write Status Register (WRSR) instruction is no longer accepted for exe cution.
Table 6. Status Register Format
b7 b0
SRWD 0 0 BP2 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
Instructions M25P128
20/41 Rev. 1
Figure 11. Read Status Register (RDSR) Instruction Sequence and Data -Out
Sequence
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
M25P128 Instructions
Rev. 1 21/41
6.5 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been e xecuted. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data Input (D).
The instruction sequence is shown in Figure 12.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the
Status Register. b6 and b5 are always read as 0.
Chip Select (S) must be driv en Hig h after the eighth bit of the d ata b yte has bee n latched in.
If not, the Write Status Register ( WRSR) instruction is not e x e cuted. As soon as Chip Sele ct
(S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WI P) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allo ws the user to change the values of the
Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in Table 2. The Write Status Register (WRSR) instruction also allows
the user to set or reset th e Status Register Write Disable (SR WD) bit in accordance with the
Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect
(W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write
Status Register (WRSR) instruction is not executed once the Hardware Protected Mode
(HPM) is entered.
The protection features of the device are summarized in Table 7
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Table 7. Protecti on Modes
W
Signal SRWD
Bit Mode Write Protection of the
Status Register
Memory Content
Protected Area(1)
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
Table 2: Protected Area Sizes.
Unprotected Area(1)
10
Software
Protected
(SPM)
Status Register is Writable
(if the WREN instruction
has set the WEL bit)
The values in the SRWD,
BP2, BP1 and BP0 bits
can be changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
00
11
01
Hardware
Protected
(HPM)
Status Register is
Hardware write protected
The values in the SRWD,
BP2, BP1 and BP0 bits
cannot be changed
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
instructions
Instructions M25P128
22/41 Rev. 1
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W) is dr iven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
●If Write Protect (W) is driv en High, it is po ssib le to write to the Status Re gister pro vided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
●If Write Protect (W) is driven Low, it is not possible to write to the Status Register even
if the Write Enable Lat ch (WEL) bi t has previously been set by a Write Enab le (WREN)
instruction. (Attempts to write to the Status Re gister are r ejected, an d are n ot accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM) by the Block Protect (BP2, BP1, BP0) bi ts of the Status
Register, are also hardware prot ect ed ag ainst da ta mo dification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
●by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
●or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardw are Protected Mode (HPM) once ent ered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mod e (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
Figure 12. Write Status Register (WRSR) Instruction Sequence
C
D
AI02282D
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB
M25P128 Instructions
Rev. 1 23/41
6.6 Read Data Bytes (READ)
The de vice is first selected by driving Chip Select (S) Low. The instruction code f or the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum
frequency fR, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase , Progr am or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 13. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
C
D
AI03748D
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
76543 1 7
0
High Impedance Data Out 1
Instruction 24-Bit Address
0
MSB
MSB
2
39
Data Out 2
Instructions M25P128
24/41 Rev. 1
6.7 Read Data Bytes at Higher Speed (FAST_READ)
The de vice is first selected by driving Chip Select (S) Low. The instruction code f or the Read
Data Bytes at Higher Speed (FAST_READ) instruction is f ollo w ed b y a 3-b yte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents , at that address, is shifted out on Serial Data Ou tput (Q), each
bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 14.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driv en High at an y time during data output. An y
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 14. Read Data Bytes at Higher Speed (FAST_READ) Instruction and Data-Out
Sequence
C
D
AI04006
S
Q
23
21 345678910 28293031
2221 3210
High Impedance
Instruction 24 BIT ADDRESS
0
C
D
S
Q
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy Byte
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
M25P128 Instructions
Rev. 1 25/41
6.8 Page Program (PP)
The Page Program (PP) inst ruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by dr iving Chip Select (S) Low, followed by
the instruction code , three address b ytes and at least one data b yte on Serial Data Input (D).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significan t bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence. The instruction sequence is
shown in Figure 15.
If more tha n 256 bytes are sent to t he device, previously latched data ar e disca rded and th e
last 256 dat a bytes ar e guaranteed to be progr ammed corr ectly within the same pag e. If less
than 256 Data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted Bytes in a single sequence versus using several Page
Progr am (PP) sequences with each containing only a few Bytes (see Table 14: AC
Characteristics).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Page Prog ram cycle is in progre ss, th e Status Register
may be read to check the value of the Write In Progre ss (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by th e Block Protect
(BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.
Instructions M25P128
26/41 Rev. 1
Figure 15. Page Program (PP) Instruction Sequence
C
D
AI04082B
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-Bit Address
0
765432 0
1
Data Byte 1
39
51
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3 Data Byte 256
2079
2078
2077
2076
2075
2074
2073
765432 0
1
2072
MSB MSB
MSB MSB MSB
M25P128 Instructions
Rev. 1 27/41
6.9 Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Lo w, f ollowed by the
instruction code, an d three address bytes on Serial Data Input (D). Any address inside the
Sector (see Table 3) is a valid add ress for the Sector Erase (SE) instruction. Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 16.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle , and is 0 when it is completed. At some unspe cified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed.
Figure 16. Sector Erase (SE) Instruction Sequence
24 Bit Address
C
D
AI03751D
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
Instructions M25P128
28/41 Rev. 1
6.10 Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 17.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the valu e of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Era se (BE) instruction is e x ecuted only if all Bloc k Protect (BP2, BP1, BP0) bits are
0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 17. Bulk Erase (BE) Instruction Sequence
C
D
AI03752D
S
21 345670
Instruction
M25P128 Power-up and power-down
Rev. 1 29/41
7 Power-up and power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on VCC) until VCC reaches the correct value:
●VCC(min) at Power-up, and then for a further delay of tVSL
●VSS at Pow e r-down
Usually a simple pull-up resistor on Chip Select (S) can be used to ensure safe and proper
Power-up and Power-down.
To avoid data corruption and inadvertent write operations during Power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less
than the Power On Reset (POR) threshold vo ltage, VWI – all operations are disabled, and
the device does not respond to an y instruction.
Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Er ase
(SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of
tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the
correct opera tion of t he device is not guaranteed if, by this time , VCC is still belo w VCC(min).
No Write Status Register, Program or Erase instructions should be sent until the late r of:
●tPUW after VCC passed the VWI threshold
●tVSL after VCC passed the VCC(min) level
These values are specified in Table 8.
If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be
selected for READ instructions even if the tPUW delay is not yet fully elapsed.
At Power-up, the device is in the following state:
●The device is in the Standby Power mode
●The Write Enable Latch (WEL) bit is reset.
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply.
Each de vice in a system should ha v e the V CC rail decoupled b y a suitab le capacitor close to
the package pins. (Generally, this capacitor is of the orde r of 0.1µF).
At Power-down, when VCC drops from the operating voltage, to below the Power On Reset
(POR) threshold voltage, VWI, all operations are disabled and the device does not respond
to any instruction. (The designer needs to be aware that if a Power-down occurs while a
Write, Program or Erase cycle is in progress, some data corruption can result.)
Initial delivery state M25P128
30/41 Rev. 1
Figure 18. Power-up Timing
8 Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each byte
contains FFh). The Status Register contains 00h (all Status Register bits are 0).
Table 8. Power-Up Timing and VWI Threshold
Symbol Parameter Min. Max. Unit
tVSL(1)
1. These parameters are characterized only.
VCC(min) to S Low 60 µs
tPUW(1) Time delay to Write instruction 1 10 ms
VWI Write Inhibit Voltage 1.5 2.5 V
VCC
AI04009C
VCC(min)
VWI
Reset State
of the
Device
Chip Selection Not Allowed
Program, Erase and Write Commands are Rejected by the Device
tVSL
tPUW
time
Read Access allowed Device fully
accessible
VCC(max)
M25P128 Maximum rating
Rev. 1 31/41
9 Maximum rating
Stressing the device outside the ratings listed in Table 9 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any oth er
conditions outside those indicated in the Operating sections of this specification, is not
implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 9. Absolute Maximum Ratings
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 150 °C
VIO Input and Output Voltage (with respect to Ground) –0.5 4.0 V
VCC Supply Voltage –0.2 4.0 V
VESD Electrostatic Discharge Vo ltage (Human Body model) (1)
1. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
–2000 2000 V
DC and AC parameters M25P128
32/41 Rev. 1
10 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The paramete rs in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summa rized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurem ent conditions when relying on the quoted parameters.
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 19. AC Measurement I/O Waveform
1. Sampled only, not 100% tested, at TA=25°C and a frequency of 20 MHz.
Table 10. Operating Conditions
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 2.7 3.6 V
TAAmbient Operating Tempe rature –40 85 °C
Table 11. AC Measurement Conditions
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 30 pF
Input Rise and Fall Times 5 ns
Input Pulse Voltages 0.2VCC to 0.8VCC V
Input Timing Reference Voltages 0.3VCC to 0.7VCC V
Output Timing Reference Voltages VCC / 2 V
Table 12. Capacitance
Symbol Parameter Test Condition Min.Max.Unit
COUT Output Capacitance (Q) VOUT = 0V 8 p F
CIN Input Capacitance (other pins) VIN = 0V 6 p F
AI07455
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and Output
Timing Reference Levels
Input Levels
0.5VCC
M25P128 DC and AC parameters
Rev. 1 33/41
Table 13. DC Characteristics
Symbol Parameter Test Condition
(in addition to those in Table 10)Min. Max. Unit
ILI Input Leakage Current ± 2 µA
ILO Output Leakage Current ± 2 µA
ICC1 Standby Current S = VCC, VIN = VSS or VCC 100 µA
ICC3 Operating Current (READ)
C = 0.1VCC / 0.9.VCC at 50MHz,
Q = open 8mA
C = 0.1VCC / 0.9.VCC at 20MHz,
Q = open 4mA
ICC4 Operating Current (PP) S = VCC 20 mA
ICC5 Operating Current
(WRSR) S = VCC 20 mA
ICC6 Operating Current (SE) S = VCC 20 mA
ICC7 Operating Current (BE) S = VCC 20 mA
VIL Input Low Voltage – 0.5 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+0.2 V
VOL Output Low Voltage IOL = 1.6mA 0.4 V
VOH Output High Voltage IOH = –100µAV
CC–0.2 V
DC and AC parameters M25P128
34/41 Rev. 1
Table 14. AC Characteristics
Test conditions specified in Table 10 and Table 11
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfCClock Frequency for the following instructions: FAST_READ,
PP, SE, BE, WREN, WRDI, RDID, RDSR, WRSR D.C. 50 MHz
fRClock Frequency for READ instructions D.C . 20 MHz
tCH(1) tCLH Clock High Time 9 ns
tCL(1) tCLL Clock Low Time 9 ns
tCLCH(2) Clock Rise Time(3) (peak to peak) 0.1 V/ns
tCHCL(2) Clock Fall Time(3) (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup Time (relative to C) 5 ns
tCHSL S Not Active Hold Time (relative to C) 5 ns
tDVCH tDSU Data In Setup Time 2 ns
tCHDX tDH Data In Hold Time 5 ns
tCHSH S Active Hold Time (relative to C) 5 ns
tSHCH S Not Active Setup Time (relative to C) 5 ns
tSHSL tCSH S Deselect Time 100 ns
tSHQZ(2) tDIS Output Disable Time 8 ns
tCLQV tVClock Low to Output Valid 8 ns
tCLQX tHO Output Hold Time 0 ns
tHLCH HOLD Setup Time (rela tive to C) 5 ns
tCHHH HOLD Hold Time (relative to C) 5 ns
tHHCH HOLD Setup Time (rela tive to C) 5 ns
tCHHL HOLD Hold Time (relative to C) 5 ns
tHHQX(2) tLZ HOLD to Output Low-Z 8 ns
tHLQZ(2) tHZ HOLD to Output High-Z 8 ns
tWHSL(4) Write Protect Setup Time 20 ns
tSHWL (4) Write Protect Hold Time 100 ns
tWWrite Status Register Cycle Time 5 15 ms
tPP(5) Page Program Cycle Time (256 Bytes) 2.5 7ms
Page Program Cycle Time (n Bytes) 2.5
tSE Sector Erase Cycle Time 2 6 s
tBE Bulk Erase Cycle Time 105 250 s
1. tCH and tCL must be greater than or equal to 1/fC (max).
2. Value is guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for WRSR instruction when SRWD is set to 1.
5. Due to the Multi Level Cell technology, when using the Page Program (PP) instruction to program consecutive Bytes,
optimized timings are obtained with one sequence including all the Bytes versus several sequences of only a few Bytes. If
only a single byte is programmed, the estimated programming time is close to the time needed to program a full page of
256 Bytes. Therefore, it is highly recommended to use the Page Program (PP) instruction with a sequence of 256
consecutive Bytes. (1 ≤ n ≤ 256)
M25P128 DC and AC parameters
Rev. 1 35/41
Figure 20. Serial Input Timing
Figure 21. Write Protect Setup and Hold Timing during WRSR when SRWD=1
C
D
AI01447C
S
MSB IN
Q
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
C
D
S
Q
High Impedance
W
tWHSL tSHWL
AI07439
DC and AC parameters M25P128
36/41 Rev. 1
Figure 22. Hold Timing
Figure 23. Output Timing
C
Q
AI02032
S
D
HOLD
tCHHL
tHLCH
tHHCH
tCHHH
tHHQXtHLQZ
C
Q
AI01449e
S
LSB OUT
DADDR.LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
M25P128 Package mechanical
Rev. 1 37/41
11 Package mechanical
Figure 24. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8x6mm,
Package Outline
1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
Table 15. VDFPN8 (MLP8), 8-lead Very thin Dual Flat Package No lead, 8x6mm,
Package Mechanical Data
Symbol millimeters inches
Typ. Min. Max. Typ. Min. Max.
A 0.85 1.00 0.0335 0.0394
A1 0.00 0.05 0.0000 0.0020
b 0.40 0.35 0.48 0.0157 0.0138 0.0189
D 8.00 0.3150
D2 6.40 0.2520
ddd 0.05 0.0020
E 6.00 0.2362
E2 4.80 0.1890
e1.27– –0.0500– –
K 0.20 0.0079
L 0.50 0.45 0.60 0.0197 0.0177 0.0236
L1 0.15 0.0059
N8 8
D
E
VDFPN-02
A
e
E2
D2
L
b
L1
A1 ddd
Package mechanical M25P128
38/41 Rev. 1
Figure 25. SO16 wide – 16 lead Plast ic Sma ll Outl ine, 300 mils body width
1. Drawing is not to scale.
Table 16. S O1 6 wi de – 16 lead Plas t ic Sma ll Outl ine, 300 mils body width
Symbol millimeters inches
Typ Min Max Typ Min Max
A 2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B 0.33 0.51 0.013 0.020
C 0.23 0.32 0.009 0.013
D 10.10 10.50 0.398 0.413
E 7.40 7.60 0.291 0.299
e1.27– –0.050– –
H 10.00 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
L 0.40 1.27 0.016 0.050
θ0° 8° 0° 8°
ddd 0.10 0.004
E
16
D
C
H
18
9
SO-H
LA1
A
ddd
A2
θ
Be
h x 45˚
M25P128 Part numbering
Rev. 1 39/41
12 Part numbering
For a list of available options (speed, package, etc.) or for further infor mation on any aspect
of this device, please contact your nearest ST Sales Office.
The category of second-Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
Table 17. Ordering Information Scheme
Example: M25P128 – V MF 6 T P
Device Type
M25P = Serial Flas h Memory for Code Storage
Device Function
128 = 128Mit ( 16Mbx 8)
Operating Voltag e
V = VCC = 2.7 to 3.6V
Package
MF = SO16 (300 mil width)
ME = VDFPN8 8x6mm (MLP8)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
P or G = ECOPACK® (RoHs compliant)
Revision history M25P128
40/41 Rev. 1
13 Revision history
Table 18. Document Revision History
Date Revision Changes
02-May-2005 0.1 First issue.
09-Jun-2005 0.2 Table 2: Protected Area Sizes updated.
Memory capacity modified in Section 6 .3: Read Identification (RDID).
28-Aug-2005 0.3
Updated tPP values in Table 14: A C Characteristics and tVSL value in
Table 8: Pow er-Up Timing and VWI Threshold. Modified inform ation
in Section 4.1: Page programming and Section 6.8: Page Program
(PP).
20-Jan-2006 1
Document status promoted from Target specification to Preliminary
data.
Packages are ECOPACK® compliant. Blank option removed under
Plating Technology in Table 17. Read Electronic Signature (RES)
instruction removed. ICC1 parameter updated in Table 13: DC
Characteristics.
M25P128
Rev. 1 41/41
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of su ch information nor for any infringement of patents or other rights of third parties which may result from its use. No license is g ranted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change withou t notice . This p ublica tion su persed es and re plac es all i nformati on prev iously suppli ed. STMi croele ctronic s prod ucts ar e not
authorized for use as crit ical components in life support devices or systems without express writt en approval of STMi croelectro nics.
The ST logo is a registered trademark of STMicro electronics .
All other na mes are the propert y of their resp ective owners
© 2006 STMicroelectronics - All rights reserved
STMicroele ctr on ic s gr ou p of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germ any - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
