19-3045; Rev 0; 10/03 EVALUATION KIT AVAILABLE Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs Features The MAX5058/MAX5059 enable secondary-side synchronous rectification in isolated power supplies using widely available power MOSFETs. These devices facilitate the commutation of the secondary-side MOSFETs by providing a clean gate-drive signal that is synchronized to the power MOSFET switching in the primary side of the isolation transformer. The MAX5058/MAX5059 complement the MAX5051 and MAX5042/MAX5043 primaryside PWM ICs and enable the design of high-efficiency synchronously rectified isolated power supplies. Simultaneous conduction of the primary side and the freewheeling synchronous rectifier MOSFET is avoided by having a look-ahead signal (before the primary-side MOSFETs turn ON), thus eliminating large current spikes resulting from a shorted transformer secondary. Clean Drive Waveforms for Synchronous MOSFETs An on-board error amplifier with a versatile current reference output enables virtually unlimited possibilities in reference-voltage generation. Reference voltage for the error amplifier is generated by connecting an appropriate resistor to this output. Internal Remote Voltage-Sense Amplifier Low on-resistance margining MOSFETs integrated onchip allow for implementation of a margining circuit without the use of external switches. The MAX5058 provides a 5V LDO output for logic-level MOSFETs while the MAX5059 provides a 10V LDO output for conventional 10V MOSFETs. The MAX5058/MAX5059 are designed to enable paralleling of multiple power supplies for accurate current sharing using a simple 2-wire, differential, current-share bus. Parallelability enables expansion of the power capabilities and simplifies thermal management in highoutput-current applications. When used in conjunction with the MAX5051, the primaries can also be synchronized and operated 180 degrees out of phase. The MAX5058/MAX5059 are available in a 28-pin thermally enhanced TSSOP package and operate over a wide -40C to +125C temperature range. Warning: The MAX5058/MAX5059 are designed to work in circuits that contain high voltages. Exercise caution. Applications Isolated Telecom Power Supplies Isolated Networking Power Supplies 48V Power-Supply Modules Industrial Power Supplies 48V/12V Server Power Supplies Utilization of a Look-Ahead Signal from the Primary for Proper Turn-On/Turn-Off Times Synchronous Rectifier Drivers Capable of Sourcing and Sinking Up to 2A Peak Current Internal Gate-Voltage Regulator for 5V (MAX5058) or 10V (MAX5059) Gate-Drive Voltage Internal Error Amplifier Accurate Differential Current-Share/Force Circuit Allows Paralleling of Several Power Supplies for High Output Current Flexible Reference-Voltage Generation Output Voltage Regulation Down to 0.5V Low Quiescent Current Consumption of 2.5mA Integrated Digital Output Margining Circuit Saves External Parts and Board Space 30ns Propagation Delay Time from Pulse Input to Output Automatic Detection of Discontinuous Current Conduction and Turn-Off of the Freewheeling MOSFET High Efficiency at Low Output Currents and Reverse-Current Protection Open-Drain Overtemperature Warning Flag 28-Pin Thermally Enhanced TSSOP Package Ordering Information PART TEMP RANGE PINPACKAGE VREG (V) MAX5058AUI -40C to +125C 28 TSSOP-EP* 5 MAX5058EUI -40C to +85C 28 TSSOP-EP* 5 MAX5059AUI -40C to +125C 28 TSSOP-EP* 10 MAX5059EUI -40C to +85C 28 TSSOP-EP* 10 *EP = Exposed paddle. Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX5058/MAX5059 General Description MAX5058/MAX5059 Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs ABSOLUTE MAXIMUM RATINGS V+ to GND .............................................................-0.3V to +30V PGND to GND .......................................................-0.3V to +0.3V COMPV, VREG, VDR, TSF to GND......................... -0.3V to +14V All Other Pins to GND ..................................-0.3V to (VP + 0.3V) VREG Source Current .........................................................50mA COMPV, RMGU, RMGD, TSF Sink Current ....................... 30mA VP to GND ................................................................-0.3V to +6V VSO, CSO Source/Sink Current ......................................... 5mA SFP Source Current ............................................................. 5mA QREC, QSYNC Continuous Current....................................50mA QREC, QSYNC Current < 500ns..............................................5A Continuous Power Dissipation (TA = +70C) 28-Pin TSSOP (derate 23.8mW/C above +70C). ....1905mW Junction Temperature ......................................................+150C Operating Temperature Ranges MAX5058EUI, MAX5059EUI ............................-40C to +85C MAX5058AUI, MAX5059AUI..........................-40C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF = VVSP = 1.785V, CVREG = 2.2F, CVP = 1F, CCOMPS = 0.1F, CSFP = 68nF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY Supply Voltage Range V+ Quiescent Supply Current MAX5058 4.5 28.0 MAX5059 9.3 28.0 IQ Switching Supply Current ISW 2.5 fSW = 250kHz at BUFIN MAX5058 4.5 MAX5059 6 5 V mA mA IREF: REFERENCE CURRENT OUTPUT Reference Current Reference Current Variation IIREF IIREF Reference Voltage Compliance Range VIREF = 1.785V 49.2 51.1 A VIREF = 0.5V to 2.5V -0.1 50 +0.1 %/V Guaranteed by reference current variation test 0.5 2.5 V VREG: LOW-DROPOUT REGULATOR Regulator Output VVREG Line Regulation Dropout IVREG = 0 to 30mA MAX5058 4.75 5 5.25 MAX5059 9.4 10 10.6 MAX5058, V+ = 6V to 28V 25 MAX5059, V+ = 11V to 28V 25 MAX5058 V+ = 4.5V, IVREG = 30mA 200 350 MAX5059 V+ = 9.3V, IVREG = 30mA 200 350 VDROP V mV mV VP: INTERNAL REGULATOR Regulator Output Setpoint VVP IVP = 0 to 5mA 3.8 4.3 V +6.5 mV +2.5 A ZC: ZERO-CURRENT COMPARATOR Zero-Current Comparator Threshold Zero-Current Comparator Input Current 2 VZCTH IZC TA = +25C +3.5 +5 -2.5 _______________________________________________________________________________________ Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs (V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF = VVSP = 1.785V, CVREG = 2.2F, CVP = 1F, CCOMPS = 0.1F, CSFP = 68nF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL Zero-Current Comparator Input Range VZC Zero-Current Comparator Propagation Delay tZC CONDITIONS MIN TYP -0.1 MAX UNITS +1.5 V 10mV overdrive, from when VZCP - VZCN is greater than VZCTH to when QSYNC goes low 65 ns BUFIN rising to QREC rising or QSYNC falling 40 ns BUFIN: SYNCHRONIZING PULSE INPUT BUFIN to Output Propagation Delay BUFIN Input Current tpd IBUFIN BUFIN Input Capacitance CBUFIN BUFIN Input-Logic High VHBUFIN BUFIN Input-Logic Low VLBUFIN -1 +1 10 A pF 2.4 V 0.8 V MARGINING INPUTS RMGD Resistance RRMGD Sinking 10mA 6.5 11 RMGU Resistance RRMGU Sinking 10mA 6.5 11 MRGD Input-Logic High VHMRGD MRGD Input-Logic Low VLMRGD 0.8 V MRGU Input-Logic High VHMRGU MRGU Input-Logic Low VLMRGU MRGU, MRGD Input Resistance RMRGD, RMRGU 40 RMGU, RMGD Leakage Current IRMGU, IRMGD -100 2.4 V 2.4 V 0.8 V k +100 nA DRIVER OUTPUTS QREC, QSYNC Peak Source Current IQREC_SO, IQSYNC_SO QREC, QSYNC Output-Voltage High VQREC_H, VQSYNC_H QREC, QSYNC Low-to-High Delay Time tPDLH QREC, QSYNC Peak Sink Current IQREC_SI, IQSYNC_SI QREC, QSYNC Output-Voltage Low VQREC_L, VQSYNC_L QREC, QSYNC High-to-Low Delay Time tPDHL 2 Measured with respect to VVDR, sourcing 50mA A MAX5058 75 150 MAX5059 75 150 CQREC = CQSYNC = 0 30 CQREC = CQSYNC = 5nF 70 ns 2 Sinking 50mA A MAX5058 50 100 MAX5059 50 100 CQREC = CQSYNC = 0 40 CQREC = CQSYNC = 5nF 70 mV mV ns _______________________________________________________________________________________ 3 MAX5058/MAX5059 ELECTRICAL CHARACTERISTICS (continued) MAX5058/MAX5059 Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs ELECTRICAL CHARACTERISTICS (continued) (V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF = VVSP = 1.785V, CVREG = 2.2F, CVP = 1F, CCOMPS = 0.1F, CSFP = 68nF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS -50 +50 nA 0 2.5 V -5 +5 mV 200 mV ERROR AMPLIFIER Inverting Input Current IINV Error-Amplifier Input Range VINV Error-Amplifier Input Offset VOS ICOMPV = 100A to 5mA Error-Amplifier Output-Voltage Low VCOMPV Error-Amplifier Unity-Gain BW GBW RCOMP = 220, ICOMP = 5mA 1.3 MHz Error-Amplifier Voltage Gain AVOL RCOMPV = 220, ICOMP = 5mA 80 dB Error-Amplifier PSRR PSRR 60 dB 1 M COMPV Output Resistance to Ground ICOMPV = 5mA (Note 1) REMOTE-SENSE AMPLIFIER (RSA) VSN Input Current IVSN -100 +100 A VSP Input Current IVSP -20 +100 A Input Common-Mode Range Input Offset Voltage -0.3 VOSRSA IVSO = -0.5mA to +0.5mA Output Impedance Amplifier -3dB Frequency IVSO = -0.5mA to +0.5mA Remote-Sense Amplifier Gain GRS IVSO = -0.5mA to +0.5mA CSN Input Current ICSN -0.3V VCSN +3.8V, -0.3V VCSP +3.8V CSP Input Current ICSP -0.3V VCSP +3.8V +3.8 mV 8 1 0.9925 V -4 1 MHz 1.0075 V/V -150 +150 A -40 +150 A CURRENT-SENSE AMPLIFIER (CSA) Input Offset Voltage Current-Sense Amplifier Gain GCSA ICSO = -500A to +500A (Note 2) +20 +25 +30 mV ICSO = -500A to +500A 19.8 20 20.2 V/V Input Differential-Mode Range Input Common-Mode Range Output-Voltage Level Shift Output Voltage Range Amplifier -3dB Frequency VLS (Note 2) VCSO(MIN) ICSO = -500A to +500A f-3dB ICSO = -500A to +500A 100 mV -0.3 +3.8 V 0.415 0.570 V 0.1 3.0 50 V kHz SHARE-FORCE AMPLIFIER (SFA) Sink Current Source Current 4 60 500 _______________________________________________________________________________________ A A Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs (V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF = VVSP = 1.785V, CVREG = 2.2F, CVP = 1F, CCOMPS = 0.1F, CSFP = 68nF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CURRENT-ADJUST AMPLIFIER (CAA) Transconductance 500 Common-Mode Input Voltage Range 0.45 Output Voltage Range 2.55 0.85 TA = +25C Offset Voltage 20 Open-Loop Gain A/V 42 V 2.75 V 65 mV 72 dB CURRENT-ADJUST VOLTAGE-TO-CURRENT CONVERTER Input Voltage Range 0.75 Input Voltage Offset 2.75 1.25 Output Voltage Range 0.5 Transconductance 2.5 1.15 Maximum Current Adjustment Value 1.38 1.5 V V V A/V 1.66 A THERMAL SHUTDOWN +125 C Thermal Warning Flag Hysteresis 15 C Internal Thermal-Shutdown Level +160 C 15 C Thermal Warning Flag Level When TSF pulls low Internal Thermal-Shutdown Hysteresis TSF Maximum Output Voltage ITSF = 5mA TSF Output Leakage Current 120 mV 0.1 A Note 1: Output resistance to ground used for unity-gain stability. Note 2: VCSO = GCSA(VCSP - VCSN) + VLS. _______________________________________________________________________________________ 5 MAX5058/MAX5059 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF = VVSP = 1.785V, VCOMPS = 0.5V, CVREG = 2.2F, CVP = 1F, CCOMPS = 0.1F, CSFP = 68nF, TA = +25C, unless otherwise noted.) 50.11 5.0025 5.0020 5.0015 5.0010 5.0005 5.0000 4.9995 4.9990 VVREG (V) 50.09 IREF (A) 5.0030 VVREG (V) VIREF = 1.785V 50.15 50.13 50.07 50.05 50.03 50.01 49.99 49.97 49.95 49.93 0 3 6 12 15 18 21 24 27 30 9 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 10 20 30 40 50 60 70 80 90 100 110 TEMPERATURE (C) IVREG (mA) LDO OUTPUT VOLTAGE (VREG) vs. TEMPERATURE (MAX5058) LDO OUTPUT VOLTAGE (VVREG) vs. INPUT VOLTAGE (MAX5059) V+ (V) LDO OUTPUT VOLTAGE (VVREG) vs. LOAD CURRENT (MAX5058) 5.00 VVREG (V) 4.98 4.96 4.94 4.92 4.90 4.88 4.86 10.010 10.008 10.002 10.000 9.998 TEMPERATURE (C) 0 3 6 9 12 15 18 21 24 27 30 V+ (V) IREF OUTPUT CURRENT vs. IREF OUTPUT VOLTAGE LDO OUTPUT VOLTAGE (VVREG) vs. TEMPERATURE (MAX5059) 50.5 50.0 49.0 IIREF (A) 49.5 10.010 VVREG (V) MAX5058/59 toc08 MAX5058/59 toc07 51.0 10.015 10.005 48.5 10.000 48.0 9.995 47.5 9.990 47.0 9.985 46.5 46.0 9.980 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 6 10.012 10.004 IVREG (mA) 10.020 10.016 10.006 -40 -25 -10 15 20 35 50 65 80 95 110 125 10.025 10.018 10.014 0 10 20 30 40 50 60 70 80 90 100 110 10.030 10.020 VVREG (V) 5.02 5.010 5.008 5.006 5.004 5.002 5.000 4.998 4.996 4.994 4.992 4.990 4.988 4.986 4.984 4.982 4.980 MAX5058/59 toc05 MAX5058/59 toc04 5.04 10.10 10.08 10.06 10.04 10.02 10.00 9.98 9.96 9.94 9.92 9.90 9.88 9.86 9.84 9.82 9.80 MAX5058/59 toc03 5.0035 50.17 MAX5058/59 toc06 IVREG = 0mA 5.0045 5.0040 MAX5058/59 toc01 5.0050 LDO OUTPUT VOLTAGE (VVREG) vs. LOAD CURRENT (MAX5059) MAX5058/59 toc02 IREF OUTPUT CURRENT vs. TEMPERATURE LDO OUTPUT VOLTAGE (VVREG) vs. INPUT VOLTAGE (MAX5058) VVREG (V) MAX5058/MAX5059 Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VIREF (V) _______________________________________________________________________________________ Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs 12 15 18 21 24 27 30 MAX5058/59 toc10 MAX5058/59 toc11 2.40 2.35 2.30 2.25 2.20 2.15 2.10 2.05 2.00 0 V+ (V) 3 6 9 12 15 18 21 24 27 30 -40 -25 -10 5 20 35 50 65 80 95 110 125 V+ (V) TEMPERATURE (C) SWITCHING SUPPLY CURRENT vs. INPUT VOLTAGE (MAX5058) QUIESCENT SUPPLY CURRENT vs. TEMPERATURE (MAX5059) 5.0 MAX5058/59 toc12 3.0 2.9 2.8 4.0 3.0 IV+ (mA) 3.5 2.6 2.5 fSW = 250kHz 4.5 2.7 2.5 2.4 2.0 2.3 1.5 2.2 1.0 2.1 0.5 0 2.0 3 5 -40 -25 -10 5 20 35 50 65 80 95 110 125 7 9 11 13 15 17 19 21 23 25 27 29 TEMPERATURE (C) V+ (V) SWITCHING SUPPLY CURRENT vs. TEMPERATURE (MAX5058) SWITCHING SUPPLY CURRENT vs. INPUT VOLTAGE (MAX5059) fSW = 250kHz 4.6 6.0 5.5 5.0 4.5 MAX5058/59 toc14 5.0 4.8 2.50 2.45 MAX5058/59 toc13 9 2.60 2.55 4.4 IV+ (mA) 4.2 4.0 3.8 3.6 fSW = 250kHz MAX5058/59 toc15 6 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 IV+ (mA) IV+ (mA) 3 IV+ (mA) 0 QUIESCENT SUPPLY CURRENT vs. TEMPERATURE (MAX5058) QUIESCENT SUPPLY CURRENT vs. INPUT VOLTAGE (MAX5059) MAX5058/59 toc09 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 IV+ (mA) IV+ (mA) QUIESCENT SUPPLY CURRENT vs. INPUT VOLTAGE (MAX5058) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 3.4 3.2 3.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 0.5 0 3 5 7 9 11 13 15 17 19 21 23 25 27 29 V+ (V) _______________________________________________________________________________________ 7 MAX5058/MAX5059 Typical Operating Characteristics (continued) (V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF = VVSP = 1.785V, VCOMPS = 0.5V, CVREG = 2.2F, CVP = 1F, CCOMPS = 0.1F, CSFP = 68nF, TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF = VVSP = 1.785V, VCOMPS = 0.5V, CVREG = 2.2F, CVP = 1F, CCOMPS = 0.1F, CSFP = 68nF, TA = +25C, unless otherwise noted.) SWITCHING SUPPLY CURRENT vs. TEMPERATURE (MAX5059) 0.013 VSO OUTPUT (dB) 5.4 5.2 5.0 4.8 VVSP = 1.785V 0.014 4.6 0.012 0.011 0.010 4.2 0.008 4.0 0.007 19.99 1k 10k MAX5058/59 toc20 25.0 24.9 INPUT OFFSET (mV) 20.00 0.1k 24.8 24.7 24.6 24.5 24.4 24.3 19.98 24.2 19.97 24.1 24.0 19.96 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) TEMPERATURE (C) CSA GAIN vs. FREQUENCY ZERO-CURRENT COMPARATOR THRESHOLD vs. TEMPERATURE 5.35 ZCP THRESHOLD (mV) 20 15 10 5 0 -5 MAX5058/59 toc22 25 GAIN (dB) 5.40 MAX5058/59 toc21 30 5.30 5.25 5.20 5.15 5.10 -10 5.05 -15 5.00 -20 0.01 0.1 1 10 100 FREQUENCY (Hz) 8 1k 10k 100k FREQUENCY (Hz) 25.1 MAX5058/59 toc19 20.01 0 CSA INPUT OFFSET vs. TEMPERATURE CURRENT-SENSE AMPLIFIER (CSA) GAIN vs. TEMPERATURE CSA GAIN (V/V) -20 -40 TEMPERATURE (C) 20.02 -15 -35 TEMPERATURE (C) 20.03 -10 -30 -40 -25 -10 5 20 35 50 65 80 95 110 125 VCSP = 100mV 0 -25 -40 -25 -10 5 20 35 50 65 80 95 110 125 20.04 5 -5 0.009 4.4 10 MAX5058/59 toc18 5.6 0.015 GAIN (dB) fSW = 250kHz RSA GAIN vs. FREQUENCY MAX5058/59 toc17 5.8 REMOTE-SENSE AMPLIFIER (RSA) GAIN vs. TEMPERATURE MAX5058/59 toc16 6.0 IV+ (mA) MAX5058/MAX5059 Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) _______________________________________________________________________________________ 1M 10M 100M Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs 70 65 60 33.4 33.2 33.0 32.8 32.6 MAX5058/59 toc25 33.6 1.60 1.59 ADJUSTMENT RANGE (A) 75 SFP = +2.5V SFN = 0V 33.8 MAX5058/59 toc24 80 34.0 SFA SINK CURRENT (A) 10mV OVERDRIVE 1.58 1.57 1.56 1.55 1.54 1.53 32.4 1.52 55 32.2 1.51 50 32.0 1.50 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) TEMPERATURE (C) TEMPERATURE (C) BUFIN TO QREC HIGH-TO-LOW PROPAGATION DELAY vs. TEMPERATURE 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 MAX5058/59 toc27 PROPAGATION DELAY (ns) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 MAX5058/59 toc26 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) TEMPERATURE (C) BUFIN TO QSYNC LOW-TO-HIGH PROPAGATION DELAY vs. TEMPERATURE BUFIN TO QSYNC HIGH-TO-LOW PROPAGATION DELAY vs. TEMPERATURE 58 56 54 52 50 48 46 40 38 36 34 32 30 28 26 44 24 42 22 40 MAX5058/59 toc29 MAX5058/59 toc28 60 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) BUFIN TO QREC LOW-TO-HIGH PROPAGATION DELAY vs. TEMPERATURE PROPAGATION DELAY (ns) ZCP TO QSYNC DELAY (ns) 85 MAX5058/59 toc23 90 CURRENT-ADJUST VOLTAGE TO CURRENTCONVERTER ADJUSTMENT RANGE vs. TEMPERATURE SFA AMPLIFIER MAXIMUM SINK CURRENT vs. TEMPERATURE ZERO-CURRENT PROPAGATION DELAY vs. TEMPERATURE 20 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) TEMPERATURE (C) _______________________________________________________________________________________ 9 MAX5058/MAX5059 Typical Operating Characteristics (continued) (V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF = VVSP = 1.785V, VCOMPS = 0.5V, CVREG = 2.2F, CVP = 1F, CCOMPS = 0.1F, CSFP = 68nF, TA = +25C, unless otherwise noted.) MAX5058/MAX5059 Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs Pin Description PIN NAME 1 ZCP Zero-Inductor Current-Sense Comparator Input. The source voltage of the freewheeling FET (N4 in the Typical Application Circuit) is sensed. The gate drive is terminated when this voltage becomes positive during a primary power-OFF cycle. 2 ZCN Zero-Inductor Current-Sense Comparator Negative Input 3 GND Ground Connection 4 SFN Negative Input of the Share-Force Amplifier. Connect the SFN inputs together from all the power-supply secondaries, then connect to the load return terminal (isolated GND). Connect to GND when current sharing is not used. 5 SFP Positive Input of the Share-Force Amplifier. Connect the SFP pins together from all the power-supply secondaries. Leave this pin unconnected when current sharing is not used. 6 FUNCTION COMPS Compensation Output of the Load-Share Transconductance Amplifier 7 TSF Thermal Warning Flag Output 8 MRGU Margin-Up Logic Input. When toggled high, the power-supply output voltage is set to the high margin. 9 MRGD Margin-Down Logic Input. When toggled high, the power-supply output voltage is set to the low margin. 10 RMGD Resistor Connection for Margin-Down 11 RMGU Resistor Connection for Margin-Up 12 IREF Reference Current Output. A resistor from this current source output to GND sets the reference voltage used by the error amplifier. 13 COMPV Compensation Connection for the Error Amplifier. The feedback optocoupler LED is also connected to this point. This open-drain output is capable of sinking at least 5mA. 14 INV Inverting Input of the Error Amplifier. A voltage-divider connected to this input scales the power-supply output voltage for regulation. 15 VSO Output of the Remote-Sense Amplifier 16 VSN Negative Input of the Remote-Sense Amplifier. Connect this to the negative terminal of the load. 17 VSP Positive Input of the Remote-Sense Amplifier. Connect this to the positive terminal of the load. 18 CSO Output of the Current-Sense Amplifier. It can be used to monitor the output current. 19 CSN Connect this input to the negative terminal of the output current-sense resistor. Connect to GND when not used. 20 CSP Connect this input to the positive terminal of the output current-sense resistor. Connect to GND when not used. 21 VP Compensation Pin for Internal +4V Preregulator. A minimum 1F low-ESR capacitor must be connected to this pin for bypassing. 22 V+ Supply Connection for the IC and Input to the Internal 5V (MAX5058) or 10V (MAX5059) Regulator. Maximum voltage on this input is 28V. 23 VREG Regulated +5V (MAX5058) or +10V(MAX5059) Output Used by the Internal Circuitry and the Output Drivers. A minimum 1F capacitor must be connected to this pin for bypassing. 24 BUFIN Input for the Synchronizing Pulse. This pulse is provided by the primary-side power IC. 25 VDR 26 QREC Driver Output for the Rectifying MOSFET PGND Power-Ground Connection. Return ground connection for the gate-driver pulse currents. 27 28 -- 10 Supply Connection for the Output Drivers. Can be connected to VREG for 5V (MAX5058) or 10V (MAX5059) operation. QSYNC Driver Output for the Recirculating MOSFET EP Exposed Pad. This is the exposed pad on the underside of the IC. Connect the exposed paddle to GND and to a large copper ground plane to aid in heat dissipation. ______________________________________________________________________________________ Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs MAX5058/MAX5059 MARGINING BLOCK MRGU MAX5058/MAX5059 8 REGULATOR AND THERMAL MANAGEMENT BLOCK 50k UVLO AND THERMAL SHUTDOWN SD DRIVERS MRGD 9 22 V+ LDO 5V/10V PREG 4V 21 VP 23 VREG 50k 7 TSF 5 SFP 4 SFN +125C FLAG RMGD 10 QMD R CURRENT-SHARE BLOCK R RMGU 11 SFA QMU R R ERROR AMPLIFIER BLOCK COMPV 13 INV 14 V TO I CAA 42mV X2 10 CSN REFERENCE CURRENT BLOCK COMPS 20 CSP 0.5V I = (1.15 x (VCAA - 1.25))A VCAA 1.25V IREF 50A IREF 12 X1 500S E/A 6 18 CSO REMOTE-SENSE AMPLIFIER BLOCK VSO 15 VSN 16 X1 RSA VSP 17 GATE-DRIVER BLOCK 25 VDR BUFIN 24 ZCP 26 QREC 1 20ns 5mV 28 QSYNC ZCN 2 GND 3 27 PGND 20ns 30ns FALLING EDGE DELAY SD DRIVERS Figure 1. MAX5058/MAX5059 Functional Diagram ______________________________________________________________________________________ 11 MAX5058/MAX5059 Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs Detailed Description The MAX5058/MAX5059 enable the design of high-efficiency, isolated power supplies using synchronous rectification on the secondary side. These devices commutate the secondary-side MOSFETs by providing a clean gate-drive signal that is synchronized to the power MOSFET switching in the primary side of the isolation transformer. Once fully enhanced, the secondaryside MOSFETs have very low on-resistance, producing a voltage drop much lower than Schottky diodes, resulting in much higher efficiencies. Simultaneous conduction of the synchronous rectifier MOSFETs is avoided by having a look-ahead signal before the primary MOSFETs turn on. This eliminates large current spikes from a shorted transformer secondary. The MAX5058 has a 5V internal gate-drive voltage regulator that can be used with logic-level MOSFETs. The MAX5059 has a 10V internal gate-drive voltage regulator that can be used with high-gate-voltage MOSFETs. In addition to the gate drivers, there are blocks that make the MAX5058/MAX5059 complete secondaryside solutions. These blocks are as follows: * Regulator and thermal-management block * Buffer input and gate-driver block * Reference-current block * Error-amplifier block * Margining block * Remote-sense amplifier block * Current-share block Regulators and Thermal Management The linear regulators in the MAX5058/MAX5059 provide power for the internal circuitry, as well as power for running the external synchronous MOSFETs. Design is simplified by deriving the power from the secondary winding before the output-filter inductor. The peak voltage at the secondary is at least twice the output voltage, yielding more than 7V peak even for output voltages down to 3.3V. Use a diode and a capacitor to rectify and filter the voltage before applying it to V+ (see D6 and C32 in the Typical Application Circuit). The input for the regulator is V+ and the output is VREG. Connect VDR to VREG to provide the supply for the gate driver's QREC and QSYNC. For logic-level MOSFETs, use the MAX5058. For conventional MOSFETs that require 10V to be fully enhanced, use the MAX5059. The V+ input voltage range is from +4.5V to +28V. Supply enough current to this input to satisfy the quies- 12 cent supply current of the MAX5058/MAX5059, as well as the current for the MOSFET drivers. Estimate the total required supply current by using the following formula: IV + = ISW + fSW x (QN3 + QN4 ) where IV+ is the current that must be supplied into V+ and QN3, QN4 are the total gate charges of MOSFETs N3 and N4 in the Typical Application Circuit. fSW is the switching frequency and ISW is the switching current of the part. Use high-quality ceramic capacitors to bypass V+ and VREG. Use additional capacitance as required for bypassing switching currents generated by the drivers when driving the chosen MOSFETs. Connect at least a 1F ceramic capacitor at the output of the regulator VREG for stability. The MAX5058/MAX5059 have an exposed pad at the back of the package to enable heatsinking directly to a ground plane. When soldered to a 1in2 copper island, these devices are able to dissipate approximately 1.9W at +70C ambient temperature. Connect the exposed pad to the GND. In addition to the regulators, this block contains a thermal-shutdown circuit that shuts down the gate drivers if the die temperature exceeds +160C. This is a last resort shutdown mechanism. The trigger of this shutdown mechanism must be avoided. Turning off the secondary synchronous rectifier drivers in this manner while the output carries the full load current causes the current to be diverted to the lossy external diodes or body diodes of the MOSFETs. This, in most cases, leads to rectifier failure due to power dissipation. To prevent this, make use of the TSF output (temperature warning flag). TSF is an open-drain output that gets asserted when the die temperature exceeds +125C, well before the actual thermal shutdown at +160C. An optocoupler connected from VREG to the TSF pin can provide a means for shutting down the switching at the primary side, thus avoiding catastrophic failure. Buffer Input (BUFIN) and MOSFET Drivers The MAX5058/MAX5059 drive external N-channel MOSFETs at QSYNC and QREC. The QSYNC output drives the gate of the freewheeling MOSFET N4 in the Typical Application Circuit. The QREC output drives the gate of the rectifying MOSFET N3 in the Typical Application Circuit. Each gate-driver output is capable of sinking and sourcing up to 2A peak current, enabling the MAX5058/MAX5059 to drive high-gatecharge MOSFETs. ______________________________________________________________________________________ Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs When BUFIN goes high, QREC goes high and QSYNC goes low. When BUFIN goes low, QREC goes low and QSYNC goes high. The MAX5058/MAX5059 provide improved efficiency at light loads by allowing discontinuous conduction operation. A zero-crossing comparator with inputs ZCP and ZCN monitors the current through the freewheeling MOSFET using a sense resistor at its source. The freewheeling MOSFET is turned off when the inductor current is near zero. The actual threshold can be externally adjusted. The Typical Application Circuit shows one method for trip-point adjustment using components R31 and R34. BUFIN is internally clamped to 4V. Use a voltage-divider, if necessary, to reduce any external voltage applied to this pin to less than 4V. MAX5042 MAX5043 MAX5058 REG5 BSS84 PPWM VREG (5V) 560 330 BUFIN 2k PS9715 OR EQUIVALENT HIGH-SPEED OPTOCOUPLER PWMNEG GND Figure 2. Interface of MAX5058 to MAX5042/MAX5043 Using a High-Speed Optocoupler MAX5042 MAX5043 MAX5059 3.10k MMBT3904 REG5 PPWM VREG (10V) BSS84 560 330 BUFIN 2k PWMNEG PS9715 OR EQUIVALENT HIGH-SPEED OPTOCOUPLER 1F 4.42k GND Figure 3. Interface of MAX5059 to MAX5042/MAX5043 Using a High-Speed Optocoupler ______________________________________________________________________________________ 13 MAX5058/MAX5059 The MOSFET drivers are synchronized to the primaryside switching by using the BUFIN input. BUFIN accepts the PWM information from the primary through a high-speed optocoupler or through a small isolation pulse transformer. Figures 2 through 6 show the interface details using an optocoupler or a pulse transformer with two different kinds of primary-side PWM controllers. For proper operation, the MAX5051, MAX5042, and MAX5043 devices generate a look-ahead signal that precedes the actual switching of the primary MOSFETs by a small amount of time, typically less than 100ns. Additional circuitry may be required when the MAX5058/MAX5059 are used with other primary-side controllers not capable of providing a look-ahead signal. MAX5058/MAX5059 Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs 4.7 MAX5051 MAX5058 REG5 LXVDD BSS84 LXH VREG (5V) 560 330 BUFIN 1F 2k 2k PS9715 OR EQUIVALENT HIGH-SPEED OPTOCOUPLER GND GND Figure 4. Interface of MAX5058 to MAX5051 Using a High-Speed Optocoupler 4.7 MAX5051 MAX5059 REG5 3.10k MMBT3904 LXVDD VREG (10V) BSS84 LXH 560 330 BUFIN 1F 2k 2k 1F PS9715 OR EQUIVALENT HIGH-SPEED OPTOCOUPLER GND 4.42k GND Figure 5. Interface of MAX5059 to MAX5051 Using a High-Speed Optocoupler MAX5051 MAX5058 MAX5059 4.7 REG5 LXVDD 1F D1 T1 LXH 1N4148 301 BUFIN 2k LXL GND D2 GND T1: PULSE ENGINEERING, PE-68386 D1, D2: CENTRAL SIMICONDUCTOR, CMOSH-3 Figure 6. Interface Circuit to MAX5051 Using a Pulse Transformer 14 ______________________________________________________________________________________ Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs When the inductor current is allowed to become discontinuous, the loop dynamics change and the circuit must be compensated accordingly to accommodate stable continuous and discontinuous mode operation. Turning off the freewheeling MOSFET is accomplished by using the zero-current comparator (pins ZCP and ZCN). Use this comparator to sense reverse current in the freewheeling MOSFET and turn off the device by pulling QSYNC low. An internal latch prevents the freewheeling MOSFET from turning on until the off-time of the next cycle. connected from IREF to GND. INV is the inverting input and connects to the center of a resistive divider from OUT to INV to GND. The output of the error amplifier, COMPV, connects to the cathode of the LED in the optocoupler to control the diode current that transmits the error signal back to the primary-side controller. An open-drain-output error amplifier simplifies interfacing with the feedback optocoupler. Use this error amplifier the same way as the industry-standard TL431 shunt reference. The open-drain output provides flexibility that may be necessary when additional functionality such as secondary current-limit regulation is required. Unlike the TL431, the output of the internal error amplifier of the MAX5058/MAX5059 is guaranteed to be a maximum of 200mV with a 5mA drain current, compared to 2.5V for the TL431 and 1.24V for the TLV431. In some cases, it is possible to avoid the use of the output voltage-divider (R1 and R2) by connecting INV to the output through just R1. This eliminates the voltage tolerance errors caused by R1 and R2. Output voltage in this configuration is set directly by using a suitable resistor at IREF. Figure 7 shows this configuration. VOUT Reference Current R1 The MAX5058/MAX5059 do not have an explicit reference voltage generator. Instead, they contain a 1%accurate trimmed 50A current source. This allows significant flexibility in setting the reference voltage. In some cases, the output-voltage resistive divider, consisting of R1 and R2 in the Typical Application Circuit, can be eliminated by selecting a suitable resistor value at the IREF pin. This reduces the error that the output voltage-divider may add. Use a low-value bypass capacitance at this pin to eliminate noise. Typical values for this capacitance are calculated by considering the pole that it presents with R12. This pole must be placed well beyond the frequency range of interest of the current-share loop. Use values less than 2.2nF. Error Amplifier The MAX5058/MAX5059 incorporate a 1.3MHz unity gain-bandwidth error amplifier with inputs INV, IREF, and output COMPV. IREF is the noninverting input and also serves as the reference voltage generator with the internal 50A current source and the external resistor COMPV 13 C28 INV 14 E/A VOUT = (50A) x R12 FOR: 0.5V VOUT 2.5V IREF 50A IREF 12 R12 Figure 7. Output Voltage Regulation for 0.5V VOUT 2.5V ______________________________________________________________________________________ 15 MAX5058/MAX5059 Reverse-Current Prevention in Synchronous Rectifiers One benefit of secondary-side synchronous rectification is increased efficiency. Another benefit is that it allows the inductor current to remain continuous throughout the operating load range. This results in constant loop dynamics that are easy to compensate. In some cases, it may be necessary to turn off the freewheeling MOSFET when the current through this device attempts to flow from drain to source. Turning off this MOSFET can be done to enhance efficiency at low output current. When multiple power supplies are paralleled, the power supply with the highest output voltage has a tendency to source current into the power-supply outputs with lower output voltage. Turning off the freewheeling MOSFET also prevents this current back-flow. MAX5058/MAX5059 Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs VOUT > 2.5V C27 R19 R12 R12 COMPV 13 C28 INV 14 Figure 8 shows a typical configuration with output voltages high enough (VOUT > 2.5V) to allow a typical optocoupler to be fully biased. In this case, there are two feedback paths--one though the error amplifier and one through the output-connected optocoupler. This second feedback path must be considered when compensating the overall feedback loop. Figure 9 shows a typical configuration with an optocoupler for output voltages lower than 2.5V. In this case, the direct connection of the optocoupler to the output is not possible. There is only one feedback path and the error-amplifier feedback network must be designed accordingly. Figure 10 shows the simplified block diagram for the error amplifier. E/A Voltage Margining IREF 12 IREF 50A R12 Figure 8. Optocoupler Connection for VOUT > 2.5V VREG (PIN 23) 0.5V < VOUT < 2.5V C27 R19 Rff COMPV C28 13 Rf R1 INV 14 Cf The margining inputs MRGU (margin up) and MRGD (margin down) control two internal MOSFETs with opendrain outputs at RMGU and RMGD, respectively. When margining is used, connect two pullup resistors from RMGU and RMGD to I REF . A logic-high voltage at MRGU causes QMU (see Figure 1) to open, increasing the equivalent resistance at IREF and the reference voltage (VIREF). The error-amplifier inverting input, INV, tracks IREF and forces the primary-side controller to increase the output voltage. MRGD has the opposite effect. When a logic high is applied to MRGD, QMD turns on, decreasing the equivalent resistance at IREF and effectively reducing VIREF. This causes INV to track and force the primary-side controller to reduce the output voltage. The margining inputs MRGU and MRGD are internally pulled to GND with 40k resistors. When margining is not used, the inputs can be left floating or connected to GND to make VIREF = 50A x R12. Calculation Procedure for Output-Voltage Setting Resistors and Margining Use the following step-by-step procedure to calculate the output-voltage setting and margining resistors (see the Typical Application Circuit): E/A IREF 50A INV 14 IREF 12 IREF R12 Figure 9. Optocoupler Connection for VOUT < 2.5V 16 12 Figure 10. Simplified Error-Amplifier Diagram ______________________________________________________________________________________ COMPV 13 Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs R32 = Req x 5) Select the margin-down percentage value: D = 5% 6) Recalculate Req with the selected values: Req = Req = 35.24k. 7) Calculate R33: 100% + U U R32 = 743.4k. Calculated Select the nearest 0.1% value. R32 = 741k. R12R32 R12 + R32 R33 = Selected 100% x Req x R12 R12 x (100% + D) - 100% x Req R33 = 361.186k. 4) Calculate R12: Calculated Select the nearest 0.1% value: R x U R12 = 32 100% R33 = 361k. Selected 8) Calculate the reference voltage with the selected chosen values: Req from step 6. VIREF = 50A Req. VIREF = 1.762V. R12 = 37.05k. Calculated Select the nearest 0.1% value. R12 = 37k. Selected VOUT COMPV 13 C28 VSP 17 VSO 15 INV 14 E/A RSA VSN 16 VOUT = (50A) x R12 FOR: 0.5V VOUT 2.5V IREF 50A IREF 12 R12 Figure 11. Remote-Sense Amplifier Connection for 0.5V VOUT 2.5V ______________________________________________________________________________________ 17 MAX5058/MAX5059 1) Select a parallel equivalent resistance Req value to produce the nominal reference voltage. For example, Req = 35.4k gives you VIREF = 1.77V. 2) Select the margin-up percentage value: U = 5% 3) Calculate R32: MAX5058/MAX5059 Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs VOUT R1 R2 COMPV 13 C28 VSP 17 VSO 15 INV 14 RSA VSN 16 E/A R1 VOUT = 1 + R2 ( IREF IREF 50A 12 ) VIREF VIREF = (50A) R12 R12 Figure 12. Remote-Sense Amplifier Connection for VOUT > 2.5V (or any Other Arbitrary Voltage) 9) Select a value for R1 and calculate R2 for VOUT = 3.3V: R1 = 19.1k R2 = VIREF R1 VOUT - VIREF 11 shows this configuration. Figure 12 shows the use of the remote-sense amplifier with a voltage-divider. The remote-sense amplifier has an input bias current of 100A. The impedance of R1 and R2 must be kept low in this configuration to avoid excessive errors in the output-voltage set point. Current Sharing R2 = 21.882k. Select the nearest 1% value. R2 = 21.8k. When margining is not used, substitute R12 for Req in step 8 and go to step 9. Remote-Sense Amplifier Use the remote-sense amplifier (RSA in Figure 1) to directly sense the voltage across the load, compensating for voltage drops in PC board tracks or load connection wires. The remote-sense amplifier is a unity-gain amplifier with sufficient bandwidth to not interfere with the normal operation of the voltage-control loop. Direct sensing of the output voltage is possible if the output voltage is between 0.5V to 2.5V. Figure 18 When multiple power modules are providing power to the same load, the load current must be shared equally to provide the best reliability and thermal distribution. The MAX5058/MAX5059 contain circuitry that enable current sharing among paralleled power supplies without requiring an explicit controlling master circuit. Current sharing is accomplished by connecting together the current-share bus pins (SFP and SFN) of all paralleled power supplies (see Figure 13), thus creating a current-force/share bus. The voltage level on this differential bus is proportional to the output current of the power supply that has the highest current compared to the other supplies. The number of power supplies that can be paralleled with this method is limited only by practical considerations. ______________________________________________________________________________________ Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs MRGD MAX5058/MAX5059 MRGU CSN POWER MODULE CSP VIN+ VOUT+ VIN- MAX5058 MAX5051 AND VSP VSN OR SYNCIN VOUT- MAX5059 STARTUP SYNCOUT SFN SFP MRGU MRGD CSN POWER MODULE CSP VIN+ 36V TO 72V VIN+ VIN- VIN- VOUT+ MAX5051 MAX5058 VSP OR VSN AND SYNCIN LOAD VOUT- MAX5059 STARTUP SYNCOUT SFN SFP MRGU MRGD CSN POWER MODULE CSP VIN+ VOUT+ VIN- MAX5051 MAX5058 VSP OR VSN AND SYNCIN STARTUP VOUT- MAX5059 SYNCOUT SFN SFP Figure 13. Paralleling Multiple Power-Supply Modules for Current Sharing When the MAX5051 is used as the primary-side controller, additional benefits are also realized with its special paralleling pins. The MAX5051 allows simultaneous shutdown and wake-up, as well as frequency synchronization and 180 degree out-of-phase operation of each connected primary. The current-share loop consists of the following functional blocks: * A diode ORed force amplifier that connects with the other modules and forces the bus to carry a voltage proportional to the highest current among the modules. * A sense amplifier that senses this share-bus voltage and applies it to internal circuitry. * A fixed gain of 20, current-sense amplifier that senses the output current through a sense resistor. * A current-adjust amplifier that functions as an erroramplifier block in the current-share loop. * A voltage-to-current (VtoI) block that adds a small amount of current to the reference current, increasing the reference voltage and enabling the module to share more current. ______________________________________________________________________________________ 19 MAX5058/MAX5059 Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs Current-sharing functions follow: The voltage across the current-sense resistor for each module is sensed and compared to the voltage on the current-share bus. The voltage on the current-share bus represents the current from the module that has the highest output current compared to the other modules. Each module compares its current to this maximum current. If its current is less than the maximum, then the module increases its reference current with the VtoI block. This raises the reference voltage presented at the noninverting input of the error amplifier. With a higher reference voltage, the output voltage of the module rises in an attempt to increase its output current. This process continues until the currents balance between the modules. The current-adjust amplifier (see Figure 1) has an offset at its inverting input that requires the share-bus voltage to reach 40mV before the current-share control loop attempts to regulate the output-load-current balance. Thus, the current-share regulation does not begin until the current-sense signals have exceeded 2mV (i.e., 42mV/20). V TO I 1.5A SLOPE = 1.15A/V VCAA 1.25V Figure 14. Transfer Function Curve of the V to I Block FEEDBACK NETWORK PWM STAGE AND FILTERS E/A VOUT RS + VSENSE - GPS (s) RLOAD GCSA (s) GV TO I (s) GCAA (s) CAA V TO I RIREF CSA CCOMPS Figure 15. Small-Signal Equivalent Current-Share Control Loop The adjustment range and thus the sharing capability of the modules is limited by the amount of additional output voltage boost possible through the VtoI block. The typical voltage boost is +3% (i.e., 1.5A/50A). Figure 14 shows the transfer function of the VtoI block. This adjustment range also sets a limit on the amount of voltage drop allowed for current sharing. For effective current sharing, the sum of all voltage drops must be kept below 3% and the output-to-load connection drop of each power module must be kept equal. 20 Figure 15 shows the simplified equivalent small-signal circuit of the current-share control loop. The currentadjust amplifier represents the error amplifier in this loop. The command signal, which is the voltage across the SFP and SFN pins, is applied to the noninverting input of this amplifier. For small-signal analysis, the noninverting pin is shown grounded in Figure 15. This is a low-bandwidth loop. Assuming a much smaller unity-gain crossover bandwidth (fCS) for the current-share loop compared to the main output-voltage-regulation loop (i.e., fCS << fC), the open-loop gain of the current-share loop can be written as: GCAA (s) GT (s) = GSFA (s) x x (GVtoI(s) x RIREF ) s x CCOMPS x GPS (s) x RS RS + RLOAD where fCS is the unity-gain crossover frequency of the current-share loop (typically 10Hz to 100Hz), fC is the unity-gain crossover frequency of the main output loop, GPS(s) is the gain of the power stage from the reference voltage input of the error amplifier to the output (GPS = VOUT/VIREF), RS is the current-sense resistor, and RLOAD is the load resistance. Note that the currentshare loop bandwidth is highest for the lowest value of RLOAD (maximum load). ______________________________________________________________________________________ Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs 90 GAIN (dB/DIV) 45 PHASE GAIN 5 0 0 -5 -10 PHASE (DEGREES/div) 15 10 Equating |GT| = 1 and solving for CCOMPS yields: CCOMPS = -45 -15 -20 -90 1 10 100 1k 10k FREQUENCY (Hz) Figure 16. Idealized (with Ideal Power Stage and Optocoupler) Frequency Response (GPS(s)) from Noninverting Input of the Error Amplifier to the Output of the Power Supply for the Typical Application Circuit of Figure 18 80 40 90 20 45 0 0 -20 -45 GAIN -40 -90 -60 -135 -80 -180 1 10 100 1k PHASE (DEGREES/div) 135 PHASE (36.61F x Hz / V) x RS x VOUT fCS x (RS + RLOAD ) The current-sharing loop is compensated with a capacitor from COMPS to GND. This results in a dominant pole that forces the loop gain of the current-share loop to cross 0dB with a single pole (20dB/decade) rolloff. When RLOAD >> RS, the above can be simplified further. CCOMPS = (36.61F x Hz / V) x RS x VOUT fCS x RLOAD Example: RS = 2m VOUT = 3.3V 180 60 GAIN (dB/DIV) x (1.15A / V ) x RIREF s x CCOMPS V RS x OUT x VIREF RS + RLOAD 10k FREQUENCY (Hz) Figure 17. Overall Open-Loop Response of the Current-Share Loop Figure 16 shows the idealized small-signal response of the Typical Application Circuit from the noninverting input of the error amplifier to the output. This response shows that the unity-gain crossover frequency of the current-share loop can easily be placed between 10Hz and 100Hz, while at the same time avoiding interaction with the main voltage-control loop. For frequencies below 100Hz, GT(s) can be written as (using the DC gain value for GPS(s)): fCS = 10Hz RLOAD = 0.22 CCOMPS = (36.61F x Hz / V) x (0.002) x (3.3V) (10Hz) x (0.22) 0.11F The resulting overall open-loop response of the currentshare control loop is shown in Figure 17. Applications Information Isolated 48V Input Power Supply Figure 18 shows a complete design of an isolated synchronously rectified power supply with a +36V to +75V telecom input voltage range. This design uses the MAX5051 as the primary-side controller and the MAX5058 as the secondary-side synchronous rectifier driver. Figures 19 though 24 show some of the performance aspects of this power-supply design. This power supply can sustain a continuous short circuit at its output terminals. This circuit is available as a completely built and tested evaluation kit (MAX5058EVKIT). ______________________________________________________________________________________ 21 MAX5058/MAX5059 20 (500S) GT (s) = 20 x POWER-STAGE GAIN/PHASE 22 D8 C17 0.33F R11 360 R3 2.2k REG5 LXL LXH R27 10 LXVDD C18 1000pF 3 4 14 13 12 11 10 9 8 7 6 5 4 3 2 1 U2 REG9 PVIN REG9 REG5 C26 0.1F C19 1F C6 0.1F C4 4.7F R15 31.6k 1% C5 4700pF C2 390pF TP5 C1 100pF C3 4.7F R16 10.5k 1% R25 100k R21 24.9k 1% REG5 C24 1000pF +VIN REG5 LXL LXH 2 1 LXVDD STT PVIN REG9 REG5 FB COMP CSS CON RCFF SYNCOUT RCOSC C27 0.15F OPTO_CAT R19 475 CS DRVL PGND DRVDD DRVB XFRMRH DRVH BST AVIN IC_PADDLE MAX5051 U1 GND UVLO STARTUP FLTINT SYNCIN VOUT 29 15 16 17 18 19 20 21 22 23 24 25 26 27 28 TP6 C8 4.7F D1 C9 1F DRVB Figure 18. Schematic of a +48V Input, 3.3V at 15A Output, Synchronous Rectified, Isolated Power Supply ______________________________________________________________________________________ LXL LXVDD LXH C31 0.1F C22 2200pF 2kV +VIN XFRMRH C20 220pF REG9 +VIN ON/OFF C7 0.22F D7 D9 R14 270 R9 8.2 R8 8.2 R7 0 R4 1M 1% R35 0 6 5 3 1 R17 0.027 1% 4 D3 1 T2 C21 4.7F 80V PVIN N2 3 2 7 8 C34 330pF 4 6 D10 R22 15k R18 4.7 D5 R13 47 R6 R5 1M 38.3k 1% 1% REG9 +VIN 6 1 5 2 3 R28 301 1% +VIN 4T 8T T1 1 2 10 2T 8 XFRMRH D2 XFRMRH 3 2 8 7 R30 2k 1% 4 N1 D6 6 7 1 6 5 4 N3 1 7 8 C16 3.3F C29 1F C35 1F 3 N4 4 R26 0.002 2 6 5 V+ VREG V+ R24 10 (CSP) TP1 R27 10 R38 10 C39 220pF R31 220 1% L1 2.4H C11 0.47F 100V VOUT (CSN) C10 0.47F 100V VOUT C30 1F C32 1F D4 C23 1000pF R10 20 5 8 C13 270F 4V 24 25 23 22 21 20 19 18 17 16 26 2 1 BUF_IN VDR VREG V+ VP CSP CSN CSO VSP VSN +VIN VDD = 3V RL = 16 fIN = 10kHz PGND GND SFN SFP COMPS TSF MRGU MRGD RMGD RMGU IREF COMPV 29 27 3 4 5 6 7 8 9 10 11 12 13 VSO 14 INV 15 C15 270F 4V (CSP) 2 N5 3 IC_PADDLE MAX5058 U3 QSYNC 28 VREG C14 270F 4V C25 0.047F 100V QREC ZCN ZCP R34 220 C12 1F 100V +VIN C36 1F R33 340k 0.5% R23 10 TP2 TP8 TPMU C37 220pF R12 34.8k 0.5% OPTO_CAT TPMD C28 0.047F SGND R20 0.004 1% TP7 R2 19.1k 1% R1 19.1k 1% VOUT DRVB C38 0.068F TP3 R36 VOUT (CSN) 0.004 1% R29 1 XFRMRH R32 698k 0.5% C33 1F 10V 1 -VIN MAX5058/MAX5059 Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs Typical Application Circuit Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs 8 90 7 POWER DISSIPATION (W) R20 = R26 = R36 = 0 EFFICIENCY (%) 85 80 75 70 65 6 5 4 3 2 1 R20 = R26 = R36 = 0 0 60 0 2 4 6 8 10 12 0 14 Figure 19. Efficiency at Nominal 3.3V Output Voltage vs. Load Current (48V Nominal Input Voltage) RL = 0.22 2 4 6 8 10 12 14 LOAD CURRENT (A) LOAD CURRENT (A) R20 = R26 = R36 = 0 Figure 20. Power Dissipation at Nominal 3.3V Output Voltage vs. Load Current (48V Nominal Input Voltage) R20 = R26 = R36 = 0 VOUT 100mV/div VOUT 1V/div ILOAD 5A/div ILOAD 5A/div 4ms/div Figure 21. Turn-On Transient at Full Load (Resistive Load) VOUT 1ms/div Figure 22. Output Voltage Response to Step Change in Load Current (ILOAD from 50%, max to 75%, max) ______________________________________________________________________________________ 23 MAX5058/MAX5059 95 MAX5058/MAX5059 Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs R20 = R26 = R36 = 0 R20 = R26 = R36 = 0 ILOAD 10A/div 1ms/div VOUT 50mV/div ILOAD 10A/div 20ms/div 2s/div Figure 23. Output Voltage Ripple at +48V Nominal Input Voltage and Full Load Current (Scope Bandwidth = 20MHz) Pin Configuration Figure 24. Load Current (10A/div) as a Function of Time when the Converter Attempts to Turn On into a 50m Short Circuit Chip Information TRANSISTOR COUNT: 1762 PROCESS: BiCMOS TOP VIEW ZCP 1 28 QSYNC ZCN 2 27 PGND GND 3 26 QREC SFN 4 25 VDR SFP 5 COMPS 6 MAX5058AUI MAX5059AUI 24 BUFIN 23 VREG TSF 7 22 V+ MRGU 8 21 VP MRGD 9 20 CSP RMGD 10 19 CSN RMGU 11 18 CSO IREF 12 17 VSP COMPV 13 16 VSN INV 14 15 VSO TSSOP CONNECT EXPOSED PADDLE TO GND. 24 ______________________________________________________________________________________ Parallelable Secondary-Side Synchronous Rectifier Driver and Feedback-Generator Controller ICs TSSOP 4.4mm BODY.EPS AA AA Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX5058/MAX5059 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)