General Description
The MAX5058/MAX5059 enable secondary-side syn-
chronous rectification in isolated power supplies using
widely available power MOSFETs. These devices facili-
tate the commutation of the secondary-side MOSFETs by
providing a clean gate-drive signal that is synchronized
to the power MOSFET switching in the primary side of
the isolation transformer. The MAX5058/MAX5059 com-
plement the MAX5051 and MAX5042/MAX5043 primary-
side PWM ICs and enable the design of high-efficiency
synchronously rectified isolated power supplies.
Simultaneous conduction of the primary side and the
freewheeling synchronous rectifier MOSFET is avoided
by having a look-ahead signal (before the primary-side
MOSFETs turn ON), thus eliminating large current spikes
resulting from a shorted transformer secondary.
An on-board error amplifier with a versatile current ref-
erence output enables virtually unlimited possibilities in
reference-voltage generation. Reference voltage for the
error amplifier is generated by connecting an appropri-
ate resistor to this output.
Low on-resistance margining MOSFETs integrated on-
chip allow for implementation of a margining circuit
without the use of external switches. The MAX5058 pro-
vides a 5V LDO output for logic-level MOSFETs while
the MAX5059 provides a 10V LDO output for conven-
tional 10V MOSFETs.
The MAX5058/MAX5059 are designed to enable paral-
leling of multiple power supplies for accurate current
sharing using a simple 2-wire, differential, current-share
bus. Parallelability enables expansion of the power
capabilities and simplifies thermal management in high-
output-current applications. When used in conjunction
with the MAX5051, the primaries can also be synchro-
nized and operated 180 degrees out of phase.
The MAX5058/MAX5059 are available in a 28-pin ther-
mally enhanced TSSOP package and operate over a
wide -40°C to +125°C temperature range.
Warning: The MAX5058/MAX5059 are designed to
work in circuits that contain high voltages. Exercise
caution.
Applications
Isolated Telecom Power Supplies
Isolated Networking Power Supplies
±48V Power-Supply Modules
Industrial Power Supplies
±48V/±12V Server Power Supplies
Features
♦Clean Drive Waveforms for Synchronous
MOSFETs
♦Utilization of a Look-Ahead Signal from the
Primary for Proper Turn-On/Turn-Off Times
♦Synchronous Rectifier Drivers Capable of
Sourcing and Sinking Up to 2A Peak Current
♦Internal Gate-Voltage Regulator for 5V (MAX5058)
or 10V (MAX5059) Gate-Drive Voltage
♦Internal Error Amplifier
♦Accurate Differential Current-Share/Force Circuit
Allows Paralleling of Several Power Supplies for
High Output Current
♦Internal Remote Voltage-Sense Amplifier
♦Flexible Reference-Voltage Generation
♦Output Voltage Regulation Down to 0.5V
♦Low Quiescent Current Consumption of 2.5mA
♦Integrated Digital Output Margining Circuit Saves
External Parts and Board Space
♦30ns Propagation Delay Time from Pulse Input
to Output
♦Automatic Detection of Discontinuous Current
Conduction and Turn-Off of the Freewheeling
MOSFET
♦High Efficiency at Low Output Currents and
Reverse-Current Protection
♦Open-Drain Overtemperature Warning Flag
♦28-Pin Thermally Enhanced TSSOP Package
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
________________________________________________________________ Maxim Integrated Products 1
19-3045; Rev 0; 10/03
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Pin Configuration appears at end of data sheet.
EVALUATION KIT
AVAILABLE
Ordering Information
PART
TEMP RANGE
PIN-
PACKAGE
VREG
(V)
MAX5058AUI -40°C to +125°C 28 TSSOP-EP*
5
MAX5058EUI
-40°C to +85°C 28 TSSOP-EP*
5
MAX5059AUI -40°C to +125°C 28 TSSOP-EP*
10
MAX5059EUI
-40°C to +85°C 28 TSSOP-EP*
10
*EP = Exposed paddle.
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF =
VVSP = 1.785V, CVREG = 2.2µF, CVP = 1µF, CCOMPS = 0.1µF, CSFP = 68nF, TA= TMIN to TMAX, unless otherwise noted. Typical values
are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V+ to GND .............................................................-0.3V to +30V
PGND to GND .......................................................-0.3V to +0.3V
COMPV, VREG, VDR, TSF to GND......................... -0.3V to +14V
All Other Pins to GND ..................................-0.3V to (VP + 0.3V)
VREG Source Current .........................................................50mA
COMPV, RMGU, RMGD, TSF Sink Current ....................... 30mA
VP to GND ................................................................-0.3V to +6V
VSO, CSO Source/Sink Current ......................................... ±5mA
SFP Source Current ............................................................. 5mA
QREC, QSYNC Continuous Current....................................50mA
QREC, QSYNC Current < 500ns..............................................5A
Continuous Power Dissipation (TA= +70°C)
28-Pin TSSOP (derate 23.8mW/°C above +70°C). ....1905mW
Junction Temperature......................................................+150°C
Operating Temperature Ranges
MAX5058EUI, MAX5059EUI ............................-40°C to +85°C
MAX5058AUI, MAX5059AUI..........................-40°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
POWER SUPPLY
MAX5058 4.5
28.0
Supply Voltage Range V+ MAX5059 9.3
28.0
V
Quiescent Supply Current IQ2.5 5 mA
MAX5058 4.5
Switching Supply Current ISW fSW = 250kHz at BUFIN MAX5059 6 mA
IREF: REFERENCE CURRENT OUTPUT
Reference Current IIREF VIREF = 1.785V
49.2
50
51.1
µA
Reference Current Variation ΔIIREF VIREF = 0.5V to 2.5V
-0.1 +0.1
%/V
Reference Voltage Compliance
Range
Guaranteed by reference current variation
test 0.5 2.5 V
VREG: LOW-DROPOUT REGULATOR
MAX5058
4.75
5
5.25
Regulator Output VVREG IVREG = 0 to 30mA MAX5059 9.4 10
10.6
V
MAX5058, V+ = 6V to 28V 25
Line Regulation MAX5059, V+ = 11V to 28V 25 mV
MAX5058 V+ = 4.5V,
IVREG = 30mA
200
350
Dropout VDROP
MAX5059 V+ = 9.3V,
IVREG = 30mA
200
350
mV
VP: INTERNAL REGULATOR
Regulator Output Setpoint VVP IVP = 0 to 5mA 3.8 4.3 V
ZC: ZERO-CURRENT COMPARATOR
Zero-Current Comparator
Threshold VZCTH TA = +25°C
+3.5
+5
+6.5
mV
Zero-Current Comparator Input
Current IZC
-2.5 +2.5
µA
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF =
VVSP = 1.785V, CVREG = 2.2µF, CVP = 1µF, CCOMPS = 0.1µF, CSFP = 68nF, TA= TMIN to TMAX, unless otherwise noted. Typical values
are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Zero-Current Comparator Input
Range VZC
-0.1 +1.5
V
Zero-Current Comparator
Propagation Delay tZC
10mV overdrive, from when VZCP - VZCN is
greater than VZCTH to when QSYNC goes
low
65 ns
BUFIN: SYNCHRONIZING PULSE INPUT
BUFIN to Output Propagation
Delay tpd BUFIN rising to QREC rising or QSYNC
falling 40 ns
BUFIN Input Current IBUFIN -1 +1 µA
BUFIN Input Capacitance
CBUFIN
10 pF
BUFIN Input-Logic High
VHBUFIN
2.4 V
BUFIN Input-Logic Low
VLBUFIN
0.8 V
MARGINING INPUTS
RMGD Resistance RRMGD Sinking 10mA 6.5 11 Ω
RMGU Resistance RRMGU Sinking 10mA 6.5 11 Ω
MRGD Input-Logic High
VHMRGD
2.4 V
MRGD Input-Logic Low
VLMRGD
0.8 V
MRGU Input-Logic High
VHMRGU
2.4 V
MRGU Input-Logic Low
VLMRGU
0.8 V
MRGU, MRGD Input Resistance RMRGD,
RMRGU 40 kΩ
RMGU, RMGD Leakage Current IRMGU,
IRMGD
-100 +100
nA
DRIVER OUTPUTS
QREC, QSYNC Peak Source
Current
IQREC_SO,
IQSYNC_SO
2A
MAX5058 75 150
QREC, QSYNC Output-Voltage
High
VQREC_H,
VQSYNC_H
Measured with respect to
VVDR, sourcing 50mA MAX5059 75 150 mV
CQREC = CQSYNC = 0 30
QREC, QSYNC Low-to-High
Delay Time tPDLH CQREC = CQSYNC = 5nF 70 ns
QREC, QSYNC Peak Sink Current
IQREC_SI,
IQSYNC_SI
2A
MAX5058 50 100
QREC, QSYNC Output-Voltage
Low
VQREC_L,
VQSYNC_L
Sinking 50mA MAX5059 50 100 mV
CQREC = CQSYNC = 0 40
QREC, QSYNC High-to-Low
Delay Time tPDHL CQREC = CQSYNC = 5nF 70 ns
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF =
VVSP = 1.785V, CVREG = 2.2µF, CVP = 1µF, CCOMPS = 0.1µF, CSFP = 68nF, TA= TMIN to TMAX, unless otherwise noted. Typical values
are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS MIN
TYP MAX
UNITS
ERROR AMPLIFIER
Inverting Input Current IINV -50 +50 nA
Error-Amplifier Input Range VINV 0 2.5 V
Error-Amplifier Input Offset VOS ICOMPV = 100µA to 5mA -5 +5 mV
Error-Amplifier Output-Voltage
Low
VCOMPV
ICOMPV = 5mA 200 mV
Error-Amplifier Unity-Gain BW GBW RCOMP = 220Ω, ICOMP = 5mA
1.3
MHz
Error-Amplifier Voltage Gain AVOL RCOMPV = 220Ω, ICOMP = 5mA 80 dB
Error-Amplifier PSRR PSRR 60 dB
COMPV Output Resistance to
Ground (Note 1) 1 MΩ
REMOTE-SENSE AMPLIFIER (RSA)
VSN Input Current IVSN -100
+100
µA
VSP Input Current IVSP -20
+100
µA
Input Common-Mode Range -0.3
+3.8
V
Input Offset Voltage
VOSRSA
IVSO = -0.5mA to +0.5mA -4 mV
Output Impedance 8Ω
Amplifier -3dB Frequency IVSO = -0.5mA to +0.5mA 1
MHz
Remote-Sense Amplifier Gain GRS IVSO = -0.5mA to +0.5mA
0.9925
1
1.0075
V/V
CURRENT-SENSE AMPLIFIER (CSA)
CSN Input Current ICSN -0.3V ≤ VCSN ≤ +3.8V,
-0.3V ≤ VCSP ≤ +3.8V -150
+150
µA
CSP Input Current ICSP -0.3V ≤ VCSP ≤ +3.8V -40
+150
µA
Input Offset Voltage ICSO = -500µA to +500µA (Note 2) +20
+25
+30 mV
Current-Sense Amplifier Gain GCSA ICSO = -500µA to +500µA 19.8 20 20.2 V/V
Input Differential-Mode Range 100 mV
Input Common-Mode Range -0.3
+3.8
V
Output-Voltage Level Shift VLS (Note 2)
0.415 0.570
V
Output Voltage Range
VCSO
(
MIN
)
ICSO = -500µA to +500µA 0.1 3.0 V
Amplifier -3dB Frequency f-3dB ICSO = -500µA to +500µA 50 kHz
SHARE-FORCE AMPLIFIER (SFA)
Sink Current 60 µA
Source Current 500 µA
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
_______________________________________________________________________________________ 5
Note 1: Output resistance to ground used for unity-gain stability.
Note 2: VCSO = GCSA(VCSP - VCSN) + VLS.
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF =
VVSP = 1.785V, CVREG = 2.2µF, CVP = 1µF, CCOMPS = 0.1µF, CSFP = 68nF, TA= TMIN to TMAX, unless otherwise noted. Typical values
are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS MIN
TYP MAX
UNITS
CURRENT-ADJUST AMPLIFIER (CAA)
Transconductance
500
µA/V
Common-Mode Input Voltage
Range 0.45 2.55 V
Output Voltage Range 0.85 2.75 V
Offset Voltage TA = +25°C204265mV
Open-Loop Gain 72 dB
CURRENT-ADJUST VOLTAGE-TO-CURRENT CONVERTER
Input Voltage Range 0.75 2.75 V
Input Voltage Offset
1.25
V
Output Voltage Range 0.5 2.5 V
Transconductance
1.15
µA/V
Maximum Current Adjustment
Value 1.38
1.5
1.66 µA
THERMAL SHUTDOWN
Thermal Warning Flag Level When TSF pulls low
+125
°C
Thermal Warning Flag Hysteresis
15 °C
Internal Thermal-Shutdown Level +160
°C
Internal Thermal-Shutdown
Hysteresis 15 °C
TSF Maximum Output Voltage ITSF = 5mA 120 mV
TSF Output Leakage Current 0.1 µA
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
6 _______________________________________________________________________________________
Typical Operating Characteristics
(V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF =
VVSP = 1.785V, VCOMPS = 0.5V, CVREG = 2.2µF, CVP = 1µF, CCOMPS = 0.1µF, CSFP = 68nF, TA= +25°C, unless otherwise noted.)
LDO OUTPUT VOLTAGE (VVREG)
vs. INPUT VOLTAGE (MAX5058)
MAX5058/59 toc01
V+ (V)
VVREG (V)
272418 216 9 12 153
4.9995
5.0000
5.0005
5.0010
5.0015
5.0020
5.0025
5.0030
5.0035
5.0040
5.0045
5.0050
4.9990
030
IVREG = 0mA
IREF OUTPUT CURRENT
vs. TEMPERATURE
MAX5058/59 toc02
TEMPERATURE (°C)
IREF (μA)
1109565 80-10 5 20 35 50-25
49.95
49.97
49.99
50.01
50.03
50.05
50.07
50.09
50.11
50.13
50.15
50.17
49.93
-40 125
VIREF = 1.785V
LDO OUTPUT VOLTAGE (VVREG)
vs. LOAD CURRENT (MAX5059)
MAX5058/59 toc03
IVREG (mA)
VVREG (V)
1009070 8020 30 40 50 6010
9.84
9.86
9.88
9.90
9.92
9.94
9.96
9.98
10.00
10.02
10.04
10.06
10.08
10.10
9.82
9.80
0 110
LDO OUTPUT VOLTAGE (VVREG)
vs. LOAD CURRENT (MAX5058)
MAX5058/59 toc04
IVREG (mA)
VVREG (V)
1009070 8020 30 40 50 6010
4.88
4.90
4.92
4.94
4.96
4.98
5.00
5.02
5.04
4.86
0110
LDO OUTPUT VOLTAGE (VREG)
vs. TEMPERATURE (MAX5058)
MAX5058/59 toc05
TEMPERATURE (°C)
VVREG (V)
1109565 80-10 15 20 35 50-25
4.984
4.986
4.988
4.990
4.992
4.994
4.996
4.998
5.000
5.002
5.004
5.006
5.008
5.010
4.982
4.980
-40 125
LDO OUTPUT VOLTAGE (VVREG)
vs. INPUT VOLTAGE (MAX5059)
MAX5058/59 toc06
V+ (V)
VVREG (V)
272418 216 9 12 153
10.000
10.002
10.004
10.006
10.008
10.010
10.012
10.014
10.016
10.018
10.020
9.998
030
LDO OUTPUT VOLTAGE (VVREG)
vs. TEMPERATURE (MAX5059)
MAX5058/59 toc07
TEMPERATURE (°C)
VVREG (V)
1109565 80-10 5 20 35 50-25
9.985
9.990
9.995
10.000
10.005
10.010
10.015
10.020
10.025
10.030
9.980
-40 125
IREF OUTPUT CURRENT
vs. IREF OUTPUT VOLTAGE
MAX5058/59 toc08
VIREF (V)
IIREF (μA)
3.53.02.0 2.51.0 1.50.5
46.5
47.0
47.5
48.0
48.5
49.0
49.5
50.0
50.5
51.0
46.0
04.0
SWITCHING SUPPLY CURRENT
vs. TEMPERATURE (MAX5058)
MAX5058/59 toc14
TEMPERATURE (°C)
IV+ (mA)
1109565 80-10 520 35 50-25
3.2
3.4
3.6
3.8
4.0
4.2
4.4
4.6
4.8
5.0
3.0
-40 125
fSW = 250kHz
SWITCHING SUPPLY CURRENT
vs. INPUT VOLTAGE (MAX5059)
MAX5058/59 toc15
V+ (V)
IV+ (mA)
2723 259 11131517192157
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
329
fSW = 250kHz
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE (MAX5059)
MAX5058/59 toc12
TEMPERATURE (°C)
IV+ (mA)
1109565 80-10 5 20 35 50-25
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
2.0
-40 125
SWITCHING SUPPLY CURRENT
vs. INPUT VOLTAGE (MAX5058)
MAX5058/59 toc13
V+ (V)
IV+ (mA)
2723 25911131517192157
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
329
fSW = 250kHz
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
_______________________________________________________________________________________ 7
QUIESCENT SUPPLY CURRENT
vs. INPUT VOLTAGE (MAX5058)
MAX5058/59 toc09
V+ (V)
IV+ (mA)
272418 216 9 12 153
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
0.6
0.4
0.2
0
030
QUIESCENT SUPPLY CURRENT
vs. INPUT VOLTAGE (MAX5059)
MAX5058/59 toc10
V+ (V)
IV+ (mA)
272418 216 9 12 153
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
0.6
0.4
0.2
0
030
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE (MAX5058)
MAX5058/59 toc11
TEMPERATURE (°C)
IV+ (mA)
1109565 80-10 5 20 35 50-25
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
2.00
-40 125
Typical Operating Characteristics (continued)
(V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF =
VVSP = 1.785V, VCOMPS = 0.5V, CVREG = 2.2µF, CVP = 1µF, CCOMPS = 0.1µF, CSFP = 68nF, TA= +25°C, unless otherwise noted.)
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF =
VVSP = 1.785V, VCOMPS = 0.5V, CVREG = 2.2µF, CVP = 1µF, CCOMPS = 0.1µF, CSFP = 68nF, TA= +25°C, unless otherwise noted.)
SWITCHING SUPPLY CURRENT
vs. TEMPERATURE (MAX5059)
MAX5058/59 toc16
TEMPERATURE (°C)
IV+ (mA)
1109565 80-10 5 20 35 50-25
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
4.0
-40 125
fSW = 250kHz
REMOTE-SENSE AMPLIFIER (RSA) GAIN
vs. TEMPERATURE
MAX5058/59 toc17
TEMPERATURE (°C)
VSO OUTPUT (dB)
11095-25 -10 5 35 50 6520 80
0.008
0.009
0.010
0.011
0.012
0.013
0.014
0.015
0.007
-40 125
VVSP = 1.785V
RSA GAIN
vs. FREQUENCY
MAX5058/59 toc18
FREQUENCY (Hz)
GAIN (dB)
10M1M10k 100k1k0.1k
-35
-30
-25
-20
-15
-10
-5
0
5
10
-40
0 100M
CSA GAIN
vs. FREQUENCY
MAX5058/59 toc21
FREQUENCY (Hz)
GAIN (dB)
1k1001010.1
-15
-10
-5
0
5
10
15
20
25
30
-20
0.01 10k
ZERO-CURRENT COMPARATOR THRESHOLD
vs. TEMPERATURE
MAX5058/59 toc22
TEMPERATURE (°C)
ZCP THRESHOLD (mV)
11095-25 -10 5 35 50 6520 80
5.05
5.10
5.15
5.20
5.25
5.30
5.35
5.40
5.00
-40 125
CURRENT-SENSE AMPLIFIER (CSA) GAIN
vs. TEMPERATURE
MAX5058/59 toc19
TEMPERATURE (°C)
CSA GAIN (V/V)
11095-25 -10 5 35 50 6520 80
19.97
19.98
19.99
20.00
20.01
20.02
20.03
20.04
19.96
-40 125
VCSP = 100mV
CSA INPUT OFFSET
vs. TEMPERATURE
MAX5058/59 toc20
TEMPERATURE (°C)
INPUT OFFSET (mV)
1109565 80-10 5 20 35 50-25
24.1
24.2
24.3
24.4
24.5
24.6
24.7
24.8
24.9
25.0
25.1
24.0
-40 125
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
_______________________________________________________________________________________ 9
ZERO-CURRENT PROPAGATION DELAY
vs. TEMPERATURE
MAX5058/59 toc23
TEMPERATURE (°C)
ZCP TO QSYNC DELAY (ns)
11095-25 -10 535 50 6520 80
55
60
65
70
75
80
85
90
50
-40 125
10mV OVERDRIVE
SFA AMPLIFIER MAXIMUM
SINK CURRENT vs. TEMPERATURE
MAX5058/59 toc24
TEMPERATURE (°C)
SFA SINK CURRENT (μA)
1109565 80-10 5 20 35 50-25
32.2
32.4
32.6
32.8
33.0
33.2
33.4
33.6
33.8
34.0
32.0
-40 125
SFP = +2.5V
SFN = 0V
CURRENT-ADJUST VOLTAGE TO CURRENT-
CONVERTER ADJUSTMENT RANGE
vs. TEMPERATURE
MAX5058/59 toc25
TEMPERATURE (°C)
ADJUSTMENT RANGE (μA)
1109565 80-10 5 20 35 50-25
1.51
1.52
1.53
1.54
1.55
1.56
1.57
1.58
1.59
1.60
1.50
-40 125
Typical Operating Characteristics (continued)
(V+ = +12V, GND = PGND = 0, VDR = VREG, CQSYNC = CQREC = 0, ZCP = ZCN = BUFIN = CSP = CSN = SFN = VSN = GND, VIREF =
VVSP = 1.785V, VCOMPS = 0.5V, CVREG = 2.2µF, CVP = 1µF, CCOMPS = 0.1µF, CSFP = 68nF, TA= +25°C, unless otherwise noted.)
BUFIN TO QREC LOW-TO-HIGH
PROPAGATION DELAY vs. TEMPERATURE
MAX5058/59 toc26
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
1109565 80-10 520 35 50-25
29
30
31
32
33
34
35
36
37
38
39
40
41
42
28
-40 125
BUFIN TO QREC HIGH-TO-LOW
PROPAGATION DELAY vs. TEMPERATURE
MAX5058/59 toc27
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
1109565 80-10 5 20 35 50-25
34
36
38
40
42
44
46
48
50
52
54
56
58
60
32
30
-40 125
BUFIN TO QSYNC LOW-TO-HIGH
PROPAGATION DELAY vs. TEMPERATURE
MAX5058/59 toc28
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
1109565 80-10 520 35 50-25
48
50
52
54
56
58
60
44
42
40
46
-40 125
BUFIN TO QSYNC HIGH-TO-LOW
PROPAGATION DELAY vs. TEMPERATURE
MAX5058/59 toc29
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
1109565 80-10 5 20 35 50-25-40 125
28
30
32
34
36
38
40
24
22
20
26
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
10 ______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1 ZCP
Zero-Inductor Current-Sense Comparator Input. The source voltage of the freewheeling FET (N4 in the Typical
Application Circuit) is sensed. The gate drive is terminated when this voltage becomes positive during a primary
power-OFF cycle.
2
ZCN
Zero-Inductor Current-Sense Comparator Negative Input
3
GND
Ground Connection
4 SFN
Negative Input of the Share-Force Amplifier. Connect the SFN inputs together from all the power-supply
secondaries, then connect to the load return terminal (isolated GND). Connect to GND when current sharing is not
used.
5 SFP Positive Input of the Share-Force Amplifier. Connect the SFP pins together from all the power-supply secondaries.
Leave this pin unconnected when current sharing is not used.
6
COMPS
Compensation Output of the Load-Share Transconductance Amplifier
7 TSF Thermal Warning Flag Output
8
MRGU
Margin-Up Logic Input. When toggled high, the power-supply output voltage is set to the high margin.
9
MRGD
Margin-Down Logic Input. When toggled high, the power-supply output voltage is set to the low margin.
10
RMGD
Resistor Connection for Margin-Down
11
RMGU
Resistor Connection for Margin-Up
12
IREF Reference Current Output. A resistor from this current source output to GND sets the reference voltage used by
the error amplifier.
13
COMPV
Compensation Connection for the Error Amplifier. The feedback optocoupler LED is also connected to this point.
This open-drain output is capable of sinking at least 5mA.
14
INV Inverting Input of the Error Amplifier. A voltage-divider connected to this input scales the power-supply output
voltage for regulation.
15
VSO
Output of the Remote-Sense Amplifier
16
VSN Negative Input of the Remote-Sense Amplifier. Connect this to the negative terminal of the load.
17
VSP Positive Input of the Remote-Sense Amplifier. Connect this to the positive terminal of the load.
18
CSO
Output of the Current-Sense Amplifier. It can be used to monitor the output current.
19
CSN
Connect this input to the negative terminal of the output current-sense resistor. Connect to GND when not used.
20
CSP Connect this input to the positive terminal of the output current-sense resistor. Connect to GND when not used.
21
VP Compensation Pin for Internal +4V Preregulator. A minimum 1µF low-ESR capacitor must be connected to this pin
for bypassing.
22
V+ Supply Connection for the IC and Input to the Internal 5V (MAX5058) or 10V (MAX5059) Regulator. Maximum
voltage on this input is 28V.
23
VREG
Regulated +5V (MAX5058) or +10V(MAX5059) Output Used by the Internal Circuitry and the Output Drivers. A
minimum 1µF capacitor must be connected to this pin for bypassing.
24
BUFIN
Input for the Synchronizing Pulse. This pulse is provided by the primary-side power IC.
25
VDR
Supply Connection for the Output Drivers. Can be connected to VREG for 5V (MAX5058) or 10V (MAX5059)
operation.
26
QREC
Driver Output for the Rectifying MOSFET
27
PGND
Power-Ground Connection. Return ground connection for the gate-driver pulse currents.
28
QSYNC
Driver Output for the Recirculating MOSFET
—
EP Exposed Pad. This is the exposed pad on the underside of the IC. Connect the exposed paddle to GND and to a
large copper ground plane to aid in heat dissipation.
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
______________________________________________________________________________________ 11
30ns FALLING
EDGE DELAY
5mV
25
26
28
27
VDR
QREC
QSYNC
PGND
3
2
1
24
ZCP
BUFIN
ZCN
GND
SD DRIVERS
20ns
20ns
GATE-DRIVER BLOCK
17VSP
16
VSN
15
VSO
6COMPS
12IREF
X1
RSA
REMOTE-SENSE AMPLIFIER BLOCK
14INV
13
COMPV
11
RMGU
E/A
ERROR AMPLIFIER BLOCK
IREF
50μA
REFERENCE CURRENT BLOCK
42mV
0.5V
CURRENT-SHARE BLOCK
18 CSO
10 CSN
20 CSP
4SFN
5SFP
R
RR
R
SFA
X1
X2
V TO I
CAA
500μS
I = (1.15 x (VCAA - 1.25))μA
VCAA ≥ 1.25V
10RMGD
9MRGD
8MRGU
MARGINING BLOCK
50kΩ
50kΩ
QMD
QMU
REGULATOR AND THERMAL MANAGEMENT BLOCK
MAX5058/MAX5059
LDO
5V/10V
PREG
4V
UVLO AND
THERMAL
SHUTDOWN
21 VP
22 V+
23 VREG
7TSF
SD DRIVERS
+125°C FLAG
Figure 1. MAX5058/MAX5059 Functional Diagram
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
12 ______________________________________________________________________________________
Detailed Description
The MAX5058/MAX5059 enable the design of high-effi-
ciency, isolated power supplies using synchronous rec-
tification on the secondary side. These devices
commutate the secondary-side MOSFETs by providing
a clean gate-drive signal that is synchronized to the
power MOSFET switching in the primary side of the iso-
lation transformer. Once fully enhanced, the secondary-
side MOSFETs have very low on-resistance, producing
a voltage drop much lower than Schottky diodes, result-
ing in much higher efficiencies. Simultaneous conduc-
tion of the synchronous rectifier MOSFETs is avoided by
having a look-ahead signal before the primary
MOSFETs turn on. This eliminates large current spikes
from a shorted transformer secondary.
The MAX5058 has a 5V internal gate-drive voltage reg-
ulator that can be used with logic-level MOSFETs. The
MAX5059 has a 10V internal gate-drive voltage regula-
tor that can be used with high-gate-voltage MOSFETs.
In addition to the gate drivers, there are blocks that
make the MAX5058/MAX5059 complete secondary-
side solutions. These blocks are as follows:
• Regulator and thermal-management block
• Buffer input and gate-driver block
• Reference-current block
• Error-amplifier block
• Margining block
• Remote-sense amplifier block
• Current-share block
Regulators and Thermal Management
The linear regulators in the MAX5058/MAX5059 provide
power for the internal circuitry, as well as power for run-
ning the external synchronous MOSFETs. Design is sim-
plified by deriving the power from the secondary
winding before the output-filter inductor. The peak volt-
age at the secondary is at least twice the output volt-
age, yielding more than 7V peak even for output
voltages down to 3.3V. Use a diode and a capacitor to
rectify and filter the voltage before applying it to V+ (see
D6 and C32 in the Typical Application Circuit). The
input for the regulator is V+ and the output is VREG.
Connect VDR to VREG to provide the supply for the gate
driver’s QREC and QSYNC. For logic-level MOSFETs,
use the MAX5058. For conventional MOSFETs that
require 10V to be fully enhanced, use the MAX5059.
The V+ input voltage range is from +4.5V to +28V.
Supply enough current to this input to satisfy the quies-
cent supply current of the MAX5058/MAX5059, as well
as the current for the MOSFET drivers. Estimate the total
required supply current by using the following formula:
where IV+ is the current that must be supplied into V+
and QN3, QN4 are the total gate charges of MOSFETs
N3 and N4 in the Typical Application Circuit. fSW is the
switching frequency and ISW is the switching current of
the part. Use high-quality ceramic capacitors to bypass
V+ and VREG. Use additional capacitance as required
for bypassing switching currents generated by the dri-
vers when driving the chosen MOSFETs. Connect at
least a 1µF ceramic capacitor at the output of the regu-
lator VREG for stability.
The MAX5058/MAX5059 have an exposed pad at the
back of the package to enable heatsinking directly to a
ground plane. When soldered to a 1in2copper island,
these devices are able to dissipate approximately 1.9W
at +70°C ambient temperature. Connect the exposed
pad to the GND.
In addition to the regulators, this block contains a ther-
mal-shutdown circuit that shuts down the gate drivers if
the die temperature exceeds +160°C. This is a last
resort shutdown mechanism. The trigger of this shut-
down mechanism must be avoided. Turning off the
secondary synchronous rectifier drivers in this manner
while the output carries the full load current causes the
current to be diverted to the lossy external diodes or
body diodes of the MOSFETs. This, in most cases,
leads to rectifier failure due to power dissipation. To
prevent this, make use of the TSF output (temperature
warning flag). TSF is an open-drain output that gets
asserted when the die temperature exceeds +125°C,
well before the actual thermal shutdown at +160°C. An
optocoupler connected from VREG to the TSF pin can
provide a means for shutting down the switching at the
primary side, thus avoiding catastrophic failure.
Buffer Input (BUFIN) and MOSFET Drivers
The MAX5058/MAX5059 drive external N-channel
MOSFETs at QSYNC and QREC. The QSYNC output
drives the gate of the freewheeling MOSFET N4 in the
Typical Application Circuit. The QREC output drives the
gate of the rectifying MOSFET N3 in the Typical
Application Circuit. Each gate-driver output is capable
of sinking and sourcing up to 2A peak current,
enabling the MAX5058/MAX5059 to drive high-gate-
charge MOSFETs.
II f QQ
VSWSW N N+=+× +
()
34
The MOSFET drivers are synchronized to the primary-
side switching by using the BUFIN input. BUFIN
accepts the PWM information from the primary through
a high-speed optocoupler or through a small isolation
pulse transformer. Figures 2 through 6 show the inter-
face details using an optocoupler or a pulse trans-
former with two different kinds of primary-side PWM
controllers.
For proper operation, the MAX5051, MAX5042, and
MAX5043 devices generate a look-ahead signal that
precedes the actual switching of the primary MOSFETs
by a small amount of time, typically less than 100ns.
Additional circuitry may be required when the
MAX5058/MAX5059 are used with other primary-side
controllers not capable of providing a look-ahead signal.
When BUFIN goes high, QREC goes high and QSYNC
goes low. When BUFIN goes low, QREC goes low and
QSYNC goes high.
The MAX5058/MAX5059 provide improved efficiency at
light loads by allowing discontinuous conduction oper-
ation. A zero-crossing comparator with inputs ZCP and
ZCN monitors the current through the freewheeling
MOSFET using a sense resistor at its source. The free-
wheeling MOSFET is turned off when the inductor cur-
rent is near zero. The actual threshold can be externally
adjusted. The Typical Application Circuit shows one
method for trip-point adjustment using components
R31 and R34.
BUFIN is internally clamped to 4V. Use a voltage-divider,
if necessary, to reduce any external voltage applied to
this pin to less than 4V.
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
______________________________________________________________________________________ 13
Figure 3. Interface of MAX5059 to MAX5042/MAX5043 Using a High-Speed Optocoupler
MAX5042
MAX5043
MAX5058
PS9715
OR EQUIVALENT
HIGH-SPEED
OPTOCOUPLER
REG5
PPWM
PWMNEG GND
BUFIN
VREG (5V)
330Ω
BSS84
560Ω
2kΩ
MAX5042
MAX5043
MAX5059
PS9715
OR EQUIVALENT
HIGH-SPEED
OPTOCOUPLER
REG5
PPWM
PWMNEG
GND
BUFIN
VREG (10V)
330Ω
3.10kΩ
BSS84
560Ω
2kΩ
MMBT3904
1μF4.42kΩ
Figure 2. Interface of MAX5058 to MAX5042/MAX5043 Using a High-Speed Optocoupler
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
14 ______________________________________________________________________________________
MAX5051 MAX5058
PS9715
OR EQUIVALENT
HIGH-SPEED
OPTOCOUPLER
REG5
LXH
GND GND
BUFIN
VREG (5V)
330Ω
BSS84
560Ω
2kΩ
2kΩ
1μF
4.7Ω
LXVDD
Figure 4. Interface of MAX5058 to MAX5051 Using a High-Speed Optocoupler
Figure 5. Interface of MAX5059 to MAX5051 Using a High-Speed Optocoupler
MAX5051
PS9715
OR EQUIVALENT
HIGH-SPEED
OPTOCOUPLER
REG5
LXH
GND
BSS84
560Ω
2kΩ
2kΩ
1μF
4.7Ω
LXVDD
MAX5059
GND
BUFIN
VREG (10V)
330Ω
3.10kΩ
MMBT3904
1μF4.42kΩ
Figure 6. Interface Circuit to MAX5051 Using a Pulse Transformer
MAX5051 MAX5058
MAX5059
REG5
LXH
GND
LXVDD
LXL
BUFIN
GND
2kΩ
301Ω1N4148
T1
1μF
D1
D2
4.7Ω
T1: PULSE ENGINEERING, PE-68386
D1, D2: CENTRAL SIMICONDUCTOR, CMOSH-3
Reverse-Current Prevention
in Synchronous Rectifiers
One benefit of secondary-side synchronous rectifica-
tion is increased efficiency. Another benefit is that it
allows the inductor current to remain continuous
throughout the operating load range. This results in
constant loop dynamics that are easy to compensate.
In some cases, it may be necessary to turn off the free-
wheeling MOSFET when the current through this device
attempts to flow from drain to source. Turning off this
MOSFET can be done to enhance efficiency at low out-
put current. When multiple power supplies are paral-
leled, the power supply with the highest output voltage
has a tendency to source current into the power-supply
outputs with lower output voltage. Turning off the free-
wheeling MOSFET also prevents this current back-flow.
When the inductor current is allowed to become dis-
continuous, the loop dynamics change and the circuit
must be compensated accordingly to accommodate
stable continuous and discontinuous mode operation.
Turning off the freewheeling MOSFET is accomplished
by using the zero-current comparator (pins ZCP and
ZCN). Use this comparator to sense reverse current in
the freewheeling MOSFET and turn off the device by
pulling QSYNC low. An internal latch prevents the free-
wheeling MOSFET from turning on until the off-time of
the next cycle.
Reference Current
The MAX5058/MAX5059 do not have an explicit refer-
ence voltage generator. Instead, they contain a 1%-
accurate trimmed 50µA current source. This allows sig-
nificant flexibility in setting the reference voltage. In
some cases, the output-voltage resistive divider, con-
sisting of R1 and R2 in the Typical Application Circuit,
can be eliminated by selecting a suitable resistor value
at the IREF pin. This reduces the error that the output
voltage-divider may add. Use a low-value bypass
capacitance at this pin to eliminate noise. Typical values
for this capacitance are calculated by considering the
pole that it presents with R12. This pole must be placed
well beyond the frequency range of interest of the cur-
rent-share loop. Use values less than 2.2nF.
Error Amplifier
The MAX5058/MAX5059 incorporate a 1.3MHz unity
gain-bandwidth error amplifier with inputs INV, IREF,
and output COMPV. IREF is the noninverting input and
also serves as the reference voltage generator with the
internal 50µA current source and the external resistor
connected from IREF to GND. INV is the inverting input
and connects to the center of a resistive divider from
OUT to INV to GND. The output of the error amplifier,
COMPV, connects to the cathode of the LED in the
optocoupler to control the diode current that transmits
the error signal back to the primary-side controller. An
open-drain-output error amplifier simplifies interfacing
with the feedback optocoupler. Use this error amplifier
the same way as the industry-standard TL431 shunt ref-
erence. The open-drain output provides flexibility that
may be necessary when additional functionality such
as secondary current-limit regulation is required. Unlike
the TL431, the output of the internal error amplifier of
the MAX5058/MAX5059 is guaranteed to be a maxi-
mum of 200mV with a 5mA drain current, compared to
2.5V for the TL431 and 1.24V for the TLV431.
In some cases, it is possible to avoid the use of the out-
put voltage-divider (R1 and R2) by connecting INV to
the output through just R1. This eliminates the voltage
tolerance errors caused by R1 and R2. Output voltage
in this configuration is set directly by using a suitable
resistor at IREF. Figure 7 shows this configuration.
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
______________________________________________________________________________________ 15
13
14
COMPV
INV
12
IREF
E/A
IREF
50μA
R1
R12
VOUT
C28
VOUT = (50μA) x R12
FOR: 0.5V ≤ VOUT ≤ 2.5V
Figure 7. Output Voltage Regulation for 0.5V ≤VOUT ≤2.5V
Figure 8 shows a typical configuration with output volt-
ages high enough (VOUT > 2.5V) to allow a typical
optocoupler to be fully biased. In this case, there are
two feedback paths—one though the error amplifier
and one through the output-connected optocoupler.
This second feedback path must be considered when
compensating the overall feedback loop.
Figure 9 shows a typical configuration with an optocou-
pler for output voltages lower than 2.5V. In this case,
the direct connection of the optocoupler to the output is
not possible. There is only one feedback path and the
error-amplifier feedback network must be designed
accordingly.
Figure 10 shows the simplified block diagram for the
error amplifier.
Voltage Margining
The margining inputs MRGU (margin up) and MRGD
(margin down) control two internal MOSFETs with open-
drain outputs at RMGU and RMGD, respectively. When
margining is used, connect two pullup resistors from
RMGU and RMGD to IREF. A logic-high voltage at
MRGU causes QMU (see Figure 1) to open, increasing
the equivalent resistance at IREF and the reference volt-
age (VIREF). The error-amplifier inverting input, INV,
tracks IREF and forces the primary-side controller to
increase the output voltage. MRGD has the opposite
effect. When a logic high is applied to MRGD, QMD
turns on, decreasing the equivalent resistance at IREF
and effectively reducing VIREF. This causes INV to track
and force the primary-side controller to reduce the out-
put voltage.
The margining inputs MRGU and MRGD are internally
pulled to GND with 40kΩresistors. When margining is
not used, the inputs can be left floating or connected to
GND to make VIREF = 50µA ×R12.
Calculation Procedure for Output-Voltage Setting
Resistors and Margining
Use the following step-by-step procedure to calculate
the output-voltage setting and margining resistors (see
the Typical Application Circuit):
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
16 ______________________________________________________________________________________
13
14
COMPV
INV
12
IREF
E/A
IREF
50μA
R12
VOUT > 2.5V
C28
R12
R12
R19
C27
Figure 8. Optocoupler Connection for VOUT > 2.5V
13
14
COMPV
INV
12
IREF
E/A
IREF
50μA
R12
0.5V < VOUT < 2.5V
C28
R1
Rff
R19
C27
Rf
Cf
VREG
(PIN 23)
Figure 9. Optocoupler Connection for VOUT < 2.5V
13
COMPV
14
INV
12
IREF
Figure 10. Simplified Error-Amplifier Diagram
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
______________________________________________________________________________________ 17
1) Select a parallel equivalent resistance Req value to
produce the nominal reference voltage. For exam-
ple, Req = 35.4kΩgives you VIREF = 1.77V.
2) Select the margin-up percentage value:
ΔU = 5%
3) Calculate R32:
R32 = 743.4kΩ. Calculated
Select the nearest 0.1% value.
R32 = 741kΩ. Selected
4) Calculate R12:
R12 = 37.05kΩ. Calculated
Select the nearest 0.1% value.
R12 = 37kΩ. Selected
5) Select the margin-down percentage value:
ΔD = 5%
6) Recalculate Req with the selected values:
Req = 35.24kΩ.
7) Calculate R33:
R33 = 361.186kΩ. Calculated
Select the nearest 0.1% value:
R33 = 361kΩ. Selected
8) Calculate the reference voltage with the selected
chosen values:
VIREF = 50µA ✕Req.R
eq from step 6.
VIREF = 1.762V.
RRR
RDR
eq
eq
33 12
12
100
100 100
=××
×+
()
×
%
%%Δ-
RRR
RR
eq =+
12 32
12 32
RRU
12 32
100
=×
%
Δ
RR U
U
eq32
100
=× +
% Δ
Δ
Figure 11. Remote-Sense Amplifier Connection for 0.5V ≤VOUT ≤2.5V
VOUT
17
VSP
16
VSN
15
VSO
13
14
COMPV
INV
12
IREF
E/A
IREF
50μA
R12
C28
VOUT = (50μA) x R12
FOR: 0.5V ≤ VOUT ≤ 2.5V
RSA
9) Select a value for R1and calculate R2for VOUT =
3.3V:
R1= 19.1kΩ
R2= 21.882kΩ.
Select the nearest 1% value.
R2= 21.8kΩ.
When margining is not used, substitute R12 for Req
in step 8 and go to step 9.
Remote-Sense Amplifier
Use the remote-sense amplifier (RSA in Figure 1) to
directly sense the voltage across the load, compensat-
ing for voltage drops in PC board tracks or load con-
nection wires. The remote-sense amplifier is a
unity-gain amplifier with sufficient bandwidth to not
interfere with the normal operation of the voltage-con-
trol loop. Direct sensing of the output voltage is possi-
ble if the output voltage is between 0.5V to 2.5V. Figure
11 shows this configuration. Figure 12 shows the use of
the remote-sense amplifier with a voltage-divider. The
remote-sense amplifier has an input bias current of
100µA. The impedance of R1 and R2 must be kept low
in this configuration to avoid excessive errors in the out-
put-voltage set point.
Current Sharing
When multiple power modules are providing power to
the same load, the load current must be shared equally
to provide the best reliability and thermal distribution.
The MAX5058/MAX5059 contain circuitry that enable
current sharing among paralleled power supplies with-
out requiring an explicit controlling master circuit.
Current sharing is accomplished by connecting togeth-
er the current-share bus pins (SFP and SFN) of all par-
alleled power supplies (see Figure 13), thus creating a
current-force/share bus. The voltage level on this differ-
ential bus is proportional to the output current of the
power supply that has the highest current compared to
the other supplies. The number of power supplies that
can be paralleled with this method is limited only by
practical considerations.
RV
VV
R
IREF
OUT IREF
21=-
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
18 ______________________________________________________________________________________
Figure 12. Remote-Sense Amplifier Connection for VOUT > 2.5V (or any Other Arbitrary Voltage)
VOUT
17
VSP
16
VSN
15
VSO
RSA
13
14
COMPV
VOUT = 1 + ✕ VIREF
VIREF = (50μA) ✕ R12
R1
R2
INV
12
IREF
E/A
IREF
50μA
R12
C28
R2
R1
( )
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
______________________________________________________________________________________ 19
Figure 13. Paralleling Multiple Power-Supply Modules for Current Sharing
CSN
CSP
VOUT+VIN+
VSP
VIN-
VSN
VOUT-
SYNCIN
SFN
STARTUP
SFP
SYNCOUT
MAX5051
MAX5058
MAX5059
ORAND
POWER MODULE
MRGU MRGD
CSN
CSP
VOUT+VIN+
VSP
VIN-
VSN
VOUT-
SYNCIN
SFN
STARTUP
SFP
SYNCOUT
MAX5051
MAX5058
MAX5059
ORAND
POWER MODULE
MRGU MRGD
CSN
CSP
VOUT+VIN+
VSP
VIN-
VSN
VOUT-
SYNCIN
SFN
STARTUP
SFP
SYNCOUT
MAX5051
MAX5058
MAX5059
ORAND
POWER MODULE
MRGU MRGD
LOAD
VIN+
VIN-
36V TO 72V
When the MAX5051 is used as the primary-side con-
troller, additional benefits are also realized with its spe-
cial paralleling pins. The MAX5051 allows simultaneous
shutdown and wake-up, as well as frequency synchro-
nization and 180 degree out-of-phase operation of
each connected primary.
The current-share loop consists of the following func-
tional blocks:
• A diode ORed force amplifier that connects with the
other modules and forces the bus to carry a voltage
proportional to the highest current among the mod-
ules.
• A sense amplifier that senses this share-bus volt-
age and applies it to internal circuitry.
• A fixed gain of 20, current-sense amplifier that
senses the output current through a sense resistor.
• A current-adjust amplifier that functions as an error-
amplifier block in the current-share loop.
• A voltage-to-current (VtoI) block that adds a small
amount of current to the reference current, increas-
ing the reference voltage and enabling the module
to share more current.
The adjustment range and thus the sharing capability of
the modules is limited by the amount of additional out-
put voltage boost possible through the VtoI block. The
typical voltage boost is +3% (i.e., 1.5µA/50µA). Figure
14 shows the transfer function of the VtoI block. This
adjustment range also sets a limit on the amount of volt-
age drop allowed for current sharing. For effective cur-
rent sharing, the sum of all voltage drops must be kept
below 3% and the output-to-load connection drop of
each power module must be kept equal.
Current-sharing functions follow:
The voltage across the current-sense resistor for each
module is sensed and compared to the voltage on the
current-share bus. The voltage on the current-share bus
represents the current from the module that has the high-
est output current compared to the other modules. Each
module compares its current to this maximum current. If
its current is less than the maximum, then the module
increases its reference current with the VtoI block. This
raises the reference voltage presented at the noninvert-
ing input of the error amplifier. With a higher reference
voltage, the output voltage of the module rises in an
attempt to increase its output current. This process con-
tinues until the currents balance between the modules.
The current-adjust amplifier (see Figure 1) has an offset
at its inverting input that requires the share-bus voltage
to reach 40mV before the current-share control loop
attempts to regulate the output-load-current balance.
Thus, the current-share regulation does not begin until
the current-sense signals have exceeded 2mV (i.e.,
42mV/20).
Figure 15 shows the simplified equivalent small-signal
circuit of the current-share control loop. The current-
adjust amplifier represents the error amplifier in this
loop. The command signal, which is the voltage across
the SFP and SFN pins, is applied to the noninverting
input of this amplifier. For small-signal analysis, the
noninverting pin is shown grounded in Figure 15. This is
a low-bandwidth loop.
Assuming a much smaller unity-gain crossover bandwidth
(fCS) for the current-share loop compared to the main out-
put-voltage-regulation loop (i.e., fCS << fC), the open-loop
gain of the current-share loop can be written as:
where fCS is the unity-gain crossover frequency of the
current-share loop (typically 10Hz to 100Hz), fCis the
unity-gain crossover frequency of the main output loop,
GPS(s) is the gain of the power stage from the refer-
ence voltage input of the error amplifier to the output
(GPS = VOUT/VIREF), RSis the current-sense resistor,
and RLOAD is the load resistance. Note that the current-
share loop bandwidth is highest for the lowest value of
RLOAD (maximum load).
Gs G s Gs
sC GsR
Gs R
RR
T SFA CAA
COMPS VtoI IREF
PS S
S LOAD
() () () ()
()
=×
×
⎛
⎝
⎜⎞
⎠
⎟××
()
××
+
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
20 ______________________________________________________________________________________
1.5μA
1.25V
VCAA
V TO I
SLOPE = 1.15μA/V
Figure 14. Transfer Function Curve of the V to I Block
CSA
CAA
V TO I
PWM STAGE
AND FILTERS
FEEDBACK
NETWORK
VOUT RS
RLOAD
RIREF
CCOMPS
E/A
+ VSENSE -
GPS (s)
GCAA (s)
GCSA (s)
GV TO I (s)
Figure 15. Small-Signal Equivalent Current-Share Control Loop
Figure 16 shows the idealized small-signal response of
the Typical Application Circuit from the noninverting
input of the error amplifier to the output. This response
shows that the unity-gain crossover frequency of the
current-share loop can easily be placed between 10Hz
and 100Hz, while at the same time avoiding interaction
with the main voltage-control loop.
For frequencies below 100Hz, GT(s) can be written as
(using the DC gain value for GPS(s)):
Equating |GT| = 1 and solving for CCOMPS yields:
The current-sharing loop is compensated with a capac-
itor from COMPS to GND. This results in a dominant
pole that forces the loop gain of the current-share loop
to cross 0dB with a single pole (20dB/decade) rolloff.
When RLOAD >> RS, the above can be simplified further.
Example:
RS= 2mΩ
VOUT = 3.3V
fCS = 10Hz
RLOAD = 0.22Ω
The resulting overall open-loop response of the current-
share control loop is shown in Figure 17.
Applications Information
Isolated 48V Input Power Supply
Figure 18 shows a complete design of an isolated syn-
chronously rectified power supply with a +36V to +75V
telecom input voltage range. This design uses the
MAX5051 as the primary-side controller and the
MAX5058 as the secondary-side synchronous rectifier
driver. Figures 19 though 24 show some of the perfor-
mance aspects of this power-supply design. This
power supply can sustain a continuous short circuit at
its output terminals. This circuit is available as a com-
pletely built and tested evaluation kit (MAX5058EVKIT).
CFHzV V
Hz
F
COMPS =×
()
×
()
×
()
()
×
()
≅
36 61 0 002 3 3
10 0 22
011
./. .
.
.
μ
μ
Ω
Ω
CFHzV R V
fR
COMPS S OUT
CS LOAD
=×
()
××
×
36 61./μ
CFHzV R V
fRR
COMPS S OUT
CS S LOAD
=×
()
××
×+
()
36 61./μ
Gs S
sC AV R
V
V
R
RR
TCOMPS IREF
OUT
IREF
S
S LOAD
() . /
=×
()
××
()
×
××
+
20 500 115
μμ
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
______________________________________________________________________________________ 21
POWER-STAGE GAIN/PHASE
FREQUENCY (Hz)
GAIN (dB/DIV)
1k10010
-15
-10
-5
0
5
10
15
20
-20
1 10k
PHASE (DEGREES/div)
-45
0
45
90
-90
GAIN PHASE
Figure 16. Idealized (with Ideal Power Stage and Optocoupler)
Frequency Response (GPS(s)) from Noninverting Input of the
Error Amplifier to the Output of the Power Supply for the
Typical Application Circuit of Figure 18
FREQUENCY (Hz)
GAIN (dB/DIV)
1k10010
-60
-40
-20
0
20
40
60
80
-80
1 10k
PHASE (DEGREES/div)
-90
0
90
180
-180
GAIN
PHASE
135
45
-45
-135
Figure 17. Overall Open-Loop Response of the Current-Share
Loop
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
22 ______________________________________________________________________________________
Typical Application Circuit
ZCP
QSYNC VSO
28 15
ZCN
QREC
VSN
VSP
CSO
CSN
CSP
VP
V+
VREG
VDR
BUF_IN
INV
L1
2.4μH
COMPV
IREF
VOUT
RMGU
RMGD
MRGD
MRGU
TSF
COMPS
SFP
SFN TP8
GND
PGND
IC_PADDLE
1
2
26
16
17
18
19
20
21
22
23
25
24
14
13
12
11
10
9
8
7
6
5
4
3
27
29
MAX5058
U3
R23
10Ω
C36
1μF
TP7
C38
0.068μF
TP2
TP1
TPMU
TPMD TP3
R12
34.8kΩ
0.5%
C37
220pF
R33
340kΩ
0.5%
R32
698kΩ
0.5%
VDD = 3V
RL = 16Ω
fIN = 10kHz
C28
0.047μFR2
19.1kΩ
1%
R1
19.1kΩ
1%
OPTO_CAT
(CSP)
R34
220Ω
VREG
R31
220Ω
1%
C39
220pF
R26
0.002Ω
R38
10Ω
R27
10Ω
VOUT (CSN)
C30
1μF
C16
3.3μF
C35
1μF
C29
1μF
R24
10Ω
VREG
V+
43
16
C31
0.1μF
R28
301Ω
1%
LXH
LXL
R30
2kΩ
1%
D10
D9
D7
LXVDD
T2
C26
0.1μF
REG9
REG5
R11
360Ω
R3
2.2kΩ
C17
0.33μF
C24
1000pF
3
4
2
1
U2
OPTO_CAT
C27
0.15μF
R19
475Ω
VOUT C22
2200pF
2kV
N4
4
23
1
67
58
C32
1μF
V+
C23
1000pF
D4 C15
270μF
4V
C14
270μF
4V
C13
270μF
4V
C33
1μF
10V
SGND
R20
0.004Ω
1%
R36
0.004Ω
1%
VOUT
VOUT (CSN)
(CSP)
-VIN
R29
1Ω
N5 DRVB
XFRMRH
3
2
1
D6
N1 +VIN
C25
0.047μF
100V
+VIN
C12
1μF
100V
C11
0.47μF
100V
C10
0.47μF
100V
D2D2
XFRMRH
456
7
83 2
1
N3
R10
20Ω
4
12
3
7
85
6
T1
1
6
4T
2T
10
8
PVIN +VIN
R22
15kΩ
R18
4.7Ω
C21
4.7μF
80V
D5
R17
0.027Ω
1%
D3
+VIN C34
330pF
XFRMRH
N2
8
3
4
6
7
21
5
R13
47Ω2
5
8T
R9
8.2Ω
R14
270Ω
RCOSC
SYNCOUT
RCFF
CON
CSS
COMP
FB
REG5
REG9
PVIN
STT
LXH
LXL
SYNCIN
FLTINT
STARTUP
UVLO
GND
AVIN
BST
DRVH
XFRMRH
DRVB
DRVDD
PGND
DRVL
CS
IC_PADDLE
1
2
3
4
5
6
7
8
9
10
11
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
29
MAX5051
U1
REG5
C1
100pF
R21
24.9kΩ
1%
+VIN
C2
390pF
R25
100kΩ
TP5
C5
4700pF
R15
31.6kΩ
1%
D8
R16
10.5kΩ
1%
REG5
C4
4.7μF
REG9
C3
4.7μF
PVIN
C6
0.1μF
C18
1000pF
LXH
LXL
LXVDD
12
REG5
C19
1μF
R27
10Ω
LXVDD
ON/OFF
XFRMRH
DRVB
+VIN
C9
1μF
REG9
C20
220pF
R8
8.2Ω
C8
4.7μF
R7
0Ω
REG9
D1
+VIN
R6
1MΩ
1%
R5
38.3kΩ
1%
C7
0.22μF
R4
1MΩ
1%
R35
0Ω
TP6
Figure 18. Schematic of a +48V Input, 3.3V at 15A Output, Synchronous Rectified, Isolated Power Supply
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
______________________________________________________________________________________ 23
60
65
75
70
85
90
80
95
0462 8 10 12 14
LOAD CURRENT (A)
EFFICIENCY (%)
R20 = R26 = R36 = 0Ω
Figure 19. Efficiency at Nominal 3.3V Output Voltage vs. Load
Current (48V Nominal Input Voltage)
1
0
2
4
3
6
7
5
8
0462 8 10 12 14
LOAD CURRENT (A)
POWER DISSIPATION (W)
R20 = R26 = R36 = 0Ω
Figure 20. Power Dissipation at Nominal 3.3V Output Voltage
vs. Load Current (48V Nominal Input Voltage)
4ms/div
R20 = R26 = R36 = 0Ω
RL = 0.22Ω
VOUT
1V/div
ILOAD
5A/div
Figure 21. Turn-On Transient at Full Load (Resistive Load)
VOUT
1ms/div
VOUT
100mV/div
ILOAD
5A/div
R20 = R26 = R36 = 0Ω
Figure 22. Output Voltage Response to Step Change in Load
Current (ILOAD from 50%, max to 75%, max)
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
24 ______________________________________________________________________________________
2μs/div
VOUT
50mV/div
R20 = R26 = R36 = 0Ω
Figure 23. Output Voltage Ripple at +48V Nominal Input
Voltage and Full Load Current (Scope Bandwidth = 20MHz)
ILOAD
10A/div
20ms/div
ILOAD
10A/div
1ms/div
R20 = R26 = R36 = 0Ω
Figure 24. Load Current (10A/div) as a Function of Time when
the Converter Attempts to Turn On into a 50mΩShort Circuit
Chip Information
TRANSISTOR COUNT: 1762
PROCESS: BiCMOS
Pin Configuration
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
QSYNC
PGND
QREC
VDR
BUFIN
VREG
VSO
V+
VP
CSP
CSN
CSO
VSP
VSN
INV
COMPV
IREF
RMGU
RMGD
MRGD
MRGU
TSF
COMPS
SFP
SFN
GND
ZCN
ZCP
TSSOP
TOP VIEW
CONNECT EXPOSED PADDLE TO GND.
MAX5058AUI
MAX5059AUI
MAX5058/MAX5059
Parallelable Secondary-Side Synchronous Rectifier
Driver and Feedback-Generator Controller ICs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
TSSOP 4.4mm BODY.EPS
AA AA
