LTC2203CUK#PBF - LINEAR TECHNOLOGY

LTC2203/LTC2202

22032fd

16-Bit, 25Msps/10Msps ADCs

The LTC

2203/LTC2202 are 25Msps/10Msps, sampling

16-bit A/D converters designed for digitizing high frequen-

cy, wide dynamic range signals with input frequencies up

to 380MHz. The input range of the ADC can be optimized

with the PGA front end.

The LTC2203/LTC2202 are perfect for demanding app-

lications, with AC performance that includes 81.6dB

SNR and 100dB spurious free dynamic range (SFDR).

Maximum DC specs include ±4LSB INL, ±1LSB DNL (no

missing codes).

A separate output power supply allows the CMOS output

swing to range from 0.5V to 3.6V.

A single-ended CLK input controls converter operation. An

optional clock duty cycle stabilizer allows high performance

at full speed with a wide range of clock duty cycles.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents including 4843302, 6949965B1.

n Telecommunications

n Receivers

n Cellular Base Stations

n Spectrum Analysis

n Imaging Systems

n ATE

n Sample Rate: 25Msps/10Msps

n 81.6dB SNR and 100dB SFDR (2.5V Range)

n SFDR 90dB at 70MHz (1.667VP-P Input Range)

n PGA Front End (2.5VP-P or 1.667VP-P Input Range)

n 380MHz Full Power Bandwidth S/H

n Optional Internal Dither

n Optional Data Output Randomizer

n Single 3.3V Supply

n Power Dissipation: 220mW/140mW

n Clock Duty Cycle Stabilizer

n Out-of-Range Indicator

n Pin Compatible Family

25Msps: LTC2203 (16-Bit)

10Msps: LTC2202 (16-Bit)

n 48-Pin (7mm × 7mm) QFN Package

–

S/H

AMP

CORRECTION

LOGIC AND

SHIFT REGISTER

OUTPUT

DRIVERS

16-BIT

PIPELINED

ADC CORE

INTERNAL ADC

REFERENCE

GENERATOR

1.25V

COMMON MODE

BIAS VOLTAGE

CLOCK/DUTY

CYCLE

CONTROL

CLK PGA SHDN DITH MODE RAND

VCM

ANALOG

INPUT

22032 TA01

D15

•

CMOS

OUTPUTS

0.5V TO 3.6V

3.3V

SENSE

OGND

OVDD

2.2μF 1μF

1μF 1μF 1μF

VDD

GND

ADC CONTROL INPUTS

AIN +

AIN –

CLKOUT+

CLKOUT–

FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 TA02

LTC2203: 128K Point FFT,

fIN = 5.1MHz, –1dBFS, PGA = 0

FEATURES DESCRIPTION

APPLICATIONS

TYPICAL APPLICATION

LTC2203/LTC2202

22032fd

TOP VIEW

UK PACKAGE

48-LEAD

(

7mm s 7mm

)

PLASTIC QFN

SENSE 1

VCM 2

VDD 3

VDD 4

GND 5

AIN+ 6

AIN–7

GND 8

GND 9

CLK 10

GND 11

VDD 12

36 OVDD

35 D11

34 D10

33 D9

32 D8

31 OGND

30 CLKOUT+

29 CLKOUT–

28 D7

27 D6

26 D5

25 OVDD

48 GND

47 PGA

46 RAND

45 MODE

44 OE

43 OF

42 D15

41 D14

40 D13

39 D12

38 OGND

37 OVDD

VDD 13

VDD 14

GND 15

SHDN 16

DITH 17

D0 18

D1 19

D2 20

D3 21

D4 22

OGND 23

OVDD 24

EXPOSED PAD IS GND (PIN 49)

MUST BE SOLDERED TO PCB BOARD

TJMAX = 150°C, θJA = 29°C/W

Supply Voltage (VDD) .................................. –0.3V to 4V

Digital Output Supply Voltage (OVDD) ......... –0.3V to 4V

Digital Output Ground Voltage (OGND) ....... –0.3V to 1V

Analog Input Voltage (Note 3) .... –0.3V to (VDD + 0.3V)

Digital Input Voltage ................... –0.3V to (VDD + 0.3V)

Digital Output Voltage ............... –0.3V to (OVDD + 0.3V)

Power Dissipation ............................................2000mW

Operating Temperature Range

LTC2203C/LTC2202C ............................. 0°C to 70°C

LTC2203I/LTC2202I ............................–40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

OVDD = VDD (Notes 1 and 2)

ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2203CUK#PBF LTC2203CUK#TRPBF LTC2203UK 48-Lead (7mm × 7mm) Plastic QFN 0°C to 70°C

LTC2202CUK#PBF LTC2202CUK#TRPBF LTC2202UK 48-Lead (7mm × 7mm) Plastic QFN 0°C to 70°C

LTC2203IUK#PBF LTC2203IUK#TRPBF LTC2203UK 48-Lead (7mm × 7mm) Plastic QFN –40°C to 85°C

LTC2202IUK#PBF LTC2202IUK#TRPBF LTC2202UK 48-Lead (7mm × 7mm) Plastic QFN –40°C to 85°C

LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2203CUK LTC2203CUK#TR LTC2203UK 48-Lead (7mm × 7mm) Plastic QFN 0°C to 70°C

LTC2202CUK LTC2202CUK#TR LTC2202UK 48-Lead (7mm × 7mm) Plastic QFN 0°C to 70°C

LTC2203IUK LTC2203IUK#TR LTC2203UK 48-Lead (7mm × 7mm) Plastic QFN –40°C to 85°C

LTC2202IUK LTC2202IUK#TR LTC2202UK 48-Lead (7mm × 7mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

LTC2203/LTC2202

22032fd

CONVERTER CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No missing codes) 16

Integral Linearity Error Differential Analog Input (Note 5) TA = 25°C ±1.2 ±4.0 LSB

Integral Linearity Error Differential Analog Input (Note 5) l±1.5 ±4.5 LSB

Differential Linearity Error Differential Analog Input l±0.3 ±1 LSB

Offset Error (Note 6) l±2 ±10 mV

Offset Drift ±10 μV/°C

Gain Error External Reference l±0.2 ±1.5 %FS

Full-Scale Drift Internal Reference

External Reference

±30

±15

ppm/°C

Transition Noise External Reference (2.5V Range, PGA = 0) 1.92 LSBRMS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Analog Input Range (AIN+ – AIN–)3.135V ≤ VDD ≤ 3.465V 1.667 or 2.5 VP-P

VIN, CM Analog Input Common Mode Differential Input (Note 7) l1 1.25 1.5 V

IIN Analog Input Leakage Current 0V ≤ AIN+, AIN– ≤ VDD (Note 9) l–1 1 μA

ISENSE SENSE Input Leakage Current 0V ≤ SENSE ≤ VDD (Note 10) l–3 3 μA

IMODE MODE Pin Pull-Down Current to GND 10 μA

IOE OE Pin Pull-Down Current to GND 10 μA

CIN Analog Input Capacitance Sample Mode CLK = 0

Hold Mode CLK = 0

10.5

1.4

tAP Sample-and-Hold

Acquisition Delay Time

0.9 ns

tJITTER Sample-and-Hold

Acquisition Delay Time Jitter

200 fSRMS

CMRR Analog Input

Common Mode Rejection Ratio

1V < (AIN+ = AIN–) <1.5V 80 dB

BW-3dB Full Power Bandwidth Rs < 20Ω 380 MHz

SYMBOL PARAMETER CONDITIONS MIN

LTC2203

TYP MAX MIN

LTC2202

TYP MAX UNITS

SNR Signal-to-Noise Ratio 1MHz Input (2.25V Range, PGA = 0)

1MHz Input (1.667V Range, PGA = 1)

81.6

79.4

81.6

79.4

dBFS

5MHz Input (2.5V Range, PGA = 0)

5MHz Input (1.667V Range, PGA = 1)

l80 81.6

79.4

80 81.6

79.4

dBFS

12.5MHz Input (2.5V Range, PGA = 0)

12.5MHz Input (1.667V Range, PGA = 1)

81.4

79.3

81.4

79.3

dBFS

30MHz Input (2.5V Range, PGA = 0)

30MHz Input (1.667V Range, PGA = 1) l77.5

80.8

78.9 77.5

80.8

78.9

dBFS

70MHz Input (2.5V Range, PGA = 0)

70MHz Input (1.667V Range, PGA =1 )

78.3

77.2

78.3

77.2

dBFS

ANALOG INPUT

DYNAMIC ACCURACY

The l denotes the speciﬁ cations which apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C. AIN = –1dBFS. (Note 4)

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise

speciﬁ cations are at TA = 25°C. (Note 4)

The

l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

LTC2203/LTC2202

22032fd

The l denotes the speciﬁ cations which apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C. AIN = –1dBFS. (Note 4)

DYNAMIC ACCURACY

SYMBOL PARAMETER CONDITIONS MIN

LTC2203

TYP MAX MIN

LTC2202

TYP MAX UNITS

SFDR Spurious Free

Dynamic Range

2nd or 3rd Harmonic

1MHz Input (2.5V Range, PGA = 0)

1MHz Input (1.667V Range, PGA = 1)

100

dBc

5MHz Input (2.5V Range, PGA = 0)

5MHz Input (1.667V Range, PGA = 1)

l85

100

dBc

12.5MHz Input (2.5V Range, PGA = 0)

12.5MHz Input (1.667V Range, PGA = 1)

100

dBc

30MHz Input (2.5V Range, PGA = 0)

30MHz Input (1.667V Range, PGA = 1) l85

95 85

dBc

70MHz Input (2.5V Range, PGA = 0)

70MHz Input (1.667V Range, PGA = 1)

dBc

SFDR Spurious Free

Dynamic Range

4th Harmonic or Higher

1MHz Input (2.5V Range, PGA = 0)

1MHz Input (1.667V Range, PGA = 1)

100

dBc

5MHz Input (2.5V Range, PGA = 0)

5MHz Input (1.667V Range, PGA = 1)

l90 100

100

90 100

100

dBc

12.5MHz Input (2.5V Range, PGA = 0)

12.5MHz Input (1.667V Range, PGA = 1)

100

dBc

30MHz Input (2.5V Range, PGA = 0)

30MHz Input (1.667V Range, PGA = 1) l90

100

100 90

100

dBc

70MHz Input (2.5V Range, PGA = 0)

70MHz Input (1.667V Range, PGA = 1)

dBc

S/(N+D) Signal-to-Noise

Plus Distortion Ratio

1MHz Input (2.5V Range, PGA = 0)

1MHz Input (1.667V Range, PGA = 1)

81.5

79.3

81.5

79.3

dBFS

5MHz Input (2.5V Range, PGA = 0)

5MHz Input (1.667V Range, PGA = 1)

l79.7 81.5

79.3

79.7 81.5

79.3

dBFS

12.5MHz Input (2.5V Range, PGA = 0)

12.5MHz Input (1.667V Range, PGA = 1)

81.3

79.2

81.3

79.2

dBFS

30MHz Input (2.5V Range, PGA = 0)

30MHz Input (1.667V Range, PGA = 1) l77.2

80.6

78.6 77.2

80.6

78.6

dBFS

70MHz Input (2.5V Range, PGA = 0)

70MHz Input (1.667V Range, PGA = 1)

78.1

dBFS

SFDR Spurious Free

Dynamic Range

at –25dBFS

Dither “OFF”

1MHz Input (2.5V Range, PGA = 0)

1MHz Input (1.667V Range, PGA = 1)

105

dBFS

5MHz Input (2.5V Range, PGA = 0)

5MHz Input (1.667V Range, PGA = 1)

105

dBFS

12.5MHz Input (2.5V Range, PGA = 0)

12.5MHz Input (1.667V Range, PGA = 1)

105

dBFS

30MHz Input (2.5V Range, PGA = 0)

30MHz Input (1.667V Range, PGA = 1)

105

dBFS

70MHz Input (2.5V Range, PGA = 0)

70MHz Input (1.667V Range, PGA = 1)

100

dBFS

LTC2203/LTC2202

22032fd

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCM Output Voltage IOUT = 0 1.15 1.25 1.35 V

VCM Output Tempco IOUT = 0 ±40 ppm/°C

VCM Line Regulation 3.135V ≤ VDD ≤ 3.465V 1 mV/ V

VCM Output Resistance 1mA ≤ | IOUT | ≤ 1mA 2 Ω

COMMON MODE BIAS CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

LOGIC INPUTS (CLK, OE, DITH, PGA, SHDN, RAND)

VIH High Level Input Voltage VDD = 3.3V l2V

VIL Low Level Input Voltage VDD = 3.3V l0.8 V

IIN Digital Input Current VIN = 0V to VDD l±10 μA

CIN Digital Input Capacitance (Note 7) 1.5 pF

LOGIC OUTPUTS

OVDD = 3.3V

VOH High Level Output Voltage VDD = 3.3V IO = –10μA

O = –200μA l3.1

3.299

3.29

VOL Low Level Output Voltage VDD = 3.3V IO = 160μA

O = 1.6mA l

0.01

0.10 0.4

ISOURCE Output Source Current VOUT = 0V –50 mA

ISINK Output Sink Current VOUT = 3.3V 50 mA

OVDD = 2.5V

VOH High Level Output Voltage VDD = 3.3V IO = –200μA 2.49 V

VOL Low Level Output Voltage VDD = 3.3V IO = 1.60mA 0.1 V

OVDD = 1.8V

VOH High Level Output Voltage VDD = 3.3V IO = –200μA 1.79 V

VOL Low Level Output Voltage VDD = 3.3V IO = 1.60mA 0.1 V

DIGITAL INPUTS AND DIGITAL OUTPUTS

SYMBOL PARAMETER CONDITIONS MIN

LTC2203

TYP MAX MIN

LTC2202

TYP MAX UNITS

SFDR Spurious Free

Dynamic Range

at –25dBFS

Dither “ON”

1MHz Input (2.5V Range, PGA = 0)

1MHz Input (1.667V Range, PGA = 1)

115

dBFS

5MHz Input (2.5V Range, PGA = 0)

5MHz Input (1.667V Range, PGA = 1)

l100 115

115

100 115

115

dBFS

12.5MHz Input (2.5V Range, PGA = 0)

12.5MHz Input (1.667V Range, PGA = 1)

115

dBFS

30MHz Input (2.5V Range, PGA = 0)

30MHz Input (1.667V Range, PGA = 1)

115

dBFS

70MHz Input (2.5V Range, PGA = 0)

70MHz Input (1.667V Range, PGA = 1)

110

dBFS

DYNAMIC ACCURACY

The l denotes the speciﬁ cations which apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C. AIN = –1dBFS. (Note 4)

The l denotes the speciﬁ cations which apply over

the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

The l denotes the speciﬁ cations which apply over the

full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

LTC2203/LTC2202

22032fd

TIMING CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND, with GND and OGND

shorted (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above VDD, they

will be clamped by internal diodes. This product can handle input currents

of greater than 100mA below GND or above VDD without latchup.

Note 4: VDD = 3.3V, fSAMPLE = 25MHz (LTC2203), 10MHz (LTC2202),

input range = 2.5VP-P with differential drive (PGA = 0), unless otherwise

speciﬁ ed.

Note 5: Integral nonlinearity is deﬁ ned as the deviation of a code from a

“best ﬁ t straight line” to the transfer curve. The deviation is measured from

the center of the quantization band.

Note 6: Offset error is the offset voltage measured from –1/2LSB when the

output code ﬂ ickers between 0000 0000 0000 0000 and 1111 1111 1111

1111 in 2’s complement output mode.

Note 7: Guaranteed by design, not subject to test.

Note 8: Recommended operating conditions.

Note 9: Dynamic current from switched capacitor inputs is large compared

to DC leakage current, and will vary with sample rate.

Note 10: Leakage current will experience transient at power up. Keep

resistance < 1K Ω.

The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

The

l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. AIN = –1dBFS. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN

LTC2203

TYP MAX MIN

LTC2202

TYP MAX UNITS

VDD Analog Supply Voltage l3.135 3.3 3.465 3.135 3.3 3.465 V

PSHDN Shutdown Power SHDN = VDD, CLK = VDD 22mW

OVDD Output Supply Voltage l0.5 3.6 0.5 3.6 V

IVDD Analog Supply Current l66 80 42 50 mA

PDIS Power Dissipation l220 264 140 165 mW

POWER REQUIREMENTS

SYMBOL PARAMETER CONDITIONS MIN

LTC2203

TYP MAX MIN

LTC2202

TYP MAX UNITS

fSSampling Frequency l1 25 1 10 MHz

tLCLK Low Time Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

18.9

500

tHCLK High Time Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

18.9

500

tAP Sample-and-Hold

Aperture Delay

0.9 0.9 ns

tDCLK to DATA Delay CL = 5pF (Note 7) l1.3 3.1 4.9 1.3 3.1 4.9 ns

tCCLK to CLKOUT Delay CL = 5pF (Note 7) l1.3 3.1 4.9 1.3 3.1 4.9 ns

tSKEW DATA to CLKOUT Skew CL = 5pF (Note 7) l–0.6 0 0.6 –0.6 0 0.6 ns

DATA Access Time

Bus Relinquish Time

CL = 5pF (Note 7)

(Note 7)

Pipeline

Latency

7 7 Cycles

LTC2203/LTC2202

22032fd

LTC2203: Integral Nonlinearity

(INL) vs Output Code

LTC2203: Differential Nonlinearity

(DNL) vs Output Code

LTC2203: AC Grounded Input

Histogram (256k Samples)

LTC2203: 128K Point FFT,

fIN = 1MHz, –1dBFS, PGA = 0

LTC2203: 128K Point FFT,

fIN = 1MHz, –10dBFS, PGA = 0

LTC2203: 128K Point FFT,

fIN = 1MHz, –20dBFS, PGA = 0

CODE

INL ERROR (LSB)

0.0

0.5

1.0

65536

22032 G01

–0.5

–1.0

–2.0 16384 32768 49152

–1.5

2.0

1.5

CODE

–1.0

DNL ERROR (LSB)

–0.8

–0.4

–0.2

0.0

1.0

0.4

16384 32768

22032 G02

–0.6

0.6

0.8

0.2

49152 6553

OUTPUT CODE

32812

COUNT

10000

20000

30000

40000

50000

60000

32816 32820 32824 32828

22032 G03

32832

FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 GO4 FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 GO5 FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 GO6

tAP

ANALOG

INPUT

N – 7 N – 6 N – 5 N – 4 N – 3

CLK

CLKOUT+

CLKOUT–

D0-D15, OF

22032 TD01

N + 1

N + 2

N + 4

N + 3

TIMING DIAGRAM

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2203/LTC2202

22032fd

LTC2203: 128K Point FFT,

fIN = 5.1MHz, –20dBFS, PGA = 0,

Internal Dither “On”

LTC2203: 32K Point 2-Tone FFT,

fIN = 4.9MHz and 30.1MHz,

–7dBFS, PGA = 0

LTC2203: 32K Point 2-Tone FFT,

fIN = 4.9MHz and 30.1MHz,

–15dBFS, PGA = 0

LTC2203: SFDR vs Input Level,

fIN = 5MHz, PGA = 0, Dither “Off”

LTC2203: SFDR vs Input Level,

fIN = 5MHz, PGA = 0, Dither “On”

LTC2203: 32K Point FFT,

fIN = 12.4MHz, –1dBFS, PGA = 0

FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 G10 FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 G11 FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 G12

INPUT LEVEL (dBFS)

–70

SFDR (dBc AND dBFS)

100

120

22032 G13

–60 –50 –40 –30 –20 –10 0

140

INPUT LEVEL (dBFS)

–70

SFDR (dBc AND dBFS)

100

120

22032 G14

–60 –50 –40 –30 –20 –10 0

140

FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 G15

LTC2203: 128K Point FFT,

fIN = 5.1MHz, –1dBFS, PGA = 0

FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 GO7

LTC2203: 128K Point FFT,

fIN = 5.1MHz, –10dBFS, PGA = 0

LTC2203: 128K Point FFT,

fIN = 5.1MHz, –20dBFS, PGA = 0,

Internal Dither “Off”

FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 GO8 FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 GO9

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2203/LTC2202

22032fd

LTC2203: 32K Point FFT,

fIN = 12.4MHz, –10dBFS, PGA = 0

LTC2203: 32K Point FFT,

fIN = 12.4MHz, –20dBFS, PGA = 0

LTC2203: SFDR vs Input Level,

fIN = 12.7MHz, PGA = 0,

Dither “Off”

FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 G16 FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 G17 INPUT LEVEL (dBFS)

–70

SFDR (dBc AND dBFS)

100

120

22032 G18

–60 –50 –40 –30 –20 –10 0

140

LTC2203: SFDR vs Input Level,

fIN = 12.7MHz, PGA = 0,

Dither “On”

LTC2203: 32K Point FFT,

fIN = 30MHz, –1dBFS, PGA = 1

LTC2203: 32K Point FFT,

fIN = 30MHz, –10dBFS, PGA = 1

LTC2203: 32K Point FFT,

fIN = 30MHz, –20dBFS, PGA = 1

LTC2203: SFDR vs Input Level,

fIN = 30.1MHz, PGA = 0,

Dither “Off”

LTC2203: SFDR vs Input Level,

fIN = 30.1MHz, PGA = 0,

Dither “On”

INPUT LEVEL (dBFS)

–70

SFDR (dBc AND dBFS)

100

120

22032 G19

–60 –50 –40 –30 –20 –10 0

140

FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 G20 FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 G21

FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 G22 INPUT LEVEL (dBFS)

–80

SFDR (dBc AND dBFS)

100

120

22032 G23

–70 –60 –50 –40 –30 –20 –10 0

140

INPUT LEVEL (dBFS)

–70

SFDR (dBc AND dBFS)

100

120

22032 G24

–60 –50 –40 –30 –20 –10 0

140

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2203/LTC2202

22032fd

LTC2203: 32K Point 2-Tone FFT,

fIN = 44.9MHz and 70.1MHz,

–7dBFS, PGA = 0

LTC2203: 32K Point 2-Tone FFT,

fIN = 44.9MHz and 70.1MHz,

–15dBFS, PGA = 0

LTC2203: SFDR vs Input Level,

fIN = 70.1MHz, PGA = 0,

Dither “Off”

LTC2203: SFDR vs Input Level,

fIN = 70.1MHz, PGA = 0,

Dither “On”

LTC2203: SFDR (HD2 or HD3)

vs Input Frequency LTC2203: SNR vs Input Frequency

FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 G28 FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 G29 INPUT LEVEL (dBFS)

–70 –60 –50 –40 –30 –20 –10 0

SFDR (dbc AND dBFS)

100

120

22032 G30

140

INPUT LEVEL (dBFS)

–70

SFDR (dBc AND dBFS)

100

120

22032 G31

–60 –50 –40 –30 –20 –10 0

140

INPUT FREQUENCY (MHz)

SFDR (dBc)

60 100

22032 G32

70 20 40 80

100

105

110

PGA = 1

PGA = 0

INPUT FREQUENCY (MHz)

SNR (dBFS)

22032 G33

20 100 120

60 140

PGA = 0

PGA = 1

LTC2203: 32K Point FFT,

fIN = 70.1MHz, –1dBFS, PGA = 1

LTC2203: 32K Point FFT,

fIN = 70.1MHz, –10dBFS, PGA = 1

LTC2203: 32K Point FFT,

fIN = 70.1MHz, –20dBFS, PGA = 1

FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 G25 FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 G26 FREQUENCY(MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–10

–30

–50

–70

–90

–110

–130

–40

–20

–60

4810 12

22032 G27

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2203/LTC2202

22032fd

LTC2203: SNR and SFDR

vs Sample Rate

LTC2203: SNR and SFDR vs

Supply Voltage (VDD), fIN = 5MHz

LTC2203: IVDD vs Sample Rate,

5MHz Sine Wave, –1dBFS

SAMPLE RATE (Msps)

SNR AND SFDR (dBFS)

100

110

525 35

22032 G34

105

20 45 50

10 15 30 40

SFDR

RATED MAX

SNR

SUPPLY VOLTAGE (V)

2.8

SNR SFDR (dBFS)

100

105

3.4 3.5

22032 G35

2.9 3.0 3.1 3.2 3.3 3.6

110

SFDR

LOWER LIMIT UPPER LIMIT

SNR

SAMPLE RATE (Msps)

IVDD (mA)

22032 G36

50 510 15 25

LTC2203: Normalized Full

Scale vs Temperature, Internal

Reference, 5 Units

LTC2203: Offset Voltage

vs Temperature, 5 Units

LTC2203: SFDR vs Input Common

Mode Voltage, fIN = 5MHz,

–1dBFS, PGA = 0

LTC2202: Integral Nonlinearity

(INL) vs Output Code

LTC2202: Differential Nonlinearity

(DNL) vs Output Code

LTC2202: AC Grounded Input

Histogram (256K Samples)

TEMPERATURE (°C)

–40

0.99

NORMALIZED FULL SCALE

0.995

1.005

1.01

–20 0 20 40

22032 G37

60 80

TEMPERATURE (˚C)

–40

OFFSET VOLTAGE (mV)

20 60

22032 G38

–2

–20 0 40 80

–4

–6

INPUT COMMON MODE VOLTAGE (V)

0.5

SFDR (dBc)

0.75 11.25 1.50

22032 G39

1.75

100

110

105

CODE

INL ERROR (LSB)

0.5

1.0

65536

22032 G40

–0.5

–1.0

–2.0 16384 32768 49152

–1.5

2.0

1.5

CODE

1.0

DNL ERROR (LSB)

0.8

0.4

0.2

1.0

0.4

16384 32768

22032 G41

0.6

0.8

0.2

49152 65536

OUTPUT CODE

32793

COUNT

40000

35000

30000

25000

15000

5000

45000

50000

32797

22032 G42

20000

10000

032801 32805 32809

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2203/LTC2202

22032fd

LTC2203: 128K Point FFT,

fIN = 5.1MHz, –20dBFS, PGA = 0,

Internal Dither “On”

LTC2202: 32K Point 2-Tone FFT,

fIN = 5.1MHz and 15.2MHz,

–7dBFS, PGA = 0

LTC2202: 32K Point 2-Tone FFT,

fIN = 5.1MHz and 15.2MHz,

–15dBFS, PGA = 0

LTC2202: SFDR vs Input Level,

fIN = 5MHz, PGA = 0, Dither “Off”

LTC2202: SFDR vs Input Level,

fIN = 5MHz, PGA = 0, Dither “On”

LTC2202: 32K Point FFT,

fIN = 12.4MHz, –1dBFS, PGA = 0

FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

134

–20

–60

–130

–110

–90

–10

–50

–30

–70

22032 G46 FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

134

–20

–60

–130

–110

–90

–10

–50

–30

–70

22032 G47 FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

134

–20

–60

–130

–110

–90

–10

–50

–30

–70

22032 G48

INPUT LEVEL (dBFS)

–70

SFDR (dBc AND dBFS)

–60 –40 –20 0

22032 G49

100

120

–50 –30 –10

INPUT LEVEL (dBFS)

–70

SFDR (dBc AND dBFS)

100

–60 –40 –20 0

22032 G50

120

140

–50 –30 –10

FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

134

–20

–60

–130

–110

–90

–10

–50

–30

–70

22032 G51

LTC2202: 128K Point FFT,

fIN = 5.1MHz, –1dBFS, PGA = 0

LTC2202: 128K Point FFT,

fIN = 5.1MHz, –10dBFS, PGA = 0

LTC2202: 128K Point FFT,

fIN = 5.1MHz, –20dBFS, PGA = 0,

Internal Dither “Off”

FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

134

–20

–60

–130

–110

–90

–10

–50

–30

–70

22032 G43 FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

134

–20

–60

–130

–110

–90

–10

–50

–30

–70

22032 G44 FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

134

–20

–60

–130

–110

–90

–10

–50

–30

–70

22032 G45

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2203/LTC2202

22032fd

LTC2202: 32K Point FFT,

fIN = 12.4MHz, –10dBFS, PGA = 0 LTC2202: 32K Point FFT,

fIN = 12.4MHz, –20dBFS, PGA = 0

LTC2202: SFDR vs Input Level,

fIN = 12.4MHz, PGA = 0,

Dither “Off

FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

134

–20

–60

–130

–110

–90

–10

–50

–30

–70

22032 G52 FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

134

–20

–60

–130

–110

–90

–10

–50

–30

–70

22032 G53 INPUT LEVEL (dBFS)

–70

SFDR (dBc AND dBFS)

–60 –40 –20 0

22032 G54

100

120

–50 –30 –10

LTC2202: 32K Point FFT,

fIN = 30.5MHz, –1dBFS, PGA = 1

LTC2202: 32K Point FFT,

fIN = 30.5MHz, –10dBFS, PGA = 1

LTC2202: 32K Point FFT,

fIN = 30.5MHz, –20dBFS, PGA = 1

LTC2202: SFDR vs Input Level,

fIN = 30.1MHz, PGA = 0,

Dither “Off”

LTC2202: SFDR vs Input Level,

fIN = 30.1MHz, PGA = 0,

Dither “On”

LTC2202: 32K Point FFT,

fIN = 70.1MHz, –1dBFS, PGA = 1

FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

134

–20

–60

–130

–110

–90

–10

–50

–30

–70

22032 G55 FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

134

–20

–60

–130

–110

–90

–10

–50

–30

–70

22032 G56 FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

134

–20

–60

–130

–110

–90

–10

–50

–30

–70

22032 G57

INPUT LEVEL (dBFS)

–70

SFDR (dBc AND dBFS)

100

–60 –40 –20 0

22032 G58

120

140

–50 –30 –10

INPUT LEVEL (dBFS)

–70

SFDR (dBc AND dBFS)

100

–60 –40 –20 0

22032 G59

120

140

–50 –30 –10

FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

134

–20

–60

–130

–110

–90

–10

–50

–30

–70

22032 G60

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2203/LTC2202

22032fd

LTC2202: 32K Point 2-Tone FFT,

fIN = 60.2MHz and 70.1MHz,

–15dBFS, PGA = 0

LTC2202: SFDR vs Input Level,

fIN = 70.1MHz, PGA = 0,

Dither “Off”

LTC2202: SFDR vs Input Level,

fIN = 70.1MHz, PGA = 0,

Dither “On”

LTC2202: SFDR (HD2 or HD3)

vs Input Frequency LTC2202: SNR vs Input Frequency

FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

–20

–60

–130

–110

–90

–10

–50

–30

–70

22032 G64

02 4

INPUT LEVEL (dBFS)

–80

SFDR (dBc AND dBFS)

100

–60 –40 –20 0

22032 G65

120

140

–70 –50 –30 –10

INPUT LEVEL (dBFS)

–80

SFDR (dBc AND dBFS)

100

–60 –40 –20 0

22032 G66

120

140

–70 –50 –30 –10

INPUT FREQUENCY (MHz)

SFDR(dBc)

60 100

22032 G67

70 20 40 80

100

105

110

PGA = 0

PGA = 1

INPUT FREQUENCY (MHz)

SNR (dBFS)

22032 G68

20 100 120

60 140

PGA = 0

PGA = 1

LTC2202: 32K Point 2-Tone FFT,

fIN = 60.2MHz and 70.1MHz,

–7dBFS, PGA = 0

FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

–20

–60

–130

–110

–90

–10

–50

–30

–70

22032 G63

02 4

LTC2202: 32K Point FFT,

fIN = 70.1MHz, –10dBFS, PGA = 1

LTC2202: 32K Point FFT,

fIN = 70.1MHz, –20dBFS, PGA = 1

FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

134

–20

–60

–130

–110

–90

–10

–50

–30

–70

22032 G61 FREQUENCY (MHz)

–140

AMPLITUDE (dBFS)

–120

–100

–80

–40

134

–20

–60

–130

–110

–90

–10

–50

–30

–70

22032 G62

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2203/LTC2202

22032fd

LTC2202: SNR and SFDR

vs Sample Rate

LTC2202: SNR and SFDR vs

Supply Voltage (VDD), fIN = 5MHz

LTC2202: IVDD vs Sample Rate,

5MHz Sine Wave, –1dBFS

LTC2202: Normalized Full

Scale vs Temperature, Internal

Reference, 5 Units

SAMPLE RATE (Msps)

100

105

110

22032 G69

4 8 12 20

SNR AND SFDR (dBFS)

SFDR

RATED MAX

SNR

SUPPLY VOLTAGE (V)

2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6

SNR SFDR (dBFS)

100

105

22032 G70

110

SFDR

LOWER LIMIT UPPER LIMIT

SNR

SAMPLE RATE (Msps)

IVDD (mA)

22032 G71

40 24610

TEMPERATURE (°C)

–40

0.99

NORMALIZED FULL SCALE

0.995

1.005

1.01

–20 0 20 40

22032 G72

60 80

TEMPERATURE (˚C)

–40

OFFSET VOLTAGE (mV)

20 60

22032 G73

–2

–20 0 40 80

–4

–6

INPUT COMMON MODE VOLTAGE (V)

0.5

SFDR (dBc)

0.75 11.25 1.50

22032 G74

1.75

100

110

105

LTC2202: Offset Voltage

vs Temperature, 5 Units

LTC2202: SFDR vs Input Common

Mode Voltage, fIN = 5MHz,

–1dBFS, PGA = 0

TYPICAL PERFORMANCE CHARACTERISTICS

TIME AFTER WAKE-UP OR CLOCK START (μs)

FULL-SCALE ERROR (%)

0.2

0.6

1.0

400

22032 G75

–0.2

–0.6

0.4

0.8

–0.4

–0.8

–1.0 10050 200150 300 350 450

250 500

TIME FROM WAKE-UP OR CLOCK START (μs)

FULL-SCALE ERROR (%)

800

22032 G76

–1

–3

–2

–4

–5 200100 400300 600 700 900

500 1000

Mid-Scale Settling After Wake

Up from Shutdown or Starting

Encode Clock

Full-Scale Settling After Wake

Up from Shutdown or Starting

Encode Clock

LTC2203/LTC2202

22032fd

SENSE (Pin 1): Reference Mode Select and External Refer-

ence Input. Tie SENSE to VDD with 1k Ω or less to select

the internal 2.5V bandgap reference. An external reference

of 2.5V or 1.25V may be used; both reference values will

set a full scale ADC range of 2.5V (PGA = 0).

VCM (Pin 2): 1.25V Output. Optimum voltage for input com-

mon mode. Must be bypassed to ground with a minimum

of 2.2μF. Ceramic chip capacitors are recommended.

VDD (Pins 3, 4, 12, 13, 14): 3.3V Analog Supply Pin.

Bypass to GND with 0.1μF ceramic chip capacitors.

GND (Pins 5, 8, 9, 11, 15, 48, 49): ADC Power

Ground.

AIN+ (Pin 6): Positive Differential Analog Input.

AIN– (Pin 7): Negative Differential Analog Input.

CLK (Pin 10): Clock Input. The hold phase of the sample-

and-hold circuit begins on the falling edge. The output

data may be latched on the rising edge of CLK.

SHDN (Pin 16): Power Shutdown Pin. SHDN = low results

in normal operation. SHDN = high results in powered

down analog circuitry and the digital outputs are placed

in a high impedance state.

DITH (Pin 17): Internal Dither Enable Pin. DITH = low

disables internal dither. DITH = high enables internal

dither. Refer to Internal Dither section of this data sheet

for details on dither operation.

D0-D15 (Pins 18-22, 26-28, 32-35 and 39-42): Digital

Outputs. D15 is the MSB.

OGND (Pins 23, 31 and 38): Output Driver Ground.

OVDD (Pins 24, 25, 36, 37): Positive Supply for the Output

Drivers. Bypass to ground with 0.1μF capacitor.

CLKOUT– (Pin 29): Data Valid Output. CLKOUT– will toggle

at the sample rate. Latch the data on the falling edge of

CLKOUT–.

CLKOUT+ (Pin 30): Inverted Data Valid Output. CLKOUT+

will toggle at the sample rate. Latch the data on the rising

edge of CLKOUT+.

OF (Pin 43): Over/Under Flow Digital Output. OF is high

when an over or under ﬂ ow has occurred.

OE (Pin 44): Output Enable Pin. Low enables the digital

output drivers. High puts digital outputs in Hi-Z state.

MODE (Pin 45): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Connecting MODE to 0V selects

offset binary output format and disables the clock duty

cycle stabilizer. Connecting MODE to 1/3VDD selects offset

binary output format and enables the clock duty cycle sta-

bilizer. Connecting MODE to 2/3VDD selects 2’s complement

output format and enables the clock duty cycle stabilizer.

Connecting MODE to VDD selects 2’s complement output

format and disables the clock duty cycle stabilizer.

RAND (Pin 46): Digital Output Randomization Selection Pin.

RAND low results in normal operation. RAND high selects

D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The

output can be decoded by again applying an XOR operation

between the LSB and all other bits. The mode of operation

reduces the effects of digital output interference.

PGA (Pin 47): Programmable Gain Ampliﬁ er Control Pin. Low

selects a front-end gain of 1, input range of 2.5VP-P. High

selects a front-end gain of 1.5, input range of 1.667VP-P.

GND (Exposed Pad, Pin 49): ADC Power Ground. The ex-

posed pad on the bottom of the package must be soldered

to ground.

PIN FUNCTIONS

LTC2203/LTC2202

22032fd

Figure 1. Functional Block Diagram

ADC CLOCKS

LOW JITTER

CLOCK

DRIVER

DITHER

SIGNAL

GENERATOR

FIRST PIPELINED

ADC STAGE

FIFTH PIPELINED

ADC STAGE

FOURTH PIPELINED

ADC STAGE

SECOND PIPELINED

ADC STAGE

CLK

CORRECTION LOGIC

AND

SHIFT REGISTER

DITHM0DE

OGND

CLKOUT+

CLKOUT–

D15

D14

OVDD

22032 F01

INPUT

S/H

AIN–

AIN+

THIRD PIPELINED

ADC STAGE

OUTPUT

DRIVERS

CONTROL

LOGIC

PGA RAND

SHDN

•

VDD

GND

PGA

SENSE

VCM BUFFER

ADC

REFERENCE

VOLTAGE

REFERENCE

RANGE

SELECT

BLOCK DIAGRAM

LTC2203/LTC2202

22032fd

DYNAMIC PERFORMANCE

Signal-to-Noise Plus Distortion Ratio

The signal-to-noise plus distortion ratio [S/(N+D)] is the

ratio between the RMS amplitude of the fundamental input

frequency and the RMS amplitude of all other frequency

components at the ADC output. The output is band lim-

ited to frequencies above DC to below half the sampling

frequency.

Signal-to-Noise Ratio

The signal-to-noise (SNR) is the ratio between the RMS

amplitude of the fundamental input frequency and the RMS

amplitude of all other frequency components, except the

ﬁ rst ﬁ ve harmonics.

Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum

of all harmonics of the input signal to the fundamental

itself. The out-of-band harmonics alias into the frequency

band between DC and half the sampling frequency. THD

is expressed as:

THD = –20Log

(

√(V22 + V32 + V42 + ... VN2)/V1

)

where V1 is the RMS amplitude of the fundamental fre-

quency and V2 through VN are the amplitudes of the second

through nth harmonics.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused

by the presence of another sinusoidal input at a different

frequency.

If two pure sine waves of frequencies fa and fb are ap-

plied to the ADC input, nonlinearities in the ADC transfer

function can create distortion products at the sum and

difference frequencies of mfa ± nfb, where m and n =

0, 1, 2, 3, etc. For example, the 3rd order IMD terms

include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). The

3rd order IMD is deﬁ ned as the ratio of the RMS value

of either input tone to the RMS value of the largest 3rd

order IMD product.

Spurious Free Dynamic Range (SFDR)

The ratio of the RMS input signal amplitude to the RMS

value of the peak spurious spectral component expressed

in dBc. SFDR may also be calculated relative to full scale

and expressed in dBFS.

Full Power Bandwidth

The Full Power bandwidth is that input frequency at which

the amplitude of the reconstructed fundamental is reduced

by 3dB for a full scale input signal.

Aperture Delay Time

The time from when CLK reaches 0.45 of VDD to the

instant that the input signal is held by the sample-and-

hold circuit.

Aperture Delay Jitter

The variation in the aperture delay time from conversion

to conversion. This random variation will result in noise

when sampling an AC input. The signal to noise ratio due

to the jitter alone will be:

SNRJITTER = –20log (2π • fIN • tJITTER)

APPLICATIONS INFORMATION

LTC2203/LTC2202

22032fd

CONVERTER OPERATION

The LTC2203/LTC2202 are CMOS pipelined multistep con-

verters with a front-end PGA. As shown in Figure 1, the

converter has ﬁ ve pipelined ADC stages; a sampled analog

input will result in a digitized value seven cycles later (see the

Timing Diagram section). The analog input is differential

for improved common mode noise immunity and to

maximize the input range. Additionally, the differential

input drive will reduce even order harmonics of the

sample-and-hold circuit.

Each pipelined stage shown in Figure 1 contains an ADC,

a reconstruction DAC and an interstage ampliﬁ er. In

operation, the ADC quantizes the input to the stage and

the quantized value is subtracted from the input by the

DAC to produce a residue. The residue is ampliﬁ ed and

output by the residue ampliﬁ er. Successive stages oper-

ate out of phase so that when odd stages are outputting

their residue, the even stages are acquiring that residue

and vice versa.

The phase of operation is determined by the state of the

CLK input pin.

When CLK is high, the analog input is sampled differen-

tially directly onto the input sample-and-hold capacitors,

inside the “input S/H” shown in the block diagram. At the

instant that CLK transitions from high to low, the volt-

age on the sample capacitors is held. While CLK is low,

the held input voltage is buffered by the S/H ampliﬁ er

which drives the ﬁ rst pipelined ADC stage. The ﬁ rst stage

acquires the output of the S/H ampliﬁ er during the low

phase of CLK. When CLK goes back high, the ﬁ rst stage

produces its residue which is acquired by the second stage.

At the same time, the input S/H goes back to acquiring

the analog input. When CLK goes low, the second stage

produces its residue which is acquired by the third stage.

An identical process is repeated for the third and fourth

stages, resulting in a fourth stage residue that is sent to

the ﬁ fth stage for ﬁ nal evaluation.

Each ADC stage following the ﬁ rst has additional range to

accommodate ﬂ ash and ampliﬁ er offset errors. Results

from all of the ADC stages are digitally delayed such that

the results can be properly combined in the correction

logic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2203/

LTC2202 CMOS differential sample and hold. The differ-

ential analog inputs are sampled directly onto sampling

capacitors (CSAMPLE) through NMOS transitors. The

capacitors shown attached to each input (CPARASITIC) are

the summation of all other capacitance associated with

each input.

During the sample phase when CLK is high, the NMOS

transistors connect the analog inputs to the sampling

capacitors and they charge to, and track the differential

input voltage. When CLK transitions from high to low, the

sampled input voltage is held on the sampling capacitors.

During the hold phase when CLK is high, the sampling

capacitors are disconnected from the input and the held

voltage is passed to the ADC core for processing. As CLK

transitions from low to high, the inputs are reconnected to

the sampling capacitors to acquire a new sample. Since

the sampling capacitors still hold the previous sample,

a charging glitch proportional to the change in voltage

between samples will be seen at this time at the input of

the converter. If the change between the last sample and

Figure 2. Equivalent Input Circuit

LTC2203/LTC2202

CLK

22032 F02

VDD

RPARASITIC

3Ω

RPARASITIC

3Ω

AIN+

AIN–

CPARASITIC

1.4pF

CPARASITIC

1.4pF

CSAMPLE

9.1pF

CSAMPLE

9.1pF

RON

20Ω

RON

20Ω

APPLICATIONS INFORMATION

LTC2203/LTC2202

22032fd

the new sample is small, the charging glitch seen at the

input will be small. If the input change is large, such as

the change seen with input frequencies near Nyquist, then

a larger charging glitch will be seen.

Common Mode Bias

The ADC sample-and-hold circuit requires differential

drive to achieve speciﬁ ed performance. Each input may

swing ±0.625V for the 2.5V range (PGA = 0) or ±0.417V

for the 1.667V range (PGA = 1), around a common mode

voltage of 1.25V. The VCM output pin (Pin 3) is designed

to provide the common mode bias level. VCM can be tied

directly to the center tap of a transformer to set the DC

input level or as a reference level to an op amp differential

driver circuit. The VCM pin must be bypassed to ground

close to the ADC with 2.2μF or greater.

Input Drive Impedence

As with all high performance, high speed ADCs the

dynamic performance of the LTC2203/LTC2202 can be

inﬂ uenced by the input drive circuitry, particularly the

second and third harmonics. Source impedance and

input reactance can inﬂ uence SFDR. At the rising edge of

CLK the sample and hold circuit will connect the 9.1pF

sampling capacitor to the input pin and start the sampling

period. The sampling period ends when CLK falls, hold-

ing the sampled input on the sampling capacitor. Ideally,

the input circuitry should be fast enough to fully charge

the sampling capacitor during the sampling period

1/(2FCLK); however, this is not always possible and the

incomplete settling may degrade the SFDR. The sampling

glitch has been designed to be as linear as possible to

minimize the effects of incomplete settling.

For the best performance it is recomended to have a source

impedence of 100Ω or less for each input. The source

impedence should be matched for the differential inputs.

Poor matching will result in higher even order harmonics,

especially the second.

INPUT DRIVE CIRCUITS

Figure 3 shows the LTC2203/LTC2202 being driven by an RF

transformer with a center-tapped secondary. The secondary

center tap is DC biased with VCM, setting the ADC input

signal at its optimum DC level. Figure 3 shows a 1:1 turns

ratio transformer. Other turns ratios can be used; however,

as the turns ratio increases so does the impedance seen by

the ADC. Source impedance greater than 50Ω can reduce

the input bandwidth and increase high frequency distor-

tion. A disadvantage of using a transformer is the loss of

low frequency response. Most small RF transformers have

poor performance at frequencies below 1MHz.

Figure 3. Single-Ended to Differential Conversion

Using a Transformer. Recommended for Input

Frequencies from 1MHz to 100MHz

LTC2203/

LTC2202

ANALOG

INPUT

T1 = COILCRAFT WBCI-IT OR

MA/COM ETC1-1T.

RESISTORS, CAPACITORS ARE

0402 PACKAGE SIZE, EXCEPT 2.2μF.

22032 F03

0.1μF

2.2μF

12pF

0.1μF

1:1

25Ω

VCM

AIN+

AIN–

Figure 4. Using a Transmission Line Balun Transformer.

Recommended for Input Frequencies from 50MHz to 250MHz

0.1μF

AIN+

AIN–

4.7pF

2.2μF

4.7pF

VCM

ANALOG

INPUT

0.1μF

1:1

T1 = MA/COM ETC1-1-13.

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE,

EXCEPT 2.2F.

22032 F04

25Ω

10Ω

25Ω

LTC2203/

LTC2202

Center-tapped transformers provide a convenient means

of DC biasing the secondary; however, they often show

poor balance at high input frequencies, resulting in large

2nd order harmonics.

Figure 4 shows transformer coupling using a transmis-

sion line balun transformer. This type of transformer has

much better high frequency response and balance than ﬂ ux

coupled center tap transformers. Coupling capacitors are

added at the ground and input primary terminals to allow

the secondary terminals to be biased at 1.25V.

APPLICATIONS INFORMATION

LTC2203/LTC2202

22032fd

Figure 5 demonstrates the use of an LTC1994 differential

ampliﬁ er to convert a single ended input signal into a

differential input signal. The advantage of this method is

that it provides low frequency input response; however,

the limited gain bandwidth of any op amp will limit the

SFDR at high input frequencies.

The internal programmable gain ampliﬁ er provides the

internal reference voltage for the ADC. This ampliﬁ er has

very stringent settling requirements and is not accessible

for external use.

Figure 5. DC Coupled Input with Differential Ampliﬁ er

VCM

22032 F05

–

CM LT1994

499Ω

100pF

2.2 μF

499Ω

523Ω 25Ω

25Ω

499Ω

53.6Ω

AIN+

AIN–

LTC2203/

LTC2202

Figure 6. Reference Circuit

PGA

1.25V

SENSE

VCM BUFFER

INTERNAL

ADC

REFERENCE

RANGE

SELECT

AND GAIN

CONTROL

2.5V

BANDGAP

REFERENCE

2.2μF

TIE TO VDD TO USE

INTERNAL 2.5V

REFERENCE

OR INPUT FOR

EXTERNAL 2.5V

REFERENCE

OR INPUT FOR

EXTERNAL 1.25V

REFERENCE

22032 F07

LTC2203/LTC2202

Figure 7. A 2.25V Range ADC with

an External 2.5V Reference

VCM

SENSE

1.25V

3.3V

2.2μF

1μF

22032 F08

LT1461-2.5

LTC2203/

LTC2202

The SENSE pin can be driven ±5% around the nominal 2.5V

or 1.25V external reference input. This adjustment range

can be used to trim the ADC gain error or other system

gain errors. When selecting the internal reference, the

SENSE pin should be tied to VDD as close to the converter

as possible. If the sense pin is driven externally it should

be bypassed to ground as close to the device as possible

with at least a 1μF ceramic capacitor.

APPLICATIONS INFORMATION

The 25Ω resistors and 12pF capacitor on the analog

inputs serve two purposes: isolating the drive circuitry

from the sample-and-hold charging glitches and limiting

the wideband noise at the converter input.

Reference Operation

Figure 6 shows the LTC2203/LTC2202 reference circuitry

consisting of a 2.5V bandgap reference, a programmable

gain ampliﬁ er and control circuit. The LTC2203/LTC2202

has three modes of reference operation: Internal Refer-

ence, 1.25V external reference or 2.5V external reference.

To use the internal reference, tie the SENSE pin to VDD. To

use the external reference, simply apply either a 1.25V or

2.5V reference voltage to the SENSE input pin. Both 1.25V

and 2.5V applied to SENSE will result in a full scale range

of 2.5VP-P (PGA = 0). A 1.25V output, VCM, is provided

for a common mode bias for input drive circuitry. An

external bypass capacitor is required for the VCM output.

This provides a high frequency low impedance path to

ground for internal and external circuitry. This is also the

compensation capacitor for the reference; it will not be

stable without this capacitor. The minimum value required

for stability is 2.2μF.

LTC2203/LTC2202

22032fd

In applications where jitter is critical, such as when digi-

tizing high input frequencies, use as large an amplitude

as possible. It is also helpful to drive the CLK pin with a

low-jitter high frequency source which has been divided

down to the appropriate sample rate. If the ADC is clocked

with a sinusoidal signal, ﬁ lter the CLK signal to reduce

wideband noise and distortion products generated by

the source.

Maximum and Minimum Conversion Rates

The maximum conversion rate for the LTC2203 is 25Msps.

The maximum conversion rate for the LTC2202 is 10Msps.

For the ADC to operate properly the CLK signal should have

a 50% (±5%) duty cycle. Each half cycle must have at least

18.9ns for the LTC2203 internal circuitry to have enough

settling time for proper operation. For the LTC2202, each

half cycle must be at least 40ns.

An on-chip clock duty cycle stabilizer may be activated if

the input clock does not have a 50% duty cycle. This circuit

uses the falling edge of CLK pin to sample the analog input.

The rising edge of CLK is ignored and an internal rising

edge is generated by a phase-locked loop. The input clock

duty cycle can vary from 30% to 70% and the clock duty

cycle stabilizer will maintain a constant 50% internal duty

cycle. If the clock is turned off for a long period of time,

the duty cycle stabilizer circuit will require one hundred

clock cycles for the PLL to lock onto the input clock. To

use the clock duty cycle stabilizer, the MODE pin must be

connected to 1/3VDD or 2/3VDD using external resistors.

The lower limit of the LTC2203/LTC2202 sample rate is

determined by droop of the sample and hold circuits. The

pipelined architecture of this ADC relies on storing analog

signals on small valued capacitors. Junction leakage will

discharge the capacitors. The speciﬁ ed minimum operating

frequency for the LTC2203/LTC2202 is 1Msps.

Figure 8. Sinusoidal Single-Ended CLK Drive

CLK

0.1μF

4.7μF

FERRITE

BEAD

CLEAN 3.3V

SUPPLY

SINUSOIDAL

CLOCK

INPUT

22032 F09

NC7SVU04

56Ω

LTC2203/

LTC2202

PGA Pin

The PGA pin selects between two gain settings for the ADC

front-end. PGA = 0 selects an input range of 2.5VP-P; PGA =

1 selects an input range of 1.667VP-P. The 2.5V input range

has the best SNR; however, the distortion will be higher for

input frequencies above 100MHz. For applications with high

input frequencies, the low input range will have improved

distortion; however, the SNR will be 2.4dB worse. See the

Typical Performance Characteristics section.

Driving the Clock Input

The CLK input can be driven directly with a CMOS or TTL

level signal. A sinusoidal clock can also be used along with a

low-jitter squaring circuit before the CLK pin (Figure 8).

The noise performance of the LTC2203/2202 can depend

on the clock signal quality as much as on the analog

input. Any noise present on the clock signal will result in

additional aperture jitter that will be RMS summed with

the inherent ADC aperture jitter.

APPLICATIONS INFORMATION

LTC2203/LTC2202

22032fd

Data Format

The LTC2203/LTC2202 parallel digital output can be

selected for offset binary or 2’s complement format. The

format is selected with the MODE pin. This pin has a four

level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD.

An external resistor divider can be user to set the 1/3VDD

and 2/3VDD logic levels. Table 1 shows the logic states

for the MODE pin.

Table 1. MODE Pin Function

MODE OUTPUT FORMAT

CLOCK DUTY

CYCLE STABILIZER

0(GND) Offset Binary Off

1/3VDD Offset Binary On

2/3VDD 2’s Complement On

VDD 2’s Complement Off

Overﬂ ow Bit

An overﬂ ow output bit (OF) indicates when the converter

is over-ranged or under-ranged. A logic high on the OF

pin indicates an overﬂ ow or underﬂ ow.

Output Clock

The ADC has a delayed version of the CLK input available

as a digital output. Both a noninverted version, CLKOUT+

and an inverted version CLKOUT– are provided. The

CLKOUT+/CLKOUT– can be used to synchronize the

converter data to the digital system. This is necesary

when using a sinusoidal clock. Data can be latched on the

rising edge of CLKOUT+ or the falling edge of CLKOUT–.

CLKOUT+ falls and CLKOUT– rises as the data outputs

are updated.

DIGITAL OUTPUTS

Digital Output Buffers

Figure 9 shows an equivalent circuit for a single output

buffer in CMOS Mode. Each buffer is powered by OVDD

and OGND, isolated from the ADC power and ground. The

additional N-channel transistor in the output driver allows

operation down to low voltages. The internal resistor in

series with the output makes the output appear as 50Ω

to external circuitry and eliminates the need for external

damping resistors.

As with all high speed/high resolution converters, the

digital output loading can affect the performance. The

digital outputs of the LTC2203/LTC2202 should drive a

minimum capacitive load to avoid possible interaction

between the digital outputs and sensitive input circuitry.

The output should be buffered with a device such as a

ALVCH16373 CMOS latch. For full speed operation the

capacitive load should be kept under 10pF. A resistor in

series with the output may be used but is not required

since the ADC has a series resistor of 43Ω on chip.

Lower OVDD voltages will also help reduce interference

from the digital outputs.

22032 F10

OVDD

VDD VDD

0.1μF

TYPICAL

DATA

OUTPUT

OGND

43Ω

OVDD 0.5V

TO 3.6V

PREDRIVER

LOGIC

DATA

FROM

LATCH

LTC2203/LTC2202

Figure 9. Equivalent Circuit for a Digital Output Buffer

APPLICATIONS INFORMATION

LTC2203/LTC2202

22032fd

Digital Output Randomizer

Interference from the ADC digital outputs is sometimes

unavoidable. Interference from the digital outputs may be

from capacitive or inductive coupling or coupling through

the ground plane. Even a tiny coupling factor can result in

discernible unwanted tones in the ADC output spectrum.

By randomizing the digital output before it is transmitted

off chip, these unwanted tones can be randomized, trading

a slight increase in the noise ﬂ oor for a large reduction

in unwanted tone amplitude.

•

CLKOUT

D15/D0

D14/D0

D2/D0

D1/D0

D0D0

RAND = HIGH,

SCRAMBLE

ENABLED

D14

D15

CLKOUT

RAND

22032 F11

LTC2203/LTC2202

Figure 10. Functional Equivalent of Digital Output Randomizer

The digital output is “Randomized” by applying an exclu-

sive-OR logic operation between the LSB and all other data

output bits. To decode, the reverse operation is applied;

that is, an exclusive-OR operation is applied between the

LSB and all other bits. The LSB, OF and CLKOUT output

are not affected. The output Randomizer function is active

when the RAND pin is high.

APPLICATIONS INFORMATION

LTC2203/LTC2202

22032fd

Figure 11. Descrambling a Scrambled Digital Output

•

D14

D15

PC BOARD

FPGA

CLKOUT

D15/D0

D14/D0

D2/D0

D1/D0

22032 F12

LTC2203/

LTC2202

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OVDD, should be tied

to the same power supply as for the logic being driven. For

example, if the converter is driving a DSP powered by a

1.8V supply, then OVDD should be tied to that same 1.8V

supply. In CMOS mode OVDD can be powered with any

logic voltage up to 3.6V. OGND can be powered with any

voltage from ground up to 1V and must be less than OVDD.

The logic outputs will swing between OGND and OVDD.

APPLICATIONS INFORMATION

LTC2203/LTC2202

22032fd

Figure 12. Functional Equivalent Block Diagram of

Internal Dither Circuit

S/H

AMP

DIGITAL

SUMMATION OUTPUT

DRIVERS

MULTIBIT DEEP

PSEUDO-RANDOM

NUMBER

GENERATOR

16-BIT

PIPELINED

ADC CORE

PRECISION

DAC

CLOCK/DUTY

CYCLE

CONTROL

CLKOUT+

CLKOUT–

D15

•

CLK

DITHER ENABLE

HIGH = DITHER ON

LOW = DITHER OFF

DITH

ANALOG

AIN+

AIN–

INPUT

22032 F13

LTC2203/LTC2202

Internal Dither

The LTC2203/LTC2202 are 16-bit ADCs with very linear

transfer functions; however, at low input levels even

slight imperfections in the transfer function will result in

unwanted tones. Small errors in the transfer function are

usually a result of ADC element mismatches. An optional

internal dither mode can be enabled to randomize the

input’s location on the ADC transfer curve, resulting in

improved SFDR for low signal levels.

As shown in Figure 12, the output of the sample-and-hold

ampliﬁ er is summed with the output of a dither DAC. The

dither DAC is driven by a long sequence pseudo-random

number generator; the random number fed to the dither

DAC is also subtracted from the ADC result. If the dither

DAC is precisely calibrated to the ADC, very little of the

dither signal will be seen at the output. The dither signal

that does leak through will appear as white noise. The dither

DAC is calibrated to result in less than 0.5dB elevation in

the noise ﬂ oor of the ADC, as compared to the noise ﬂ oor

with dither off.

Grounding and Bypassing

The LTC2203/LTC2202 require a printed circuit board with a

clean unbroken ground plane; a multilayer board with an

internal ground plane is recommended. The pinout of the

LTC2203/LTC2202 has been optimized for a ﬂ owthrough

layout so that the interaction between inputs and digital

outputs is minimized. Layout for the printed circuit board

should ensure that digital and analog signal lines are

separated as much as possible. In particular, care should

be taken not to run any digital track alongside an analog

signal track or underneath the ADC.

High quality ceramic bypass capacitors should be used

at the VDD, VCM, and OVDD pins. Bypass capacitors must

be located as close to the pins as possible. The traces

connecting the pins and bypass capacitors must be kept

short and should be made as wide as possible.

The LTC2203/LTC2202 differential inputs should run

parallel and close to each other. The input traces should

be as short as possible to minimize capacitance and to

minimize noise pickup.

Heat Transfer

Most of the heat generated by the LTC2203/LTC2202 is

transferred from the die through the bottom-side exposed

pad. For good electrical and thermal performance, the

exposed pad must be soldered to a large grounded pad

on the PC board. It is critical that the exposed pad and all

ground pins are connected to a ground plane of sufﬁ cient

area with as many vias as possible.

APPLICATIONS INFORMATION

LTC2203/LTC2202

22032fd

VCC

74VCX245BQX

U1*

EXPOSED PAD

OVP

GND

3201S-40G1

24LC025

NC7SV86P5X

RN1A, 33

RN1B, 33

RN1C, 33

RN1D, 33

RN2A, 33

RN2B, 33

RN2C, 33

RN2D, 33

RN3A, 33

RN3B, 33

RN3C, 33

RN3D, 33

RN4A, 33

RN4B, 33

RN4C, 33

RN4D, 33

VCC

74VCX245BQX

OVP

VCC

SCL

SDA

R17

10K

R18

10K

R19

10K

GND

OE T/R

OVDD

D11

D10

OGND

CLKOUT +

CLKOUT –

OVDD

SENSE

0.1μF

VCM

VDD

GND

AIN +

AIN –

GND

GND/ENC +

GND/ENC –

GND

VDD

GND

PGA

RAND

MODE

D15

D14

D13

D12

OGND

OVDD

VDD

GND

SHDN

DITH

OGND

OVDD

JP6

DITH

VDD

GND

JP6

DITH

VDD

R20

10k

R21

10k

GND C19

0.1μF

C14

0.1μF

GND

C18

0.1μF

C17

0.1μF

2.2μF

C16

0.1μF

C15

0.1μF

C28

0.1μF

C13

0.1μF

OGND

VDD

OVP

LT1763 R25

OUT

ADJ

GND

VDD

+ 3.3V

R29

R30

OPEN

R28

ENCODE

INPUT

GND

BYP

GND

SHDN

C21

0.01μF

C22

1.0μF

C20

10μF

6.3V

C27

100μF

6.3V OPT

C23

4.7μF

R23

100K

R22

105K

VDD

OSC1

OPT.

VDD VDD

R33 *

EN FO

GND

0.1μF

8.2pF

R12

OPEN

R11

OPEN

R24

OPEN

R32

R27

10Ω R8

51Ω

5.1Ω

R10

5.1Ω

OPEN

R26

10Ω

5T1

ANALOG

INPUT

DCIN+

ETC1-1T

C26

0.1μF

C25

0.1μF 22032 F014

OPEN

VDD

JP2

SENSE

JP4

RAND

JP3

PGA

VDD

R31

OVDD

OPEN

10K

OPEN

OVP

GND

GND GND

ASSEMBLY TYPE

* VERSION TABLE

U1 R33 INPUT FREQUENCY BITS MSPS

DC919A-A LTC2207CUK 0.01μF DC < AIN < 70MHz 16 105

DC919A-B LTC2206CUK 0.01μF DC < AIN < 70MHz 16 80

DC919A-C LTC2205CUK 0.01μF DC < AIN < 70MHz 16 65

DC919A-D LTC2204CUK 0.01μF DC < AIN < 70MHz 16 40

DC919A-E LTC2203CUK 0Ω DC < AIN < 70MHz 16 25

DC919A-F LTC2202CUK 0Ω DC < AIN < 70MHz 16 10

OPEN

R13

OPEN

Evaluation Circuit Schematic of the LTC2203/LTC2202

APPLICATIONS INFORMATION

LTC2203/LTC2202

22032fd

Silkscreen Top

Silkscreen Topside

APPLICATIONS INFORMATION

LTC2203/LTC2202

22032fd

Inner Layer 2

Inner Layer 3

APPLICATIONS INFORMATION

LTC2203/LTC2202

22032fd

Silkscreen Bottom Side

Silkscreen Bottom

APPLICATIONS INFORMATION

LTC2203/LTC2202

22032fd

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However,

no responsibility is assumed for its use. Linear Technology Corporation makes no representation that

the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

UK Package

48-Lead Plastic QFN (7mm × 7mm)

(Reference LTC DWG # 05-08-1704)

7.00 ± 0.10

(4 SIDES)

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

PIN 1 TOP MARK

(SEE NOTE 6)

PIN 1

CHAMFER

C = 0.35

0.40 ± 0.10

4847

BOTTOM VIEW—EXPOSED PAD

5.50 REF

(4-SIDES)

0.75 ± 0.05 R = 0.115

TYP

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UK48) QFN 0406 REV C

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

5.50 REF

(4 SIDES) 6.10 ±0.05 7.50 ±0.05

0.25 ±0.05

0.50 BSC

PACKAGE OUTLINE

5.15 ± 0.10

5.15 ± 0.05

R = 0.10

TYP

LTC2203/LTC2202

22032fd

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0909 REV D • PRINTED IN USA

PART NUMBER DESCRIPTION COMMENTS

LTC1748 14-Bit, 80Msps ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package

LTC1750 14-Bit, 80Msps Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR

LT1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain

LT1994 Low Noise, Low Distortion Fully

Differential Input/Output Ampliﬁ er/Driver

Low Distortion: –94dBc at 1MHz

LTC2204 16-Bit, 40Msps, 3.3V ADC 480mW, 79.1dB SNR, 100dB SFDR, 48-Pin QFN

LTC2205 16-Bit, 65Msps, 3.3V ADC 610mW, 79dB SNR, 100dB SFDR, 48-Pin QFN

LTC2206 16-Bit, 80Msps, 3.3V ADC 725mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN

LTC2207 16-Bit, 105Msps, 3.3V ADC 900mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN

LTC2208 16-Bit, 130Msps, 3,3V ADC, LVDS Outputs 1250mW, 77.1dB SNR, 100dB SFDR, 64-Pin QFN

LTC2220-1 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN

LTC2224 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN

LTC2242-12 12-Bit, 250Msps, 2.5V ADC, LVDS Outputs 740mW, 65.4dB SNR, 84dB SFDR, 64-Pin QFN

LTC2255 14-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN

LTC2284 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 540mW, 72.4dB SNR, 88dB SFDR, 64-pin QFN

LT5512 DC-3GHz High Signal Level

Downconverting Mixer

DC to 3GHz, 21dBm IIP3, Integrated LO Buffer

LT5514 Ultralow Distortion IF Ampliﬁ er/ADC Driver

with Digitally Controlled Gain

450MHz to 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step

LT5515 1.5GHz to 2.5GHz Direct Conversion

Quadrature Demodulator

High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator

LT5516 800MHz to 1.5GHz Direct Conversion

Quadrature Demodulator

High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator

LT5517 40MHz to 900MHz Direct Conversion

Quadrature Demodulator

High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator

LT5522 600MHz to 2.7GHz High Linearity

Downconverting Mixer

4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz. NF = 12.5dB, 50Ω Single Ended

RF and LO Ports

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