TEA1713T/N2,518 - NXP SEMICONDUCTORS

1. General description

The TEA1713 integrates a Power Factor Corrector (PFC) controller and a controller for a

Half-Bridge resonant Converter (HBC) in a multi-chip IC. It provides the drive function for

the discrete MOSFET in an up -converter and for the two discrete power MOSFETs in a

resonant half-bridge configuration.

The efficient operation of the PFC is achieved by implementing functions such as

quasi-resonant operation at high power levels and quasi-resona nt operation with valley

skipping at lower power levels. OverCurrent Protection (OCP), OverVoltage Protection

(OVP), and demagnetization sensing ensure safe operation under all conditions.

The HBC module is a is a high-voltage controller for a zero-voltage switching LLC

resonant converter. It contains a high-voltage level shift circuit and several protection

circuits including OCP, open-loop protection, capacitive mode protection and a general

purpose latched protection input.

The high-volta ge chip is fabricated using a prop rietary high-volt age Bipolar-CMOS-D MOS

power logic process that enables efficient direct start-up from the rectified universal mains

voltage. The low-voltage Silicon On Insulator (SOI) chip is used for accurate, high-speed

protection fu nct i on s and co ntrol.

The topology of a PFC circui t and a reso nant converter controlled by the T EA1713 is ve ry

flexible, enabling it to be used in a broad range of applications with a wide mains voltage

range. Combining PFC and HBC controllers in a single IC makes the TEA1713 ideal for

controlling power supplies in LCD and plasma televisions.

Highly efficient and reliable power supplies providing over 100 W can be designed easily

using the TEA1713, with a minimu m of external components.

TEA1713T

Resonant power supply control IC with PFC

Rev. 2 — 9 February 2011 Product data sheet

Product data sheet Rev. 2 — 9 February 2011 2 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

2. Features and benefits

2.1 General features

Integrated PFC and HBC controllers

Universal mains supply operation (70 V to 276 V (AC))

High level of integration resulting in a low external comp on e nt count an d a co st

effective design

Enable input (enable only PFC or both PFC and HBC controllers)

On-chip high-voltage star t-up source

Stand-alone operation or IC supplied from external DC source

2.2 PFC controller features

Boundary mode operation with on-time contr ol

Valley/zero voltage switching for minimum switching losses

Frequency limiting to reduce switching losses

Accurate boost voltage regulation

Burst mode switching with soft start and soft stop

2.3 HBC controller features

Integrated high-voltage level shifter

Adjustable minimum and maximum frequency

Maximum 500 kHz half-bridge switching frequency

Adaptive non-overlap time

Burst mode switching

2.4 Protection features

Safe restart mode for system fault conditions

General latched protection input for output overvoltage protection or external

temperature protection

Protection timer for time-out and restart

Overtemperature protection

Soft (re)start for both controllers

Undervoltage protection for mains (brownout), boost, IC supply and output voltage

Overcurrent regulation and protection for both controllers

Accurate overvoltage pr ot ect ion for boost vo ltage

Capacitive mode protection for HBC controller

3. Applications

LCD television

Plasma television

Adapters

Product data sheet Rev. 2 — 9 February 2011 3 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

4. Ordering information

5. Block diagram

Tabl e 1. Ordering information

Type number Package

Name Description Version

TEA1713T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

Fig 1. Block diagram of TEA1713

High-side driver

LEVEL

SHIFTER

Low-side driver

SUPREG

SWITCH

CONTROL

BOOST

COMPENSATION

ADAPTIVE

NON-OVERLAP

SENSING

CAPACITIVE

MODE

SENSING

BURST

SENSING

PFC / HBC

OVERCURRENT

REGULATION

SENSING

OUTPUT

UNDERVOLTAGE

SENSING

OVERCURRENT

PROTECTION

SENSING

OUTPUT

OVERVOLTAGE

SENSING

SERIES

STABILIZER AND

SUPREG SENSING

SUPPLY

CONTROL

INTERNAL

SUPPLIES

OPEN-LOOP

SENSING

CONTROLLED

OSCILLATOR

FEEDBACK

INPUT

HIGH

FREQUENCY

SENSING

I-V

V-I

SUPHS

SUPREG

SUPIC

SUPHV

SNSMAINS

COMPPFC

GATEPFC

SNSAUXPFC

SNSCURPFC

RCPROT

SNSBOOST

GATEHS

GATELS

PGND

SNSCURHBC

SNSOUT

SNSFB

CFMIN

SGND

SSHBC/EN RFMAX 014aaa850

+1.83 V

+3.5 V

+1 V

−1 V

+2.3 V

+0.5 V

−0.5 V

+0.4 V

+1.0 V

4.1 V

7.7 V

6.4 V

HV START-UP

SOURCE

SUPPLY MODULE

PFC CONTROLLER

HBC CONTROLLER

TEA1713

HV START-UP

SELECTION

MAINS

COMPENSATION

ON-TIMER

OFF-TIME LIMIT

FREQUENCY LIMIT

PFC

CONTROL

PFC driver

SUPREG

Error

amplifier

and clamp

PGND

MAINS RESET,

UNDERVOLTAGE

SENSING

AND CLAMP

+22/17 V

+20 V

+2.5 V

+15 V

BOOST

OVERVOLTAGE

SENSING

BOOST SHORT

SENSING

+0.4 V

+8.0 V

+3.0 V

+2.3 V

+1.6 V

+8.0 V

+5.6 V

+3.2 V

+2.63 V

+10.3 V

+10.9 V

SOFT START

CONTROL

DEMAGNETIZING

SENSING

OVERCURRENT

SENSING

VALLEY

SENSING

BOOST

UNDERVOLTAGE

SENSING

−0.1 V

+0.45 V

PROTECTION

AND RESTART

TIMER

OVER-

TEMPERATURE

SENSING

POLARITY

INVERSION

FREQUENCY

CONTROL

TWO SPEED

SOFT START

SWEEP

AND CLAMP

ENABLE

SENSING

PFC/HBC

+2 V

+1 V

+0.5 V

SOFT START

RESET

+1.15 V

SUPIC

START AND

UNDERVOLTAGE

SENSING

Product data sheet Rev. 2 — 9 February 2011 4 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 2. Pin configuration

TEA1713T

COMPPFC SNSBOOST

SNSMAINS RCPROT

SNSAUXPFC SSHBC/EN

SNSCURPFC SNSFB

SNSOUT RFMAX

SUPIC CFMIN

GATEPFC SGND

PGND SNSCURHBC

SUPREG n.c.

GATELS HB

n.c. SUPHS

SUPHV GATEHS

014aaa826

Table 2. Pin description

Symbol Pin Description

COMPPFC 1 frequency compensation for PFC controller; externally connected to filter

SNSMAINS 2 sense input for mains voltage; externally conn ected to resistive divided

mains voltage

SNSAUXPFC 3 sense input for PFC demagnetization timing; externally connected to

auxiliary winding of PFC

SNSCURPFC 4 sense input for momentary current and soft start of the PFC controller;

externally connected to current sense resistor and soft start filter

SNSOUT 5 sense input for monito ring the output voltage of the HBC; externally

connected to the auxiliary win ding; sense input for burst mode of HBC

controller or PFC and HBC controllers

SUPIC 6 low-voltage supply for SUPIC input; output of internal HV start-up source;

externally connected to auxiliary win ding of HBC or to external DC supply

GATEPFC 7 gate driver output for PFC MOSFET

PGND 8 power ground; reference (ground) for HBC low-side and PFC driver

SUPREG 9 regulated SUPREG IC supply; output from internal regulator; inpu t for

drivers; externally connected to SUPREG buffer capacitor

GATELS 10 gate driver output for low-side MOSFET of HBC

n.c. 11 not connected; high-voltage spacer.

SUPHV 12 high-voltage supply input for internal HV start-up source; externally

connected to boost voltage

GATEHS 13 gate driver output for high-side MOSFET of HBC

SUPHS 14 high-side driver supply input; externally connected to bootstrap capacitor

(CSUPHS)

Product data sheet Rev. 2 — 9 February 2011 5 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

7. Functional description

7.1 Overview of IC modules

The functionality of the TEA1713 can be grouped as follows:

•Supply module:

Supply management for the IC; includes the restart and (latched) shut-down states

•Protection and restart timer:

Externally adjustable timer used for delayed protection and restart timing

•Enable input:

Control input for enabling and disabling the controllers; very low current consumption

when disabled

•PFC controller:

Controls and protects the power factor conver te r; ge n er at es a 40 0 V (DC) boo st

voltage from the rectified AC mains input with a high power factor

•HBC controller:

Controls and protects the resonant converter; generates a regulated (mains isolated)

output voltage from the 400 V (DC) boost voltage

Figure 1 shows the block diagram of the TEA1713. A typical application is illustrated in

Figure 19.

HB 15 reference for high-side driver; input for half-bridge slope detection;

externally connected to half-bridge node HB between HBC MOSFETs (see

Figure 19)

n.c. 16 not connected; high-voltage spacer

SNSCURHBC 17 sense input for momentary HBC current; externally connected to resonant

current sense resistor

SGND 18 signal ground; reference (ground) for IC.

CFMIN 19 minimum frequency setting for HBC; externally connected to capacitor

RFMAX 20 maximum frequency setting for HBC; externally connected to resistor

SNSFB 21 sense input for output voltage regulation feedback; externally connected to

opto-coupler

SSHBC/EN 22 combined soft start timing of HBC and IC enable input; enabling of PFC or

PFC and HBC controllers; externally connected to soft start capacitor and

enable pull-down signal

RCPROT 23 protection timer setting for time-out and restart; externally connected to

resistor and capacitor

SNSBOOST 24 sense input for boost voltage; externally connecte d to resistive divided

boost voltage

Table 2. Pin description …continued

Symbol Pin Description

Product data sheet Rev. 2 — 9 February 2011 6 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

7.2 Power supply

The TEA1713 contains several supply related pins.

7.2.1 Low-voltage supply input (pin SUPIC)

The SUPIC pin is the main low-voltage supply input to the IC. All internal circ uits (other

than the high voltage circu it) are directly o r indirectly (via SUPREG) supplied from this pin.

SUPIC is connected externally to a buffer capacitor CSUPIC. This buffer capacitor can be

charged in several ways:

•from the internal high voltage start-up source

•from the auxiliary winding of the HBC transformer

•from the capacitive supply of the switching half-bridge node

•from an external DC supply, e.g. a standby supply

The IC starts operating when voltage on SUPIC reaches the start level, provided that the

voltage on SUPREG has also reached the start level. The start level depends on the

condition of the SUPHV pin:

•High voltage present on SUPHV, VSUPHV >V

det(SUPHV).

This is the case with a stand-alone application where CSUPIC is initially charged from

the HV start-up source. The start level is Vstart(hvd)(SUPIC) (typ. 22 V). The wide

diff erence between the st art and stop (V uvp(SUPIC)) levels allows energy to be stored in

the SUPIC buff er capacitor which is used to supply the IC until the output voltage has

stabilized.

•Not connected or no voltage present at SUPHV, VSUPHV <V

det(SUPHV).

This is the case when the TEA1713 is supplied fr om an extern al DC source. Th e st art

level is Vstart(nohvd)(SUPIC) (typ. 17 V). The IC is supplied from the DC supply during

start-up . To minimize power dissip ation, the DC supply to pin SUPIC should be above,

but close to, Vuvp(SUPIC) (typ. 15 V).

The IC will stop operating when VSUPIC drops below Vuvp(SUPIC). This is the SUPIC

UnderVoltage Protection (UVP) voltage (UVP-SUPIC; see Section 7.9). The PFC

controller will stop switching immediately, but the HBC controller will continue operating

until the low-side MOSFET becomes active.

The current consumption depends on the state of the IC. The TEA1713 operating states

are described in Section 7.3.

•Disabled IC state

When the IC is disabled via the SSHBC/EN pin, the current consumption is very low

(Idism(SUPIC)).

•SUPIC charge, SUPREG charge, Thermal hold, Restart and Protection shut-down

states

Only a small section of the IC is active while CSUPIC and CSUPREG are charging dur ing

a restart seq uence prior to st art-up or durin g shut-down after a protection function has

been activated. The PFC and HBC controllers are disabled. Current consumption is

limited to Iprotm(SUPIC).

Product data sheet Rev. 2 — 9 February 2011 7 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

•Boost charge state

The PFC controller is switching; the HBC controller is off. The current from the high

voltage start-up source is large enough to supply SUPIC (current consumption <

Ich(nom)(SUPIC)).

•Operational supply state

Both the PFC and HBC controllers are switching. Current consum ption is Ioper(SUPIC).

When the HBC controller is enabled, the switching frequency will be high initially and

the current consumption of the HBC MOSFET drivers will be dominant. The stored

energy in CSUPIC will supply the initial SUPIC current before the SUPIC supply source

takes over.

Pin SUPIC has a low short-circuit detection voltage (Vscp(SUPIC); typ. 0.65 V). The current

dissipated in the HV start-up source is limited while VSUPIC < Vscp(SUPIC) (see

Section 7.2.4).

7.2.2 Regulated supply (pin SUPREG)

The voltage range on pin SUPIC exceeds that of the gate voltages of the external

MOSFETs. For this reason, the TEA1713 contains an integrated series stabilizer. The

series stabilizer creates an accurate regulated voltage (Vreg(SUPREG); typ. 10.9 V) at the

buffer capacitor CSUPREG. This stabilized voltage is used to:

•supply the internal PFC driver

•supply the internal low-side HBC driver

•supply the internal high-side driver via external components

•as a reference voltage for optional external circuits

The SUPREG series stabilizer is enabled after CSUPIC has been fully charged. This

ensures that any optional external circuitry connected to SUPREG will not dissipate any of

the start-up current.

To ensure that the external MOSFETs receive sufficient gate drive current, the voltage on

SUPREG must reach Vstart(SUPREG) (and the voltage on SUPIC must reach the st art level)

before the IC starts operating.

SUPREG is provided with undervoltage protection (UVP-SUPREG; see Section 7.9).

When VSUPREG falls below Vuvp(SUPREG) (typ. 10.3 V), two events will be triggered:

•The IC will stop operating to prevent unreliable switching because the gate driver

voltage is too low. The PFC controller will stop switching immediately, but the HBC

controller will continue until the low-side stroke is active.

•The maximum current from the internal SUPREG series stabilizer is reduced to

Ich(red)(SUPREG) (typ. 5.4 mA). This will reduce the dissipation in the series stabilizer in

the event of an overload at SUPREG while SUPIC is supplied from an external DC

source.

7.2.3 High-side driver floating supply (pin SUPHS)

The high-side driver is supplied by an external bootstrap buffer capacitor, CSUPHS. The

bootstrap capacitor is connecte d be twe e n th e hig h-s id e re fe re nc e pin HB and the

high-side driver supply input pin SUPHS. CSUPHS is charged from pin SUPREG via an

Product data sheet Rev. 2 — 9 February 2011 8 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

external diod e DSUPHS. The voltage drop between SUPREG and SUPHS can be

minimized by carefully selecting the appropriate diode, especially when using large

MOSFETs and high switching frequencies.

7.2.4 High voltage supply input (pin SUPHV)

In a stand-alone power supply application, this pin is connected to the boost voltage.

CSUPIC and CSUPREG will be charged by the HV start-up source (which delivers a constant

current from SUPHV to SUPIC) via this pin.

Short-circuit protection on pin SUPIC (SCP-SUPIC; see Section 7.9) limits the dissipation

in the HV start-up source when SUPIC is shor te d to gr ou nd an d lim its the curr en t on

SUPHV (to Ired(SUPHV)) as long as the volt age on SUPIC is below Vscp(SUPIC).

Under normal operating conditions, the voltage on pin SUPIC will exceed Vscp(SUPIC) very

quickly after start-up and the HV start-up source will switch to the nominal current

Inom(SUPHV).

During start-up and restart, the HV start-up source will charge CSUPIC and regulate the

voltage on SUPIC by hysteretic contr ol. So the st art level has a sma ll degree of hystere sis

Vstart(hys)(SUPIC). The HV start-up source switches-off when VSUPIC exceeds the start level

Vstart(hvd)(SUPIC). Current consumption through pin SUPHV will be low (Itko(SUPHV)).

Once start-up is complete and the HBC controller is operating, SUPIC can be supplied

from the auxiliary winding of the HBC transformer. In this operational state, the HV

start-up source is disabled.

7.3 Flow diagram

The operation of the TEA1713 can be divided into a number of states - see Figure 3. The

abbreviations used in Figure 3 ar e exp l a ine d In Table 8.

Product data sheet Rev. 2 — 9 February 2011 9 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

Fig 3. Flow diagram of the TEA171 3

NO SUPPLY

-All off

UVP supplies = no

UVP supplies = yes

DISABLED lC

-Only "Enable lC" detection active

Enable PFC = yes

THERMAL HOLD

-Minimum functionality active

OTP = no

SUPIC CHARGE

-HV start-up source on

UVP SUPIC = no OTP = yes

STATE NAME

Explanation flow diagram symbols

-action 1

-action 2

-...

Disabled items are not mentioned

exit condition 1

reached

exit condition 2

reached

SUPREG CHARGE

-HV start-up source on

-Series stabilizer on

UVP SUPREG = no OTP = yesUVP SUPIC= yes

BOOST CHARGE

-HV start-up source on

-Series stabilizer on

-PFC on

UVP boost = no &

Enable lC = yes

SCP boost = yes UVP SUPIC = yes OTP = yesUVP SUPREG = yes

OPERATIONAL SUPPLY

-Series stabilizer on

-PFC on

-HBC on

OVP output =yes

Protection timer

passed *1

-HV start-up source on

-Restart timer on

SCP boost = yes UVP SUPREG = yes UVP SUPIC = yes OTP = yes

UVP boost = yes

or Enable IC = no

START

014aaa85

enable PFC = no

exit condition

next state can be entered

from any state when exit

condition is true

PROTECTION SHUTDOWN

Mains reset = yes

RESTART

Restart time passed

*1Protection timer is activated by:

-UVP output

-OLP HBC

-OCR HBC

-HFP

Table 3. Operating states

State Description

No supply Supply voltages on SUPIC and SUPHV are too low to provide any functionality. Undervoltage

protection (UVP-supplies; see Section 7.9) is active when VSUPHV <V

rst(SUPHV) and

VSUPIC <V

rst(SUPIC). The IC is reset.

Disabled IC IC is completely disabled because pin SSHBC/EN is LOW.

Thermal hold Activated as long as OTP is active. IC is not operating. PFC and HBC controllers are di sabled

and CSUPIC and CSUPREG are not charged.

SUPIC charge IC supply capacitor (CSUPIC) is charged by HV start-up source. CSUPREG is not charged.

SUPREG charge Stabilized supply capacitor (CSUPREG) is charged by series regulator.

Product data sheet Rev. 2 — 9 February 2011 10 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

7.4 Enable input (pin SSHBC/E N)

The power supply application can be comple tely disable d by pulling pin SSHBC/EN LOW.

Figure 4 illustrates the internal functionality. When a voltage is present on pin SUPHV or

on pin SUPIC, a current Ipu(EN) (typ. 42 μA) flows out of SSHBC/EN. If the pin is not

pulled-down, this current will lift the voltage up to Vpu(EN) (typ. 3 V). Since this voltage is

above both Ven(PFC)(EN) (typ. 1.2 V) and Ven(IC)(EN) (typ. 2.2 V), the IC will be completely

enabled.

The IC can be completely disabled by pulling the volt age on SSHBC/EN down below both

Ven(PFC)(EN) and Ven(IC)(EN) via an opto-coupler driven from the seco ndary sid e of the HBC

transforme r (se e Figure 4). The PFC controller will stop switching immediately, but the

HBC controller will continue switching until the low-side stroke is active. It is also possible

to control the voltag e on SSHBC/EN from another circuit on the secondary side via a

diode. The external pull-down current must be larger than the internal soft start charge

current Iss(hf)(SSHBC).

If the voltage on SSHBC/EN is pulled down below Ven(IC)(EN), but not below Ven(PFC)(EN),

only the HBC will be disabled. Thi s feature can be useful wh en another power con verter is

connected to the boo st vo ltage of the PFC.

The low-side power switch of the HBC will be on when the HBC is disabled via the

SSHBC/EN pin.

Boost charge Boost voltage is built up by operational PFC.

Operational supply Output voltage is generated. Both PFC and HBC controllers are fully operational.

Restart Activated when a protection function is triggered. Restart timer is activated. During this time,

PFC and HBC controllers are disabled and CSUPREG is not charged. CSUPIC is charged.

Protection shut-down Activated when a pr otection fun ction is triggered. IC is not operational. PFC and HBC controllers

are disabled and CSUPIC and CSUPREG are not charged.

Table 3. Operating states …continued

State Description

Product data sheet Rev. 2 — 9 February 2011 11 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

7.5 IC protection

7.5.1 IC restart and shut-down

In addition to the protection functions that influence the operation of the PFC and HBC

controllers, a nu m be r of pro te ctio n functions are prov ide d that disa ble bot h contr olle r s.

See the protection overvie w in Section 7.9 for det ails on which protections trigge r a restart

or a protection shut-down.

•Restart

When the TEA1713 enters the Restart state, the PFC and HBC controllers are

switched off. After a period defined by the Restart timer, the IC automatically restarts

following the normal start-up cycle.

•Protection shut-down

When the TEA1713 enters the Protection shut-down state, the PFC and HBC

controllers are switched off. The Protection shut-down state is latched, so the IC will

not start up again automatically. It can be restarted by resetting the Protection

shut-down state in one of the following ways:

–by lowering VSUPIC and VSUPHV below their respective reset levels, Vrst(SUPIC) and

Vrst(SUPHV)

–via a fast shut-down reset (see Section 7.5.3).

–via the enable pin (se e Section 7.4)

•Thermal hold

In the Thermal hold st ate, the PFC and HBC controllers are switched of f. The Thermal

hold state remains active until the IC junction temperature drops to about 10 °C below

Totp (see Section 7.5.6).

Fig 4. Circuit configuration around pin SSHBC/EN

Ven(PFC)(EN)

Ven(IC)(EN)

SSHBC/EN

Enable supply

signal (0 to > 2 V)

Disable supply

Css(HBC)

To soft start

circuit

lpu(EN)

Vpu(EN)

Enable detection

EnableIc

EnableIcPfc

014aaa85

TEA1713

Product data sheet Rev. 2 — 9 February 2011 12 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

7.5.2 Protection and restart timer

The TEA1713 contains a programmable timer which can be used for timing several

protection functions. The timer can be used in two ways - as a protection timer and as a

restart timer. The timing of the timers can be set independently via an external resistor

Rprot and capacitor Cprot connected to pin RCPROT.

7.5.2.1 Protection timer

Certain error conditions can be allowed to persist for a period of time before protective

action needs to be taken. Th e protection timer define s the protection p eriod - how long th e

error is allowed to persist before the protection function is trig gered. The protection

functions that use the protection timer can be found in the protection overview in

Section 7.9.

Figure 5 shows the operation of the protection timer. When an er ro r co nd ition occurs, a

fixed current Ich(slow)(RCPROT) (typ. 100 μA) flows out of th e RCPRO T pin an d charge s

Cprot. Rprot will cause the voltage to rise exponentially. The protection time has elapsed

when the volt ag e on RCPROT rea ches the upper switching level Vu(RCPROT) (typ. 4 V). At

this instant, the appropriate protective action is taken and Cprot is discharged.

If the error condition is removed before the volt age on RCPROT reaches Vu(RCPROT), Cprot

is discharged via Rprot and no action is taken.

The volta ge on RCPROT may b e raised above Vu(RCPROT) by an external circuit to for ce a

restart.

7.5.2.2 Rest art timer

Certain error conditions require the IC to be disabled for a period of time, particularly when

the error cond itio n ca n cau se com p on en ts to overhe a t. In such case s, th e IC sho u ld be

disabled to allow the power supply to cool down, before restarting automatically. The

restart time is determined by the restart timer. The restart timer is active in the Restart

state. The protection functions that trigger a restart can be found in the protection

overview in Section 7.9.

Fig 5. Operation of the protection timer

passed

none

present

short

error

long

error

repetative

error

Vu(RCPROT)

Ich(slow)(RCPROT)

IRCPROT

Error

VRCPROT

Protection time

014aaa853

Product data sheet Rev. 2 — 9 February 2011 13 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

Figure 6 shows the operation of the restart timer. Normally Cprot is discharged to 0 V.

When a restart is requested, Cprot is quickly charged to the upper switching level

Vu(RCPROT). Then the RCPROT pin becomes high ohmic and Cprot discharges through

Rprot. The restart time has elapsed when VRCPROT reaches the lower switching level

Vl(RCPROT) (typ. 0.5 V). The IC then restarts and Cprot is discharged.

7.5.3 Fast shut-down reset (pin SNSMAINS)

The latched Protection shut-down state will be reset when VSUPIC and VSUPHV drop below

their respective reset levels, Vrst(SUPIC) and Vrst(SUPHV). Typically, the PFC boost capacitor,

Cboost, will need to discharge before VSUPIC and VSUPHV drop below their reset levels,

which can take a long time.

Fast shut-down reset facilitates a faster reset. When the mains supply is interrupted, the

voltage on pin SNSMAINS will fall. As soon as VSNSMAINS falls below Vrst(SNSMAINS) and

subsequently rises again by a hysteresis value, the IC will leave the Protection shut-down

state. The boost cap acitor Cboost does not need to be discharged to initiate a new st ar t-up.

The Protection shut-down state can also be ended by pulling down the en able input (pin

SSHBC/EN).

7.5.4 Output overvoltage protection (pin SNSOUT)

The TEA1713 outputs are provided with overvoltage protection (OVP-output; see

Section 7.9). The output voltage can be measured via the auxiliary winding of the

resonant transformer. This volt age can be sensed at the SNSOUT pin via an external

rectifier and resistiv e divid e r. An ov er vo ltage is detected when the SNSOUT voltage

exceeds Vovp(SNSOUT) (typ. 3.5 V). Once an overvolt a ge has be en detecte d, the TEA1 713

will go to the Protection shut-down state.

Additional external protection cir cuits, such as an external overtemperature protection

circuit, can be connected to this pin. They should be connected to pin SNSOUT via a

diode so that the error condition will trigger an OVP event.

7.5.5 Output undervoltage protection (pin SNSOUT)

In applications where the TEA1713 is supplied from the auxiliary winding of the HBC

transformer, a SUPIC undervoltage protection event (UVP-SUPIC) will be triggered

automatically when an error condition results in a drop in the output voltage.

Fig 6. Operation of the restart timer

passed

yes

Vu(RCPROT)

Vl(RCPROT)

Restart request

014aaa854

VRCPROT

Restart time

Product data sheet Rev. 2 — 9 February 2011 14 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

In applications where the TEA1713 is supplied from a separate DC source (e.g. a standb y

supply), the TEA1713 will not automatically stop switching if an error condition causes the

output voltage to fall. For this reason, the TEA1713 outputs are provided with

undervolta ge protection (UVP output; see Section 7.9). A UVP output event will restart the

IC if VSNSOUT drops below Vuvp(SNSOUT) (typ. 2.3 V).

During start-up, the output voltage will be below Vuvp(SNSOUT) for a time. This should not

be considered an error condition provided it doesn’t last longer than expected. For this

reason, the protection timer is star ted as soo n as V SNSOUT drops below Vuvp(SNSOUT). The

Restart state is activated if the UVP output event is still active once the protection time has

expired.

7.5.6 OverTemperature Protection (OTP)

Accurate internal overtemperature protection is provided in the TEA1713. When the

junction temperature exceeds the overtemperature protection activation temperature, Totp

(typ. 150 °C), the IC will go to the Thermal hold state. The TEA1713 will exit the Thermal

hold state when the temperature falls again, to around 10 °C below Totp.

7.6 Burst mode operation (pin SNSOUT)

The HBC and PFC controllers can be operated in Burst mode. In Burst mode the

controllers will be on for a period, then off for a period. Burst mode operation increases

efficiency under low-load conditions.

A low-load condition can be detected using a simple external circuit that makes use of the

information from the feedback loop or from the average primary current. The detection

circuit can pull down p in SNSOUT to p ause o peration of the TEA1713 for a burst-off time.

Both controllers, or only the HBC controller, can be paused during the burst-off time:

•Burst-off level for HBC, Vburst(HBC) (typ. 1 V).

When VSNSOUT drops below Vburst(HBC), operation of the HBC controller will be

suspended. Both the high-side and the low-side power switches will be off. The PFC

continues to operate normally. When VSNSOUT rises above Vburst(HBC) again, the HBC

controller will resume normal operation, without executing a soft start sequence.

•Burst-off level for PFC, Vburst(PFC) (typ. 0.4 V).

When VSNSOUT drops below Vburst(PFC), operation of the PFC controller will also be

suspended (the HBC will have been paused already). When VSNSOUT rises above

Vburst(PFC) again, the PFC controller will resume normal operation via a PFC soft start

(see Section 7.7.6).

To ensure Burst mode is not activated before the output voltage becomes valid, a current

from the SNSOUT pin (typ. 100 μA) will hold VSNSOUT at Vpu(SNSOUT), which is above both

burst levels. The resistance between the SNSOUT pin and ground should therefore be

greater than 20 kΩ.

7.7 PFC controller

The PFC controller converts the rectified universal mains voltage into an accurately

regulated boost voltage of 400 V (DC). It operates in quasi-resonant or discontinuous

conduction mode and is controlled via an on-time control system. The resulting mains

harmonic current emissions of a typical application will easily meet the class-D MHR

requirements.

Product data sheet Rev. 2 — 9 February 2011 15 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

The PFC controller uses valley switching to minimize losses. A primary stroke is only

starte d once the previous secondary stroke has ended and the voltage across the PFC

MOSFET has reached a minimum value.

7.7.1 PFC gate driver (pin GATEPFC)

The circuit driving the gate of the power MOSFET has a high current sourcing capability

Isource(GATEPFC) (typ. 500 mA) and a high current sink capability Isink(GATEPFC) (typ. 1.2 A).

This permits fast turn-on and turn-off of the power MOSFET to ensure efficient operation.

The driver is supplied from the regulated SUPREG supply.

7.7.2 PFC on-time control

The PFC operates under on-time control. The on-time of the PFC MOSFET is determined

by:

•The error amplifier a nd the loop compensation via the voltage on pin COMPPFC

At Vton(COMPPFC)zero (typ. 3.5 V), the on-time is reduced to zero. At Vton(COMPPFC)max

the on-time is at a maximum

•Mains compensation via the voltage on pin SNSMAINS

7.7.2.1 PFC error amplifier (pins COMPPFC and SNSBOOST)

The boost volta ge is divided via a high-oh mic resistive divider. It is fed to the SNSBOOST

pin. The transconductance error amplifier, which compares the SNSBOOST voltage with

an accurate trimmed reference voltage Vreg(SNSBOOST), is connected to this pin. The

output current is filtered by the external loop compensation network at th e COMPPFC pin.

In a typical application, the bandwidth of the regulation loop is set by a resistor and two

capacitors.

The COMPPFC volt age is clamped at a maximum of Vclamp(COMPPFC). This avoids a long

recovery time in the event that the boost voltage rises above the regulation level for a

period of time.

7.7.2.2 PFC mains compensation (pin SNSMAINS)

The mathematical equation for the transfer function of a power factor corrector contains

the square of the mains input voltage. In a typical application, this will result in a low

bandwidth for low mains input voltages, while at high mains input voltages the MHR

requirements may be hard to meet.

The TEA1713 contains a correction circuit to compensate for this effect. The average

mains volt age is measured via the SNSMAINS pin and this information is fed to an

internal compensation circuit. Figure 7 illustrates the relationship between the SNSMAINS

voltage, the COMPPFC vo ltage, and the on-time. This compensation makes it is possible

to keep the regulation loop bandwidth constant over the full mains input range, yielding a

fast transient response on load steps, while still complying with class-D MHR

requirements.

Product data sheet Rev. 2 — 9 February 2011 16 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

7.7.3 PFC demagnetization sensing (pin SNSAUXPFC)

The voltage on the SNSAUXPFC pin is used to detect transformer demagnetization.

During the seco ndary stroke, the transformer is magnetized a nd curren t flows in the bo ost

output. During this time, VSNSAUXPFC <V

demag(SNSAUXPFC) (typ. −100 mV) and the PF C

MOSFET is kept off.

After some time, the tran sfor mer beco mes dem agnetized an d curr ent stops flowing in the

boost output. Fro m that momen t , VSNSAUXPFC >V

demag(SNSAUXPFC) and valley detection is

started. The MOSFET remains off.

To ensure switching continues under all circumstances, the MOSFET is forced to

switch on if the magnetizing of the transformer (VSNSAUXPFC <V

demag(SNSAUXPFC)) is not

detected within tto(mag) (typ. 50 μs) after GATEPFC goes LOW.

It is recommended that a 5 kΩ series resistor be connected to this pin to protect the

internal circuitry, against lightning for example. The resistor should be placed close to the

IC on the printed circuit board to prevent incorrect switching due to external disturbances.

7.7.4 PFC valley sensing (pin SNSAUXPFC)

The PFC MOSFET is switched on for the next stroke to reduce switching losses and EMI

if the voltage at the drain of the MOSFET is at its minimum (valley switching),

see Figure 8.

Fig 7. Relationship between on-time, SNSMAINS vo ltage and COMPPFC voltage

on-time

Vton(COMPPFC)max Vton(COMPPFC)zero VCOMPPFC

014aaa85

ton(max)(lowmains)

ton(max)(highmains)

VSNSMAINS = 0.9 V

VSNSMAINS = 3.3 V

Product data sheet Rev. 2 — 9 February 2011 17 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

Valleys are detected by the valley sensing block connected to the SNSAUXPFC pin. This

block measures the voltage at the auxiliary winding of the PFC transformer, which is a

reduced and inverted copy of the MOSFET drain voltage. When a valley of the drain

voltage (= top at SNSAUXPFC voltage) is detected, the MOSFET is switched on.

If no top is detected on the SNSAUXPFC pin (= valley at the drain) within tto(vrec)

(typ. 4 μs) after demagnetization was detected, the MOSFET is forced to switch on.

7.7.5 PFC frequency and off-time limiting

For transformer optimization and to minimize switching losses, the switching frequency is

limited to fmax(PFC). If the frequency for quasi-resonant operation is above fmax(PFC), the

system will switch to Discontinuous conduction mode. The PFC MOSFET is switched on

when the drain-source voltage is at a minimum (valley switching).

The minimum off-time is limited to toff(PFC)min to ensure proper control of the PFC MOSFET

under all circumstances.

7.7.6 PFC soft start and soft stop (pin SNSCURPFC)

The PFC controller features a soft start function which slowly increases the primary peak

current at start-up and a soft stop function which slowly decreases the tran sformer peak

current, before operations are halted. This is to prevent transformer rattle at start-up or

during Burst mode operation.

Fig 8. Demagnetization and va lley detection

demagnetized

VRect/N

VRect

VBoost

(VBoost − VRect)/N

Vdemag(SNSAUXPFC)

magnetized

Demagnetization

lTr(PFC)

Aux(PFC)

Dr(PFC)

GATEPFC

Valley

(= top for detection)

off

014aaa856

Product data sheet Rev. 2 — 9 February 2011 18 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

This is achieved by connecting a resistor Rss(PFC) and a capacitor Css(PFC) between

pin SNSCURPFC and the current sense resistor Rcur(PFC). At start-up, an internal current

source Ich(ss)(PFC) charges the capacitor to VSNSCURPFC =I

ch(ss)(PFC) ×Rss(PFC). The

voltage is limited to the maximum PFC soft start clamp voltage, Vclamp(ss)PFC. The

additional voltage across the charged capacitor results in a reduced peak current. After

start-up, the internal current source is switched-off, capacitor Css(PFC) discharges across

Rss(PFC) and the peak current increases.

The start level and the time constant of the rising primary current can be adjusted

externally by changing the va lues of Rss(PFC) and Css(PFC).

Soft stop is achieved by switching on the internal current source Ich(ss)(PFC).This current

charges Css(PFC) and the increasing capacitor voltage reduces the peak current. The

charge current will flow as long as the voltage on pin SNSCURPFC is below the maximum

PFC soft start voltage (typ. 0.5 V). If VSNSCURPFC exceeds the maximum PFC soft start

voltage, the soft start current source will start limiting the charge current. To accurately

determine if the capacitor is charged, the voltage is only measured during the off-time of

the PFC power switch. The operation of the PFC is stopped when VSNSCURPFC >

Vstop(ss)(PFC).

7.7.7 PFC overcurrent regulation, OCR-PFC (pin SNSCURPFC)

The maximum peak current is limited cycle-by-cycle by sensing the voltage across an

external sens e re sisto r (R cur(PFC)) connecte d to the so ur ce of the external MOSFET. The

voltage is measured via the SNSCURPFC pin and is limited to Vocr(PFC).

A voltage peak will appear on VSNSCURPFC when the PFC MOSFET is switched on due to

the discharging of the drain capacitance. The leading edge blanking time, tleb(PFC),

ensures that the overcurrent sensing block will not react to this transitory peak.

7.7.8 PFC mains undervoltage protection/brownout protection, UVP-mains

(pin SNSMAINS)

The voltage on the SNSMAINS pin is sensed continuously to prevent the PFC trying to

operate at very low mains input voltages. PFC switching stops as soon as VSNSMAINS

drops below Vuvp(SNSMAINS). Mains undervolta ge protection is also called brownout

protection.

VSNSMAINS is clamped to a minimum value of Vpu(SNSMAINS) for fast restart as soon as the

mains input volt age recovers after a mains-dropout. The PFC (re)starts once VSNSMAINS

exceeds the start level Vstart(SNSMAINS).

7.7.9 PFC boost overvoltage protection, OVP-boost (pin SNSBOOST)

An overvoltage protection circuit has been built in to prevent boost overvoltages during

load steps and mains transients.

ICur PFC()pk()

Vocr PFC()

Ich ss()PFC()

Rss PFC()

×()–

Rcur PFC()

---------------------------------------------------------------------------------------------

τRss PFC()

Css PFC()

×=

Product data sheet Rev. 2 — 9 February 2011 19 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

Switching of the power factor correction circuit is inhibited as soon as the voltage on the

SNSBOOST pin rises above Vovp(SNSBOOST). PFC switching resumes as soon as

VSNSBOOST drops below Vovp(SNSBOOST) again.

Overvoltage protection will also be triggered in the event of an open circuit at the resistor

connected between SNSBOOST and ground.

7.7.10 PFC short circuit/open-loop protection, SCP/OLP-PFC (pin SNSBOOST)

The power factor correction circuit will not start switching until the voltage on the

SNSBOOST pin rises above Vscp(SNSBOOST). This acts as short circuit protection for the

boost voltage (SCP-boost).

The SNSBOOST pin draws a small input current Iprot(SNSBOOST). If this pin gets

disconnected, the residual current will pull down VSNSBOOST, triggering short circuit

protection (SCP -b oo st ). Th is co mb ina ti on creates an open-loop protection (OLP-PFC).

7.8 HBC controller

The HBC controller converts the 400 V boost voltage from the PFC into one or more

regulated DC output voltages and drives two external MOSFETS in a half-bridge

configuration connected to a transformer. The transforme r, which has a leakage

inductance and a magnetizing inductance, forms the resonant circuit in combination with

the resonant ca pa citor an d the load at th e out put. The re gulation is realize d via frequency

control.

7.8.1 HBC high-side and low-side driver (pin GATEHS and GATELS)

Both drivers have identical driving capability. The output of each driver is connected to the

equivalent gate of an external high-voltage power MOSFET.

The low-side driver is referenced to pin PGND and is supplied from SUPREG.

The high-side driver is floating . The reference for the high- side driver is pin HB, connected

to the midpoint of the exte rnal half-bridge. The high-side driver is supplied from SUPHS

which is connected to the external b oot strap cap acitor C SUPHS. The boot stra p cap acitor is

charged from SUPREG via external diode DSUPHS when the low-side MOSFET is on.

7.8.2 HBC boost undervoltage protection, UVP-boost (pin SNSBOOST)

The voltage on the SNSBOOST pin is sensed continuously to prevent the HBC controller

trying to operate at very low boost input voltages. Once VSNSBOOST drops below

Vuvp(SNSBOOST), HBC switching stops the next time GATELS goes HIGH. HBC switching

resumes as soon as VSNSBOOST rises above Vstart(SNSBOOST).

7.8.3 HBC switch control

HBC switch control determines when the MOSFETs switch on and off. It uses the output

from several other blocks.

•A divider is used to re alize alternate switching of the hi gh- and low-side MOSFETs for

each oscillator cycle. The oscillator frequency is twice the half-bridge frequency.

•The controlled oscillator determines the switch-off point.

•Adaptive non-overlap time sensing determines the switch-on point. This is the

adaptive non-overlap time function.

Product data sheet Rev. 2 — 9 February 2011 20 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

•Several protection circuit s a nd the state of the SSHBC/EN input determine whether

the resonant converter is allowed to st art switching.

Figure 9 provides an overview of typical switching behavior.

7.8.4 HBC Adaptive Non-Overlap (ANO) time function (pin HB)

7.8.4.1 Inductive mode (normal operation)

The high efficiency characteristic of a resonant converter is the resu lt of Zero-Voltage

Switching (ZVS) of the power MOSFETs, also called soft switching. To facilitate soft

switching, a small non-overlap time is required between the on-times of the high- and

low-side MOSFETs. During this non-overlap time, the primary resonant current

(dis-)charges the capacitance of the half-bridge between groun d an d th e bo os t v oltage.

After th is (dis- )ch arge, the bod y diod e of th e MOSFET starts conducting and b ecau se the

voltage across the MOSFET is zero, there are no switching losses when the MOSFET is

switched on. This mode of operation is called inductive mode because the switching

frequency is above the resonance frequency and the resonant t ank has an inductive

impedance.

The time required fo r the HB transition depends on the amplitud e of the resonant current

at the instant of switching. There is a complex relationship between this amplitu de, the

frequency, the boost voltage and the outp ut voltage. Ideally the IC sho u ld switc h th e

MOSFET on as soon as the HB transition has been completed. If it waits any longer, the

HP voltage may swing back, especially at high output loads. The advanced adaptive

non-overlap time function takes care of this timing, so that it’s not necessary to chose a

fixed dead time (which is always a compromise). This saves on external components.

Adaptive non-overlap time sensing measures the HB slope after one MOSFET has been

switched off. Normally, the HB slope starts immediately (the voltage start s rising or falling).

Once the transition at the HB node is comple te, the slope ends (the voltage stops

rising/falling). This is detected by the ANO time sensor and the other MOSFET is switched

Fig 9. Swi t ching behavior of the HBC

GATELS

GATEHS

Tr(HBC)

CFMIN

Boost

014aaa857

Product data sheet Rev. 2 — 9 February 2011 21 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

on. In this way the non-overlap time is optimized automatically, minimizing switching

losses, even if the HB transition cannot be fully completed. Figure 10 illustrates the

operation of the adaptive non-overlap time function in Inductive mode.

The non-overlap time depends on the HB slope, but has upper and lower limits.

An integrated minimum non-overlap time, tno(min), prevents cross conduction occurring

under any circumstances.

The maximum non-overlap time is limited to the oscillator charge time. If the HB slope

lasts longer than the oscillator charge time (= 1⁄4 of HB switching period) the MOSFET is

forced to switch on. In this case the MOSFET is not soft switching. This limitation ensures

that, at very high switching frequencies, the MOSFET on-time is at least 1⁄4 of the HB

switching period.

7.8.4.2 Capacitive mode

The description above holds for normal operation with a switching frequency above the

resonance frequency. When an error condition occurs (e.g. output short, load pulse too

high) the switching frequency can be lower than the resonance frequency. The resonant

tank then has a capacitive impedance. In Capacitive mode, the HB slope does not start

afte r the MOSFET has switched off. Switching on the other MOSFET is not recommended

in this situation. The ab se nc e of so ft switching increases dissipation in the MOSFETs. In

Capacitive mode, the body di od e in the switched-off MOSFET may start conducting.

Switching on the other MOSFET at this instant can result in the immediate destruction of

the MOSFETs.

The advanced adaptive non-overlap time of the TEA1713 will always wait until the slope

at the half-bridge node starts. It guarantees safe switching of the MOSFETs in all

circumstances. Figure 11 illustrates the operation of the adaptive non-overlap time

function in Capacitive mode.

In Capacitive mode, half the re so na nc e pe ri od may elapse before the resonant current

changes back to the correct polarity and starts charging the half-bridge node. The

oscillator is slowed down until the half-bridge slope starts to allow this relatively long

waiting time. See Section 7.8.5 for more details on the oscillator.

Fig 10. Adaptive non-overlap time function (normal inductive operation)

fast HB slope

Boost

GATELS

GATEHS

0slow HB slope incomplete HB slope t

014aaa858

Product data sheet Rev. 2 — 9 February 2011 22 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

The MOSFET will be forced to switch on if the half-bridge slope fails to start and the

oscillator voltage reaches Vu(CFMIN).

The switching frequen cy is increased to eliminate the problems associated with

Capacitive mode operation. This is explained in Section 7.8.11.

7.8.5 HBC slope controlled oscillator (pins CFMIN and RFMAX)

The slope-controlled oscillator determines the switching frequency of the half-bridge. The

oscillator generates a triangular waveform between Vu(CFMIN) and Vl(CFMIN) at the external

capacitor Cfmin.

Figure 12 shows how the frequency is determined.

Fig 11. Adaptive non-overlap time function (capacitive operation)

014aaa93

delayed

oscillator

delayed switch-on

during capacitive mode

no HB slope

wrong polarity

GATEHS

GATELS

VBoost

ITr(HBC)

CFMIN

Product data sheet Rev. 2 — 9 February 2011 23 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

Two external com p on e nts deter min e th e fre q ue n cy ra ng e:

•Capacitor Cfmin connected between pin CFMIN and ground sets the minimum

frequency in combination with an internally trimmed current source Iosc(min).

•Resistor Rfmax connected between pin RFMAX and ground set s the frequency rang e

and thus the maximum frequency.

The oscillator frequency depends on the charge and discharge currents of Cfmin. The

(dis-)charge current contains a fixed component, Iosc(min), that determines the minimum

frequency, and a variable component that is 4.9 times greater than the current in pin

RFMAX. IRFMAX is determined by the value of Rfmax and the voltage on pin RFMAX:

•The voltage on pin RFMAX is Vfmin(RFMAX) (typ. 0 V) at the minimum frequency.

•The voltage on pin RFMAX is Vfmax(fb)(RFMAX) (typ. 1.5 V) at the maximum feedback

frequency.

•The voltage on pin RFMAX is Vfmax(ss)(RFMAX) (typ. 2.5 V) at the maximu m so ft start

frequency.

The maximum frequency of the oscillator is limited internally. The HB frequency is limited

to flimit(HB) (min. 500 kHz). Figure 13 illustrates the relationship between VRFMAX, Rfmax,

Cfmin and fHB.

Fig 12. Determination of frequency

VOLTAGE PIN SSHBC

POLARITY INVERSION

(max 2.5 V)

VOLTAGE PIN RFMAX

CONVERSION TO CURRENT

via Rfmax

FEEDBACK CURRENT

PIN SNSFB

FIXED fmin CURRENT

CONVERSION TO

VOLTAGE (max 1.5 V)

(DIS-)CHARGE CURRENT

PIN CFMIN

CONVERSION TO

FRQUENCY via Cfmin 014aaa860

Product data sheet Rev. 2 — 9 February 2011 24 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

The oscillator is controlled by the slope of the half-bridge. The oscillator charge current is

initially set to a low value Iosc(red) (typ. 30 μA). When the start of the half-bridge slope is

detected, the charge current is increased to its normal value. This feature is used in

combination with the adaptive non-overlap time function as described in Section 7.8.4.2

and Figure 11. Since the half-bridge slope normally starts directly after the MOSFET is

switched off, the length of time the oscillator current is low will be negligible under normal

operating cond itio ns .

7.8.6 HBC feedback input (pin SNSFB)

In a typical power supply application, the out put volt ag e is comp ared an d amplified on th e

secondary side. The output of the error amplifier is transferred to the primary side via an

opto-coupler. This opto-coupler can be connected directly to the SNSFB pin.

The SNSFB pin supplies the opto-coupler from an internal voltage source Vpu(SNSFB)

(typ. 8.4 V) with a series resistance RO(SNSFB). The series resistance allows spike filter ing

via an external capacitor. To ensure sufficient bias current for the opto-coupler, the

feedback input has a threshold current Ifmin(SNSFB) (typ. 0.66 mA) at which the frequency is

at a minimum. The maximum frequen cy is reached at Ifmax(SNSFB) (typ 2.2 mA). The

maximum frequency that can be reached via the SNSFB pin is lower (typ. 60 %) than the

maximum frequency that can be reached via the SSHBC/EN pin. Figure 14 shows the

relationship between ISNSFB, VSNSFB and VRFMAX.

A: Cfmin =high, R

fmax =high

B: Cfmin =low, R

fmax =low

C: Cfmin = low, Rfmax = too low

Fig 13. Function of Rfmax and Cfmin

flimit(HB)

fmax(B)

Vfmax(fb)(RFMAX) Vfmax(ss)(RFMAX)

VRFMAX

fmax(A)

fmin(B and C)

fmin(A)

fHB

014aaa86

Product data sheet Rev. 2 — 9 February 2011 25 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

Below the level for minimum frequency, VSNSFB is clamped at Vclamp(SNSFB) (typ. 3.2 V).

This clamp enables a fast recovery of the output voltage regulation loop after an

overshoot of the output voltage. The maximum current the clamp can deliver is

Iclamp(SNSFB) (typ. 7.3 mA).

7.8.7 HBC open-loop protection, OLP-HBC (pin SNSFB)

Under normal operating conditions, the opto-coupler current will be between Ifmin(SNSFB)

and Ifmax(SNSFB) and will pull down the voltage at pin SNSFB. Due to an error in the

feedback loop, the current could be less than Ifmin(SNSFB) with the HBC controller

delivering maximum output power.

The HBC controller features open-lo op protection (OLP-HBC), which monitors the voltage

on pin SNSFB. When VSNSFB exceeds Volp(SNSFB), the protection timer is started. The

Restart state is activated if the OLP condition is still present after the protection time has

elapsed.

7.8.8 HBC soft start (pin SSHBC/EN)

The relationship between switching frequency and output current is not constant. It

depends stro ng ly on the out put v oltage and th e bo os t v oltage. This re lat i on sh ip ca n be

complex. The TEA1713 cont ains a soft st art function to ensure that the r esonant converter

starts or restarts with safe currents. This soft start function forces a start at such a high

frequency that currents will be acceptable under all conditions. Soft start then slowly

decreases the frequency. Normally, output voltage regulation will have taken over

frequency control before sof t st art has reached it s minimum freque ncy. Limiting the output

current during start-up also limits the rate at which the output voltage rises and prevents

an overshoot.

Soft start utilizes the voltage on pin SSHBC/EN. The timing of the soft start is set by

external capacitor Css(HBC). Pin SSHBC/EN is also used as an enable input. Soft start

voltage levels are above the enable voltage thresholds.

7.8.8.1 Soft start voltage levels

The relationship between the soft start voltage at pin SSHBC/EN and the voltage at pin

RFMAX, which is directly related to the frequency, is illustrated in Figure 15.

Fig 14. Transfer function of feedb ack input

VSNSFB

ISNSFB

Vpu(SNSFB)

Ifmin(SNSFB)

VRFMAX

Ifmax(SNSFB)

VSSHBC = 8.4 V

Iolp(SNSFB)

Volp(SNSFB)

Vfmin(SNSFB)

Vfmax(SNSFB)

Vclamp(SNSFB)

VSNSFB

Iclamp(SNSFB)

014aaa862

Vfmax(ss)(RFMAX)

Vfmax(fb)(RFMAX)

Product data sheet Rev. 2 — 9 February 2011 26 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

VRFMAX and VSSHBC/EN are of opposite polarity. At initial start- up, VSSHBC/EN is below

Vfmax(SSHBC) (typ. 3.2 V), which correspo nd s to th e ma xim u m fr eq ue n c y. During start-up,

Css(HBC) is charged, VSSHBC/EN rises and the frequency decreases. The co ntribution of the

soft st art function is zero when VSSHBC/EN is above Vfmin(SSHBC) (typ. 7.9 V).

VSSHBC/EN is clamped at a maximum of Vclamp(SSHBC) (typ. 8.4 V) (frequency is at a

minimum) and at a minimum ( ≈3 V ). Below Vfmax(SSHBC) (maximum frequency), the

discharge cu rrent is reduced to a maximum-frequency soft start current of typically 5 μA

The voltage is clamped at a minimum of Vpu(EN) (typ. 3 V). Both clamp levels are just

outside the operating area of Vfmax(SSHBC) to Vfmin(SSHBC). The margins avoid frequency

disturbance during normal output voltage regulation, but ensure that overcurrent

regulation can respond quickly.

7.8.8.2 Soft start charge and discharge

At initial start-up, the soft start capacitor Css(HBC) is charged to obtain a decreasing

frequency sweep from maxi mum to operating frequency. As well as being used to softly

start up the resonant converter, the soft start functionality is also used for regulation

purposes (such as overcurrent regulation). Css(HBC) can therefore be charged or

discharged. In the case of overcurrent regulation, a continuous alternation between

charging and discharging takes place. In this way VSSHBC/EN can be regulated, thereby

overruling the signal from the feedback input.

The (dis-)charge cur rent can have a high value, Iss(hf)(SSHBC) (typ. 160 μA), resulting in a

fast (dis-)charge, or it can have a low value Iss(lf)(SSHBC) (typ. 40 μA), resulting in a slow

(dis-)charge. This two-speed soft start sweep allows for a combination of a short start-up

time for the resonant converter and stable regulation loops (such as overcurrent

regulation).

The fast (dis-)charge speed is used for the upper frequency range where VSSHBC/EN is

below Vss(hf-lf)(SSHBC) (typ. 5.6 V). In the upper frequency range, the currents in the

converter do not react strongly to frequency variations.

Fig 15. Relation between SSHBC/EN voltage and frequency

fHB

VSSHBC

Vfmax,ss(RFMAX)

VRFMAX

fmin

fmax

Vfmax(SSHBC)

Vfmin(SSHBC)

Vclamp(SSHBC)

Vpu(EN)

ISNSFB < Ifmin(SNSFB)

Ifmin(SNSFB) < ISNSFB < Ifmax(SNSFB)

VRFMAX

fHB

Vfmax,fb(RFMAX)

014aaa863

Product data sheet Rev. 2 — 9 February 2011 27 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

The slow (dis-)charge speed is used for the lower frequency range where VSSHBC/EN is

above Vss(hf-lf)(SSHBC) (typ. 5.6 V). In the lower frequency range, the currents in the

converter react strongly to frequency variations.

Section 7.8.10.2 describes how the two-speed soft start function is used for overcurrent

regulation.

The soft start capacitor is neither charged nor discharged during non-operation time in

Burst mode. The soft start voltage will not change during this time.

7.8.8.3 Soft start reset

Some protection functions, such as overcurrent protection, require fast correction of the

operating frequency set point, but do not require switching to stop. See the protection

overview in Section 7.9 for detai ls on which protection functions use this step to the

maximum frequency. The TEA1713 has a special fast soft start reset feature for the HBC

controller that forces Vfmax(ss)(RFMAX) on pin RFMAX. Soft sta rt reset is also used when the

HBC controller is enabled via the SSHBC/EN pin or af ter a rest art to ensure a safe star t at

maximum frequency. Soft sta rt reset is not used wh en the operation was sto pped in Bur st

mode.

When a protection function is activated, the oscillator control input is disconnected from

the soft start capacitor, Css(HBC), connected between pin SSHBC/EN and ground and the

switching frequency is immediately set to a maximum. Setting the switching frequency to

a maximum will restore safe switching operation in most cases. At the same time, the

capacitor is discharged to the maximum frequency level, Vfmax(SSHBC). Once VSSHBC/EN

has reached this level, the oscillator control input is connected to the pin again and the

normal soft start sweep follows. Figure 16 shows the soft start reset and the two-speed

frequency sweep downwards.

Fig 16. Soft start reset and two-speed soft start

Protection

Vfmax(SSHBC)

VSSHBC/EN

Vfmin(SSHBC)

fmin

fHB

fmax

off

fmax

forced

fast

sweep

slow sweep regulationregulation

Vss(hf-lf)(SSHBC)

014aaa864

Product data sheet Rev. 2 — 9 February 2011 28 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

7.8.9 HBC high-frequency protection, HFP-HBC (pin RFMAX)

Normally the converter will not operate continuously at maximum frequency because it will

sweep down to much lower values. Certain error conditions, such as a disconnected

transformer, could cause the converter to operate continuously at maximum frequency. If

zero-voltage switching conditions are no longer present, the MOSFETs can overheat. The

TEA1713 features High-Frequency Protection (HFP) for the HBC controller to protect it

from being damaged in such circumstances.

HFP senses the voltage at pin RFMAX. This voltage indicates the current frequency.

When the frequency is higher than 75 % of the soft start frequency range, the protection

timer is star ted. The 75 % level corresponds to an RFMAX voltage of Vhfp(RFMAX)

(typ. 1.83 V).

7.8.10 HBC overcurrent regulation and protection, OCR and OCP

(pin SNSCURHBC)

The HBC controller is protected against overcurrent in two ways:

•Overcurrent regulation (OCR-HBC) which increases the frequency slowly; the

protection timer is also started.

•Overcurrent protection (OCP-HBC) which steps to maximum frequency.

A boost voltag e compensation function is included to reduce the variation in the output

current prot ect ion leve l.

7.8.10.1 Boost voltage compensation

The primary current, also known as the resonant current, is sensed via pin SNSCURHBC.

It senses the mom en tary voltage acro ss an ex ter na l curre nt se ns e re sisto r R cur(HBC). The

use of the momentary current signal allows for fast overcurrent protection and simplifies

the stabilizing of overcurrent regulation. The OCR and OCP comparators compare

VSNSCURHBC with the maximum po sitiv e an d ne g at ive va lue s.

For the same outp ut powe r, the primary current is higher wh en the b oo st voltage is low. A

boost compensati on is in cluded to redu ce the depend ency of the prot ected output curr ent

level on the boost voltage. The boost compensation sources and sinks a current from the

SNSCURHBC pin. This current creates a voltage drop across the series resistor Rcurcmp.

The amplitude of the current depends linearly on the boost voltage. At nominal boost

voltage the current is zero and the voltage VCur(HBC) across the current sense resistor is

also present at the SNSCURHBC pin. At the UVP-boost start level Vuvp(SNSBOOST), the

current is at a maximum. The direction of the current, sink or source, depends on the

active gate signal. The voltage drop created across Rcurcmp reduces the amplitude at the

pin, resulting in a higher ef fective cur rent protection level. The amount of compensa tion is

set by the value of Rcurcmp. Figure 17 shows how the boost compensation works for an

artificial current signal. The sinking compensation current only flows when VSNSCURHBC is

positive because of the circuit implementation.

Product data sheet Rev. 2 — 9 February 2011 29 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

7.8.10.2 Overcurrent regulation, OCR-HBC

The lowest comparator levels at the SNSCURHBC pin, Vocr(HBC) (typ. −0.5 V and +0.5 V),

relate to the overcurrent regulation voltage. There are comparators for both the positive

and negative polarities. The positive comp arator is active during the high-side on-time an d

the following high-side to low-side non-overlap time. The negative comparator is active

during the remaining time. If either level is exceeded, the frequency will be slowly

increased. This is accomplished by dischargin g the soft start capacitor. Each time the

OCR level is exceeded, the event is latched until the next stroke and the soft start

discharge current is enabled. When both the positive and negative OCR levels are

exceeded, the soft start discharge current will flow continuously.

Overcurrent regulation is very effective at limiting the output current during start-up. A

smaller soft start capacitor can be used to achieve a faster start-up. Using a smaller

capacitor may result in an output current that is too high at times, but the OCR function will

slow down the frequency sweep when needed to keep the output current within the

specified limits. Figure 18 shows the operation of the OCR during output voltage start-up.

Fig 17. Boost volt age compensation

VCur(HBC) = Rcur(HBC) × ICur(HBC)

Iocr(high)

Iocp(high)

Iocp(nom)

Iocr(nom)

−Iocr(nom)

−Iocp(nom)

−Iocr(high)

−Iocp(high)

ICur(HBC)

ISNSCURHBC

Vreg

Vuvp

VBoost

GATELS

GATEHS

sink current only with positive VSNSCURHBC

sink

source

low VBoost

strong compensation

high OCP

low VBoost

strong compensation

high OCR

nominal VBoost

no compensation

nominal OCP

nominal VBoost

no compensation

nominal OCR

VSNSCURHBC

014aaa865

VSNSCURHBC

Vocr(HBC)

−Vocr(HBC)

Vocp(HBC)

−Vocp(HBC)

Product data sheet Rev. 2 — 9 February 2011 30 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

The protection timer is also started. The Restart state is activated when the OCR-HBC

condition is still present after the protection time has elapsed.

7.8.10.3 Overcurrent protection, OCP-HBC

Under normal operating conditions, OCR is able to ensure the current remains below the

specified maxim u m va lu e s. In the ev en t of ce rtain erro r co nd itio ns , how ev er, it might not

be fast enough to li mit the current. OCP is implemented to protect against those error

conditions. The OCP level, Vocp(HBC) (typ. −1 V and +1 V), is higher than the OCR level

Vocr(HBC).

When the OCP level is reached, the frequency immediately jumps to the maximum value

via the soft start reset, followed by a normal sweep down.

7.8.11 HBC capacitive mode regulation, CMR (pin HB)

The MOSFETs in the half-bridge drive the resonant circ uit. Depending on the output load,

the output volt age, and the switching frequency this r esonant circuit can have an inductive

impedance or a capacitive impedance. Inductive impedance is preferred because it

facilitates efficient zero-voltage switching.

Harmful switching in Capacitive mode is prevented by the adaptive non-overlap time

function (see Section 7.8.4.2). An extra action is performed which results in Capacitive

Mode Regulation (CMR). CMR causes the half-bridge circuit to return to Inductive mode

from Capacitive mode.

Fig 18. Overcurrent regulation during start-up

Iocr

−Iocr

ICur(HBC)

Iss(hf)(SSHBC)

Iss(If)(SSHBC)

−Iss(If)(SSHBC)

−Iss(hf)(SSHBC)

ISSHBC/EN

VSSHBC/EN

Vfmin(SSHBC)

Vss(hf-lf)(SSHBC)

Vfmax(SSHBC)

VOutput

Vreg

0 t

Fast soft-start sweep (charge and discharge) Slow soft-start sweep (charge and discharge)

014aaa866

Product data sheet Rev. 2 — 9 February 2011 31 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

Capacitive mode is detected when the HB slope does not start within tto(cmr) after the

MOSFETs have switched off. Detection of Capacitive mode will increase the switching

frequency. This is realized by discharging the soft start capacitor with a relatively high

current Icmr(hf)(SSHBC) from the instant tto(cmr) has expired until the half-bridge slope has

started. The frequency increase regulates the HBC to the border between capacitive and

inductive mode.

7.9 Protection overview

Table 4. Overview protections

Protected

Part Symbol Protection Affected Action Description

IC UVP-SUPIC Undervoltage protection SUPIC IC disable Section 7.2.1

IC UVP-SUPREG Undervoltage protection SUPREG IC disable Section 7.2.2

IC UVP-supplies Undervoltage protection supplies IC disable and reset Section 7.3

IC SCP-SUPIC Short circuit protection SUPIC IC low HV start-up current Section 7.2.4

IC OVP-output Overvoltage protection outpu t IC shut-down Section 7.5.4

IC UVP-output Undervoltage protection output IC restart after protection time Section 7.5.5

IC OTP Overtemperature protection IC disable Section 7.5.6

PFC OCR-PFC Overcurrent regulation PFC PFC switch off cycle-by-cycle Section 7.7.7

PFC UVP-mains Undervoltage protection mains PFC suspend switching Section 7.7.8

PFC OVP-boost Overvoltage protection boost PFC suspend switching Section 7.7.9

PFC SCP-boost Short circuit protection boost IC restart Section 7.7.10

PFC OLP-PFC Open-loop protection PFC IC restart Section 7.7.10

HBC UVP-boost Undervoltage protection boost HBC disable Section 7.8.2

HBC OLP-HBC Open-loop protection HBC IC restart after protection time Section 7.8.7

HBC HFP-HBC High-frequency protection HB C IC restart after protection time Section 7.8.9

HBC OCR-HBC Overcurrent regulation HBC HBC

IC increase frequency

restart after protection time Section 7.8.10.2

HBC OCP-HBC Overcurrent protection HBC HBC step to maximum

frequency Section 7.8.10.3

HBC CMR Capacitive mode regulation HBC increase frequency Section 7.8.11

HBC ANO Adaptive non-overlap HBC prevent hazardous

switching Section 7.8.4

Product data sheet Rev. 2 — 9 February 2011 32 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).; All voltages are measured with respect to pin SGND;

Currents are positive when flowing into the IC; The voltage ratings are valid provided other ratings are not violated; Current

ratings are valid provided the maximum power rating is not violated.

Symbol Parameter Conditions Min Max Unit

Voltages

VSUPHV voltage on pin SUPHV continuous −0.4 +630 V

VSUPHS voltage on pin SUPHS DC −0.4 +570 V

t<0.5s −0.4 +630 V

referenced to pin HB −0.4 +14 V

VSUPIC voltage on pin SUPIC −0.4 +38 V

VSNSAUXPFC voltage on pin SNSAUXPFC −25 +25 V

VSUPREG voltage on pin SUPREG −0.4 +12 V

VSNSOUT voltage on pin SNSOUT −0.4 +12 V

VRCPROT voltage on pin RCPROT −0.4 +12 V

VSNSFB voltage on pin SNSFB −0.4 +12 V

VSSHBC/EN voltage on pin SSHBC/EN −0.4 +12 V

VGATEHS voltage on pin GATEHS t < 10 µs for I > 10 mA −0.4 VSUPHS +0.4 V

VGATELS voltage on pin GATELS t < 10 µs for I > 10 mA −0.4 VSUPREG +0.4 V

VGATEPFC voltage on pin GATEPFC t < 10 µs for I > 10 mA −0.4 VSUPREG +0.4 V

VSNSCURHBC voltage on pin SNSCURHBC −5+5 V

VSNSBOOST voltage on pin SNSBOOST −0.4 +5 V

VSNSMAINS voltage on pin SNSMAINS −0.4 +5 V

VSNSCURPFC voltage on pin SNSCURPFC current limited −0.4 +5 V

VCOMPPFC voltage on pin COMPPFC −0.4 +5 V

VCFMIN voltage on pin CFMIN −0.4 +5 V

VPGND voltage on pin PGND −1+1 V

Currents

IGATEPFC current into pin GATEPFC duty cycle < 10 % −0.8 +2 A

ISNSCURPFC current into pin SNSCURPFC −1+10 mA

General

Ptot total power dissipation Tamb < 75 °C-0.8W

Tstg storage temperature −55 +150 °C

Tjjunction temperature −40 +150 °C

Product data sheet Rev. 2 — 9 February 2011 33 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

[1] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

[2] Equivalent to discharging a 200 pF capacitor through a 0.75 μH coil and a 10 Ω resistor.

9. Thermal characteristics

10. Characteristics

ESD

VESD Electrostatic discharge voltage Human body model

Pin 12 (SUPHV) [1] - 1500 V

Pin 13,14,15 (HS driver) [1] - 1000 V

other pins [1] - 2000 V

Machine model

All pins [2] - 200 V

Charged device model

All pins - 500 V

Table 5. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).; All voltages are measured with respect to pin SGND;

Currents are positive when flowing into the IC; The voltage ratings are valid provided other ratings are not violated; Current

ratings are valid provided the maximum power rating is not violated.

Symbol Parameter Conditions Min Max Unit

Table 6. Thermal characteristics

Symbol Parameter Conditions Typ Unit

Rth(j-a) thermal resistance from junction to ambient In free air; JEDEC single

layer test board 90 K/W

Table 7. Characteristics

Tamb =25

C; VSUPIC =20V; V

SUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when

flowing into the IC; unless otherwise specifi ed.

Symbol Parameter Conditions Min Typ Max Unit

High-voltage star t-up source (pin SUPHV)

Idism(SUPHV) disable mode current on pin

SUPHV Disabled IC state - 150 - μA

Ired(SUPHV) reduced current on pin SUPHV VSUPIC <V

scp(SUPIC) -1.1-mA

Inom(SUPHV) nominal current on pin SUPHV VSUPIC <V

start(hvd)(SUPIC) -5.1-mA

Itko(SUPHV) takeover current on pin SUPHV VSUPIC >V

start(hvd)(SUPIC) -7-μA

Vdet(SUPHV) detection voltage on pin SUPHV - - 25 V

Vrst(SUPHV) reset voltage on pin SUPHV VSUPIC <V

rst(SUPIC) -7-V

Low-voltage IC supply (pin SUPIC)

Vstart(hvd)(SUPIC) start voltage with high voltage

detected VSUPHV >V

det(SUPHV) 21.0 22.0 23.0 V

Vstart(nohvd)(SUPIC) start voltage with no high voltage

detected VSUPHV <V

det(SUPHV) or open 16.1 17.0 17.9 V

Vstart(hys)(SUPIC) hysteresis of start voltage on pin

SUPIC -0.3-V

Product data sheet Rev. 2 — 9 February 2011 34 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

Vuvp(SUPIC) undervoltage protection voltage on

pin SUPIC 14.2 15.0 15.8 V

Vrst(SUPIC) reset voltage on pin SUPIC VSUPHV <V

rst(SUPHV) -7-V

Vscp(SUPIC) short-circuit protection voltage on

pin SUPIC 0.55 0.65 0.75 V

Ich(red)(SUPIC) reduced charge current on pin

SUPIC VSUPIC <V

scp(SUPIC) -−0.95 - mA

Ich(nom)(SUPIC) nominal charge current on pin

SUPIC -−4.8 - mA

Idism(SUPIC) current on pin SUPIC in disabled

mode Disabled IC state - 0.25 - mA

Iprotm(SUPIC) current on pin SUPIC in protection

mode SUPIC charge, SUPREG

charge; Restart or

Shut-down state

-0.4-mA

Ioper(SUPIC) current on pin SUPIC in operating

mode Operational supply state;

Driver pins open. -3-mA

Regulated supply (pin SUPREG)

Vreg(SUPREG) regulation voltage on pin SUPREG ISUPREG =−40 mA [1] 10.6 10.9 11.2 V

Vstart(SUPREG) st art voltage on pin SUPREG [1] - 10.7 - V

Vuvp(SUPREG) undervoltage protection voltage on

pin SUPREG [1] - 10.3 - V

Ich(SUPREG)max maximum charge current on pin

SUPREG VSUPREG > Vuvp(SUPREG) −40 −100 - mA

Ich(red)(SUPREG) reduced charge current on pin

SUPREG VSUPREG <V

uvp(SUPREG);

T=25°C. -−5.5 - mA

T=140°C−2.5 - - mA

Enable input (pin SSHBC/EN)

Ven(PFC)(EN) PFC enable voltage on pin EN PFC only [2] 0.8 1.2 1.4 V

Ven(IC)(EN) IC enable voltage on pin EN PFC + HBC [2] 1.8 2.2 2.4 V

Ipu(EN) pull-up current on pin EN VSSHBC/EN =2.5V - −42 - μA

Vpu(EN) pull-up voltage on pin EN - 3.0 - V

Fast shut-down reset (pin SNSMAINS)

Vrst(SNSMAINS) reset level on pin SNSMAINS [2] -0.8-V

Protection and restart timer (pin RCPROT)

Vu(RCPROT) upper voltage on pin RCPROT 3.8 4.0 4.2 V

Vl(RCPROT) lower voltage on pin RCPROT 0.4 0.5 0.6 V

Ich(fast)(RCPROT) fast-charge current on pin RCPROT - −2.2 - mA

Ich(slow)(RCPROT) slow-charge current on pin

RCPROT −120 −100 −80 μA

Table 7. Characteristics …continued

Tamb =25

C; VSUPIC =20V; V

SUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when

flowing into the IC; unless otherwise specifi ed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 2 — 9 February 2011 35 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

Output voltage protection sensing, UVP/OVP output (pin SNSOUT)

Vovp(SNSOUT) overvoltage protection voltage on

pin SNSOUT [2] 3.40 3.50 3.60 V

Vuvp(SNSOUT) under-voltage protection voltage on

pin SNSOUT [2] 2.20 2.35 2.50 V

Overtemper ature protection

Totp overtempe rature protection trip

temperature [2] 130 150 160 °C

Burst mode activation (pin SNSOUT)

Vburst(HBC) HFC burst mode voltage [2] 0.9 1.1 1.2 V

Vburst(PFC) PFC burst mode voltage [2] 0.3 0.4 0.5 V

Ipu(SNSOUT) pull-up current on pin SNSOUT - −100 −80 μA

Vpu(SNSOUT) pull-up voltage on pin SNSOUT RSNSOUT =25kΩ to SGND - 1.5 - V

PFC driver (pin GATEPFC)

Isource(GATEPFC) source current on pin GATEPFC VGATEPFC =2V - −0.5 A

Isink(GATEPFC) sink current on pin GATEPFC VGATEPFC =2V - 0.7 - A

VGATEPFC =10V - 1.2 - A

PFC on-timer (pin COMPPFC)

Vton(COMPPFC)zero zero on-time voltage on pin

COMPPFC -3.5-V

Vton(COMPPFC)max maximum on-time voltage on pin

COMPPFC -1.25-V

fmax(PFC) PFC maximum frequency 100 125 150 kHz

toff(PFC)min minimum PFC off-time - 1.4 - μs

PFC error amplifier (pin SNSBOOST and COMPPFC)

Vreg(SNSBOOST) regulation voltage on pin

SNSBOOST pin ICOMPPFC = 0 2.475 2.500 2.525 V

gmtransconductance VSNSBOOST to ICOMPPFC -80-μA/V

Isink(COMPPFC) sink current on pin COMPPFC VSNSBOOST =3.3V - 39 - μA

Isource(COMPPFC) compen sation source current VSNSBOOST =2.0V - −39 - μA

Vclamp(COMPPFC) clamp voltage on pin COMPPFC [3] -3.9-V

PFC mains compensation (pin SNSMAINS)

ton(max) maximum on-time high mains;

VSNSMAINS =3.3V 3.5 4.7 5.9 μs

low mains;

VSNSMAINS =0.97V 29 44 59 μs

Vmvc(SNSMAINS)max maximum mains voltage

compensation voltage on pin

SNSMAINS

4.0 - - V

Table 7. Characteristics …continued

Tamb =25

C; VSUPIC =20V; V

SUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when

flowing into the IC; unless otherwise specifi ed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 2 — 9 February 2011 36 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

PFC demagnetization sensing (pin SNSAUXPF C)

Vdemag(SNSAUXPFC) demagnetization voltage on pin

SNSAUXPFC −150 −100 −50 mV

tto(mag) magnetization time-out time 40 50 60 μs

Iprot(SNSAUXPFC) protection current on pin

SNSAUXPFC VSNSAUXPFC =50mV −75 −33 - nA

PFC valley sensing (pin SNSAUXPFC)

(dV/dt)vrec(min) minimum valley recognition rate of

voltage change --1.7V/μs

tslope(vrec)min minimum valley recognition slope

time VSNSAUXPFC =1V

pp [4] - - 300 ns

demagnetization to ΔV/Δt=0 [5] --50ns

td(val-dem)max maximum valley-to-demag delay

time - 200 - ns

tto(vrec) valley recognition time-out time 3 4 6 μs

PFC soft start (pin SNSCURPFC)

Ich(ss)(PFC) PFC soft-start charge current - −60 - μA

Vclamp(ss)(PFC) PFC soft-start clamp voltage [1] 0.46 0.50 0.54 V

Vstop(ss)(PFC) PFC soft-start stop voltage [1] -0.45-V

Rss(PFC) PFC soft-start resistor 12 - - kΩ

PFC overcurrent sensing (pin SNSCURPFC)

Vocr(PFC) PFC overcurrent regulation voltage dV/dt = 50 mV/μs 0.49 0.52 0.55 V

dV/dt = 200 mV/μs 0.51 0.54 0.57 V

tleb(PFC) leading edge blanking time 250 310 370 ns

Iprot(SNSCURPFC) protection current on pin

SNSCURPFC −50 −33 - nA

PFC mains voltage sensing and clamp (pin SNSMAINS)

Vstart(SNSMAINS) start voltage on pin SNSMAINS [1] 1.11 1.15 1.19 V

Vuvp(SNSMAINS) undervoltage protection voltage on

pin SNSMAINS [1] 0.84 0.89 0.94 V

Vpu(SNSMAINS) pull-up voltage on pin SNSMAINS UVP-mains active [1] -1.05-V

Ipu(SNSMAINS) maximum clamp current UVP-mains active - −42 −35 μA

Iprot(SNSMAINS) Protection current on pin

SNSMAINS VSNSMAINS >V

uvp(SNSMAINS) - 33 100 nA

PFC boost vol tage protection se nsing, SCP/UVP/OVP boost (pin SNSBOOST)

Vscp(SNSBOOST) short-circuit protection voltage on

pin SNSBOOST 0.35 0.40 0.45 V

Vstart(SNSBOOST) st art volt age on pin SNSBOOST - 2.30 2.40 V

Vuvp(SNSBOOST) undervoltage protection voltage on

pin SNSBOOST 1.50 1.60 - V

Vovp(SNSBOOST) overvoltage protection voltage on

pin SNSBOOST 2.59 2.63 2.67 V

Table 7. Characteristics …continued

Tamb =25

C; VSUPIC =20V; V

SUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when

flowing into the IC; unless otherwise specifi ed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 2 — 9 February 2011 37 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

Iprot(SNSBOOST) protection current on pin

SNSBOOST VSNSBOOST = 2.5 V - 45 100 nA

HBC high-side and low-side driver (pin GATEHS and GATELS)

Isource(GATEHS) source current on pin GATEHS VGATEHS −VHB =4V - −310 - mA

Isource(GATELS) source current on pin GATELS VGATELS −VPGND =4V - −310 - mA

Isink(GATEHS) sink current on pin GATEHS VGATEHS −VHB = 2 V; - 560 - mA

VGATEHS −VHB =11V - 1.9 - A

Isink(GATELS) sink current on pin GATELS VGATELS −VPGND = 2 V - 560 - mA

VGATELS −VPGND =11V - 1.9 - A

Vrst(SUPHS) reset voltage on pin SUPHS - 4.5 - V

Iq(SUPHS) quiescent current on pin SUPHS VSUPHS −VHB =11V - 37 - μA

HBC adaptive non-overlap time (pin HB)

(dV/dt)ano(min) minimum adaptive non-overlap time

rate of voltage change - - 120 V/μs

tno(min) minimum non-overlap time - - 160 ns

HBC current controlled oscillator (pin CFMIN and RFMAX)

fmin(HB) minimum frequency on pin HB Cfmin =390pF;

VSSHBC/EN >V

fmin(SSHBC)

VSNSFB > Vfmin(SNSFB)

40 44 48 kHz

Iosc(min) minimum oscillator current VRFMAX = 0 V; charge and

discharge - 150 - μA

Iosc(max) maximum oscillator current Rfmax =15kΩ;

VRFMAX=2.5 V;

VSSHBC/EN <V

fmax(SSHBC)

- 970 - μA

Iosc(red) reduced oscillator current Slowed-down oscillator - −30 - μA

ICFMIN/IRFMAX current on pin CFMIN to current on

pin RFMAX ratio -4.9-

flimit(HB) limit frequency on pin HB Cfmin = 20 pF 500 670 - kHz

Vu(CFMIN) upper voltage on pin CFMIN - 3.0 - V

Vl(CFMIN) lower voltage on pin CFMIN - 1.0 - V

Vfmin(RFMAX) minimum frequency voltage on pin

RFMAX -0-V

Vfmax(ss)(RFMAX) maximum soft start frequency

voltage on pin RFMAX VSSHBC/EN < Vfmax(SSHBC) 2.40 2.50 2.60 V

Vfmax(fb)(RFMAX) maximum feedback frequency

voltage on pin RFMAX VSNSFB < Vfmax(SNSFB) 1.45 1.55 1.65 V

HBC feedback input (pin SNSFB)

Vpu(SNSFB) pull-up voltage on pin SNSFB - 8.4 - V

RO(SNSFB) output resistance on pin SNSFB - 1.5 - kΩ

Volp(SNSFB) open-loop protection voltage on pin

SNSFB [2] 7.0 7.7 7.9 V

Iolp(SNSFB) open-loop protection current on pin

SNSFB [2] −0.35 −0.26 −0.10 mA

Table 7. Characteristics …continued

Tamb =25

C; VSUPIC =20V; V

SUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when

flowing into the IC; unless otherwise specifi ed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 2 — 9 February 2011 38 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

Vfmin(SNSFB) minimum frequency voltage on pin

SNSFB 6.1 6.4 6.9 V

Ifmin(SNSFB) minimum frequency current on pin

SNSFB VSSHBC/EN > Vfmin(SSHBC) −0.86 −0.66 −0.46 mA

Vfmax(SNSFB) maximum frequency voltage on pin

SNSFB VSSHBC/EN > Vfmin(SSHBC) 3.9 4.1 4.3 V

Ifmax(SNSFB) maximum frequency current on pin

SNSFB VSSHBC/EN > Vfmin(SSHBC) -−2.2 - mA

Vclamp(SNSFB) clamp voltage on pin SNSFB maximum frequency;

ISNSFB =−4mA -3.2-V

Iclamp(SNSFB) clamp current on pin SNSFB maximum frequency;

VSNSFB =0V -−7.3 - mA

HBC soft-start (pin SSHBC/EN)

Vfmax(SSHBC) maximum frequency voltage on pin

SSHBC -3.2-V

Vfmin(SSHBC) minimum frequency voltage on pin

SSHBC VSNSFB > Vfmin(SNSFB) 7.5 7.9 8.3 V

Vclamp(SSHBC) clamp voltage on pin SSHBC - 8.4 - V

Vss(hf-lf)(SSHBC) high-low frequency soft-start

voltage on pin SSHBC [2] -5.6-V

Iss(hf)(SSHBC) high frequency soft-start current on

pin SSHBC VSSHBC < Vss(lf-hf)(SSHBC)

charge current - −160 - μA

discharge current - 160 - μA

Iss(lf)(SSHBC) low frequency soft-start current on

pin SSHBC VSSHBC > Vss(lf-hf)(SSHBC)

charge current - −40 - μA

discharge current - 40 - μA

Icmr(hf)(SSHBC) high frequency CMR current on pin

SSHBC VSSHBC < Vss(lf-hf)(SSHBC)

discharge only - 1800 - μA

Icmr(lf)(SSHBC) low frequency CMR current on pin

SSHBC VSSHBC > Vss(lf-hf)(SSHBC)

discharge only - 440 - μA

HBC high frequency se nsing, HFP - HBC (pin RFMAX)

Vhfp(RFMAX) High-frequency protection voltage

on pin RFMAX [2] 1.70 1.83 2.00 V

HBC overcurrent sensing, OCR/OCP - HBC (pin SNSCURHBC)

Vocr(HBC) HBC overcurrent regulation voltage posit ive level;

HS on + HS-LS non-overlap

time

0.45 0.50 0.55 V

negative level;

LS on + LS-HS non-overlap

time

−0.55 −0.50 −0.45 V

Table 7. Characteristics …continued

Tamb =25

C; VSUPIC =20V; V

SUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when

flowing into the IC; unless otherwise specifi ed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 2 — 9 February 2011 39 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

[1] The marked levels on this pin are correlated. The voltage difference between the levels has much less spread than the absolute value of

the levels themselves.

[2] Switching level has some hysteresis. The hysteresis falls within the limits.

[3] For a typical application with a compensation network on pin COMPPFC, like the example in Figure 19.

[4] Minimum required voltage change time for valley recognition on pin SNSAUXPFC.

[5] Minimum time required between demagnetization detection and ΔV/Δt = 0 on pin SNSAUXPFC.

Vocp(HBC) HBC overcurrent protection voltage positive level;

HS on + HS-LS non-overlap

time

0.90 1.00 1.10 V

negative level;

LS on + LS-HS non-overlap

time

−1.10 −1.00 −0.90 V

Ibstc(SNSCURHBC)max maximum boost compensation

current on pin SNSCURHBC VSNSBOOST =1.8V

source current;

VSNSCURHBC =−0.5 V -−170 - μA

sink current;

VSNSCURHBC =0.5V - 170 - μA

HBC Capacitive Mode Protection (CMP) (pin HB)

tto(cmr) time-out capacitive mode regulation - 690 - ns

Table 7. Characteristics …continued

Tamb =25

C; VSUPIC =20V; V

SUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when

flowing into the IC; unless otherwise specifi ed.

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 2 — 9 February 2011 40 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

11. Application information

Fig 19. Application dia gram of TEA1713

Disable

Css(HBC)

Cfmin

Rfmax

SNSBOOST

SUPHSSUPREG

DSUPHS

CSUPREG

TEA1713

SUPHV

PGND SGND

Power Factor

Controller

Resonant

Half-Bridge

Controller

SUPIC

GATEHS

CSUPIC

CSUPHS

CRes

Cboost

Crect

Tr (HBC)

Output

CHB

Rcurcmp

Rcur(HBC)

Cur(HBC)

GATELS

SNSCURHBC

SNSOUT

SNSFB

RFMAX

CFMIN

SSHBC/EN

SNSAUXPFC

SNSMAINS

GATEPFC

SNSCURPFC

Rss(PFC)

Css(PFC)

Rprot

Cprot

COMPPFC

Rcur(PFC)

Cur(PFC)

Dr(PFC)

Aux(PFC)

Rect Boost

Mains

RCPROT

014aaa867

Tr (PFC)

Product data sheet Rev. 2 — 9 February 2011 41 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

12. Package outline

Fig 20. Package outline SOT137 (SO24)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

2.65 0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

15.6

15.2

7.6

7.4 1.27 10.65

10.00

1.1

1.0

0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.1

0.4

SOT137-1

detail X

vMA

(A )

0.25

075E05 MS-013

pin 1 index

0.1 0.012

0.004

0.096

0.089

0.019

0.014

0.013

0.009

0.61

0.60

0.30

0.29 0.05

1.4

0.055

0.419

0.394

0.043

0.039

0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

0 5 10 mm

scale

O24: plastic small outline package; 24 leads; body width 7.5 mm SOT137

-1

99-12-27

03-02-19

Product data sheet Rev. 2 — 9 February 2011 42 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

13. Abbreviations

Table 8. Abbreviations

Acronym Description

ANO Adaptive Non-Overlap

CMOS Complementary Metal-Oxide-Semiconductor'

CMR Capacitive Mode Regulation

DMOS Double-diffused Metal-Oxide-Semiconductor

EMI ElectroMagnetic Interfer ence

HBC Half-Bridge Converter or Controller. Resonant converter which generates the

regulated output voltage.

HFP High-Frequency Prote c tion

HV High-voltage

OCP OverCurrent Protection

OCR OverCurrent Regulation

OLP Open-Loop Protection

OTP OverTemperature Protection

OVP OverVoltage Prot e cti on

PFC Power Factor Converter or Controller. Co nverter which pe rforms the power factor

correction.

UVP UnderVoltage Protection

SCP Short-Circuit Protec ti on

Product data sheet Rev. 2 — 9 February 2011 43 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

14. Revision history

Table 9. Revision history

Document ID Release date Data sheet status Change notice Supersedes

TEA1713T v.2 20110209 Product data sheet - TEA1713T v.1

TEA1713T v.1 20091222 Product data sheet - -

Product data sheet Rev. 2 — 9 February 2011 44 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conf lict with the short data sheet, the

full data sheet shall pre va il.

Product specificat ion — The information and data provided in a Product

data sheet shall define the specification of the product as agr eed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

15.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconduct ors’ aggregate and cumulati ve liability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suit able for use in life support, life-crit ical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe propert y or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whet her the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with t heir

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo m er(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 2 — 9 February 2011 45 of 47

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It i s neit her qualif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims resulting from custome r design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

15.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 2 — 9 February 2011 46 of 47

continued >>

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2

2.1 General features. . . . . . . . . . . . . . . . . . . . . . . . 2

2.2 PFC controller features. . . . . . . . . . . . . . . . . . . 2

2.3 HBC controller features . . . . . . . . . . . . . . . . . . 2

2.4 Protection features . . . . . . . . . . . . . . . . . . . . . . 2

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 5

7.1 Overview of IC modules . . . . . . . . . . . . . . . . . . 5

7.2 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.2.1 Low-voltage supply input

(pin SUPIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.2.2 Regulated supply

(pin SUPREG) . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.2.3 High-side driver floating supply

(pin SUPHS). . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.2.4 High voltage supply input (pin SUPHV) . . . . . . 8

7.3 Flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.4 Enable input (pin SSHBC/EN) . . . . . . . . . . . . 10

7.5 IC protection. . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.5.1 IC restart and shut-down . . . . . . . . . . . . . . . . 11

7.5.2 Protection and restart timer . . . . . . . . . . . . . . 12

7.5.2.1 Protection timer . . . . . . . . . . . . . . . . . . . . . . . 12

7.5.2.2 Restart timer. . . . . . . . . . . . . . . . . . . . . . . . . . 12

7.5.3 Fast shut-down reset

(pin SNSMAINS). . . . . . . . . . . . . . . . . . . . . . . 13

7.5.4 Output overvoltage protection

(pin SNSOUT) . . . . . . . . . . . . . . . . . . . . . . . . 13

7.5.5 Output undervoltage protection

(pin SNSOUT) . . . . . . . . . . . . . . . . . . . . . . . . 13

7.5.6 OverTemperature Protection (OTP) . . . . . . . . 14

7.6 Burst mode operation (pin SNSOUT). . . . . . . 14

7.7 PFC controller. . . . . . . . . . . . . . . . . . . . . . . . . 14

7.7.1 PFC gate driver (pin GATEPFC). . . . . . . . . . . 15

7.7.2 PFC on-time control . . . . . . . . . . . . . . . . . . . . 15

7.7.2.1 PFC error amplifier (pins COMPPFC and

SNSBOOST) . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.7.2.2 PFC mains compensation

(pin SNSMAINS). . . . . . . . . . . . . . . . . . . . . . . 15

7.7.3 PFC demagnetization sensing

(pin SNSAUXPFC) . . . . . . . . . . . . . . . . . . . . . 16

7.7.4 PFC valley sensing (pin SNSAUXPFC) . . . . . 16

7.7.5 PFC frequency and off-time limiting. . . . . . . . 17

7.7.6 PFC soft start and soft stop

(pin SNSCURPFC) . . . . . . . . . . . . . . . . . . . . 17

7.7.7 PFC overcurrent regulation, OCR-PFC

(pin SNSCURPFC) . . . . . . . . . . . . . . . . . . . . 18

7.7.8 PFC mains undervoltage protection/brownout

protection, UVP-mains (pin SNSMAINS). . . . 18

7.7.9 PFC boost overvoltage protection,

OVP-boost (pin SNSBOOST) . . . . . . . . . . . . 18

7.7.10 PFC short circuit/open-loop protection,

SCP/OLP-PFC (pin SNSBOOST) . . . . . . . . . 19

7.8 HBC controller . . . . . . . . . . . . . . . . . . . . . . . . 19

7.8.1 HBC high-side and low-side driver

(pin GATEHS and GATELS) . . . . . . . . . . . . . 19

7.8.2 HBC boost undervoltage protection,

UVP-boost (pin SNSBOOST) . . . . . . . . . . . . 19

7.8.3 HBC switch control. . . . . . . . . . . . . . . . . . . . . 19

7.8.4 HBC Adaptive Non-Overlap (AN O) ti me

function (pin HB) . . . . . . . . . . . . . . . . . . . . . . 20

7.8.4.1 Inductive mode (normal operation) . . . . . . . . 20

7.8.4.2 Capacitive mode . . . . . . . . . . . . . . . . . . . . . . 21

7.8.5 HBC slope controlled oscillator

(pins CFMIN and RFMAX). . . . . . . . . . . . . . . 22

7.8.6 HBC feedback input (pin SNSFB) . . . . . . . . . 24

7.8.7 HBC open-loop protection, OLP-HBC (p in

SNSFB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.8.8 HBC soft start (pin SSHBC/EN). . . . . . . . . . . 25

7.8.8.1 Soft start voltage levels . . . . . . . . . . . . . . . . . 25

7.8.8.2 Soft start charge and discharge. . . . . . . . . . . 26

7.8.8.3 Soft start reset . . . . . . . . . . . . . . . . . . . . . . . . 27

7.8.9 HBC high-frequency protection, HFP-HBC

(pin RFMAX) . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.8.10 HBC overcurrent regulation and protection,

OCR and OCP (pin SNSCURHBC). . . . . . . . 28

7.8.10.1 Boost voltage compensation . . . . . . . . . . . . . 28

7.8.10.2 Overcurrent regulation, OCR-HBC . . . . . . . . 29

7.8.10.3 Overcurrent protection, OCP-HBC. . . . . . . . . 30

7.8.11 HBC capacitive mode regulation, CMR

(pin HB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.9 Protection overview . . . . . . . . . . . . . . . . . . . . 31

8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 32

9 Thermal characteristics . . . . . . . . . . . . . . . . . 33

10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33

11 Application information . . . . . . . . . . . . . . . . . 40

12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 41

13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 42

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 43

NXP Semiconductors TEA1713T

Resonant power supply control IC with PFC

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 9 February 2011

Document identifier: TEA1713T

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 44

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 44

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 44

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 45

16 Contact information. . . . . . . . . . . . . . . . . . . . . 45

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46