[AK4440] AK4440 192kHz 24-Bit 8ch DAC with 2Vrms Output GENERAL DESCRIPTION The AK4440 is a 5V 24-bit 8ch DAC with an integrated 2Vrms output buffer. A charge pump in the buffer develops an internal negative power supply rail that enables a ground-referenced 2Vrms output. Using AKM's multi bit modulator architecture, the AK4440 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4440 integrates a combination of switched-capacitor and continuous-time filters, increasing performance for systems with excessive clock jitter. The 24-bit word length and 192kHz sampling rate make this part ideal for a wide range of consumer audio applications, such as DVD/BD, AV receiver, Home theater systems and set-top boxes. The AK4440 is offered in a space saving 30pin VSOP package. FEATURES Sampling Rate Ranging from 8kHz to 192kHz 128 times Oversampling (Normal Speed Mode) 64 times Oversampling (Double Speed Mode) 32 times Oversampling (Quad Speed Mode) 24Bit 8 times FIR Digital Filter with Slow roll-off option Switched-Capacitor Filter with High Tolerance to Clock Jitter Single Ended 2Vrms Output Buffer Digital De-emphasis Filter: 32kHz, 44.1kHz or 48kHz Soft mute Control I/F: 3-wire Serial and I2C Bus Audio I/F format: MSB justified, LSB justified (16bit, 20bit, 24bit), I2S, TDM Master clock: 256fs, 384fs, 512fs or 768fs or 1152fs (Normal Speed Mode) 128fs, 192fs, 256fs or 384fs (Double Speed Mode) 128fs or 192fs (Quad Speed Mode) THD+N: -93dB Dynamic Range: 105dB Automatic Power-on Reset Circuit Power Supply: +4.5 to +5.5V Ta = -20 to 85C Small Package: 30 pin VSOP (9.7mm x 7.6mm) MS1088-E-01 2011/03 -1- [AK4440] Audio I/F LOUT1 LPF SCF DAC ROUT1 LPF SCF DAC LOUT2 LPF SCF DAC ROUT2 LPF SCF DAC LOUT3 LPF SCF DAC ROUT3 LPF SCF DAC LOUT4 LPF SCF DAC ROUT4 LPF SCF DAC MCLK LRCK BICK SDTI1 SDTI2 SDTI3 SDTI4 PCM Control Register 3-wire 2 or I C AK4440 Charge Pump CP CN 1 VEE VSS2 VDD VSS1 AVDD 1 Block Diagram MS1088-E-01 2011/03 -2- [AK4440] Ordering Guide AK4440EF AKD4440 -20 +85C 30pin VSOP Evaluation Board for AK4440 Pin Layout MCLK 1 30 VDD BICK 2 29 VSS2 SDTI1 3 28 CP LRCK 4 27 CN TEST 5 26 VEE SMUTE/CSN/CAD0 6 25 LOUT1 ACKS/CCLK/SCL 7 24 ROUT1 DIF0/CDTI/SDA 8 23 LOUT2 SDTI2 9 22 ROUT2 SDTI3 10 21 LOUT3 SDTI4 11 20 ROUT3 TDM0B 12 19 LOUT4 DEM0 13 18 ROUT4 I2C/DEM1 14 17 VSS1 P/S 15 16 AVDD AK4440 Top View MS1088-E-01 2011/03 -3- [AK4440] PIN/FUNCTION No. 1 Pin Name MCLK I/O I 2 3 4 5 6 BICK SDTI1 LRCK TEST SMUTE CSN CAD0 ACKS I I I O I I I I I 9 10 11 12 CCLK SCL DIF0 CDTI SDA SDTI2 SDTI3 SDTI4 TDM0B I I I/O I I I I 13 14 DEM0 I2C I I 15 DEM1 P/S I I 16 17 18 19 20 21 22 23 24 25 26 AVDD VSS1 ROUT4 LOUT4 ROUT3 LOUT3 ROUT2 LOUT2 ROUT1 LOUT1 VEE O O O O O O O O O 27 CN I 28 CP I 7 8 Function Master Clock Input Pin An external TTL clock should be input on this pin. Audio Serial Data Clock Pin DAC1 Audio Serial Data Input Pin L/R Clock Pin TEST pin. This pin should be open. Soft Mute Pin in parallel mode "H": Enable, "L": Disable Chip Select Pin in serial 3-wire mode Chip Address Pin in serial I2C mode Auto Setting Mode Pin in parallel mode "L": Manual Setting Mode, "H": Auto Setting Mode Control Data Clock Pin in serial 3-wire mode Control Data Clock Pin in serial I2C mode Audio Data Interface Format Pin in parallel mode Control Data Input Pin in serial 3-wire mode Control Data Pin in serial I2C mode DAC2 Audio Serial Data Input Pin DAC3 Audio Serial Data Input Pin DAC4 Audio Serial Data Input Pin TDM I/F Format Mode in parallel control mode "L": TDM256 mode, "H": Normal mode De-emphasis Filter Enable Pin in parallel mode Control Mode Select Pin in serial mode "L": 3-wire Serial, "H": I2C Bus De-emphasis Filter Enable Pin in parallel mode Parallel/Serial Select Pin (Internal pull-up pin, typ 100k) "L": Serial control mode, "H": Parallel control mode DAC Analog Power Supply Pin: 4.5V5.5V Ground Pin DAC4 Rch Analog Output Pin DAC4 Lch Analog Output Pin DAC3 Rch Analog Output Pin DAC3 Lch Analog Output Pin DAC2 Rch Analog Output Pin DAC2 Lch Analog Output Pin DAC1 Rch Analog Output Pin DAC1 Lch Analog Output Pin Negative Voltage Output Pin Connect to VSS2 with a 1.0F capacitor that should have the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the VSS2 pin. Non polarity capacitors can also be used. Negative Charge Pump Capacitor Terminal Pin Connect to CP with a 1.0F capacitor that should have the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP pin. Non polarity capacitors can also be used. Positive Charge Pump Capacitor Terminal Pin Connect to CN with a 1.0F capacitor that should have the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP pin. Non polarity capacitors can also be used. MS1088-E-01 2011/03 -4- [AK4440] PIN/FUNCTION (Continued) No. 29 30 Pin Name VSS2 VDD I/O - Function Ground Pin Charge Pump and DAC Digital Power Supply Pin: 4.5V5.5V Note: All input pins except for the P/S pin should not be left floating. Handling of Unused Pin The following tables illustrate recommended states for open pins: Classification Pin Name Analog LOUT4-1, ROUT4-1 SDTI4-1 DEM0, TDM0B (Serial control mode) Digital TEST Setting Leave open. Connect to VSS2. Connect to VDD or VSS2. Leave open. ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=0V; Note 1) Parameter Power Supply Symbol VDD AVDD IIN VIND Ta Tstg min -0.3 -0.3 -0.3 -20 -65 max +6.0 +6.0 10 VDD+0.3 85 150 Input Current (any pins except supplies) Input Voltage Ambient Operating Temperature Storage Temperature Note 1. All voltages with respect to ground. Note 2. VSS1 and VSS2 must be connected to the same analog ground plane. Units V V mA V C C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=0V; Note 1) Parameter Power Supply Symbol VDD AVDD min +4.5 typ +5.0 VDD max +5.5 Units V Note 3. VDD and AVDD are the same voltage. *AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS1088-E-01 2011/03 -5- [AK4440] ANALOG CHARACTERISTICS (Ta=25C; VDD=AVDD = +5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data; Measurement frequency=20Hz 20kHz; RL 5k; unless otherwise specified) Parameter min typ max Units Resolution 24 Bits Dynamic Characteristics (Note 4) THD+N (0dBFS) fs=44.1kHz, BW=20kHz -93 -84 dB fs=96kHz, BW=40kHz -92 dB fs=192kHz, BW=40kHz -92 dB Dynamic Range (-60dBFS with A-weighted, Note 5) 98 105 dB S/N (A-weighted, Note 6) 98 105 dB Interchannel Isolation (1kHz) 90 100 dB Interchannel Gain Mismatch 0.2 0.5 dB DC Accuracy DC Offset (at output pin) -60 0 +60 mV Gain Drift 100 ppm/C Output Voltage (Note 7) 1.97 2.12 2.27 Vrms Load Capacitance (Note 8) 25 pF Load Resistance 5 k Power Supplies Power Supply Current: (Note 9) Power Supply Current: (Note 9) 80 110 mA Normal Operation (fs96kHz) 85 120 mA Normal Operation (fs=192kHz) 20 100 Power-Down Mode (Note 10) A Note 4. Measured by Audio Precision (System Two). Refer to the evaluation board manual. Note 5. 98dB for 16bit input data Note 6. S/N does not depend on input data size. Note 7. Full-scale voltage (0dB). Output voltage is proportional to the voltage of AVDD, AOUT (typ.@0dB) = 2.12Vrms x VDD/5. Note 8. In case of driving capacitive load, inset a resistor between the output pin and the capacitive load. Note 9. The current into VDD and AVDD. Note 10. The P/S pin is tied to VDD and the all other digital inputs including clock pins (MCLK, BICK and LRCK) are tied to VSS2. MS1088-E-01 2011/03 -6- [AK4440] SHARP ROLL-OFF FILTER CHARACTERISTICS (Ta = 25C; VDD=AVDD = 4.5 5.5V; fs = 44.1kHz; DEM = OFF; SLOW = "0") Parameter Symbol min typ max Units Digital filter PB 0 20.0 kHz Passband 0.05dB (Note 11) 22.05 kHz -6.0dB Stopband (Note 11) SB 24.1 kHz Passband Ripple PR dB 0.02 Stopband Attenuation SA 54 dB Group Delay (Note 12) GD 19.3 1/fs Digital Filter + SCF + LPF Frequency Response 20.0kHz Fs=44.1kHz FR dB 0.05 40.0kHz Fs=96kHz FR dB 0.05 80.0kHz Fs=192kHz FR dB 0.05 Note 11. The passband and stopband frequencies scale with fs(system sampling rate). For example, PB=0.4535xfs (@0.05dB), SB=0.546xfs. Note 12. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both channels to input register to the output of analog signal. SLOW ROLL-OFF FILTER CHARACTERISTICS (Ta = 25C; VDD=AVDD = 4.5~5.5V; fs = 44.1kHz; DEM = OFF; SLOW = "1") Parameter Symbol min (Note 13) PB (Note 13) SB PR SA GD 0 39.2 typ max Units 18.2 8.1 - kHz kHz kHz dB dB 1/fs Digital Filter Passband 0.04dB -3.0dB Stopband Passband Ripple Stopband Attenuation Group Delay (Note 12) 0.005 72 - 19.3 - Digital Filter + SCF + LPF FR +0.1/-4.3 dB 20.0kHz fs=44.kHz FR +0.1/-3.3 dB 40.0kHz fs=96kHz FR +0.1/-3.7 dB 80.0kHz fs=192kHz Note 13. The passband and stopband frequencies scale with fs. For example, PB = 0.185xfs (@0.04dB), SB = 0.888xfs. Frequency Response DC CHARACTERISTICS (Ta = 25C; VDD=AVDD = 4.5 5.5V) Parameter Symbol min typ max High-Level Input Voltage VIH 2.2 Low-Level Input Voltage VIL 0.8 Low-Level Output Voltage DIF0/CDTI/SDA (Iout = 3mA) VOL 0.4 Input Leakage Current (Note 14) Iin 10 Note 14. The current of the P/S pin is not included. The P/S pin has an internal pull-up resistor (typ.100k). Units V V V V A MS1088-E-01 2011/03 -7- [AK4440] SWITCHING CHARACTERISTICS (Ta = 25C; VDD=AVDD= +4.5 +5.5V; CL = 20pF) Parameter Symbol min fCLK 2.048 Master Clock Frequency Duty Cycle dCLK 40 LRCK Frequency Normal Mode (TDM0= "0", TDM1= "0") Normal Speed Mode fsn 8 Double Speed Mode fsd 60 Quad Speed Mode fsq 120 Duty Cycle Duty 45 TDM256 mode (TDM0= "1", TDM1= "0") Normal Speed Mode fsn 8 High time tLRH 1/256fs Low time tLRL 1/256fs TDM128 mode (TDM0= "1", TDM1= "1") Normal Speed Mode fsn 8 Double Speed Mode 60 fsd High time 1/128fs tLRH Low time 1/128fs tLRL Audio Interface Timing BICK Period tBCK 81 BICK Pulse Width Low tBCKL 30 Pulse Width High tBCKH 30 tBLR 20 BICK "" to LRCK Edge (Note 15) tLRB 20 LRCK Edge to BICK "" (Note 15) tSDH 10 SDTI Hold Time tSDS 10 SDTI Setup Time Control Interface Timing (3-wire Serial control mode): CCLK Period tCCK 200 CCLK Pulse Width Low tCCKL 80 Pulse Width High tCCKH 80 CDTI Setup Time tCDS 40 CDTI Hold Time tCDH 40 CSN High Time tCSW 150 tCSS 50 CSN "" to CCLK "" tCSH 50 CCLK "" to CSN "" Control Interface Timing (I2C Bus mode): fSCL SCL Clock Frequency 1.3 tBUF Bus Free Time Between Transmissions 0.6 tHD:STA Start Condition Hold Time (prior to first clock pulse) 1.3 tLOW Clock Low Time 0.6 tHIGH Clock High Time 0.6 tSU:STA Setup Time for Repeated Start Condition 0 tHD:DAT SDA Hold Time from SCL Falling (Note 16) 0.1 tSU:DAT SDA Setup Time from SCL Rising tR Rise Time of Both SDA and SCL Lines tF Fall Time of Both SDA and SCL Lines 0.6 tSU:STO Setup Time for Stop Condition 0 tSP Pulse Width of Spike Noise Suppressed by Input Filter Cb Capacitive load on bus Note 15. BICK rising edge must not occur at the same time as LRCK edge. Note 16. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 17. I2C-bus is a trademark of NXP B.V. MS1088-E-01 typ max 36.864 60 Units MHz % 48 96 192 55 kHz kHz kHz % 48 kHz ns ns 48 96 kHz kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 400 0.3 0.3 50 400 kHz s s s s s s s s s s ns pF 2011/03 -8- [AK4440] Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Figure 1. Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDH tSDS VIH SDTI VIL Figure 2. Audio Serial Interface Timing MS1088-E-01 2011/03 -9- [AK4440] VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 tCDH C0 R/W VIH A4 VIL Figure 3. WRITE Command Input Timing tCSW VIH CSN VIL tCSH VIH CCLK VIL CDTI D3 D2 D1 VIH D0 VIL Figure 4. WRITE Data Input Timing VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop Figure 5. I2C Bus mode Timing MS1088-E-01 2011/03 - 10 - [AK4440] OPERATION OVERVIEW System Clock The external clocks, which are required to operate the AK4440, are MCLK, LRCK and BICK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS bit = "0": Register 00H), the sampling speed is set by DFS1-0 bits (Table 1). The frequency of MCLK for each sampling speed is set automatically. (Table 2~Table 4) In auto setting mode (ACKS bit = "1": Default), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomes the appropriate frequency (Table 6), it is not necessary to set DFS1-0 bits. In parallel control mode, the sampling speed can be set by only the ACKS pin. When ACKS pin = "L", the AK4440 operates by Normal Speed Mode. When ACKS pin = "H", auto setting mode is enabled. The parallel control mode does not support 128fs and 192fs of double speed mode. The AK4440 is automatically placed in power saving mode when MCLK, LRCK and BICK stop during normal operation mode, and the analog output is forced to 0V(typ). When MCLK, LRCK and BICK are input again, the AK4440 is powered up. After power-up, the AK4440 is in the power-down mode until MCLK, LRCK and BICK are input. DFS1 bit DFS0 bit Sampling Rate (fs) 0 0 Normal Speed Mode 8kHz~48kHz 0 1 Double Speed Mode 60kHz~96kHz 1 0 Quad Speed Mode (default) 120kHz~192kHz Table 1. Sampling Speed (Manual Setting Mode) LRCK MCLK BICK fs 256fs 384fs 512fs 768fs 1152fs 64fs 32.0kHz 8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 36.8640MHz 2.0480MHz 44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz N/A 2.8224MHz 48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz N/A 3.0720MHz Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode) (N/A: Not available) MS1088-E-01 2011/03 - 11 - [AK4440] LRCK MCLK BICK fs 128fs 192fs 256fs 384fs 64fs 88.2kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 5.6448MHz 96.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 6.1440MHz Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode) LRCK MCLK BICK fs 128fs 192fs 64fs 176.4kHz 22.5792MHz 33.8688MHz 11.2896MHz 192.0kHz 24.5760MHz 36.8640MHz 12.2880MHz Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode) MCLK Sampling Speed 512fs 768fs Normal 256fs 384fs Double 128fs 192fs Quad Table 5. Sampling Speed (Auto Setting Mode) LRCK Fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz 128fs 22.5792 24.5760 MCLK (MHz) 192fs 256fs 384fs 512fs 768fs 16.3840 24.5760 22.5792 33.8688 24.5760 36.8640 22.5792 33.8688 24.5760 36.8640 33.8688 36.8640 Table 6. System Clock Example (Auto Setting Mode) MS1088-E-01 1152fs 36.8640 - Sampling Speed Normal Double Quad 2011/03 - 12 - [AK4440] Audio Serial Interface Format In parallel control mode, the DIF0 and TDM0B pins as shown in Table 7 can select four serial data modes. The register value of DIF0 and TDM0B bits are ignored. In serial control mode, the DIF2-0 and TDM1-0 bits shown in Table 8 can select 11 serial data modes. Initial value of DIF2-0 bits is "010". In all modes the serial data is MSB-first, 2's complement format and is latched on the rising edge of BICK. Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs. In parallel control mode, when the TDM0B pin = "L", the audio interface format is TDM256 mode (Table 7). The audio data of all DACs (eight channels) are input to the SDTI1 pin. The input data to SDTI2-4 pins are ignored. BICK should be fixed to 256fs. In serial control mode, when the TDM0 bit = "1" and the TDM1 bit = "0", the audio interface format is TDM256 mode (Table 8), and the audio data of all DACs (eight channels) are input to the SDTI1 pin. The input data to the SDTI2-4 pins are ignored. BICK should be fixed to 256fs. "H" time and "L" time of LRCK should be at least 1/256fs. The audio data is MSB-first, 2's complement format. The input data to the SDTI1 pin is latched on the rising edge of BICK. In TDM128 mode (TDM1-0 bits = "11", Table 8), the audio data of DACs (four channels; L1, R1, L2, R2) are input to the SDTI1 pin. The other four data (L3, R3, L4, R4) are input to the SDTI2 pin. The input data to SDTI3-4 pins are ignored. BICK should be fixed to 128fs. The audio data is MSB-first, 2's complement format. The input data to SDTI1-2 pins are latched on the rising edge of BICK. Mode Normal TDM256 Mode Normal 0 1 2 3 4 TDM256 5 6 7 TDM128 8 9 10 2 3 5 6 TDM0B pin DIF0 pin SDTI Format LRCK H L 24-bit MSB Justified H/L 2 L/H H H 24-bit I S Compatible L L 24-bit MSB Justified L H 24-bit I2S Compatible Table 7. Audio Data Formats (Parallel control mode) BICK 48fs 48fs 256fs 256fs TDM1 TDM0 DIF2 DIF1 DIF0 SDTI Format LRCK bit bit bit bit bit 0 0 0 0 0 16-bit LSB Justified H/L 0 0 0 0 1 20-bit LSB Justified H/L 0 0 0 1 0 24-bit MSB Justified H/L 0 0 0 1 1 24-bit I2S Compatible L/H 0 0 1 0 0 24-bit LSB Justified H/L 0 1 0 0 0 N/A 0 1 0 0 1 N/A 0 1 0 1 0 24-bit MSB Justified 0 1 0 1 1 24-bit I2S Compatible 0 1 1 0 0 24-bit LSB Justified 1 1 0 0 0 N/A 1 1 0 0 1 N/A 1 1 0 1 0 24-bit MSB Justified 1 1 0 1 1 24-bit I2S Compatible 1 1 1 0 0 24-bit LSB Justified Table 8. Audio Data Formats (Serial control mode) (N/A: Not available) MS1088-E-01 Figure Figure 8 Figure 9 Figure 10 Figure 11 BICK Figure 32fs 40fs 48fs 48fs 48fs Figure 6 Figure 7 Figure 8 Figure 9 Figure 7 256fs 256fs 256fs Figure 10 Figure 11 Figure 12 128fs 128fs 128fs Figure 13 Figure 14 Figure 15 2011/03 - 13 - [AK4440] LRCK 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 BICK (32fs) SDTI Mode 0 15 14 6 1 0 5 14 4 15 3 2 16 1 17 0 31 15 0 14 6 5 14 1 4 15 3 16 2 1 17 0 31 15 14 0 1 0 1 0 1 BICK (64fs) SDTI Mode 0 Don't care 15 14 15 Don't care 0 14 0 15:MSB, 0:LSB Lch Data Rch Data Figure 6. Mode 0 Timing LRCK 0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 BICK (64fs) SDTI Mode 1 Don't care 19 0 Don't care 19 0 Don't care 19 0 19 0 19:MSB, 0:LSB SDTI Mode 4 Don't care 23 22 21 20 23 22 20 21 23:MSB, 0:LSB Lch Data Rch Data Figure 7. Mode 1/4 Timing LRCK 0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 BICK (64fs) SDTI 23 22 1 0 Don't care 23 22 1 0 Don't care 23 22 23:MSB, 0:LSB Lch Data Rch Data Figure 8. Mode 2 Timing MS1088-E-01 2011/03 - 14 - [AK4440] LRCK 0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1 BICK (64fs) SDTI 0 1 23 22 Don't care 23 22 0 1 23 Don't care 23:MSB, 0:LSB Lch Data Rch Data Figure 9. Mode 3 Timing 256 BICK LRCK BICK(256fs) SDTI1(i) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK Figure 10. Mode 5 Timing 256 BICK LRCK BICK(256fs) SDTI1(i) 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 23 Figure 11. Mode 6 Timing 256 BICK LRCK BICK(256fs) SDTI1(i) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 L1 R1 L2 R2 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 0 23 Figure 12. Mode 7 Timing MS1088-E-01 2011/03 - 15 - [AK4440] 128 BICK LRCK BICK(128fs) SDTI1(i) SDTI2(i) 23 22 23 22 0 0 23 22 23 22 0 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 23 22 0 23 22 0 23 22 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 0 23 22 0 23 22 0 23 0 23 Figure 13. Mode 8 Timing 128 BICK LRCK BICK(128fs) SDTI1(i) SDTI2(i) 23 22 0 23 22 0 0 23 22 23 22 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 23 22 0 23 22 0 23 22 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK Figure 14. Mode 9 Timing 128 BICK LRCK BICK(128fs) SDTI1(i) SDTI2(i) 23 22 0 23 22 0 23 22 0 23 22 L1 R1 L2 R2 32 BICK 32 BICK 32 BICK 32 BICK 23 22 0 23 22 0 23 22 0 23 22 L3 R3 L4 R4 32 BICK 32 BICK 32 BICK 32 BICK 0 19 0 19 Figure 15. Mode 10 Timing MS1088-E-01 2011/03 - 16 - [AK4440] Analog Output Block The internal negative power supply generation circuit (Figure 16) provides a negative power supply for the internal 2Vrms amplifier. It allows the AK4440 to output an audio signal centered at VSS (0V, typ) as shown in Figure 17. The negative power generation circuit (Figure 16) needs 1.0F low ESR (Equivalent Series Resistance) capacitors (Ca, Cb). If this capacitor is polarized, the positive polarity pin should be connected to the CP and VSS2 pins. This circuit operates by clocks generated from MCLK. When MCLK stops, the AK4440 is placed in the reset mode automatically and the analog outputs settle to VSS (0V, typ). AK4440 VDD Charge Pump CP Negative Power CN (+) 1uF VSS2 VEE Cb 1uF (+) Ca Figure 16. Negative Power Generation Circuit AK4440 2.12Vrms 0V LOUT (ROUT) Figure 17. Audio Signal Output De-emphasis Filter A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15s). For double speed and quad speed modes, the digital de-emphasis filter is always off. In serial control mode, the DEM1-0 bits are valid for the DAC enabled by the DEMA-D bits (Table 9). In parallel control mode, DEM1-0 pins are valid (Table 10). DEM1 bit DEM0 bit Mode 0 0 1 1 0 1 0 1 44.1kHz OFF 48kHz 32kHz (default) Table 9 De-emphasis Filter Control in Serial Control Mode (Normal Speed Mode) MS1088-E-01 2011/03 - 17 - [AK4440] DEM1 pin DEM0 pin Mode L L H H L H L H 44.1kHz OFF 48kHz 32kHz (default) Table 10 De-emphasis Filter Control in Parallel Control Mode (Normal Speed Mode) Soft Mute Operation Soft mute operation is performed in the digital domain. When the SMUTE pin/bit is set "1", the output signal is attenuated to - in 1024 LRCK cycles. When the SMUTE pin/bit is returned to "0", the mute is cancelled and the output attenuation gradually changes to 0dB in 1024 LRCK cycles. If the soft mute is cancelled within the 1024 LRCK cycles after starting this operation, the attenuation is discontinued and it is returned to 0dB by the same cycle. Soft mute is effective for changing the signal source without stopping the signal transmission. SMUTE pin/bit 1024/fs 0dB 1024/fs (1) (3) Attenuation - GD (2) GD LOUT/ROUT DZF pin (4) 8192/fs Notes: (1) The time for input data to be attenuated to -, is Normal Speed Mode: 1024 LRCK cycles (1024/fs). Double Speed Mode: 2048 LRCK cycles (2048/fs). Quad Speed Mode: 4096 LRCK cycles (4096/fs). (2) The analog output corresponding to a specific digital input has group delay, GD. (3) If soft mute is cancelled before attenuating to -, the attenuation is discontinued and returned to ATT level in the same cycle. Figure 18. Soft Mute Function MS1088-E-01 2011/03 - 18 - [AK4440] System Reset The AK4440 is in power down mode upon power-up. The MLCK should be input after the power supplies are ramped up. The AK4440 is in power-down mode until LRCK are input. tW<20ms Power Supply 0.8xVDD (VDD, AVDD) 0.3V (1) MCLK 20 s (3) Internal Reset Reset Release 10ms (max) (2) Reset Audio circuit Power-up 8~10 LRCK Clocks (4) Charge Pump Circuit Power-up Power down Time A VEE Pin 0V (5) "0" data D/A In (Digital) 0V D/A Out (Analog) Active (D/A Out) MUTE (D/A Out) Notes: (1) The AK4440 includes an internal Power on Reset Circuit which is used reset the digital logic into a default state after power up. Therefore, the power supply voltage must reach 80% VDD from 0.3V in less than 20msec. (2) Register writings are valid after 10ms (max). (3) When internal reset is released, approximately 20us after a MCLK input, the internal analog circuit is powered-up. (4) The digital circuit and charge pump circuit are powered-up in 8~10 LRCK cycles when the analog circuit is powered-up. (5) The charge pump counter starts after the charge pump circuit is powered-up. The DAC outputs a valid analog signal after Time A. Time A = 1024/(fs x 16): Normal speed mode Time A = 1024/(fs x 8): Double speed mode Time A = 1024/(fs x 4): Quad speed mode Figure 19. System Reset Diagram MS1088-E-01 2011/03 - 19 - [AK4440] Reset Function When the MCLK, LRCK or BICK stops, the AK4440 is placed in reset mode and its analog outputs are set to VSS (0V, typ). When the MCLK, LRCK and BICK are restarted, the AK4440 returns to normal operation mode. Clock In (1) (2) MCLK, BICK, LRCK MCLK or BICK or LRCK Stop Internal State Normal Operation Reset D/A In (Digital) Normal Operation (3) GD D/A Out (Analog) (5) VSS (4) (5) Notes: (1) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK or LRCK or BICK is stopped). (2) The AK4440 detects the stop of LRCK or BICK if LRCK or BICK stops for more than 2048/fs. When LRCK is stopped, the AK4440 exits reset mode after LRCK is inputted. When BICK is stopped, the AK4440 exits reset mode after BICK is input. (3) Digital data can be stopped. The click noise after MCLK, LRCK and BICK are input again can be reduced by inputting the "0" data during this period. (4) The analog output corresponding to a specific digital input has group delay (GD). (5) No audible click noise occurs under normal conditions. Figure 20. Reset Timing Example MS1088-E-01 2011/03 - 20 - [AK4440] Register Control Interface The AK4440's functions are controlled by registers. Two types of control mode write internal registers. In the I2C-bus mode, the chip address is determined by the state of the CAD0 pin. In 3-wire mode, the chip address is fixed to "11". Writing "0" to the RSTN bit resets the internal timing circuit, but the registers are not initialized. * The AK4440 does not support read commands. * When the state of the P/S pin is changed, the AK4440 should be reset by the RSTB bit = "0". * In serial control mode, the setting of parallel pins is invalid. Function Parallel Control Mode Serial Control Mode X X X - X X X X X X Double sampling mode at 128/192fs De-emphasis SMUTE 16/20/24bit LSB justified format TDM256 mode TDM128 mode Table 11 Function Table (X: Available, -: Not available) (1) 3-wire Serial Control Mode (I2C pin = "L") The 3-wire P interface pins, CSN, CCLK and CDTI, write internal registers. The data on this interface consists of Chip Address (2bits, C1/0; fixed to "11"), Read/Write (1bit; fixed to "1", Write only), Register Address (MSB first, 5bits) and Control Data (MSB first, 8bits). The AK4440 latches the data on the rising edge of CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by the rising edge of CSN. The clock speed of CCLK is 5MHz (max). CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: R/W: A4-A0: D7-D0: Chip Address (Fixed to "11") READ/WRITE (Fixed to "1", Write only) Register Address Control Data Figure 21. Control I/F Timing MS1088-E-01 2011/03 - 21 - [AK4440] (2) I2C-bus Control Mode (I2C pin = "H") The AK4440 supports the fast-mode I2C-bus system (max: 400kHz). Figure 22 shows the data transfer sequence at the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 26). After the START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit which is a data direction bit (R/W) (Figure 23). The most significant six bits of the slave address are fixed as "001001". The next one bit is CAD0 (device address bit). The bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) set them. If the slave address match that of the AK4440 and R/W bit is "0", the AK4440 generates an acknowledge and the write operation is executed. If R/W bit is "1", the AK4440 does not answer any acknowledge (Figure 27). The second byte consists of the address for control registers of the AK4440. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 24). Those data after the second byte contain control data. The format is MSB first, 8bits (Figure 25). The AK4440 generates an acknowledge after each byte is received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines STOP condition (Figure 26). The AK4440 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4440 generates an acknowledge, and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the addresses exceed 03H prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 28) except for the START and the STOP condition. S T A R T SDA S S T O P R/W Slave Address Sub Address(n) A C K Data(n+1) Data(n) A C K A C K Data(n+x) A C K A C K P A C K Figure 22. Data transfer sequence at the I2C-bus mode 0 0 1 0 0 1 CAD0 R/W A2 A1 A0 D2 D1 D0 (This CAD0 should match with CAD0 pin) Figure 23. The first byte 0 0 0 A4 A3 Figure 24. The second byte D7 D6 D5 D4 D3 Figure 25. Byte structure after the second byte MS1088-E-01 2011/03 - 22 - [AK4440] SDA SCL S P start condition stop condition Figure 26. START and STOP conditions DATA OUTPUT BY MASTER not acknowledge DATA OUTPUT BY SLAVE(AK4440) acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 27. Acknowledge on the I2C-bus SDA SCL data line stable; data valid change of data allowed Figure 28. Bit transfer on the I2C-bus MS1088-E-01 2011/03 - 23 - [AK4440] Register Map Addr 00H 01H 02H 03H Register Name Control 1 Control 2 Power Down Control DEM Control D7 ACKS RRST 0 0 D6 TDM1 0 0 0 D5 TDM0 SLOW 0 0 D4 DIF2 DFS1 0 0 D3 DIF1 DFS0 PW4 DEMA D2 DIF0 DEM1 PW3 DEMB D1 0 DEM0 PW2 DEMC D0 RSTN SMUTE PW1 DEMD Note: For addresses from 04H to 1FH, data must not be written. Do not write the registers within 10msec after the power supplies are fed. All data can be written to the registers even if PW1-4 and RSTN bits are "0". When RSTN bit goes to "0", only internal timing is reset, and the registers are not initialized to their default values. Register Definitions Addr 00H Register Name Control 1 Default D7 ACKS D6 TDM1 D5 TDM0 D4 DIF2 D3 DIF1 D2 DIF0 D1 0 D0 RSTN 1 0 0 0 1 0 0 1 RSTN: Internal timing reset 0: Reset. Any registers are not initialized. 1: Normal operation DIF2-0: Audio data interface modes (Table 8) Default: "010" TDM0-1: TDM Mode Select Mode Normal TDM256 TDM128 TDM1 0 0 1 TDM0 0 1 1 BICK 32fs 256fs fixed 128fs fixed SDTI 1-4 1 1-2 Sampling Speed Normal, Double, Quad Speed Normal Speed Normal, Double Speed ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit "1". In this case, the setting of DFS1-0 bits is ignored. When this bit is "0", DFS1-0 bits set the sampling speed mode. Addr 01H Register Name Control 2 Default D7 RRST 0 D6 0 0 D5 SLOW D4 DFS1 D3 DFS0 D2 DEM1 D1 DEM0 D0 SMUTE 0 0 0 0 1 0 SMUTE: Soft Mute Enable 0: Normal operation 1: DAC outputs soft-muted DEM1-0: De-emphasis Response (Table 9, Table 10) Default: "01", OFF DFS1-0: Sampling speed control (Table 1) 00: Normal speed 01: Double speed MS1088-E-01 2011/03 - 24 - [AK4440] 10: Quad speed When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs. SLOW: Slow Roll-off Filter Enable 0: Sharp Roll-off Filter 1: Slow Roll-off Filter RRST: All registers are initialized. 0: Normal Operation 1: Reset. All registers are initialized. Addr 02H Register Name Power Down Control Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 PW4 1 D2 PW3 1 D1 PW2 1 D0 PW1 1 D4 0 0 D3 DEMA 0 D2 DEMB 0 D1 DEMC 0 D0 DEMD 0 PW4-1: Power-down control (0: Power-down, 1: Power-up) PW1: Power down control of DAC1 PW2: Power down control of DAC2 PW3: Power down control of DAC3 PW4: Power down control of DAC4 Addr 03H Register Name DEM Control Default D7 0 0 D6 0 0 D5 0 0 DEMA-D: De-emphasis Enable bit of DAC1/2/3/4 0: Disable 1: Enable MS1088-E-01 2011/03 - 25 - [AK4440] SYSTEM DESIGN Figure 29 and Figure 30 show the system connection diagram. The evaluation board (AKD4440) demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. 0.1u 10u Master Clock 1 MCLK VDD 30 VSS2 29 Analog 5V + 64fs 2 BICK 24bit Audio Data 3 SDTI1 CP 28 fs 4 LRCK CN 27 5 TEST VEE 26 6 SMUTE LOUT1 25 L1ch Out + 1u (1) ModeSetting AK4440 + 1u (1) ACKS ROUT1 24 R1ch Out 8 DIF0 LOUT2 23 L2ch Out 24bit Audio Data 9 SDTI2 ROUT2 22 R2ch Out 24bit Audio Data 10 SDTI3 LOUT3 21 L3ch Out 24bit Audio Data 11 SDTI4 ROUT3 20 R3ch Out 12 ModeSetting 7 TDM0B LOUT4 19 L4ch Out 13 DEM0 ROUT4 18 R4ch Out 14 DEM1 VSS1 17 P/S AVDD 16 15 Digital Ground + Analog 5V 0.1u 10u Analog Ground Figure 29. Typical Connection Diagram (Parallel Control Mode) Notes: - LRCK = fs, BICK = 64fs. - When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load. - The capacitor of low ESR should be used to the capacitor (1). When it uses the capacitor with the polarity, the positive pole of the capacitor should be connected to CP pin and VSS2 pin. - All input pins except for the P/S pin should not be left floating. MS1088-E-01 2011/03 - 26 - [AK4440] 0.1u 10u Master Clock 1 Analog 5V MCLK VDD 30 64fs 2 BICK VSS2 29 24bit Audio Data 3 SDTI1 CP 28 fs 4 LRCK CN 27 5 TEST VEE 26 6 CSN LOUT1 25 L1ch Out + + 1u (1) Microcontroller AK4440 + 1u (1) 7 CCLK ROUT1 24 R1ch Out 8 CDTI LOUT2 23 L2ch Out 24bit Audio Data 9 SDTI2 ROUT2 22 R2ch Out 24bit Audio Data 10 SDTI3 LOUT3 21 L3ch Out 11 SDTI4 ROUT3 20 R3ch Out L4ch Out R4ch Out 24bit Audio Data 12 TDM0B LOUT4 19 13 DEM0 ROUT4 18 14 I2C VSS1 17 15 P/S AVDD 16 + 0.1u Digital Ground Analog 5V 10u Analog Ground Figure 30. Typical Connection Diagram (3-wire Serial Control Mode) Notes: - LRCK = fs, BICK = 64fs. - When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load. - The capacitor of low ESR should be used to the capacitor (1). When it uses the capacitor with the polarity, the positive pole of the capacitor should be connected to CP pin and VSS2 pin. - All input pins except for the P/S pin should not be left floating. MS1088-E-01 2011/03 - 27 - [AK4440] 1. Grounding and Power Supply Decoupling VDD and AVDD are supplied from the analog supply and should be separated from the system digital supply. Decoupling capacitors, especially 0.1F ceramic capacitors for high frequency bypass, should be placed as near to VDD and AVDD as possible. The VSS1 and VSS2 must be connected to the same analog ground plane. Power-up sequence between VDD and AVDD is not critical. 2. Analog Outputs The analog outputs are single-ended and centered around the VSS (ground) voltage. The output signal range is typically 2.12Vrms (typ @AVDD=5V). The internal switched-capacitor filter (SCF) and continuous-time filter (CTF) attenuate the noise generated by the delta-sigma modulator beyond the audio passband. Using single a 1st-order LPF (Figure 31) can reduce noise beyond the audio passband. The output voltage is a positive full scale for 7FFFFFH (@24bit data) and a negative full scale for 800000H (@24bit data). The ideal output is 0V (VSS) voltage for 000000H (@24bit data). The DC offset is 60mV or less. AK4440 560 Analog Out AOUT 2.12Vrms (typ) 3.3nF (fc = 86.1kHz, gain = -0.85dB @ 40kHz, gain = -2.70dB @ 80kHz) Figure 31. External 1st order LPF Circuit Example1 MS1088-E-01 2011/03 - 28 - [AK4440] PACKAGE 30pin VSOP (Unit: mm) 1.5MAX *9.70.1 0.3 30 16 15 1 0.220.1 7.60.2 5.60.1 A 0.15 +0.10 -0.05 0.65 0.12 M 0.450.2 +0.10 0.08 0.10 -0.05 1.20.10 Detail A NOTE: Dimension "*" does not include mold flash. Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy, Halogen (bromine and chlorine) free Cu Solder (Pb free) plate RoHS Compliance *All integrated circuits form Asahi Kasei Microdevices Corporation (AKM) assembled in "lead-free" packages are fully compliant with RoHS. MS1088-E-01 2011/03 - 29 - [AK4440] MARKING AKM AK4440EF XXXBYYYYC XXXBYYYYC Date code identifier XXXB: Lot number (X: Digit number, B: Alpha character) YYYYC: Assembly date (Y: Digit number, C: Alpha character) REVISION HISTORY Date (YY/MM/DD) 09/10/15 11/03/01 Revision 00 01 Reason First Edition Error Correction Page Contents 28 1. Grounding and Power Supply Decoupling The description was changed. MS1088-E-01 2011/03 - 30 - [AK4440] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS1088-E-01 2011/03 - 31 -