Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.5
1. DESCRIPTION
The M37272M6/M8-XXXSP/FP and M37272MA-XXXSP are single-
chip microcomputers designed with CMOS silicon gate technology.
They have a OSD, data slicer, and I2C-BUS interface, so it is useful
for a channel selection system for TV with a closed caption decoder.
The features of the M37272E8SP/FP and M37272EFSP are similar
to those of the M37272M6-XXXSP except that the chip has a built-in
PROM which can be written electrically. The difference between
M37272M6-XXXSP/FP, M37272M8-XXXSP/FP and M37272MA-
XXXSP are the ROM size and RAM size. Accordingly, the following
descriptions will be for the M37272M6-XXXSP/FP.
2. FEATURES
●Number of basic instructions .................................................... 71
●Memory sizeROM .............. 24K bytes
(
M37272M6-XXXSP/FP
)
32K bytes
(
M37272M8-XXXSP/FP, M37272E8SP/FP
)
40K bytes
(
M37272MA-XXXSP
)
60K bytes
(
M37272EFSP
)
RAM ...............
1024
bytes
(
M37272M6-XXXSP/FP
)
1152
bytes
(
M37272M8-XXXSP/FP, M37272E8SP/FP
)
1472
bytes
(
M37272MA-XXXSP, M37272EFSP
)
(*ROM correction memory included)
●Minimum instruction execution time
......................................... 0.5 µs
(at 8 MHz oscillation frequency)
●Power source voltage ................................................. 5 V ± 10 %
●Subroutine nesting .............................................128 levels (Max.)
●Interrupts....................................................... 17 types, 16 vectors
●8-bit timers .................................................................................. 6
●Programmable I/O ports (Ports P0, P1, P2, P30, P31) ............. 26
●Input ports (Ports P50, P51) ........................................................ 2
●Output ports (Ports P52–P55) ..................................................... 4
●12 V withstand ports ................................................................... 6
●LED drive ports ........................................................................... 4
●Serial I/O ............................................................8-bit ✕ 1 channel
●Multi-master I2C-BUS interface .............................. 1 (2 systems)
●A-D comparator (6-bit resolution) ................................6 channels
●PWM output circuit......................................................... 8-bit ✕ 6
●Power dissipation
In high-speed mode .........................................................165 mW
(at VCC = 5.5V, 8 MHz oscillation frequency, OSD on, and Data
slicer on)
In low-speed mode .........................................................0.33 mW
(at VCC = 5.5V, 32 kHz oscillation frequency)
●ROM correction function ................................................ 2 vectors
●Closed caption data slicer
●OSD function
Display characters ................................... 32 characters ✕ 2 lines
(It is possible to display 3 lines or more by software)
Kinds of characters ........................................................254 kinds
Character display area............................ CC mode: 16 ✕ 26 dots
OSD mode: 16 ✕ 20 dots
Kinds of character sizes..................................... CC mode: 1 kind
OSD mode: 8 kinds
Kinds of character colors .................................. 8 colors (R, G, B)
Coloring unit................... character, character background, raster
Display position
Horizontal: 128 levels Vertical: 512 levels
Attribute ........................................................................................
CC mode: smooth italic, underline, flash, automatic solid space
OSD mode: border
Smoth roll-up
Window function
3. APPLICA TION
TV with a closed caption decoder
2
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
TABLE OF CONTENTS
1. DESCRIPTION ..........................................................................1
2. FEAUTURES .............................................................................1
3. APPLICATION............................................................................1
4. PIN CONFIGURATION ..............................................................3
5. FUNCTIONAL BLOCK DIAGRAM .............................................4
6. PERFORMANCE OVERVIEW...................................................5
7. PIN DESCRIPTION ...................................................................7
8. FUNCTIONAL DESCRIPTION.................................................11
8.1 CENTRAL PROCESSING UNIT (CPU) .................... 11
8.2 MEMORY ..................................................................12
8.3 INTERRUPTS ...........................................................18
8.4 TIMERS.....................................................................23
8.5 SERIAL I/O................................................................26
8.6 MULTI-MASTER I2C-BUS INTERFACE....................29
8.7 PWM OUTPUT CIRCUIT ..........................................42
8.8 A-D COMPARA T OR ..................................................46
8.9 ROM CORRECTION FUNCTION .............................48
8.10 DATA SLICER .........................................................49
8.11 OSD FUNCTIONS ...................................................60
8.11.1 Display Position .......................................65
8.11.2 Dot size ....................................................69
8.11.3 Clock for OSD ..........................................70
8.11.4 Field Determination Display .....................71
8.11.5 Memory For OSD.....................................73
8.11.6 Character Color .......................................77
8.11.7 Character Background Color ...................77
8.11.8 OUT1, OUT2 Signals ...............................78
8.1 1.9 Attribute....................................................79
8.11.10 Multiple Display......................................84
8.11.11 Automatic Solid Space Function ............85
8.11.12 Window Function ...................................86
8.11.13 OSD Output Pin Control ........................88
8.11.14 Raster Coloring Function .......................89
8.12. SOFTW ARE RUNAWAY DETECT FUNCTION .....91
8.13. RESET CIRCUIT....................................................92
8.14. CLOCK GENERATING CIRCUIT ...........................93
8.15. DISPLAY OSCILLATION CIRCUIT ........................96
8.16. AUTO-CLEAR CIRCUIT.........................................96
8.17. ADDRESSING MODE............................................96
8.18. MACHINE INSTRUCTIONS...................................96
9. PROGRAMMING NOTES........................................................96
10. ABSOLUTE MAXIMUM RATINGS .........................................97
11. RECOMMENDED OPERATING CONDITIONS.....................97
12. ELECTRIC CHARACTERISTICS ..........................................98
13. A-D COMPARISON CHARACTERISTICS...........................100
14.
MULTI-MASTER I
2
C-BUS BUS LINE CHARACTERISTICS .........
100
15. PROM PROGRAMMING METHOD.....................................101
16. DATA REQUIRED FOR MASK ORDERS ............................102
17. MASK CONFIRMATION FORM...........................................103
18. MARK SPECIFICATION FORM........................................... 112
19. ONE TIME PROM VERSIONS M37272E8SP/FP,
M37272EFSP MARKING..................................................... 114
20. APPENDIX ........................................................................... 115
21. PACKAGE OUTLINE ...........................................................140
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
P
0
6
/
I
N
T
2
/
A
D
4
X
O
U
T
P
5
0
/
H
S
Y
N
C
P
5
1
/
V
S
Y
N
C
P
0
0
/
P
W
M
0
P
0
1
/
P
W
M
1
P
0
2
/
P
W
M
2
P
0
3
/
P
W
M
3
P
0
4
/
P
W
M
4
P
0
5
/
P
W
M
5
P
0
7
/
I
N
T
1
P
2
3
/
T
I
M
3
P
2
4
/
T
I
M
2
P
2
5
A
V
C
C
H
L
F
V
H
O
L
D
C
V
I
N
C
N
V
S
S
X
I
N
V
S
S
P
5
2
/
R
P
5
3
/
G
P
5
4
/
B
P
5
5
/
O
U
T
1
P
2
0
/
S
C
L
K
P
2
1
/
S
O
U
T
P
2
2
/
S
I
N
P
1
0
/
O
U
T
2
P
1
1
/
S
C
L
1
P
1
2
/
S
C
L
2
P
1
3
/
S
D
A
1
P
1
4
/
S
D
A
2
P
1
5
/
A
D
1
/
I
N
T
3
P
1
6
/
A
D
2
P
3
0
/
A
D
5
P
3
1
/
A
D
6
R
E
S
E
T
P
2
6
/
O
S
C
1
/
X
C
I
N
P
2
7
/
O
S
C
2
/
X
C
O
U
T
V
C
C
P
1
7
/
A
D
3
M
3
7
2
7
2
M
6
/
M
8
/
M
A
-
X
X
X
S
P
M
3
7
2
7
2
E
8
/
E
F
S
P
4. PIN CONFIGURATION
Outline 42P4B
Fig. 4.1 Pin Configuration (1) (Top View)
Outline 42P2R-A/E
Fig. 4.2 Pin Configuration (2) (Top View)
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
P
0
6
/
I
N
T
2
/
A
D
4
X
O
U
T
P
5
0
/
H
S
Y
N
C
P
5
1
/
V
S
Y
N
C
P
0
0
/
P
W
M
0
P
0
1
/
P
W
M
1
P
0
2
/
P
W
M
2
P
0
3
/
P
W
M
3
P
0
4
/
P
W
M
4
P
0
5
/
P
W
M
5
P
0
7
/
I
N
T
1
P
2
3
/
T
I
M
3
P
2
4
/
T
I
M
2
P
2
5
A
V
C
C
H
L
F
V
H
O
L
D
C
V
I
N
C
N
V
S
S
X
I
N
V
S
S
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
P
5
2
/
R
P
5
3
/
G
P
5
4
/
B
P
5
5
/
O
U
T
1
P
2
0
/
S
C
L
K
P
2
1
/
S
O
U
T
P
2
2
/
S
I
N
P
1
0
/
O
U
T
2
P
1
1
/
S
C
L
1
P
1
2
/
S
C
L
2
P
1
3
/
S
D
A
1
P
1
4
/
S
D
A
2
P
1
5
/
A
D
1
/
I
N
T
3
P
1
6
/
A
D
2
P
3
0
/
A
D
5
P
3
1
/
A
D
6
R
E
S
E
T
P
2
6
/
O
S
C
1
/
X
C
I
N
P
2
7
/
O
S
C
2
/
X
C
O
U
T
V
C
C
P
1
7
/
A
D
3
M
3
7
2
7
2
M
6
/
M
8
-
X
X
X
F
P
M
3
7
2
7
2
E
8
F
P
3
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.4
4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
5. FUNCTIONAL BLOCK DIAGRAM
Fig. 5.1 Functional Block Diagram of M37272
XI
N
XO
U
T
O
S
C
1
/
XC
I
N
O
S
C
2
/
XC
O
U
T
P
0
(
8
)
I
N
T
1
I
N
T
2
I
N
T
3
P
1
(
8
)
P
W
M
5
P
W
M
4
P
W
M
3
P
W
M
2
P
W
M
1
P
W
M
0
P
W
M
T
I
M
2
T
I
M
3
1
9
2
0
2
5
1
4
2
2
2
1
1
8
C
VI
N
1
7
1
6
1
5
VH
O
L
D
H
L
F
2
4
2
3
1
0
9
8
7
6
5
4
3
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
P
2
(
8
)
1
3
1
2
1
1
3
6
3
7
I
/
O
p
o
r
t
P
1
I
/
O
p
o
r
t
P
2
P
3
(
2
)
2
7
2
6
3
8
S
D
A
2
S
D
A
1
S
C
L
2
S
C
L
1
S
I
/
O
SI
N
SC
L
K
SO
U
T
P
5
(
6
)
3
9
4
0
4
1
4
2
2
O
u
t
p
u
t
p
o
r
t
s
P
52–
P
55
O
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t
p
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f
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d
i
s
p
l
a
y
1
H
S
Y
N
C
V
S
Y
N
C
R
G
B
O
U
T
1
O
U
T
2
P
10
I
/
O
p
o
r
t
s
P
30,
P
31
A
D
1
–
6
D
a
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a
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N
XO
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R
e
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p
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A
VC
C
VC
C
VS
S
C
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VS
S
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t
a
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s
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-
c
l
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c
k
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p
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/
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t
s
P
26,
P
27
C
l
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c
k
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n
p
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f
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r
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D
/
s
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b
-
c
l
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c
k
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p
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t
8
-
b
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t
a
r
i
t
h
m
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t
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c
a
n
d
l
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c
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t
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c
c
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m
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l
a
t
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r
A
(
8
)
T
i
m
e
r
6
T
6
(
8
)
T
i
m
e
r
5
T
5
(
8
)
T
i
m
e
r
4
T
4
(
8
)
T
i
m
e
r
3
T
3
(
8
)
T
i
m
e
r
2
T
2
(
8
)
T
i
m
e
r
1
T
1
(
8
)
T
i
m
e
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c
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n
t
s
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t
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r
(
8
)
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n
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t
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d
e
c
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P
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(
8
)
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t
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(
8
)
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Y
(
8
)
I
n
d
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X
(
8
)
R
O
M
P
r
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r
a
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CL
(
8
)
P
r
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a
m
c
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CH
(
8
)
R
A
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b
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C
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d
d
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s
s
b
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/
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p
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t
P
0
R
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c
o
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r
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c
t
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c
i
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c
u
i
t
M
u
l
t
i
-
m
a
s
t
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r
I2C
-
B
U
S
i
n
t
e
r
f
a
c
e
I
n
p
u
t
p
o
r
t
s
P
50,
P
51
S
y
n
c
h
r
o
n
o
u
s
s
i
g
n
a
l
i
n
p
u
t
5
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Number of basic instructions
Instruction execution time
Clock frequency
Memory size
Input/Output
ports
Serial I/O
Multi-master I2C-BUS interface
A-D comparator
PWM output circuit
Timers
ROM correction function
Subroutine nesting
Interrupt
Clock generating circuit
Data slicer
ROM
RAM
OSD ROM
OSD RAM
P0
P10–P17
P20–P27
P30, P31
P50, P51
P52–P55
M37272M6-XXXSP/FP
M37272M8-XXXSP/FP,M37272E8SP/FP
M37272MA-XXXSP
M37272EFSP
M37272M6-XXXSP/FP
M37272M8-XXXSP/FP,M37272E8SP/FP
M37272MA-XXXSP, M37272EFSP
I/O
I/O
I/O
I/O
Input
Output
71
0.5 µs (the minimum instruction execution time, at 8 MHz oscillation fre-
quency)
8 MHz (maximum)
24K bytes
32K bytes
40K bytes
60K bytes
1024 bytes (ROM correction memory included)
1152 bytes (ROM correction memory included)
1472 bytes (ROM correction memory included)
10K bytes
128 bytes
8-bit ✕ 1 (N-channel open-drain output structure, can be used as PWM
output pins, INT input pins, A-D input pin)
8-bit ✕ 1 (CMOS input/output structure, however, N-channel open-drain
output structure, when P11–P14 are used as multi-master I2C-BUS inter-
face, can be used as OSD output pin, A-D input pins, INT input pin, multi-
master I2C-BUS interface)
8-bit ✕ 1 (P2 is CMOS input/output structure, however, N-channel open-
drain output structure when P20 and 21 are used as serial output, can be
used as serial input/output pins, timer external clock input pins, OSD clock
input/output pin, sub-clock input/output pins)
2-bit ✕ 1 (CMOS input/output or N-channel open-drain output structure,
can be used as A-D input pins)
2-bit ✕ 1 (can be used as OSD input pins)
4-bit ✕ 1 (CMOS output structure, can be used as OSD output pins)
8-bit ✕ 1
1 (2 systems)
6 channels (6-bit resolution)
8-bit ✕ 6
8-bit timer ✕ 6
2 vectors
128 levels (maximum)
<17 types>
INT external interrupt ✕ 3, Internal timer interrupt ✕ 6, Serial I/O interrupt ✕
1, OSD interrupt ✕ 1, Multi-master I2C-BUS interface interrupt ✕ 1, Data
slicer interrupt ✕ 1, f(XIN)/4096 interrupt ✕ 1, VSYNC interrupt ✕ 1, BRK
instruction interrupt ✕ 1, reset ✕ 1
2 built-in circuits (externally connected to a ceramic resonator or a quartz-
crystal oscillator)
Built-in
Parameter
6. PERFORMANCE OVERVIEW
Table 6.1 Performance Overview
Functions
6
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
32 characters ✕ 2 lines
CC mode: 16 ✕ 26 dots (character display area : 16 ✕ 20 dots)
OSD mode: 16 ✕ 20 dots
254 kinds
CC mode: 1 kinds
OSD mode: 8 kinds
1 screen: 8 kinds (per character unit)
Horizontal: 128 levels, Vertical: 512 levels
5V ± 10%
165 mW typ. ( at oscillation frequency f(XIN) = 8 MHz, fOSC = 27 MHz)
82.5 mW typ. ( at oscillation frequency f(XIN) = 8 MHz)
0.33 mW typ. ( at oscillation frequency f(XCIN) = 32 kHz, f(XIN) = stopped)
0.055 mW ( maximum )
–10 °C to 70 °C
CMOS silicon gate process
42-pin plastic molded DIP
42-pin plastic molded SSOP
Power source voltage
Power
dissipation
Number of display characters
Dot structure
Kinds of characters
Kinds of character sizes
1 screen : 8
Character font coloring
Display position
Functions
Table 6.2 Performance Overview (Continued)
OSD function
Parameter
In high-speed
mode
In low-speed
mode
In stop mode
Operating temperature range
Device structure
Package
OSD ON
OSD OFF
OSD OFF
Data slicer ON
Data slicer OFF
Data slicer OFF
Pin Name Input/ Functions
Output
VCC, AVCC, Power source Apply voltage of 5 V ± 10 % to (typical) VCC and AVCC, and 0 V to VSS.
VSS
CNVSS CNVSS This is connected to VSS.
RESET Reset input Input To enter the reset state, the reset input pin must be kept at a LOW for 2 µs or more (under
normal VCC conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this LOW condition should
be maintained for the required time.
XIN Clock input Input This chip has an internal clock generating circuit. To control generating frequency, an
external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and
XOUT Clock output Output XOUT. If an external clock is used, the clock source should be connected to the XIN pin and
the XOUT pin should be left open.
P0
0
/PWM0–
I/O port P0 I/O Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually
P0
5
/PWM5,
programmed as input or output. At reset, this port is set to input mode. The output structure
P0
6
/INT2/AD4,
is N-channel open-drain output. (See note 1)
P07/INT1 PWM output Output Pins P00–P05 are also used as PWM output pins PWM0–PWM5 respectively. The output
structure is N-channel open-drain output.
External interrupt Input
Pins P0
6
and P0
7
are also used as INT external interrupt input pins INT2 and INT1 respectively.
input
Analog input Input P06 pin is also used as analog input pin AD4.
P10/OUT2, I/O port P1 I/O Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output
P11/SCL1, structure is CMOS output. (See note 1)
P12/SCL2, OSD output Output Pins P10 is also used as OSD output pin OUT2. The output structure is CMOS output.
P13/SDA1, Multi-master I/O Pins P11–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master
P14/SDA2, I2C-BUS interface I2C-BUS interface is used. The output structure is N-channel open-drain output.
P1
5
/AD1/INT3,
Analog input Input Pins P10, P15–P17 are also used as analog input pin AD8, AD1–AD3 respectively.
P16/AD2, External interrupt Input P15 pin is also used as INT external interrupt input pin INT3.
P17/AD3 input
P20/SCLK, I/O port P2 I/O Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
P21/SOUT,structure is CMOS output. (See note 1)
P22/SIN,
Serial I/O synchronous
I/O P20 pin is also used as serial I/O synchronous clock input/output pin SCLK. The output
P23/TIM3,
clock input/output port
structure is N-channel open-drain output.
P24/TIM2, Serial I/O data I/O P21 pin is also used as serial I/O data output pin SOUT. The output structure is open-drain
P25,output output.
P26/OSC1/
Serial I/O data input
Input P22 pin is also used as serial I/O data input pin SIN.
XCIN,External clock Input Pins P23 and P24 are also used as timer external clock input pins TIM3 and TIM2
P27/OSC2/
input for timer respectively.
XCOUT
Clock input for OSD
Input P26 pin is also used as OSD clock input pin OSC1. (See note 2)
Clock output for OSD
Output P27 pin is also used as OSD clock input pin OSC2. The output structure is CMOS output.
(See note 2)
Sub-clock input Input P26 pin is also used as sub-clock input pin XCIN.
Sub-clock output Output P27 pin is also used as sub-clock output pin XCOUT.
7. PIN DESCRIPTION
Table 7.1 Pin Description
7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.4
Pin Name Input/ Functions
Output
P30/AD5, I/O port P3 I/O Ports P30 and P31 are a 2-bit I/O port and has basically the same functions as port 0.
P31/AD6 The output structure can be selected either CMOS output or N-channel open-drain output
structure. (See notes 1, 3)
Analog input Input Pins P30 and P31 are also used as analog input pins AD5 and AD6 respectively.
P5
0
/H
SYNC
,
Input port P5 Input Pin P50 and P51 are 2-bit input ports.
P5
1
/V
SYNC
HSYNC input Input Pin P50 is also used as HSYNC input. This is a horizontal synchronous signal input for OSD.
VSYNC input Input Pin P51 is also used as VSYNC input. This is a vertical synchronous signal input for OSD.
P52/R, Output port P5 Output Ports P52–P55 are a 4-bit output port. The output structure is CMOS output.
P53/G,
P54/B, OSD output Output Pins P52–P55 are also used as OSD output pins R, G, B, OUT1 respectively. The output
P55/OUT1 structure is CMOS output.
CVIN I/O for data slicer Input Input composite video signal through a capacitor.
VHOLD Input Connect a capacitor between VHOLD and Vss.
HLF I/O Connect a filter using of a capacitor and a resistor between HLF and Vss.
Notes 1: Port Pi (i = 0 to 3) has the port Pi direction register which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1”
in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data
are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read.
This allows a previously-output value to be read correctly even if the output LOW voltage has risen, for example, because a light emitting diode was directly
driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, it is written only into the port
latch, while the pin remains in the floating state.
2: To switch output functions, set the raster color register and OSD control register. When pins P26 and P27 are used as the OSD clock input/output pins, set
the corresponding bits of the port P2 direction register to “0” (input mode).
3: To switch output structures, set bits 2 and 3 of the port P3 direction register, When “0,” CMOS output ; when “1,” N-channel open-drain output.
Table 7.2 Pin Description (continued)
8
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.4
9
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 7.1 I/O Pin Block Diagram (1)
N-channel open-drain output
Ports P00–P05
Note :Each port is also used as follows :
P00–P05 : PWM0–PWM5
CMOS output
Ports P1, P2, P30, P31
P
o
r
t
s
P
1
,
P
2
,
P
30,
P
31
P
o
r
t
s
P
00
–P
05
D
a
t
a
b
u
s
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
D
a
t
a
b
u
s
Notes 1: Each port is also used as follows :
P10 : OUT2
P11 : SCL1
P12 : SCL2
P13 : SDA15
P14 : SDA2
P15 : AD1/INT3
P16 : AD2
P17 : AD3
2: The output structure of ports P30 and P31 can be selected either CMOS output or N-channel open-
drain output structure (when selecting N-channel open-drain, it is the same with P06 and P07).
3: The output structure of ports P11–P14 is N-channel open-drain output when using as multi-master
I2C-BUS interface (it is the same with P06 and P07).
4: The output structure of ports P20 and P21 is N-channel open-drain output when using as serial
output (it is the same as P06 and P07).
P20 : SCLK
P21 : SOUT
P22 : SIN
P23 : TIM3
P24 : TIM2
P30 : AD5
P31 : AD6
I
n
t
e
r
n
a
l
c
i
r
c
u
i
t
P
5
2
–
P
5
5
P
5
0
,
P
5
1
I
n
t
e
r
n
a
l
c
i
r
c
u
i
t
P
o
r
t
s
P
0
6
,
P
0
7
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
D
a
t
a
b
u
s
CMOS input
Ports P50, P51
Note : Each pin is also used
as follows :
P50 : HSYNC
P51 : VSYNC
Fig. 7.2 I/O Pin Block Diagram (2)
CMOS output
Ports P52–P55
Note : Each pin is also used
as follows :
P52 : R
P53 : G
P54 : B
P55 : OUT1
N-channel open-drain output
Ports P06, P07
Note :Each port is also used
as follows :
P06 : INT2/AD4
P07 : INT1
10
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.4
11
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8. FUNCTIONAL DESCRIPTION
8.1 CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses the standard 740 Family instruction set.
Refer to the table of 740 Family addressing modes and machine
instructions or the SERIES 740 <Software> User’s Manual for de-
tails on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
8.1.1 CPU Mode Register
The CPU mode register contains the stack page selection bit and
internal system clock selection bit. The CPU mode register is allo-
cated at address 00FB16.
Fig. 8.1.1 CPU Mode Register
b
7b
6 b
5b
4b
3 b
2b
1b
0
B
A
f
t
e
r
r
e
s
e
t
RW
C
P
U
M
o
d
e
R
e
g
i
s
t
e
r
0
,
1
2
3
,
4
0
1
N
a
m
eF
u
n
c
t
i
o
n
s
P
r
o
c
e
s
s
o
r
m
o
d
e
b
i
t
s
(
C
M
0
,
C
M
1
)0
0
:
S
i
n
g
l
e
-
c
h
i
p
m
o
d
e
0
1
:
1
0
:
N
o
t
a
v
a
i
l
a
b
l
e
1
1
:
F
i
x
t
h
e
s
e
b
i
t
s
t
o
“
1
.
”
1
S
t
a
c
k
p
a
g
e
s
e
l
e
c
t
i
o
n
b
i
t
(
C
M
2
) (
S
e
e
n
o
t
e
)
1
b
1
b
0
0
:
0
p
a
g
e
1
:
1
p
a
g
e
1
0
0
5
1
6
0
M
a
i
n
C
l
o
c
k
(
X
I
N
–
X
O
U
T
)
s
t
o
p
b
i
t
(
C
M
6
)
C
P
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m
o
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s
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r
(
C
M
)
[
A
d
d
r
e
s
s
0
0
F
B
1
6
]
R
W
RW
R
W
R
W
RW
X
C
O
U
T
d
r
i
v
a
b
i
l
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y
s
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c
t
i
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n
b
i
t
(
C
M
5
) 0
:
L
O
W
d
r
i
v
e
1
:
H
I
G
H
d
r
i
v
e
0
:
O
s
c
i
l
l
a
t
i
n
g
1
:
S
t
o
p
p
e
d
7
0
I
n
t
e
r
n
a
l
s
y
s
t
e
m
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
(
C
M
7
)
RW
0
:
X
I
N
–
X
O
U
T
s
e
l
e
c
t
e
d
(
h
i
g
h
-
s
p
e
e
d
m
o
d
e
)
1
:
X
C
I
N
–
X
C
O
U
T
s
e
l
e
c
t
e
d
(
h
i
g
h
-
s
p
e
e
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m
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e
)
N
o
t
e
:
T
h
i
s
b
i
t
i
s
s
e
t
t
o
“
1
”
a
f
t
e
r
t
h
e
r
e
s
e
t
r
e
l
e
a
s
e
.
8.2 MEMORY
8.2.1 Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
8.2.2 RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
8.2.3 ROM
ROM is used for storing user programs as well as the interrupt vector
area.
8.2.4 OSD RAM
RAM for display is used for specifying the character codes and col-
ors to display.
8.2.5 OSD ROM
ROM for display is used for storing character data.
8.2.6 Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
8.2.7 Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
8.2.8 Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the spe-
cial page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
8.2.9 ROM Correction Memory (RAM)
This is used as the program area for ROM correction.
Fig. 8.2.1 Memory Map (M37272M6/M8-XXXSP/FP, M37272E8SP/FP)
0
0
0
0
1
6
0
0
C
0
1
6
0
0
F
F
1
6
0
8
7
F
1
6
S
F
R
1
a
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a
N
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F
F
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1
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1
6
F
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0
0
1
6
0
8
0
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1
6
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0
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1
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2
:
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2
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0
5
3
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M
3
7
2
7
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6
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8
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6
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X
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S
P
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(
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2
4
b
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s
)
M
3
7
2
7
2
M
8
-
X
X
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S
P
/
F
P
,
M
3
7
2
7
2
E
8
S
P
/
F
P
R
A
M
(
1
1
5
2
b
y
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s
)
■ M
3
7
2
7
2
M
6
/
M
8
-
X
X
X
S
P
/
F
P
,
M
3
7
2
7
2
E
8
S
P
/
F
P
12
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.4
13
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.2.2 Memory Map (M37272MA-XXXSP, M37272EFSP)
0
0
0
0
1
6
0
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0
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Fig. 8.2.3 Memory Map of Special Function Register 1 (SFR1) (1)
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0
01
6
14
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.4
15
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.2.4 Memory Map of Special Function Register 1 (SFR1) (2)
F
01
6
F
11
6
F
21
6
F
31
6
F
41
6
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51
6
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61
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71
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81
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31
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41
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51
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(
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4
(
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1
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16
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.2.5 Memory Map of Special Function Register 2 (SFR2)
2
0
0
1
6
2
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1
1
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2
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(
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6
17
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.2.6 Internal State of Processor Status Register and Program Counter at Reset
b
7b
0b
7b
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1
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0
18
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
8.3 INTERRUPTS
Interrupts can be caused by 17 different sources consisting of 4 ex-
ternal, 11 internal, 1 software, and reset. Interrupts are vectored in-
terrupts with priorities as shown in Table 8.3.1. Reset is also included
in the table because its operation is similar to an interrupt.
When an interrupt is accepted,
①The contents of the program counter and processor status regis-
ter are automatically stored into the stack.
➁The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
➂The jump destination address stored in the vector address enters
the program counter.
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figures 8.3.2 to 8.3.6 show the
interrupt-related registers.
Interrupts other than the BRK instruction interrupt and reset are ac-
cepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority .
Figure 8.3.1 shows interrupt control.
8.3.1 Interrupt Causes
(1) VSYNC, OSD interrupts
The VSYNC interrupt is an interrupt request synchronized with
the vertical sync signal.
The OSD interrupt occurs after character block display to the
CRT is completed.
(2) INT1 to INT3 external interrupts
The INT1 to INT3 interrupts are external interrupt inputs, the sys-
tem detects that the level of a pin changes from LOW to HIGH or
from HIGH to LOW, and generates an interrupt request. The in-
put active edge can be selected by bits 3 to 5 of the interrupt
input polarity register (address 00DC16) : when this bit is “0,” a
change from LOW to HIGH is detected; when it is “1,” a change
from HIGH to LOW is detected. Note that both bits are cleared to
“0” at reset.
(3) Timers 1 to 4 interrupts
An interrupt is generated by an overflow of timers 1 to 4.
V ector Addresses
FFFF16, FFFE16
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF716, FFF616
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
FFE916, FFE816
FFE716, FFE616
FFE516, FFE416
FFE316, FFE216
FFDF16, FFDE16
Interrupt Source
Reset
OSD interrupt
INT1 external interrupt
Data slicer interrupt
Serial I/O interrupt
Timer 4 interrupt
f(XIN)/4096 interrupt
VSYNC interrupt
Timer 3 interrupt
Timer 2 interrupt
Timer 1 interrupt
INT3 external interrupt
INT2 external interrupt
Multi-master I2C-BUS interface interrupt
Timer 5 • 6 interrupt
BRK instruction interrupt
Remarks
Non-maskable
Active edge selectable
Active edge selectable
Active edge selectable
Source switch by software (see note)
Non-maskable
Table 8.3.1 Interrupt Vector Addresses and Priority
Note: Switching a source during a program causes an unnecessary interrupt. Therefore, set a source at initializing of program.
19
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial I/O
function.
(5) f(XIN)/4096 interrupt
The f (XIN)/4096 interrupt occurs regularly with a f(XIN)/4096 pe-
riod. Set bit 0 of the PWM mode register 1 to “0.”
(6) Data slicer interrupt
An interrupt occurs when slicing data is completed.
(7) Multi-master I2C-BUS interface interrupt
This is an interrupt request related to the multi-master I2C-BUS
interface.
(8) Timer 5 • 6 interrupt
An interrupt is generated by an overflow of timer 5 or 6. Their
priorities are same, and can be switched by software.
(9) BRK instruction interrupt
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not af-
fected by the interrupt disable flag I (non-maskable).
Fig. 8.3.1 Interrupt Control
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
f
l
a
g
I
B
R
K
i
n
s
t
r
u
c
t
i
o
n
R
e
s
e
t
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
20
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.3.2 Interrupt Request Register 1
Fig. 8.3.3 Interrupt Request Register 2
b
7b
6 b
5b
4b
3 b
2b
1b
0I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
1
(
I
R
E
Q
1
)
[
A
d
d
r
e
s
s
0
0
F
C
1
6
]
BN
a
m
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u
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c
t
i
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n
s
A
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r
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t
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r
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u
p
t
R
e
q
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s
t
R
e
g
i
s
t
e
r
1
00
:
N
o
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
e
d
1
:
I
n
t
e
r
r
u
p
t
r
e
q
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e
s
t
i
s
s
u
e
d
T
i
m
e
r
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
(
T
M
1
R
)
1T
i
m
e
r
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
(
T
M
2
R
)
2T
i
m
e
r
3
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
(
T
M
3
R
)
3T
i
m
e
r
4
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
(
T
M
4
R
)
4O
S
D
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
(
O
S
D
R
)
5V
S
Y
N
C
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
(
V
S
C
R
)
6I
N
T
3
e
x
t
e
r
n
a
l
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
(
V
S
C
R
)
7
0
:
N
o
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
e
d
1
:
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
e
d
0
:
N
o
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
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d
1
:
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
e
d
0
:
N
o
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
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d
1
:
I
n
t
e
r
r
u
p
t
r
e
q
u
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s
t
i
s
s
u
e
d
0
:
N
o
i
n
t
e
r
r
u
p
t
r
e
q
u
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s
t
i
s
s
u
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d
1
:
I
n
t
e
r
r
u
p
t
r
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q
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s
t
i
s
s
u
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d
0
:
N
o
i
n
t
e
r
r
u
p
t
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q
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s
t
i
s
s
u
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d
1
:
I
n
t
e
r
r
u
p
t
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q
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s
t
i
s
s
u
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d
0
:
N
o
i
n
t
e
r
r
u
p
t
r
e
q
u
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s
t
i
s
s
u
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d
1
:
I
n
t
e
r
r
u
p
t
r
e
q
u
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s
t
i
s
s
u
e
d0
0✽
0✽
0✽
0✽
0✽
0✽
0✽
✽:
“
0
”
c
a
n
b
e
s
e
t
b
y
s
o
f
t
w
a
r
e
,
b
u
t
“
1
”
c
a
n
n
o
t
b
e
s
e
t
.
—
R
R
R
R
R
R
R
R
N
o
t
h
i
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g
i
s
a
s
s
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n
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d
.
T
h
i
s
b
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i
s
a
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r
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d
i
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a
b
l
e
b
i
t
.
W
h
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n
t
h
i
s
b
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r
e
a
d
o
u
t
,
t
h
e
v
a
l
u
e
i
s
“
0
.
”
b
7b
6
b
5b
4b
3 b
2b
1b
0I
n
t
e
r
r
u
p
t
r
e
q
u
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s
t
r
e
g
i
s
t
e
r
2
(
I
R
E
Q
2
)
[
A
d
d
r
e
s
s
0
0
F
D
BN
a
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u
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c
t
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n
sA
f
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q
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2
0I
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1
e
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b
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(
I
N
I
R
)0
:
N
o
i
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t
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r
r
u
p
t
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q
u
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s
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d
1
:
I
n
t
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r
r
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p
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q
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t
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s
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d
1D
a
t
a
s
l
i
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r
i
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t
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r
r
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q
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b
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t
(
D
S
R
)
2S
e
r
i
a
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I
/
O
i
n
t
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r
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q
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b
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t
(
S
1
R
)
3
4I
N
T
2
e
x
t
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n
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t
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(
I
N
2
R
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5
7F
i
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t
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i
s
b
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t
t
o
“
0
.
”
0
0
:
N
o
i
n
t
e
r
r
u
p
t
r
e
q
u
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s
t
i
s
s
u
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d
1
:
I
n
t
e
r
r
u
p
t
r
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q
u
e
s
t
i
s
s
u
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d
0
:
N
o
i
n
t
e
r
r
u
p
t
r
e
q
u
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s
t
i
s
s
u
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d
1
:
I
n
t
e
r
r
u
p
t
r
e
q
u
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s
t
i
s
s
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d
0
✽:
“
0
”
c
a
n
b
e
s
e
t
b
y
s
o
f
t
w
a
r
e
,
b
u
t
“
1
”
c
a
n
n
o
t
b
e
s
e
t
.
0
0✽
0
0✽
0✽
0✽
0
:
N
o
i
n
t
e
r
r
u
p
t
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q
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s
t
i
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s
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d
1
:
I
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t
e
r
r
u
p
t
r
e
q
u
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t
i
s
s
u
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d
1
6]
R
R
R
R✽
R
R✽
R
W
f
(
XI
N)
/
4
0
9
6
i
n
t
e
r
r
u
p
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r
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q
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e
s
t
b
i
t
(
C
K
R
)0
:
N
o
i
n
t
e
r
r
u
p
t
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q
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s
t
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s
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d
1
:
I
n
t
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r
r
u
p
t
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e
q
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s
t
i
s
s
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d
M
u
l
t
i
-
m
a
s
t
e
r
I2C
-
B
U
S
i
n
t
e
r
r
u
p
t
r
e
q
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s
t
b
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t
(
I
I
C
R
)0
:
N
o
i
n
t
e
r
r
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p
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1
:
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n
t
e
r
r
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p
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q
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d
6
T
i
m
e
r
5
•
6
i
n
t
e
r
r
u
p
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e
q
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t
b
i
t
(
T
M
5
6
R
)0
:
N
o
i
n
t
e
r
r
u
p
t
r
e
q
u
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s
t
i
s
s
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d
1
:
I
n
t
e
r
r
u
p
t
r
e
q
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s
t
i
s
s
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d
0
✽
R
21
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.3.4 Interrupt Control Register 1
b
7b
6 b
5b
4b
3 b
2b
1b
0I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
I
C
O
N
1
)
[
A
d
d
r
e
s
s
0
0
F
E
1
6
]
BN
a
m
eF
u
n
c
t
i
o
n
s
A
f
t
e
r
r
e
s
e
t
RW
I
n
t
e
r
r
u
p
t
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
1
0T
i
m
e
r
1
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
(
T
M
1
E
)0
:
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
d
1
:
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
d
1T
i
m
e
r
2
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
(
T
M
2
E
)
2T
i
m
e
r
3
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
(
T
M
3
E
)
3
4O
S
D
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
(
O
S
D
E
)
0
:
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
d
1
:
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
d
0
:
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
d
1
:
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
d
0
:
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
d
1
:
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
d
0
0
0
0
0
0RW
RW
RW
RW
RW
R—
7
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
T
h
i
s
b
i
t
i
s
a
w
r
i
t
e
d
i
s
a
b
l
e
b
i
t
.
W
h
e
n
t
h
i
s
b
i
t
i
s
r
e
a
d
o
u
t
,
t
h
e
v
a
l
u
e
i
s
“
0
.
”
T
i
m
e
r
4
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
(
T
M
4
E
)0
:
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
d
1
:
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
d
5
V
S
Y
N
C
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
(
V
S
C
E
)0
:
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
d
1
:
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
d0RW
6
I
N
T
3
e
x
t
e
r
n
a
l
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
(
I
N
3
E
)0
:
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
d
1
:
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
d0RW
Fig. 8.3.5 Interrupt Control Register 2
b
7b
6 b
5b
4b
3 b
2b
1b
0I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
I
C
O
N
2
)
[
A
d
d
r
e
s
s
0
0
F
F
1
6
]
BN
a
m
eF
u
n
c
t
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22
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.3.6 Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt input polarity register (RE) [Address 00DC
16
]
B Name Functions After reset R W
Interrupt Input Polarity Register
INT1 polarity switch bit
(INT1)
0
0
0
0 : Positive polarity
1 : Negative polarity
0
4
0 : Positive polarity
1 : Negative polarity
5
4
to
7
INT2 polarity switch bit
(INT2)
INT3 polarity switch bit
(INT3)
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
0RW
RW
RW
R—
0 : Positive polarity
1 : Negative polarity
23
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.4 TIMERS
This microcomputer has 6 timers: timer 1, timer 2, timer 3, timer 4,
timer 5, and timer 6. All timers are 8-bit timers with the 8-bit timer
latch. The timer block diagram is shown in Figure 8.4.3.
All of the timers count down and their divide ratio is 1/(n+1), where n
is the value of timer latch. By writing a count value to the correspond-
ing timer latch (addresses 00F016 to 00F316 : timers 1 to 4, addresses
00EE16 and 00EF16 : timers 5 and 6), the value is also set to a timer ,
simultaneously.
The count value is decremented by 1. The timer interrupt request bit
is set to “1” by a timer overflow at the next count pulse, after the
count value reaches “0016”.
8.4.1 Timer 1
Timer 1 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• f(XIN)/4096 or f(XCIN)/4096
• External clock from the TIM2 pin
The count source of timer 1 is selected by setting bits 5 and 0 of
timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register.
Timer 1 interrupt request occurs at timer 1 overflow.
8.4.2 Timer 2
Timer 2 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• Timer 1 overflow signal
• External clock from the TIM2 pin
The count source of timer 2 is selected by setting bits 4 and 1 of
timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register. When timer 1 overflow
signal is a count source for the timer 2, the timer 1 functions as an 8-
bit prescaler.
Timer 2 interrupt request occurs at timer 2 overflow.
8.4.3 Timer 3
Timer 3 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• f(XCIN)
• External clock from the TIM3 pin
The count source of timer 3 is selected by setting bit 0 of timer mode
register 2 (address 00F516) and bit 6 at address 00C716. Either f(XIN)
or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer 3 interrupt request occurs at timer 3 overflow.
8.4.4 Timer 4
Timer 4 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• f(XIN)/2 or f(XCIN)/2
• f(XCIN)
The count source of timer 3 is selected by setting bits 1 and 4 of the
timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register. When timer 3 overflow
signal is a count source for the timer 4, the timer 3 functions as an 8-
bit prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.
8.4.5 Timer 5
Timer 5 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• Timer 2 overflow signal
• Timer 4 overflow signal
The count source of timer 3 is selected by setting bit 6 of timer mode
register 1 (address 00F416) and bit 7 of the timer mode register 2
(address 00F516). When overflow of timer 2 or 4 is a count source
for timer 5, either timer 2 or 4 functions as an 8-bit prescaler. Either
f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer 5 interrupt request occurs at timer 5 overflow.
8.4.6 Timer 6
Timer 6 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• Timer 5 overflow signal
The count source of timer 6 is selected by setting bit 7 of the timer
mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected
by bit 7 of the CPU mode register. When timer 5 overflow signal is a
count source for timer 6, the timer 5 functions as an 8-bit prescaler.
Timer 6 interrupt request occurs at timer 6 overflow.
At reset, timers 3 and 4 are connected by hardware and “FF16” is
automatically set in timer 3; “0716” in timer 4. The f(XIN) ✽ /16 is se-
lected as the timer 3 count source. The internal reset is released by
timer 4 overflow in this state and the internal clock is connected.
At execution of the STP instruction, timers 3 and 4 are connected by
hardware and “FF16” is automatically set in timer 3; “0716” in timer 4.
However , the f(XIN) ✽ /16 is not selected as the timer 3 count source.
So set both bit 0 of timer mode register 2 (address 00F516) and bit 6
at address 00C716 to “0” before the execution of the STP instruction
(f(XIN) ✽ /16 is selected as timer 3 count source). The internal STP
state is released by timer 4 overflow in this state and the internal
clock is connected.
As a result of the above procedure, the program can start under a
stable clock.
✽: When bit 7 of the CPU mode register (CM7) is “1,” f(XIN) becomes
f(XCIN).
The timer-related registers is shown in Figures 8.4.1 and 8.4.2.
24
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.4.2 Timer Mode Register 2
b7b6 b5b4b3 b2b1b0 Timer mode register 2 (TM2) [Address 00F5
16
]
B
After reset
RW
Timer Mode Register 2
0Name Functions
Timer 3 count source
selection bit (TM20) 0RW
1, 4 Timer 4 count source
selection bits
(TM21, TM24)
0RW
2
3
0
Timer 3 count
stop bit (TM22) 0: Count start
1: Count stop
Timer 4 count stop bit
(TM23) 0: Count start
1: Count stop 0
0
5Timer 5 count stop bit
(TM25) 0: Count start
1: Count stop 0
6Timer 6 count stop bit
(TM26) 0: Count start
1: Count stop 0
RW
RW
RW
RW
RW
7Timer 5 count source
selection bit 1
(TM27)
0: f(X
IN
)/16 or f(X
CIN
)/16 (See note)
1: Count source selected by bit 6
of TM1
b0
0 0 : f(X
IN
)/16 or f(X
CIN
)/16 (See note)
0 1 : f(X
CIN
)
1 0 :
11 :
(b6 at address 00C7
16
)
External clock from TIM3 pin
b4 b1
0 0 : Timer 3 overflow signal
0 1 : f(X
IN
)/16 or f(X
CIN
)/16 (See note)
1 0 : f(X
IN
)/2 or f(X
CIN
)/2 (See note)
1 1 : f(X
CIN
)
Note: Either f(X
IN
) or f(X
CIN
) is selected by bit 7 of the CPU mode register.
Fig. 8.4.1 Timer Mode Register 1
b7b6 b5b4b3 b2b1b0 Timer mode register 1 (TM1) [Address 00F4 16]
BAfter reset W
Timer Mode Register 1
0
1
2
3
4
Name Functions
Timer 1 count source
selection bit 1 (TM10) 0: f(XIN)/16 or f(XCIN)/16 (See note)
1: Count source selected by bit 5 of TM1
Timer 2 count source
selection bit 1 (TM11) 0: Count source selected by bit 4 of TM1
1: External clock from TIM2 pin
Timer 1 count
stop bit (TM12) 0: Count start
1: Count stop
Timer 2 count stop
bit (TM13) 0: Count start
1: Count stop
Timer 2 count source
selection bit 2
(TM14)
R
0
0
0
0
0
WR
WR
WR
WR
WR
0: f(XIN)/16 or f(XCIN)/16 (See note)
1: Timer 1 overflow
5Timer 1 count source
selection bit 2 (TM15) 0: f(XIN)/4096 or f(XCIN)/4096 (See note)
1: External clock from TIM2 pin 0WR
6Timer 5 count source
selection bit 2 (TM16) 0: Timer 2 overflow
1: Timer 4 overflow 0WR
7 Timer 6 internal count
source selection bit
(TM17)
0WR0: f(XIN)/16 or f(XCIN)/16 (See note)
1: Timer 5 overflow
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
25
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.4.3 Timer Block Diagram
Timer 1 (8)
1/4096
1/2
CM7 TM15
1/8
Timer 1 latch (8)
8
8
8
TM10TM12
TM14
TM11TM13
Timer 2 (8)
Timer 2 latch (8)
8
8
8
Timer 3 (8)
Timer 3 latch (8)
8
8
8
Timer 4 (8)
Timer 4 latch (8)
8
8
8
Timer 5 (8)
Timer 5 latch (8)
8
8
8
Timer 6 (8)
Timer 6 latch (8)
8
8
8
Data bus
Timer 1
interrupt request
Timer 2
interrupt request
Timer 3
interrupt request
Reset
STP instruction
TM20TM22
T3SC
Timer 4
interrupt request
TM24TM23
TM21
TM16
Timer 5
interrupt request
TM27TM25
Timer 6
interrupt request
TM17TM26
TM21
XCIN
XIN
TIM2
TIM3
Selection gate: Connected to
black side at
reset
TM1 : Timer mode register 1
TM2 : Timer mode register 2
T3SC : Timer 3 count source
switch bit (address 00C716)
CM : CPU mode register
Notes 1: HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more.
2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal.
FF16
0716
3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
26
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8
Serial I/O shift register (8)
Data bus
Serial I/O
interrupt request
Selection gate: Connect to
black side at
reset.
Synchronous
circuit
Frequency divider
1/81/4 1/16
SM1
SM0
Serial I/O counter (8)
SM5
: LSB MSB
S
SM2
1/2
X
IN
S
IN
S
OUT
S
CLK
1/2
X
CIN
1/2
CM7
1/2
Note : When the data is set in the serial I/O register (address 00EA
(See note)
CM : CPU mode register
SM : Serial I/O mode register
16
), the register functions as the serial I/O shift register.
P2
0
Latch
SM3
P2
1
Latch
SM3
SM6
8.5 SERIAL I/O
This microcomputer has a built-in serial I/O which can either transmit
or receive 8-bit data serially in the clock synchronous mode.
The serial I/O block diagram is shown in Figure 8.5.1. The synchro-
nous clock I/O pin (SCLK), and data output pin (SOUT) also function
as port P4, data input pin (SIN) also functions as port P20–P22.
Bit 3 of the serial I/O mode register (address 00EB16) selects whether
the synchronous clock is supplied internally or externally (from the
SCLK pin). When an internal clock is selected, bits 1 and 0 select
whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use the SIN
pin for serial I/O, set the corresponding bit of the port P2 direction
register (address 00C516) to “0.”
Fig. 8.5.1 Serial I/O Block Diagram
The operation of the serial I/O is described below. The operation of
the serial I/O differs depending on the clock source; external clock or
internal clock.
27
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Internal clock : The serial I/O counter is set to “7” during the write
cycle into the serial I/O register (address 00EA16), and the transfer
clock goes HIGH forcibly. At each falling edge of the transfer clock
after the write cycle, serial data is output from the SOUT pin. T ransfer
direction can be selected by bit 5 of the serial I/O mode register. At
each rising edge of the transfer clock, data is input from the SIN pin
and data in the serial I/O register is shifted 1 bit.
After the transfer clock has counted 8 times, the serial I/O counter
becomes “0” and the transfer clock stops at HIGH. At this time the
interrupt request bit is set to “1.”
Fig. 8.5.2 Serial I/O Timing (for LSB first)
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the interrupt request is set to “1” after the transfer clock has been
counted 8 counts. However , transfer operation does not stop, so the
clock should be controlled externally . Use the external clock of 1 MHz
or less with a duty cycle of 50%.
The serial I/O timing is shown in Figure 8.5.2. When using an exter-
nal clock for transfer, the external clock must be held at HIGH for
initializing the serial I/O counter. When switching between an inter-
nal clock and an external clock, do not switch during transfer. Also,
be sure to initialize the serial I/O counter after switching.
Notes 1: On programming, note that the serial I/O counter is set by writing to
the serial I/O register with the bit managing instructions, such as SEB
and CLB.
2:When an external clock is used as the synchronous clock, write trans-
mit data to the serial I/O register when the transfer clock input level is
HIGH.
28
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.5.3 Serial I/O Mode Register
b
7b
6 b
5b
4b
3 b
2b
1b
0S
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(
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:
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,
P
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:
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C
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K
,
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k
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L
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s
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“
0
.
”
0
0
0
0
0
0
T
r
a
n
s
f
e
r
c
l
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c
k
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p
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b
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(
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:
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n
p
u
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g
n
a
l
f
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m
S
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p
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:
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n
p
u
t
s
i
g
n
a
l
f
r
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m
S
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p
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RW
RW
R
W
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RW
0
7F
i
x
t
h
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s
b
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o
“
0
.
”0R
W
29
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Function
In conformity with Philips I2C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I2C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at φ
= 4 MHz)
Table 8.6.1 Multi-master I2C-BUS Interface Functions
Item
Format
Communication mode
SCL clock frequency
φ
: System clock = f(XIN)/2
Note :We are not responsible for any third party’s infringement of patent rights
or other rights attributable to the use of the control function (bits 6 and 7
of the I2C control register at address 00F916) for connections between
the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).
8.6 MULTI-MASTER I2C-BUS INTERFACE
The multi-master I2C-BUS interface is a serial communications cir-
cuit, conforming to the Philips I2C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
Figure 8.6.1 shows a block diagram of the multi-master I2C-BUS in-
terface and Table 8.6.1 shows multi-master I2C-BUS interface func-
tions.
This multi-master I2C-BUS interface consists of the I2C address reg-
ister , the I2C data shift register, the I2C clock control register , the I2C
control register, the I2C status register and other control circuits.
Fig. 8.6.1 Block Diagram of Multi-master I2C-BUS Interface
I
2
C address register (S0D)
b7 b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Noise
elimination
circuit
Serial
data
(SDA)
Address comparator
b7
I C data shift register
b0
Data
control
circuit
I
2
C clock control register (S2)
System clock
(φ)
Interrupt
generating
circuit
Interrupt
request signal
(IICIRQ)
b7
MST TRX BB PIN AL AAS AD0 LRB
b0
I C status
register
(S1)
b7 b0
BSEL1
BSEL0
10BIT
SAD ALS BC2 BC1 BC0
I
2
C control register (S1D)
Bit counter
BB
circuit
Clock
control
circuit
Noise
elimination
circuit
Serial
clock
(SCL) b7 b0
ACK ACK
BIT FAST
MODE CCR4 CCR3 CCR2 CCR1 CCR0
Internal data bus
Clock division
S0
AL
circuit
ESO
2
2
30
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.6.1 I2C Data Shift Register
The I2C data shift register (S0 : address 00F616) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register , it is transferred to the
outside from bit 7 in synchronization with the SCL clock, and each
time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0
in synchronization with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
The I2C data shift register is in a write enable status only when the
ESO bit of the I2C control register (address 00F916) is “1.” The bit
counter is reset by a write instruction to the I2C data shift register.
When both the ESO bit and the MST bit of the I2C status register
(address 00F816) are “1,” the SCL is output by a write instruction to
the I2C data shift register . Reading data from the I2C data shift regis-
ter is always enabled regardless of the ESO bit value.
Note: To write data into the I2C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
Fig. 8.6.2 Data Shift Register
b
7b
6b
5b
4b
3b
2b
1b
0
I
C
d
a
t
a
s
h
i
f
t
r
e
g
i
s
t
e
r
1
(
S
0
)
[
A
d
d
r
e
s
s
0
0
F
6
1
6
]
B
F
u
n
c
t
i
o
n
s
A
f
t
e
r
r
e
s
e
tRW
I
C
D
a
t
a
S
h
i
f
t
R
e
g
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s
t
e
r
0
t
o
7
T
h
i
s
i
s
a
n
8
-
b
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f
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2
2
N
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:
2
T
o
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M
S
T
b
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o
“
0
”
(
s
l
a
v
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m
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d
e
)
,
k
e
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a
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t
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v
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f
8
m
a
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s
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r
m
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.
N
a
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D
0
t
o
D
7RW
31
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.6.2 I2C Address Register
The I2C address register (address 00F716) consists of a 7-bit slave
address and a read/write bit. In the addressing mode, the slave ad-
dress written in this register is compared with the address data to be
received immediately after the START condition are detected.
(1) Bit 0: read/write bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode.
In the 10-bit addressing mode, the first address data to be received
is compared with the contents (SAD6 to SAD0 + RBW) of the I2C
address register.
The RBW bit is cleared to “0” automatically when the stop condition
is detected.
(2) Bits 1 to 7: slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address-
ing mode and the 10-bit addressing mode, the address data trans-
mitted from the master is compared with the contents of these bits.
Fig. 8.6.3 I2C Address Register
b
7b
6b
5b
4b
3b
2b
1b
0
0R
e
a
d
/
w
r
i
t
e
b
i
t
(
R
B
W
)
1
t
o
7
S
l
a
v
e
a
d
d
r
e
s
s
(
S
A
D
0
t
o
S
A
D
6
)
<
O
n
l
y
i
n
1
0
-
b
i
t
a
d
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r
e
s
s
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n
g
(
i
n
s
l
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)
m
o
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>
T
h
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l
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s
t
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f
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0
:
W
a
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S
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d
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n
(
r
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a
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)
1
:
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(
w
r
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)
<
I
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t
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m
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>
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p
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.
I
2
C
A
d
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r
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s
s
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g
i
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t
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r
I
2
C
a
d
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r
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s
r
e
g
i
s
t
e
r
(
S
0
D
)
[
A
d
d
r
e
s
s
0
0
F
7
1
6
]
B
N
a
m
e
F
u
n
c
t
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o
n
s
0
0
A
f
t
e
r
r
e
s
e
t
R
W
R—
R
W
32
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.6.3 I2C Clock Control Register
The I2C clock control register (address 00FA16) is used to set ACK
control, SCL mode and SCL frequency.
(1) Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency.
(2) Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the stan-
dard clock mode is set. When the bit is set to “1,” the high-speed
clock mode is set.
(3) Bit 6: ACK bit (ACK BIT)
This bit sets the SDA status when an ACK clock✽ is generated. When
this bit is set to “0,” the ACK return mode is set and SDA goes to
LOW at the occurrence of an ACK clock. When the bit is set to “1,”
the ACK non-return mode is set. The SDA is held in the HIGH status
at the occurrence of an ACK clock.
However, when the slave address matches the address data in the
reception of address data at ACK BIT = “0,” the SDA is automatically
made LOW (ACK is returned). If there is a mismatch between the
slave address and the address data, the SDA is automatically made
HIGH (ACK is not returned).
✽ACK clock: Clock for acknowledgement
Fig. 8.6.4 I2C Address Register
(4) Bit 7: ACK clock bit (ACK)
This bit specifies a mode of acknowledgment which is an acknowl-
edgment response of data transmission. When this bit is set to “0,”
the no ACK clock mode is set. In this case, no ACK clock occurs
after data transmission. When the bit is set to “1,” the ACK clock
mode is set and the master generates an ACK clock upon comple-
tion of each 1-byte data transmission.The device for transmitting
address data and control data releases the SDA at the occurrence of
an ACK clock (make SDA HIGH) and receives the ACK bit generated
by the data receiving device.
Note: Do not write data into the I2C clock control register during transmission.
If data is written during transmission, the I2C clock generator is reset, so
that data cannot be transmitted normally.
b7 b6 b5 b4 b3 b2 b1 b0
I
2
C clock control register (S2 : address 00FA
16
)
I
2
C Clock Control Register
0
to
4
SCL frequency control
bits
(CCR0 to CCR4)
7
5
6
SCL mode
specification bit
(FAST MODE)
0: Standard clock mode
1: High-speed clock mode
0
Standard clock
mode
B Name Functions
After reset
RW
0
0
0
ACK bit
(ACK BIT)
ACK clock bit
(ACK)
0: ACK is returned.
1: ACK is not returned.
0: No ACK clock
1: ACK clock
High speed
clock mode
Setup disabled Setup disabled
00 to 02
Setup disabled
33303
Setup disabled
25004 100
400 (See note)
05 83.3 16606
500/CCR value 1000/CCR value
...
17.2 34.5
1D 16.6 33.3
1E 16.1 32.3
1F (at
φ
= 4 MHz, unit : kHz)
Note: At 4000kHz in the high-speed clock mode, the duty is as below .
“0” period : “1” period = 3 : 2
In the other cases, the duty is as below.
“0” period : “1” period = 1 : 1
Setup value
of CCR4–
CCR0
RW
RW
RW
RW
33
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.6.4 I2C Control Register
The I2C control register (address 00F916) controls the data commu-
nication format.
(1) Bits 0 to 2: bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. An interrupt request signal occurs immediately after the
number of bits specified with these bits are transmitted.
When a START condition is received, these bits become “0002” and
the address data is always transmitted and received in 8 bits.
(2) Bit 3: I2C interface use enable bit (ESO)
This bit enables usage of the multimaster I2C BUS interface. When
this bit is set to “0,” the use disable status is provided, so the SDA
and the SCL become high-impedance. When the bit is set to “1,” use
of the interface is enabled.
When ESO = “0,” the following is performed.
• PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I 2C
status register at address 00F816 ).
• Writing data to the I2C data shift register (address 00F616) is dis-
abled.
(3) Bit 4: data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses. When
this bit is set to “0,” the addressing format is selected, so that ad-
dress data is recognized. When a match is found between a slave
address and address data as a result of comparison or when a gen-
eral call (refer to “8.6.5 I2C Status Register ,” bit 1) is received, trans-
mission processing can be performed. When this bit is set to “1,” the
free data format is selected, so that slave addresses are not recog-
nized.
(4) Bit 5: addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is
set to “0,” the 7-bit addressing format is selected. In this case, only
the high-order 7 bits (slave address) of the I2C address register (ad-
dress 00F716) are compared with address data. When this bit is set
to “1,” the 10-bit addressing format is selected, all the bits of the I2C
address register are compared with address data.
(5) Bits 6 and 7: connection control bits between
I2C-BUS interface and ports
(BSEL0, BSEL1)
These bits controls the connection between SCL and ports or SDA
and ports (refer to Figure 8.6.5).
Fig. 8.6.5 Connection Port Control by BSEL0 and BSEL1
Note: Set the corresponding direction register to “1” to use the
port as multi-master I2C-BUS interface.
“
0
”
“
1
”
B
S
E
L
0S
C
L
/
P
1
1
S
C
L
2
/
P
1
2
“
0
”
“
1
”
B
S
E
L
1
“
0
”
“
1
”
B
S
E
L
0S
D
A
1
/
P
1
3
S
D
A
2
/
P
1
4
“
0
”
“
1
”
B
S
E
L
1
M
u
l
t
i
-
m
a
s
t
e
r
I
2
C
-
B
U
S
i
n
t
e
r
f
a
c
e
S
C
L
S
D
A
34
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.6.6 I2C Control Register
b
7b
6b
5b
4b
3b
2b
1b
0
0
t
o
2
B
i
t
c
o
u
n
t
e
r
(
N
u
m
b
e
r
o
f
t
r
a
n
s
m
i
t
/
r
e
c
i
e
v
e
b
i
t
s
)
(
B
C
0
t
o
B
C
2
)
b
2
b
1
b
0
0
0
0
:
8
0
0
1
:
7
0
1
0
:
6
0
1
1
:
5
1
0
0
:
4
1
0
1
:
3
1
1
0
:
2
1
1
1
:
1
3I2C
-
B
U
S
i
n
t
e
r
f
a
c
e
u
s
e
e
n
a
b
l
e
b
i
t
(
E
S
O
)0
:
D
i
s
a
b
l
e
d
1
:
E
n
a
b
l
e
d
4D
a
t
a
f
o
r
m
a
t
s
e
l
e
c
t
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o
n
b
i
t
(
A
L
S
)0
:
A
d
d
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e
s
s
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n
g
m
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e
1
:
F
r
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d
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t
a
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a
t
5A
d
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s
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f
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m
a
t
s
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l
e
c
t
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b
i
t
(
1
0
B
I
T
S
A
D
)0
:
7
-
b
i
t
a
d
d
r
e
s
s
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g
f
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m
a
t
1
:
1
0
-
b
i
t
a
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r
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s
s
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f
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6
,
7
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r
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b
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6
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(
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0
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:
N
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0
1
:
S
C
L
1
,
S
D
A
1
1
0
:
S
C
L
2
,
S
D
A
2
1
1
:
S
C
L
1
,
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D
A
1
S
C
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2
,
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D
A
2
0
0
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35
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.6.5 I2C Status Register
The I2C status register (address 00F816) controls the I2C-BUS inter-
face status. The low-order 4 bits are read-only bits and the high-
order 4 bits can be read out and written to.
(1) Bit 0: last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an ACK
clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is
set to “1.” Except in the ACK mode, the last bit value of received data
is input. The state of this bit is changed from “1” to “0” by executing a
write instruction to the I2C data shift register (address 00F616).
(2) Bit 1: general call detecting flag (AD0)
This bit is set to “1” when a general call✽ whose address data is all
“0” is received in the slave mode. By a general call of the master
device, every slave device receives control data after the general
call. The AD0 bit is set to “0” by detecting the STOP condition or
START condition.
✽General call: The master transmits the general call address “0016”
to all slaves.
(3) Bit 2: slave address comparison flag (AAS)
This flag indicates a comparison result of address data.
■In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions.
• The address data immediately after occurrence of a ST ART con-
dition matches the slave address stored in the high-order 7 bits
of the I2C address register (address 00F716).
• A general call is received.
■ In the slave reception mode, when the 10-bit addressing format is
selected, this bit is set to “1” with the following condition.
• When the address data is compared with the I2C address regis-
ter (8 bits consists of slave address and RBW), the first bytes
match.
■ The state of this bit is changed from “1” to “0” by executing a write
instruction to the I2C data shift register (address 00F616).
(4) Bit 3: arbitration lost✽ detecting flag (AL)
n the master transmission mode, when a device other than the mi-
crocomputer sets the SDA to “L,”, arbitration is judged to have been
lost, so that this bit is set to “1.” At the same time, the TRX bit is set to
“0,” so that immediately after transmission of the byte whose arbitra-
tion was lost is completed, the MST bit is set to “0.” When arbitration
is lost during slave address transmission, the TRX bit is set to “0” and
the reception mode is set. Consequently, it becomes possible to re-
ceive and recognize its own slave address transmitted by another
master device.
✽Arbitration lost: The status in which communication as a master is
disabled.
(5) Bit 4: I
2
C-BUS interface interrupt request bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte data
is transmitted, the state of the PIN bit changes from “1” to “0.” At the
same time, an interrupt request signal is sent to the CPU. The PIN bit
is set to “0” in synchronization with a falling edge of the last clock
(including the ACK clock) of an internal clock and an interrupt re-
quest signal occurs in synchronization with a falling edge of the PIN
bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock
generation is disabled. Figure 8.6.8 shows an interrupt request sig-
nal generating timing chart.
The PIN bit is set to “1” in any one of the following conditions.
• Executing a write instruction to the I2C data shift register (address
00F616).
• When the ESO bit is “0”
• At reset
The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (includ-
ing when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after
completion of slave address or general call address reception
• In the slave reception mode, with ALS = “1” and immediately after
completion of address data reception
(6) Bit 5: bus busy flag (BB)
This bit indicates the status of use of the bus system. When this bit is
set to “0,” this bus system is not busy and a START condition can be
generated. When this bit is set to “1,” this bus system is busy and the
occurrence of a ST AR T condition is disabled by the ST ART condition
duplication prevention function (See note).
This flag can be written by software only in the master transmission
mode. In the other modes, this bit is set to “1” by detecting a START
condition and set to “0” by detecting a STOP condition. When the
ESO bit of the I2C control register (address 00F916) is “0” and at
reset, the BB flag is kept in the “0” state.
(7) Bit 6: communication mode specification bit
(transfer direction specification bit: TRX)
This bit decides the direction of transfer for data communication. When
this bit is “0,” the reception mode is selected and the data of a trans-
mitting device is received. When the bit is “1,” the transmission mode
is selected and address data and control data are output into the
SDA in synchronization with the clock generated on the SCL.
When the ALS bit of the I2C control register (address 00F916) is “0” in
the slave reception mode is selected, the TRX bit is set to “1” (trans-
mit) if the least significant bit (R/W bit) of the address data transmit-
ted by the master is “1.” When the ALS bit is “0” and the R/W bit is
“0,” the TRX bit is cleared to “0” (receive).
The TRX bit is cleared to “0” in one of the following conditions.
• When arbitration lost is detected.
• When a STOP condition is detected.
• When occurence of a STAR T condition is disabled by the START
condition duplication prevention function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
36
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
(8) Bit 7: Communication mode specification bit
(master/slave specification bit: MST)
This bit is used for master/slave specification for data communica-
tion. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are received,
and data communication is performed in synchronization with the
clock generated by the master. When this bit is “1,” the master is
specified and a START condition and a STOP condition are gener-
ated, and also the clocks required for data communication are gen-
erated on the SCL.
The MST bit is cleared to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transmission when
arbitration lost is detected
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START
condition duplication preventing function (Note).
• At reset
Fig. 8.6.7 I2C Status Register
b
7b
6b
5b
4b
3b
2b
1b
0
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R—
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(
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(
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Fig. 8.6.8 Interrupt Request Signal Generation Timing
S
C
L
P
I
N
I
I
C
I
R
Q
Note:The ST ART condition duplication prevention function disables the ST ART
condition generation, reset of bit counter reset, and SCL output, when
the following condition is satisfied:
a START condition is set by another master device.
37
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.6.6 START Condition Generation Method
When the ESO bit of the I2C control register (address 00F916) is “1,”
execute a write instruction to the I2C status register (address 00F816)
to set the MST, TRX and BB bits to “1.” A START condition will then
be generated. After that, the bit counter becomes “0002” and an SCL
for 1 byte is output. The START condition generation timing and BB
bit set timing are different in the standard clock mode and the high-
speed clock mode. Refer to Figure 8.6.9 for the START condition
generation timing diagram, and Table 8.6.2 for the ST AR T condition/
STOP condition generation timing table.
Fig. 8.6.9 START Condition Generation Timing Diagram
I2C
s
t
a
t
u
s
r
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f
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r
B
B
f
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8.6.7 STOP Condition Generation Method
When the ESO bit of the I2C control register (address 00F916) is “1,”
execute a write instruction to the I2C status register (address 00F816)
for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A
STOP condition will then be generated. The STOP condition genera-
tion timing and the BB flag reset timing are different in the standard
clock mode and the high-speed clock mode. Refer to Figure 8.6.10
for the STOP condition generation timing diagram, and Table 8.6.2
for the START condition/STOP condition generation timing table.
Fig. 8.6.10 STOP Condition Generation Timing Diagram
Table 8.6.2 START Condition/STOP Condition Generation Tim-
ing Table
Item
Setup time
(START condition)
Setup time
(STOP condition)
Hold time
Set/reset time
for BB flag
Standard Clock Mode
5.0 µs (20 cycles)
4.25 µs (17 cycles)
5.0 µs (20 cycles)
3.0 µs (12 cycles)
High-speed Clock Mode
2.5 µs (10 cycles)
1.75 µs (7 cycles)
2.5 µs (10 cycles)
1.5 µs (6 cycles)
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
I
2
C
s
t
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t
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B
B
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38
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.6.8 ST ART/STOP Condition Detect Conditions
The START/STOP condition detect conditions are shown in
Figure 8.6.11 and Table 8.6.3. Only when the 3 conditions of Table
8.6.3 are satisfied, a START/STOP condition can be detected.
Note: When a STOP condition is detected in the slave mode
(MST = 0), an interrupt request signal “IICIRQ” is generated to the
CPU.
Fig. 8.6.1 1 ST ART Condition/STOP Condition Detect Timing Dia-
gram
Standard Clock Mode
6.5 µs (26 cycles) < SCL
release time
3.25 µs (13 cycles) < Setup time
3.25 µs (13 cycles) < Hold time
High-speed Clock Mode
1.0 µs (4 cycles) < SCL
release time
0.5 µs (2 cycles) < Setup time
0.5 µs (2 cycles) < Hold time
T able 8.6.3 ST ART Condition/STOP Condition Detect Conditions
Note:Absolute time at φ = 4 MHz. The value in parentheses denotes the num-
ber of φ cycles.
H
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t
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(
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H
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t
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p
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8.6.9 Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective ad-
dress communication formats is described below.
(1) 7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the I2C
control register (address 00F916) to “0.” The first 7-bit address data
transmitted from the master is compared with the high-order 7-bit
slave address stored in the I2C address register (address 00F716).
At the time of this comparison, address comparison of the RBW bit of
the I2C address register (address 00F716) is not made. For the data
transmission format when the 7-bit addressing format is selected,
refer to Figure 8.6.12, (1) and (2).
(2) 10-bit addressing format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the
I2C control register (address 00F916) to “1.” An address comparison
is made between the first-byte address data transmitted from the
master and the 7-bit slave address stored in the I2C address register
(address 00F716). At the time of this comparison, an address com-
parison between the RBW bit of the I2C address register (address
00F716) and the R/W bit which is the last bit of the address data
transmitted from the master is made. In the 10-bit addressing mode,
the R/W bit which is the last bit of the address data not only specifies
the direction of communication for control data but also is processed
as an address data bit.
When the first-byte address data matches the slave address, the
AAS bit of the I2C status register (address 00F816) is set to “1.” After
the second-byte address data is stored into the I2C data shift register
(address 00F616), make an address comparison between the sec-
ond-byte data and the slave address by software. When the address
data of the 2nd bytes matches the slave address, set the RBW bit of
the I2C address register (address 00F716) to “1” by software. This
processing can match the 7-bit slave address and R/W data, which
are received after a RESTART condition is detected, with the value
of the I2C address register (address 00F716). For the data transmis-
sion format when the 10-bit addressing format is selected, refer to
Figure 8.6.12, (3) and (4).
39
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.6.10 Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is shown
below.
➀Set a slave address in the high-order 7 bits of the I2C address
register (address 00F716) and “0” in the RBW bit.
➁Set the ACK return mode and SCL = 100 kHz by setting “8516” in
the I2C clock control register (address 00FA16).
➂Set “1016” in the I2C status register (address 00F816) and hold the
SCL at the HIGH.
➃Set a communication enable status by setting “4816” in the I2C
control register (address 00F916).
➄Set the address data of the destination of transmission in the high-
order 7 bits of the I2C data shift register (address 00F616) and set
“0” in the least significant bit.
➅Set “F016” in the I2C status register (address 00F816) to generate
a START condition. At this time, an SCL for 1 byte and an ACK
clock automatically occurs.
➆Set transmit data in the I2C data shift register (address 00F616). At
this time, an SCL and an ACK clock automatically occurs.
➇When transmitting control data of more than 1 byte, repeat step ➆.
➈Set “D016” in the I2C status register (address 00F816). After this, if
ACK is not returned or transmission ends, a STOP condition will
be generated.
8.6.11 Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the
SCL frequency of 400 kHz, in the ACK non-return mode, using the
addressing format, is shown below.
➀Set a slave address in the high-order 7 bits of the I2C address
register (address 00F716) and “0” in the RBW bit.
➁Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in
the I2C clock control register (address 00FA16).
➂Set “1016” in the I2C status register (address 00F816) and hold the
SCL at the HIGH.
➃Set a communication enable status by setting “4816” in the I2C
control register (address 00F916).
➄When a START condition is received, an address comparison is
made.
➅ •When all transmitted address are“0” (general call):
AD0 of the I2C status register (address 00F816) is set to “1”and
an interrupt request signal occurs.
•When the transmitted addresses match the address set in ➀:
ASS of the I2C status register (address 00F816) is set to “1” and
an interrupt request signal occurs.
•In the cases other than the above:
AD0 and AAS of the I2C status register (address 00F816) are set
to “0” and no interrupt request signal occurs.
➆ Set dummy data in the I2C data shift register (address 00F616).
➇ When receiving control data of more than 1 byte, repeat step ➆.
➈ When a STOP condition is detected, the communication ends.
40
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.6.12 Address Data Communication Format
SS
l
a
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8.6.12 Precautions when using multi-master
I2C-BUS interface
(1) Read-modify-write instruction
The precautions when the raead-modify-write instruction such as SEB,
CLB etc. is executed for each register of the multi-master I2C-BUS
interface are described below.
•I2C data shift register (S0)
When executing the read-modify-write instruction for this register
during transfer, data may become a value not intended.
•I2C address register (S0D)
When the read-modify-write instruction is executed for this register
at detecting the STOP condition, data may become a value not
intended. It is because hardware changes the read/write bit (RBW)
at the above timing.
•I2C status register (S1)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by hardware.
•I2C control register (S1D)
When the read-modify-write instruction is executed for this register
at detecting the ST ART condition or at completing the byte transfer,
data may become a value not intended. Because hardware changes
the bit counter (BC0–BC2) at the above timing.
•I2C clock control register (S2)
The read-modify-write instruction can be executed for this register .
(2) START condition generating procedure us-
ing multi-master
➀Procedure example (The necessary conditions of the generating
procedure are described as the following ➁ to ➄).
•
•
LDA — (Taking out of slave address value)
SEI (Interrupt disabled)
BBS 5,S1,BUSBUSY
(BB flag confirming and branch process)
BUSFREE:
STA S0 (Writing of slave address value)
LDM #$F0, S1
(Trigger of ST ART condition generating)
CLI (Interrupt enabled)
•
•
BUSBUSY:
CLI (Interrupt enabled)
•
•
➁Use “ST A,” “STX” or “STY” of the zero page addressing instruction
for writing the slave address value to the I2C data shift register.
➂Use “LDM” instruction for setting trigger of ST AR T condition gener-
ating.
➃Write the slave address value of above ➁ and set trigger of START
condition generating of above ➂ continuously shown the above
procedure example.
➄Disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
41
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
(3) RESTART condition generating procedure
➀Procedure example (The necessary conditions of the generating
procedure are described as the following ➁ to ➅.)
Execute the following procedure when the PIN bit is “0.”
•
•
LDM #$00, S1 (Select slave receive mode)
LDA — (Taking out of slave address value)
SEI (Interrupt disabled)
STA S0 (Writing of slave address value)
LDM #$F0, S1 (Trigger of RESTART condition generating)
CLI (Interrupt enabled)
•
•
➁Select the slave receive mode when the PIN bit is “0.” Do not write
“1” to the PIN bit. Neither “0” nor “1” is specified for the writing to
the BB bit.
The TRX bit becomes “0” and the SDA pin is released.
➂The SCL pin is released by writing the slave address value to the
I2C data shift register. Use “ST A,” “STX” or “STY” of the zero page
addressing instruction for writing.
➃Use “LDM” instruction for setting trigger of REST ART condition gen-
erating.
➄Write the slave address value of above ➂ and set trigger of RE-
START condition generating of above ➃ continuously shown the
above procedure example.
➅Disable interrupts during the following two process steps:
• Writing of slave address value
• Trigger of RESTART condition generating
(4) STOP condition generating procedure
➀Procedure example (The necessary conditions of the generating
procedure are described as the following ➁ to ➃.)
•
•
SEI (Interrupt disabled)
LDM #$C0, S1 (Select master transmit mode)
NOP (Set NOP)
LDM #$D0, S1 (Trigger of STOP condition generating)
CLI (Interrupt enabled)
•
•
➁Write “0” to the PIN bit when master transmit mode is select.
➂Execute “NOP” instruction after setting of master transmit mode.
Also, set trigger of STOP condition generating within 10 cycles af-
ter selecting of master trasmit mode.
➃Disable interrupts during the following two process steps:
• Select of master transmit mode
• Trigger of STOP condition generating
(5) Writing to I2C status register
Do not execute an instruction to set the PIN bit to “1” from “0” and an
instruction to set the MST and TRX bits to “0” from “1” simultaneously .
It is because it may enter the state that the SCL pin is released and
the SDA pin is released after about one machine cycle. Do not ex-
ecute an instruction to set the MST and TRX bits to “0” from “1” si-
multaneously when the PIN bit is “1.” It is because it may become the
same as above.
(6) Process of after STOP condition generating
Do not write data in the I2C data shift register S0 and the I2C status
register S1 until the bus busy flag BB becomes “0” after generating
the STOP condition in the master mode. It is because the STOP
condition waveform might not be normally generated. Reading to the
above registers do not have the problem.
42
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.7 PWM OUTPUT FUNCTION
This microcomputer is equipped with six 8-bit PWMs (PWM0–
PWM5). PWM0–PWM5 have the same circuit structure and an 8-bit
resolution with minimum resolution bit width of 4
µ
s (for f(XIN) = 8
MHz) and repeat period of 1024
µ
s (for f(XIN) = 8 MHz).
Figure 8.7.1 shows the PWM block diagram. The PWM timing gen-
erating circuit applies individual control signals to PWM0–PWM5 us-
ing f(XIN) divided by 2 as a reference signal.
8.7.1 Data Setting
When outputting PWM0–PWM5, set 8-bit output data to the PWMi
register (i means 0 to 5; addresses 020016 to 020516).
8.7.2 Transmitting Data from Register to PWM
circuit
Data transfer from the 8-bit PWM register to the 8-bit PWM circuit is
executed at writing data to the register.
The signal output from the 8-bit PWM output pin corresponds to the
contents of this register.
8.7.3 Operating of 8-bit PWM
The following explains PWM operation.
First, set the bit 0 of PWM mode register 1 (address 020816) to “0”
(at reset, bit 0 is already set to “0” automatically), so that the PWM
count source is supplied.
PWM0–PWM5 are also used as pins P00–P05. Set the correspond-
ing bits of the port P0 direction register to “1” (output mode). And
select each output polarity by bit 3 of PWM mode register 1 (address
020816). Then, set bits 5 to 0 of PWM mode register 2 (address
020916) to “1” (PWM output).
The PWM waveform is output from the PWM output pins by setting
these registers.
Figure 17 shows the 8-bit PWM timing. One cycle (T) is composed
of 256 (28) segments. The 8 kinds of pulses relative to the weight of
each bit (bits 0 to 7), are output inside the circuit during 1 cycle.
Refer to Figure 17 (a). The 8-bit PWM outputs waveform which is
the logical sum (OR) of pulses corresponding to the contents of bits
0 to 7 of the 8-bit PWM register. Several examples are shown in
Figure 17 (b). 256 kinds of output (HIGH area: 0/256 to 255/256) are
selected by changing the contents of the PWM register. A length of
entirely HIGH cannot be output, i.e. 256/256.
8.7.4 Output after Reset
At reset, the output of ports P00–P05 is in the high-impedance state,
and the contents of the PWM register and the PWM circuit are unde-
fined. Note that after reset, the PWM output is undefined until setting
the PWM register.
43
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.7.1 PWM Block Diagram
1/2
PM10
X
IN
b7 b0
8
PM13 P0
0
PM20
D0
0
PWM0
P0
1
PM21
D0
1
PWM1
P0
2
PM22
D0
2
PWM2
P0
3
PM23
D0
3
PWM3
P0
4
PM24
D0
4
PWM4
P0
5
PM25
D0
5
PWM5
PM1
PM2
P0
D0
: PWM mode register 1 (address 0208
16
)
: PWM mode register 2 (address 0209
16
)
: Port P0 register (address 00C0
16
)
: Port P0 direction register (address 00C1
16
)
Selection gate:
Connected to
black side at
reset.
is as same contents with the others.
PWM1 register (Address 0201
16
)
PWM2 register (Address 0202
16
)
PWM3 register (Address 0203
16
)
PWM4 register (Address 0204
16
)
PWM5 register (Address 0205
16
)
PWM timing
generating
circuit
Data bus
PWM0 register
(Address 0200
16
)
8-bit PWM circuit
Inside of
44
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.7.2 PWM Timing
(a) Pulses showing the weight of each bit
13579 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255
4 12 20 28 36 44 52 60 68 76 84 92 100 108 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252
8
16 48 80 112 144 176 208 240
24 40 56 72 88 104 120 136 152 168 184 200 216 232 248
32 96 160 224
64 192
Bit 7
2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
128
Bit 0
PWM output t = 4 µs T = 1024 µs
f(XIN) = 8 MHz
(b) Example of 8-bit PWM
t
0016 (0)
0116 (1)
1816 (24)
FF16 (255)
T = 256 t
45
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
b7b6 b5b4b3 b2b1b0 PWM mode register 2 (PM2) [Address 0209 16]
BAfter reset RW
PWM Mode Register 2
0
1
2
3
4
0
Name Functions
P00/PWM0 output
selection bit (PM20) 0 : P00 output
1 : PWM0 output
P02/PWM2 output
selection bit (PM22) 0 : P02 output
1 : PWM2 output
P03/PWM3 output
selection bit (PM23) 0 : P03 output
1 : PWM3 output
P04/PWM4 output
selection bit (PM24) 0 : P04 output
1 : PWM4 output
5P05/PWM5 output
selection bit (PW25) 0: P05 output
1: PWM5 output
6, 7 Fix these bits to “0.”
P01/PWM1 output
selection bit (PM21) 0 : P01 output
1 : PWM1 output
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
00
Fig. 8.7.3 PWM Mode Register 1
Fig. 8.7.4 PWM Mode Register 2
b
7b
6 b
5b
4b
3 b
2b
1b
0P
W
M
m
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1
(
P
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1
)
[
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0
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0
8
1
6
]
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0
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e
“
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”
R—
46
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.8 A-D COMPARA T OR
A-D comparator consists of 6-bit D-A converter and comparator . A-D
comparator block diagram is shown in Figure 8.8.1.
The reference voltage “Vref” for D-A conversion is set by bits 0 to 5 of
A-D control register 2 (address 00ED16).
The comparison result of the analog input voltage and the reference
voltage “Vref” is stored in bit 4 of A-D control register 1 (address
00EC16).
For A-D comparison, set “0” to corresponding bits of the direction
register to use ports as analog input pins. Write the data for select of
analog input pins to bits 0 to 2 of A-D control register 1 and write the
digital value corresponding to Vref to be compared to the bits 0
to 5 of A-D control register 2. The voltage comparison starts by writ-
ing to A-D control register 2, and it is completed after 16 machine
cycles (NOP instruction ✕ 8).
Fig. 8.8.1 A-D Comparator Block Diagram
A-D control register 1
Bits 0 to 2 Comparator control
Data bus
Bit 4
Switch tree
A-D control
register 2
Resistor ladder
Compa-
rator
Analog
signal
switch Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
A-D control
register 1
AD1
AD2
AD3
AD4
AD5
AD6
47
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.8.2 A-D Control Register 1
b
7b
6b
5b
4b
3b
2b
1b
0
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
A
D
1
)
[
A
d
d
r
e
s
s
0
0
E
C
1
6
]
B
A
f
t
e
r
r
e
s
e
t
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A
-
D
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n
t
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:
A
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2
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0
:
A
D
3
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:
A
D
4
1
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:
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:
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”
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RW
R—
0
5
t
o
7
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“
0
.
”
R—
Fig. 8.8.3 A-D Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 2 (AD2) [Address 00ED
16
]
BAfter reset RW
A-D Control Register 2
0
to
5
6, 7
0
0
Name Functions
D-A converter set bits
(ADC20 to ADC25) b0b1b2 b3 b4 b5
Nothing is assigned. These bits are write disable bits.
When these bits are reed out, the values are “ 0.”
1
000000
00000
0
0000
0
0
111
1
1
11111
1
111111
: 3/128Vcc
: 5/128Vcc
: 123/128Vcc
: 125/128Vcc
: 127/128Vcc
: 1/128Vcc RW
R—
48
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.9.2 ROM Correction Enable Register
Fig. 8.9.1 ROM Correction Address Registers
8.9 ROM CORRECTION FUNCTION
This can correct program data in ROM. Up to 2 addresses can be
corrected, a program for correction is stored in the ROM correction
vector in RAM as the top address. The ROM correction vectors are 2
vectors.Vector 1 : address 030016
Vector 2 : address 032016
Set the address of the ROM data to be corrected into the ROM cor-
rection address register . When the value of the counter matches the
ROM data address in the ROM correction vector as the top address,
the main program branches to the correction program stored in the
ROM memory for correction. To return from the correction program
to the main program, the op code and operand of the JMP instruction
(total of 3 bytes) are necessary at the end of the correction program.
The ROM correction function is controlled by the ROM correction
enable register.
Notes 1:Specify the first address (op code address) of each
instruction as the ROM correction address.
2:Use the JMP instruction (total of 3 bytes) to return from
the correction program to the main program.
3:Do not set the same ROM correction address to vectors 1
and 2.
020A
16
ROM correction address 1 (high-order)
020B
16
ROM correction address 1 (low-order)
020C
16
ROM correction address 2 (high-order)
020D
16
ROM correction address 2 (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
ROM correction enable register (RCR) [Address 020E
16
]
B
After reset
RW
ROM Correction Enable Register
0 Vector 1 enable bit (RC0)
Name Functions
0: Disabled
1: Enabled
1 Vector 2 enable bit (RC1) 0: Disabled
1: Enabled
2
to
7
Nothing is assigned. These bits are write disable bits. When
these bits are read out, the values are “0.”
0
0
0
RW
RW
R—
49
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.10 DATA SLICER
This microcomputer includes the data slicer function for the closed
caption decoder (referred to as the CCD). This function takes out the
caption data superimposed in the vertical blanking interval of a com-
posite video signal. A composite video signal which makes the sync
chip’s polarity negative is input to the CVIN pin.
When the data slicer function is not used, the data slicer circuit and
the timing signal generating circuit can be cut off by setting bit 0 of
the data slicer control register 1 (address 00E016) to “0.” These set-
tings can realize the low-power dissipation.
Fig. 8.10.1 Data Slicer Block Diagram
Composite
video
signal 1 MΩSync pulse counter
register
(address 00E9
16
)
Data slicer control register 2
(address 00E1
16
)
Data slicer control register 1
(address 00E0
16
)
Clock run-in defect register
(address 00E4
16
)
Caption position register
(address 00E6
16
)
Data clock position register
(address 00E5
16
)
Interrupt request
generating circuit
Data slicer
interrupt
request
Synchronizing
signal counter
Synchronizing
separation
circuit
Sync slice
circuit
Clamping
circuit
Low-pass
filter
Timing signal
generating
circuit
Clock run-in
determination
circuit
Data slice line
specification
circuit
Start bit detecting
circuit
Data clock
generating circuit
16-bit shift register
Caption data register 1
(address 00E216)
Caption data register 2
(address 00E316)
Data bus
Comparator
0.1 µF470 Ω
560 pF
CV
IN
1 µF
1 kΩ
200 pF
H
SYNC
HLF
+
–
Reference
voltage
generating
circuit
V
HOLD
1000 pF
high-order low-order
Data slicer ON/OFF
Caption data register 4
(address 00CF16)Caption data register 3
(address 00CE16)
External circuit
Note : Make the length of wiring which is
connected to VHOLD, HLF, and CVIN pin as
short as possible so that a leakage current
may not be generated when mounting a
resistor or a capacitor on each pin.
50
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.10.1 Notes When not Using Data Slicer
When bit 0 of data slicer control register 1 (address 00E016) is “0,”
terminate the pins as shown in Figure 8.10.2.
Fig. 8.10.2 Termination of Data Slicer Input/Output Pins when Data Slicer Circuit and Timing Generating Circuit Is in OFF State
When both bits 0 and 2 of data slicer control register 1 (address
00E016) are “1,” terminate the pins as shown in Figure 8.10.3.
Fig. 8.10.3 Termination of Data Slicer Input/Output Pins when Timing Signal Generating Circuit Is in ON State
<When data slicer circuit and timing signal generating circuit is in OFF state>
<When using a reference clock generated in timing signal generating circuit as OSD clock>
AV
CC
HLF
V
HOLD
CV
IN
Apply the same voltage as V
CC
to
AV
CC
pin.
Open
Open
Leave HLF pin open.
Leave V
HOLD
pin open.
Pull-down CV
IN
pin to V
SS
through
a resistor of 5 kΩ or more. 5 kΩ or more
19
20
21
22
Apply the same voltage as V
CC
to AV
CC
pin.
Connect the same external circuit as when
using data slicer to HLF pin.
Leave V
HOLD
pin open.
Pull-up CV
IN
to V
CC
through a resistor
of 5 kΩ or more.
AV
CC
V
HOLD
CV
IN
Open
5 kΩ or more
HLF
1 kΩ
200pF1 µF
19
20
21
22
51
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Figures 8.10.4 and 8.10.5 the data slicer control registers.
Fig. 8.10.4 Data Slicer Control Register 1
Fig. 8.10.5 Data Slicer Control Register 2
b
7b
6b
5b
4b
3b
2b
1b
0D
a
t
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g
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r
1
(
D
S
C
1
)
[
A
d
d
r
e
s
s
0
0
E
0
1
6
]
D
a
t
a
S
l
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e
f
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n
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k
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t
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b
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t
(
D
S
C
1
2
)0
:
V
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d
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s
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l
1
:
H
S
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s
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11
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:
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b
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(
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S
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)
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b
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t
o
“
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.
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3
,
4
000
10
:
F
2
1
:
F
1
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e
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t
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f
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d
(
D
S
C
1
1
)
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i
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b
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s
t
o
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1
.
”
5
,
6
D
e
f
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n
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t
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n
o
f
f
i
e
l
d
s
1
(
F
1
)
a
n
d
2
(
F
2
)
H
s
e
p
V
s
e
p
F
1
:
H
s
e
p
V
s
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p
F
2
:
B
A
f
t
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o
“
0
.
”
7
b
7b
6b
5b
4b
3b
2b
1b
0
D
a
t
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s
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r
c
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n
t
r
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l
r
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g
i
s
t
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r
2
(
D
S
C
2
)
[
A
d
d
r
e
s
s
0
0
E
1
1
6
]
R
W
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a
t
a
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m
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10R
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m
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a
t
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I
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01
0
:
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k
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m
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.
1
:
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a
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k
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.
C
a
p
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d
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c
h
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p
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f
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1
(
D
S
C
2
0
)
F
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b
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“
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.
”
2R
e
a
d
-
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n
l
y
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s
t
b
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30
:
F
2
1
:
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1
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r
m
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a
t
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f
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g
(
D
S
C
2
3
)
40
:
M
e
t
h
o
d
(
1
)
1
:
M
e
t
h
o
d
(
2
)
V
e
r
t
i
c
a
l
s
y
n
c
h
r
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o
u
s
s
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n
a
l
(
V
s
e
p
)
g
e
n
e
r
a
t
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m
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t
h
o
d
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b
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(
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2
4
)
0RW
50
:
M
a
t
c
h
1
:
M
i
s
m
a
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c
h
V
-
p
u
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a
p
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m
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t
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f
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g
(
D
S
C
2
5
)I
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r
m
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60RWF
i
x
t
h
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b
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o
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o
.
”
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A
f
t
e
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r
e
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t
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u
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c
t
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a
m
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e
f
i
n
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t
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n
o
f
f
i
e
l
d
s
1
(
F
1
)
a
n
d
2
(
F
2
)
H
s
e
p
V
s
e
p
F
1
:
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s
e
p
V
s
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p
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2
:
R—
7R
e
a
d
-
o
n
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y
T
e
s
t
b
i
tI
n
d
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t
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r
m
i
n
a
t
e
52
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.10.2 Clamping Circuit and Low-pass Filter
The clamp circuit clamps the sync chip part of the composite video
signal input from the CVIN pin. The low-pass filter attenuates the noise
of clamped composite video signal. The CVIN pin to which composite
video signal is input requires a capacitor (0.1 µF) coupling outside.
Pull down the CVIN pin with a resistor of hundreds of kiloohms to 1
MΩ. In addition, we recommend to install externally a simple low-
pass filter using a resistor and a capacitor at the CVIN pin (refer to
Figure 8.10.1).
8.10.3 Sync Slice Circuit
This circuit takes out a composite sync signal from the output signal
of the low-pass filter.
8.10.4 Synchronous Signal Separation Circuit
This circuit separates a horizontal synchronous signal and a vertical
synchronous signal from the composite sync signal taken out in the
sync slice circuit.
(1)Horizontal Synchronous Signal (Hsep)
A one-shot horizontal synchronizing signal Hsep is generated at
the falling edge of the composite sync signal.
(2)V ertical Synchronous Signal (Vsep)
As a Vsep signal generating method, it is possible to select one of
the following 2 methods by using bit 4 of the data slicer control
register 2 (address 00E116).
•Method 1 The LOW level width of the composite sync signal is
measured. If this width exceeds a certain time, a Vsep
signal is generated in synchronization with the rising
of the timing signal immediately after this LOW level.
•Method 2 The LOW level width of the composite sync signal is
measured. If this width exceeds a certain time, it is
detected whether a falling of the composite sync sig-
nal exits or not in the LOW level period of the timing
signal immediately after this LOW level. If a falling
exists, a Vsep signal is generated in synchronization
with the rising of the timing signal (refer to Figure
8.10.6).
Figure 8.10.6 shows a Vsep generating timing. The timing signal shown
in the figure is generated from the reference clock which the timing
generating circuit outputs.
Reading bit 5 of data slicer control register 2 permits determinating
the shape of the V-pulse portion of the composite sync signal. As
shown in Figure 8.10.7, when the A level matches the B level, this bit
is “0.” In the case of a mismatch, the bit is “1.”
Fig. 8.10.6 Vsep Generating Timing (method 2)
C
o
m
p
o
s
i
t
e
s
T
i
m
i
n
g
s
i
g
n
a
l
Vs
e
p
s
i
g
n
a
l
M
e
a
s
u
r
e
L
O
W
p
e
r
i
o
d
A
Vs
e
p
s
i
g
n
a
l
i
s
g
e
n
e
r
a
t
e
d
a
t
a
r
i
s
i
n
g
o
f
t
h
e
t
i
m
i
n
g
s
i
g
n
a
l
i
m
m
e
d
i
a
t
e
l
y
a
f
t
e
r
t
h
e
L
O
W
l
e
v
e
l
w
i
d
t
h
o
f
t
h
e
c
o
m
p
o
s
i
t
e
s
y
n
c
s
i
g
n
a
l
e
x
c
e
e
d
s
a
c
e
r
t
a
i
n
t
i
m
e
.
53
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.10.5 Timing Signal Generating Circuit
This circuit generates a reference clock which is 832 times as large
as the horizontal synchronous signal frequency. It also generates
various timing signals on the basis of the reference clock, horizontal
synchronous signal and vertical synchronizing signal. The circuit
operates by setting bit 0 of data slicer control register 1 (address
00E016) to “1.”
The reference clock can be used as a display clock for OSD function
in addition to the data slicer. The HSYNC signal can be used as a
count source instead of the composite sync signal. However, when
the HSYNC signal is selected, the data slicer cannot be used. A count
source of the reference clock can be selected by bit 2 of data slicer
control register 1 (address 00E016).
For the pins HLF, connect a resistor and a capacitor as shown in
Figure 8.10.1. Make the length of wiring which is connected to these
pins as short as possible so that a leakage current may not be gener-
ated.
Note: It takes a few tens of milliseconds until the reference clock becomes
stable after the data slicer and the timing signal generating circuit are
started. In this period, various timing signals, Hsep signals and Vsep sig-
nals become unstable. For this reason, take stabilization time into con-
sideration when programming.
Fig. 8.10.7 Determination of V-pulse Waveform
Composite
sync signal
AB
0
1
1
Bit 5 of
DSC2
54
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.10.6 Data Slice Line Specification Circuit
(1) Specification of data slice line
This circuit decides a line on which caption data is superimposed.
The line 21 (fixed), 1 appropriate line for a period of 1 field (total 2
line for a period of 1 field), and both fields (F1 and F2) are sliced
their data. The caption position register (address 00E616) is used
for each setting (refer to Table 8.10.1).
The counter is reset at the falling edge of Vsep and is incremented
by 1 every Hsep pulse. When the counter value matched the value
specified by bits 4 to 0 of the caption position register , this Hsep is
sliced.
The values of “0016” to “1F16” can be set in the caption position
register (at setting only 1 appropriate line). Figure 8.10.8 shows
the signals in the vertical blanking interval. Figure 8.10.9 shows
the structure of the caption position register.
(2) Specification of line to set slice voltage
The reference voltage for slicing (slice voltage) is generated for
the clock run-in pulse in the particular line (refer to Table 8.10.1).
The field to generate slice voltage is specified by bit 1 of data
slicer control register 1. The line to generate slice voltage 1 field is
specified by bits 6, 7 of the caption position register (refer to
Table 8.10.1).
Fig. 8.10.8 Signals in Vertical Blanking Interval
(3) Field determination
The field determination flag can be read out by bit 3 of data slicer
control register 2. This flag charge at the falling edge of Vsep.
Video signal Vertical blanking interval
Composite
video signal
Count value to be set in the caption position register (“0F 16” in this case)
Hsep
Vsep
Hsep
Magnified
drawing
Clock run-in Start bit + 16-bit data
Start bit
Window for
deteminating
clock-run-in
Composite video
signal
Line 21
1 appropriate line is set by
the caption position register
(when setting line 19)
55
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.10.9 Caption Position Register
Field and Line to Generate Slice V oltage
• Field specified by bit 1 of DSC1
• Line 21 (total 1 line)
• Field specified by bit 1 of DSC1
• A line specified by bits 4 to 0 of CPS
(total 1 line) (See note 3)
• Field specified by bit 1 of DSC1
• Line 21 (total 1 line)
• Field specified by bit 1 of DSC1
• Line 21 and a line specified by bits 4 to 0 of CPS
(total 2 lines) (See note 2)
Field and Line to Be Sliced Data
• Both fields of F1 and F2
• Line 21 and a line specified by bits 4 to 0 of CPS
(total 2 lines) (See note 2)
• Both fields of F1 and F2
• A line specified by bits 4 to 0 of CPS
(total 1 line) (See note 3)
• Both fields of F1 and F2
• Line 21 (total 1 line)
• Both fields of F1 and F2
• Line 21 and a line specified by bits 4 to 0 of CPS
(total 2 lines) (See note 2)
CPS
b7
0
0
1
1
b6
0
1
0
1
Notes 1:DSC1 is data slicer control register 1.
CPS is caption position register .
2:Set “0016” to “1016” to bits 4 to 0 of CPS.
3:Set “0016” to “1F16” to bits 4 to 0 of CPS.
Table 8.10.1 Specification of Data Slice Line
b
7b
6b
5b
4b
3b
2b
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56
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.10.7 Reference Voltage Generating Circuit
and Comparator
The composite video signal clamped by the clamping circuit is input
to the reference voltage generating circuit and the comparator.
(1) Reference voltage generating circuit
This circuit generates a reference voltage (slice voltage) by us-
ing the amplitude of the clock run-in pulse in line specified by the
data slice line specification circuit. Connect a capacitor between
the VHOLD pin and the VSS pin, and make the length of wiring as
short as possible so that a leakage current may not be gener-
ated.
(2) Comparator
The comparator compares the voltage of the composite video
signal with the voltage (reference voltage) generated in the refer-
ence voltage generating circuit, and converts the composite video
signal into a digital value.
Fig. 8.10.10 Clock Run-in Detect Register
8.10.8 Start Bit Detecting Circuit
This circuit detects a start bit at line decided in the data slice line
specification circuit.
The detection of a start bit is described below.
➀A sampling clock is generated by dividing the reference clock out-
put by the timing signal.
➁A clock run-in pulse is detected by the sampling clock.
➂After detection of the pulse, a start bit pattern is detected from the
comparator output.
8.10.9 Clock Run-in Determination Circuit
This circuit determinates clock run-in by counting the number of pulses
in a window of the composite video signal.
The reference clock count value in one pulse cycle is stored in bits 3
to 7 of the clock run-in detect register (address 00E416). Read out
these bits after the occurrence of a data slicer interrupt (refer to
“8.10.12 Interrupt Request Generating Circuit”).
Figure 8.10.10 shows the structure of clock run-in detect register.
b7 b6 b5 b4 b3 b2 b1 b0
Clock run-in detect register (CRD) [Address 00E4
16
]
RW
Clock Run-in Detect Register
0
to
2
0R—
Test bits
3
to
7
Number of reference clocks to
be counted in one clock run-in
pulse period.
Clock run-in detection bit
(CRD3 to CRD7) 0R—
Read-only
B After resetFunctionsName
57
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.10.10 Data Clock Generating Circuit
This circuit generates a data clock synchronized with the start bit
detected in the start bit detecting circuit. The data clock stores cap-
tion data to the 16-bit shift register. When the 16-bit data has been
stored and the clock run-in determination circuit determines clock
run-in, the caption data latch completion flag is set. This flag is reset
at a falling of the vertical synchronous signal (Vsep).
Fig. 8.10.11 Data Clock Position Register
b
7b
6b
5b
4b
3b
2b
1b
0
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58
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.10.11 16-bit Shift Register
The caption data converted into a digital value by the comparator is
stored into the 16-bit shift register in synchronization with the data
clock. The contents of the high-order 8 bits of the stored caption data
can be obtained by reading out data register 2 (address 00E316) and
data register 4 (address 00CF16). The contents of the low-order 8
bits can be obtained by reading out data register 1 (address 00E216)
and data register 3 (address 00CE16), respectively. These registers
are reset to “0” at a falling of Vsep. Read out data registers 1 and 2
after the occurrence of a data slicer interrupt (refer to “8.10.12 Inter-
rupt Request Generating Circuit”).
8.10.12 Interrupt Request Generating Circuit
The interrupt requests as shown in Table 8.10.3 are generated by
combination of the following bits; bits 6 and 7 of the caption position
register (address 00E616). Read out the contents of data registers 1
to 4 and the contents of bits 3 to 7 of the clock run-in detect register
after the occurrence of a data slicer interrupt request.
Slice Line Specification Mode
CPS Completion Flag 1
(bit 0 of DSC2) Completion Flag 2
(bit 5 of CPS) Caption Data
Registers 1, 2 Caption Data
Registers 3, 4
Line 21
A line specified by
bits 4 to 0 of CPS
Line 21
Line 21
A line specified by
bits 4 to 0 of CPS
Invalid
Invalid
A line specified by
bits 4 to 0 of CPS
16-bit data of line 21
16-bit data of a line specified
by bits 4 to 0 of CPS
16-bit data of line 21
16-bit data of line 21
16-bit data of a line specified by
bits 4 to 0 of CPS
Invalid
Invalid
16-bit data of a line specified by
bits 4 to 0 of CPS
Contents of Caption Data Latch Completion Flag Contents of 16-bit Shift Register
bit 7
0
0
1
1
bit 6
0
1
0
1
CPS: Caption position register
DSC2: Data slicer control register 2
Table 8.10.2 Contents of Caption Data Latch Completion Flag and 16-bit Shift Register
Caption position register Occurence Souces of Interrupt Request at End of Data Slice Line
After slicing line 21
After a line specified by bits 4 to 0 of CPS
After slicing line 21
After slicing line 21
b7
0
1
b6
0
1
0
1
Table 8.10.3 Occurence Sources of Interrupt Request
59
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.10.12 Sync Pulse Counter Register
8.10.13 Synchronous Signal Counter
The synchronous signal counter counts the composite sync signal
taken out from a video signal in the data slicer circuit or the vertical
synchronous signal Vsep as a count source.
The count value in a certain time (T time) generated by f(XIN)/213 or
f(XIN)/213 is stored into the 5-bit latch. Accordingly, the latch value
changes in the cycle of T time. When the count value exceeds “1F16,”
“1F16” is stored into the latch.
Fig. 8.10.13 Synchronous Signal Counter Block Diagram
The latch value can be obtained by reading out the sync pulse counter
register (address 00E916). A count source is selected by bit 5 of the
sync pulse counter register.
The synchronous signal counter is used when bit 0 of PWM mode
register 1 (address 020816).
Figure 8.10.12 shows the structure of the sync pulse counter and
Figure 8.10.13 shows the synchronous signal counter block diagram.
b7 b6 b5 b4 b3 b2 b1 b0
Sync pulse counter register (HC) [Address 00E9
16
]
RW
Sync Pulse Counter Register
0
to
4
0R—
6, 7 0 R —
Count value (HC0 to HC4)
50RWCount source (HC5) 0: H
SYNC
signal
1: Composite sync signal
BAfter resetFunctionsName
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Reset
5-bit counter
Latch (5 bits)
f(X
IN
)/2
13
Composite
sync signal
H
SYNC
signal Counter
Sync pulse
counter register
Data bus
Selection gate : connected to black
side when reset.
b5
60
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.11 OSD FUNCTIONS
Table 8.11.1 outlines the OSD functions.
This microcomputer incorporates an OSD circuit of 32 characters ✕
2 lines. And also, there are 2 display modes and they are selected by
a block unit. The display modes are selected by bits 0 and 1 of block
control register i (i = 1 and 2).
The features of each mode are described below.
Table 8.11.1 Features of Each Display Mode
Number of display characters 32 characters ✕ 2 lines
Dot structure
16 ✕ 26 dots (Character display area : 16 ✕ 20 dots)
16 ✕ 20 dots
Kinds of characters 254 kinds
Kinds of character sizes 1 kinds 8 kinds
Pre-divide ratio (See note) ✕ 2 (fixed) ✕ 2, ✕ 3
Dot size 1T
C
✕ 1/2H 1T
C
✕ 1/2H, 1T
C
✕ 1H, 2T
C
✕ 2H, 3T
C
✕ 3H
Attribute Smooth italic, under line, flash Border (black)
Character font coloring 1 screen : 8 kinds (per character unit)
Character background coloring 1 screen : 8 kinds (per character unit)
OSD output R, G, B
Raster coloring Possible (per character unit)
Function Auto solid space function
Window function
Display position Horizontal: 128 levels, Vertical: 512 levels
Display expansion (multiline display) Possible
Parameter
Notes 1: The divide ratio of the frequency divider (the pre-divide circuit) is referred as “pre-divide ratio” hereafter.
2: The character size is specified with dot size and pre-divide ratio (refer to 8.11.2 Dot Size).
Display mode
CC mode
(Closed caption mode) OSD mode (Border OFF)
(On-screen display mode)
61
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
16 dots
26 dots
20 dots
'Underline area✽
'Blank area✽
✽: Displayed only in CCD mode.
'Blank area✽
20 dots
OSD mode CC mode
16 dots
The OSD circuit has an extended display mode. This mode allows
multiple lines (3 lines or more) to be displayed on the screen by inter-
rupting the display each time one line is displayed and rewriting data
in the block for which display is terminated by software.
Figure 8.1 1.1 shows the configuration of OSD character. Figure 8.1 1.2
shows the block diagram of the OSD circuit. Figure 8.1 1.3 shows the
OSD control register . Figure 8.1 1.4 shows the block control register i.
Fig. 8.11.1 Configuration of OSD Character Display Area
62
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.11.2 Block Diagram of OSD Circuit
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63
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.11.3 OSD Control Register
b7b6b5b4b3b2b1b0 OSD control register (OC) [Address 00D0
16
]
B Name Functions After reset RW
OSD Control Register
0 OSD control bit
(OC0) (See note) 0 : All-blocks display off
1 : All-blocks display on 0
1Automatic solid space
control bit (OC1) 0 : OFF
1 : ON 0
20 : OFF
1 : ON 0
0
4 OSD mode clock
selection bit (OC4) 0
Window control bit
(OC2)
RW
RW
RW
RW
RW
30 : Data slicer clock
1 : Clock from OSC1 pin
CC mode clock
selection bit (OC3)
5, 6 OSC1 clock
selection bit
(OC5, OC6)
0 0: 32 kHz oscillating
0 1: Do not set.
1 0: LC oscillating,
Ceramic oscillating
1 1: Do not set.
b6 b5
0 : Data slicer clock
1 : Clock from OSC1 pin
7 Fix this bit to “0.”
0RW
0RW
0
Note: Even this bit is switched during display, the display screen
remains unchanged until a rising (falling) of the next V
SYNC
.
64
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.11.4 Block Control Register i
b7b6b5b4b3b2b1b0 Block control register i (BCi) (i=1, 2) [Addresses 00D2
16
and 00D3
16
]
Block Control register i
0, 1 Display mode
selection bits
(BCi0, BCi1)
(See note 1)
Indeterminate
2, 3 Dot size selection
bits (BCi2, BCi3)
b4 b3 b2
Pre-divide Ratio
Dot Size
4 Pre-divide ratio
selection bit (BCi4)
5
7 Window top/bottom
boundary control bit
(BCi7)
Notes 1: Bit RA3 of OSD RAM controls OUT1 output when bit 5 is “0.”
Bit RA3 of OSD RAM controls OUT2 output when bit 5 is “1.”
2: Tc is OSD clock cycle divided in pre-divide circuit.
3: H is H
SYNC
.
OUT1/OUT2 output control
bit (BCi5) (See note 1) 0: OUT1 output control
1: OUT2 output control
6Vertical display start
position control bit
(BCi6)
BC16: Block 1
BC26: Block 1
b1 b0
0 0: Display OFF
0 1: CC mode
1 0: OSD mode (Border OFF)
1 1: OSD mode (Border ON)
00
01
10
11
00
01
10
11
0
1
✕ 2
✕ 3
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
BC17: Window top boundary
BC27: Window bottom boundary
B Name Functions
After reset
RW
RW
Indeterminate
RW
Indeterminate
RW
Indeterminate
RW
Indeterminate
RW
Indeterminate
RW
65
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.11.1 Display Position
The display positions of characters are specified in units called a
“block.” There are 2 blocks, blocks 1 and 2. Up to 32 characters can
be displayed in each block (refer to “8.11.5 Memory for OSD”).
The display position of each block can be set in both horizontal and
vertical directions by software.
The display start position in the horizontal direction can be selected
for all blocks in common from 128-step display positions in units of
4TOSC (TOSC = OSD oscillation cycle).
The display start position in the vertical direction for each block can
be selected from 512-step display positions in units of 1 TH ( TH =
HSYNC cycle).
Blocks are displayed in conformance with the following rules:
• When the display position of block 1 is overlapped with that of block
2 (Figure 8.11.5 (b)), the block 1 is displayed on the front.
• When another block display position appears while one block is
displayed (Figure 8.11.5 (c)), the block with a larger set value as
the vertical display start position is displayed.
Fig. 8.11.5 Display Position
(
H
P
)
V
P
2
B
l
o
c
k
1
B
l
o
c
k
2
(
a
)
E
x
a
m
p
l
e
w
h
e
n
e
a
c
h
b
l
o
c
k
i
s
s
e
p
a
r
a
t
e
d
B
l
o
c
k
1
(
b
)
E
x
a
m
p
l
e
w
h
e
n
b
l
o
c
k
2
o
v
e
r
l
a
p
s
w
i
t
h
b
l
o
c
k
1
(
B
l
o
c
k
2
i
s
n
o
t
d
i
s
p
l
a
y
e
d
)
(
H
P
)
V
P
1
V
P
2
(
c
)
E
x
a
m
p
l
e
w
h
e
n
b
l
o
c
k
2
o
v
e
r
l
a
p
s
i
n
p
r
o
c
e
s
s
o
f
b
l
o
c
k
1
B
l
o
c
k
1
B
l
o
c
k
2
N
o
t
e
:
V
P
1
o
r
V
P
2
i
n
d
i
c
a
t
e
s
t
h
e
v
e
r
t
i
c
a
l
d
i
s
p
l
a
y
s
t
a
r
t
p
o
s
i
t
i
o
n
o
f
d
i
s
p
l
a
y
b
l
o
c
k
1
o
r
2
.
V
P
1
(
H
P
)
V
P
1
=
V
P
2
66
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
The vertical display start position is determined by counting the hori-
zontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are
positive polarity (negative polarity), it starts to count the rising edge
(falling edge) of HSYNC signal from after fixed cycle of rising edge
(falling edge) of VSYNC signal. So interval from rising edge (falling
edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal
needs enough time (2 machine cycles or more) for avoiding jitter.
The polarity of HSYNC and VSYNC signals can select with the I/O po-
larity control register (address 00D816).
Fig. 8.11.6 Supplement Explanation for Display Position
W
h
e
n
b
i
t
s
0
a
n
d
1
o
f
t
h
e
I
/
O
p
o
l
a
r
i
t
y
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
a
d
d
r
e
s
s
0
0
D
81
6)
a
r
e
s
e
t
t
o
“
1
”
(
n
e
g
a
t
i
v
e
p
o
l
a
r
i
t
y
)
VS
Y
N
C
s
i
g
n
a
l
i
n
p
u
t
VS
Y
N
C
c
o
n
t
r
o
l
s
i
g
n
a
l
i
n
m
i
c
r
o
c
o
m
p
u
t
e
r
0
.
2
5
t
o
0
.
5
0
[
µ
s
]
(
a
t
f
(
XI
N)
=
8
M
H
z
)
P
e
r
i
o
d
o
f
c
o
u
n
t
i
n
g
HS
Y
N
C
s
i
g
n
a
l(
S
e
e
n
o
t
e
2
)
HS
Y
N
C
s
i
g
n
a
l
i
n
p
u
t
N
o
t
c
o
u
n
t
12345
N
o
t
e
s
1
:T
h
e
v
e
r
t
i
c
a
l
p
o
s
i
t
i
o
n
i
s
d
e
t
e
r
m
i
n
e
d
b
y
c
o
u
n
t
i
n
g
f
a
l
l
i
n
g
e
d
g
e
o
f
HS
Y
N
C
s
i
g
n
a
l
a
f
t
e
r
r
i
s
i
n
g
e
d
g
e
o
f
VS
Y
N
C
c
o
n
t
r
o
l
s
i
g
n
a
l
i
n
t
h
e
m
i
c
r
o
c
o
m
p
u
t
e
r
.
2
:D
o
n
o
t
g
e
n
e
r
a
t
e
f
a
l
l
i
n
g
e
d
g
e
o
f
HS
Y
N
C
s
i
g
n
a
l
n
e
a
r
r
i
s
i
n
g
e
d
g
e
o
f
VS
Y
N
C
c
o
n
t
r
o
l
s
i
g
n
a
l
i
n
m
i
c
r
o
c
o
m
p
u
t
e
r
t
o
a
v
o
i
d
j
i
t
t
e
r
.
3
:T
h
e
p
u
l
s
e
w
i
d
t
h
o
f
VS
Y
N
C
a
n
d
HS
Y
N
C
n
e
e
d
s
8
m
a
c
h
i
n
e
c
y
c
l
e
s
o
r
m
o
r
e
.
8
m
a
c
h
i
n
e
c
y
c
l
e
s
o
r
m
o
r
e
8
m
a
c
h
i
n
e
c
y
c
l
e
s
o
r
m
o
r
e
67
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.11.7 Vertical Position Register i (i = 1 and 2)
The vertical display start position for each block can be set in 512
steps (where each step is 1TH (TH: HSYNC cycle)) as values “0016” to
“FF16” in vertical position register i (i = 1 and 2) (addresses 00D416
and 00D516) and values “0” or “1” in bit 6 of block control register i (i
= 1 and 2) (addresses 00D216 and 00D316). The vertical position
registers is shown in Figure 8.11.7.
b7 b6 b5 b4 b3 b2 b1 b0
0
to
7
R W
Vertical Position Register i
Vertical position register i (VPi) (i = 1 and 2) [Addresses 00D4
16
, 00D5
16
]
BName Functions After reset RW
InderterminateVertical display start
position control bits
(VPi0 to VPi7)
(See note)
Vertical display start position =
T
H
✕ (BCi6 ✕ 16
2
+ n)
(n: setting value, T
H
: H
SYNC
cycle,
BCi6: bit 6 of block control register i)
Note: Set values except “00
16
” to VPi when BCi6 is “0.”
68
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
The horizontal display start position is common to all blocks, and can
be set in 128 steps (where 1 step is 4TOSC, TOSC being the OSD
oscillation cycle) as values “0016” to “FF16” in bits 0 to 6 of the hori-
zontal position register (address 00D116). The horizontal position reg-
ister is shown in Figure 8.11.8.
Fig. 8.11.8 Horizontal Position Register
Notes 1 : 1TC (TC : OSD clock cycle divided in pre-divide circuit) gap occurs
between the horizontal display start position set by the horizontal
position register and the most left dot of the 1st block. Accordingly,
when 2 blocks have different pre-divide ratios, their horizontal dis-
play start position will not match.
2 : The horizontal start position is based on the OSD clock source cycle
selected for each block. Accordingly, when 2 blocks have different
OSD clock source cycles, their horizontal display start position will
not match.
3 : When setting “0016” to the horizontal position register, it needs ap-
proximately 62TOSC (= Tdef) interval from a rising edge (when nega-
tive polarity is selected) of HSYNC signal to the horizontal display start
position.
Fig. 8.11.9 Notes on Horizontal Display Start Position
4
T
O
S
C
’
✕
N
4
T
O
S
C
✕
N
H
S
Y
N
C
1
T
C
1
T
C
1
T
C
N
o
t
e
1
N
o
t
e
2
B
l
o
c
k
2
(
P
r
e
-
d
i
v
i
d
e
r
a
t
i
o
=
2
,
c
l
o
c
k
s
o
u
r
c
e
=
d
a
t
a
s
l
i
c
e
r
c
l
o
c
k
)
B
l
o
c
k
3
(
P
r
e
-
d
i
v
i
d
e
r
a
t
i
o
=
3
,
c
l
o
c
k
s
o
u
r
c
e
=
d
a
t
a
s
l
i
c
e
r
c
l
o
c
k
)
B
l
o
c
k
4
(
P
r
e
-
d
i
v
i
d
e
r
a
t
i
o
=
3
,
c
l
o
c
k
s
o
u
r
c
e
=
O
S
C
1
)
T
d
e
f
T
d
e
f
’
N:
V
a
l
u
e
o
f
h
o
r
i
z
o
n
t
a
l
p
o
s
i
t
i
o
n
r
e
g
i
s
t
e
r
(
d
e
c
i
m
a
l
n
o
t
a
t
i
o
n
)
1
T
C
:
O
S
D
c
l
o
c
k
c
y
c
l
e
d
i
v
i
d
e
d
i
n
p
r
e
-
d
i
v
i
d
e
c
i
r
c
u
i
t
T
O
S
C
:
O
S
D
o
s
c
i
l
l
a
t
i
o
n
c
y
c
l
e
T
d
e
f
:
6
2
T
O
S
C
b7b6b5b4b3b2b1b0 Horizontal position register (HP) [Address 00D1
16
]
B Name
Horizontal Position Register
7
Horizontal display start
position control bits
(HP0 to HP6)
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
Functions After reset R W
Horizontal display start positions
128 steps (00
16
to 7F
16
)
(1 step is 4T
OSC
)
0
0
RW
R—
0
to
6
Note: The setting value synchronizes with the V
SYNC
.
69
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.11.10 Block Diagram of Dot Size Control Circuit
8.11.2 Dot Size
The dot size can be selected by a block unit. The dot size in vertical
direction is determined by dividing HSYNC in the vertical dot size con-
trol circuit. The dot size in horizontal is determined by dividing the
following clock in the horizontal dot size control circuit : the clock
gained by dividing the OSD clock source (data slicer clock, OSC1) in
the pre-divide circuit. The clock cycle divided in the pre-divide circuit
is defined as 1TC.
The dot size of each block is specified by bits 2 to 4 of the block
control register i.
Refer to Figure 8.11.4 (the structure of the block control register).
The block diagram of dot size control circuit is shown in Figure 8.1 1.10.
Fig. 8.11.11 Definition of Dot Sizes
D
a
t
a
s
l
i
c
e
r
c
l
o
c
k
HS
Y
N
C
O
S
C
1
O
C
3
o
r
O
C
4
S
y
n
c
h
r
o
n
o
u
s
c
i
r
c
u
i
t
C
y
c
l
e
✕
3
P
r
e
-
d
i
v
i
d
e
c
i
r
c
u
i
t
C
l
o
c
k
c
y
c
l
e
=
1
TCH
o
r
i
z
o
n
t
a
l
d
o
t
s
i
z
e
c
o
n
t
r
o
l
c
i
r
c
u
i
t
V
e
r
t
i
c
a
l
d
o
t
s
i
z
e
c
o
n
t
r
o
l
c
i
r
c
u
i
t
O
S
D
c
o
n
t
r
o
l
c
i
r
c
u
i
t
C
y
c
l
e
✕
2“
0
”
“
1
”B
C
i
4
N
o
t
e
:
T
o
u
s
e
d
a
t
a
s
l
i
c
e
r
c
l
o
c
k
,
s
e
t
b
i
t
0
o
f
d
a
t
a
s
l
i
c
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
t
o
“
1
.
”
1
d
o
t
S
c
a
n
n
i
n
g
l
i
n
e
o
f
F
1
(
F
2
)
S
c
a
n
n
i
n
g
l
i
n
e
o
f
F
2
(
F
1
)
1
/
2
H1
H2
H3
H
3
T
C
2
T
C
1
T
C
1
T
C
70
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
b7 of raster color
register
OSD control
register
I/O
Port
1
1
0
8.11.3 Clock for OSD
As a clock for display to be used for OSD, it is possible to select one
of the following 3 types.
• Data slicer clock output from the data slicer (approximately 26 MHz)
• OSC1 clock supplied from the pins OSC1 and OSC2
• Clock from the ceramic resonator or the LC oscillator from the pins
OSC1 and OSC2
This OSD clock for each block can be selected by the following bits
: bit 7 of the raster color register (address 00D916), bits 3 to 6 of the
clock source control register (addresses 00D016). A variety of char-
acter sizes can be obtained by combining dot sizes with OSD clocks.
When not using the pins OSC1 and OSC2 for the OSD clock I/O
pins, the pins can be used as sub-clock I/O pins or port P2.
Fig. 8.11.12 Block Diagram of OSD Selection Circuit
Table 8.11.2 Setting for P26/OSC1/XCIN, P27/OSC2/XCOUT
OSD clock
I/O Pin
0
1
0
Sub-clock
I/O Pin
0
0
0
Function
Register
b6
b5
“
0
”
“
1
0
”
“
0
”
D
a
t
a
s
l
i
c
e
r
c
i
r
c
u
i
t
D
a
t
a
s
l
i
c
e
r
c
l
o
c
k
(
S
e
e
n
o
t
e
)
O
S
C
1
c
l
o
c
k
C
e
r
a
m
i
c
·
L
C
O
s
c
i
l
l
a
t
i
n
g
m
o
d
e
f
o
r
O
S
D
O
C
6
,
O
C
5
“
1
”
“
1
”
O
C
3
O
C
4
C
C
m
o
d
e
b
l
o
c
k
O
S
D
m
o
d
e
b
l
o
c
k
N
o
t
e
:
T
o
u
s
e
d
a
t
a
s
l
i
c
e
r
c
l
o
c
k
,
s
e
t
b
i
t
0
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a
t
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l
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r
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t
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o
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g
i
s
t
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r
1
t
o
“
1
.
”
71
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.11.4 Field Determination Display
To display the block with vertical dot size of 1/2H, whether an even
field or an odd field is determined through differences in a synchro-
nizing signal waveform of interlacing system. The dot line 0 or 1 (re-
fer to Figure 8.11.14) corresponding to the field is displayed alter-
nately.
In the following, the field determination standard for the case where
both the horizontal sync signal and the vertical sync signal are nega-
tive-polarity inputs will be explained. A field determination is deter-
mined by detecting the time from a falling edge of the horizontal sync
signal until a falling edge of the VSYNC control signal (refer to Figure
8.11.6) in the microcomputer and then comparing this time with the
time of the previous field. When the time is longer than the compar-
ing time, it is regarded as even field. When the time is shorter, it is
regarded as odd field
The contents of this field can be read out by the field determination
flag (bit 6 of the I/O polarity control register at address 00D816). A dot
line is specified by bit 5 of the I/O polarity control register (refer to
Figure 8.11.14).
However, the field determination flag read out from the CPU is fixed
to “0” at even field or “1” at odd field, regardless of bit 5.
Fig. 8.11.13 I/O Polarity Control Register
0 : “ ” at even field
“ ” at odd field
1 : “ ” at even field
“ ” at odd field
b7 b6 b5 b4 b3 b2 b1 b0
I/O polarity control register (PC) [Address 00D8
16
]
B Name Functions
After reset
RW
I/O Polarity Control Register
0H
SYNC
input polarity
switch bit (PC0) 0 : Positive polarity input
1 : Negative polarity input 0
10 : Positive polarity input
1 : Negative polarity input 0
2 R, G, B output polarity
switch bit (PC2) 0 : Positive polarity output
1 : Negative polarity output 0
3 OUT1 output polarity
switch bit (PC3) 0 : Positive polarity output
1 : Negative polarity output 0
4 OUT2 output polarity
switch bit (PC4) 0 : Positive polarity output
1 : Negative polarity output 0
5 Display dot line selection
bit (PC5) (See note) 0
6 Field determination flag
(PC6) 0 : Even field
1 : Odd field 1
70
V
SYNC
input polarity
switch bit (PC1)
RW
RW
RW
RW
RW
RW
R—
RWFix this bit to “0.”
Note: Refer to the corresponding figure (8.11.14).
0
72
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.11.14 Relation between Field Determination Flag and Display Font
Both H
SYNC
signal and V
SYNC
signal are negative-polarity input
Field
Even
Odd
Field
determination
flag(Note)
Display dot line
selection bit Display dot line
0 (T2 > T1)
1 (T3 < T2)
0
1
0
1
When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 0208
16
) to “0.”
T2
T3
OSD ROM font configuration diagram
Dot line 0
Dot line 1
Odd
Dot line 0
Dot line 1
(n |1) field
(Odd-numbered)
T1 0.25 to 0.50[ ˚s] at
f(XIN) 8 MHz
CC mode
13579111315
1
3
5
7
9
11
13
15
17
19
21
23
25
26
24
22
20
18
16
14
12
10
8
6
4
2
2 4 6 8 10 12 14 16 1
3
5
7
9
11
13
15
17
19
20
18
16
14
12
10
8
6
4
2
135791113152 4 6 8 10 12 14 16
OSD mode
H
SYNC
V
SYNC
and
V
SYNC
control
signal
in microcom-
puter
Upper :
V
SYNC
signal
Lower :
V
SYNC
control
signal in
micro-
computer
(n) field
(Even-numbered)
(n {1) field
(Odd-numbered)
When the display dot line selection bit is “0,”
the “ ” font is displayed at even field, the
“ ” font is displayed at odd field. Bit 6 of the
I/O polarity control register can be read as the
field determination flag : “1” is read at odd field,
“0” is read at even field.
Note : The field determination flag changes at a rising edge of the V
SYNC
control signal (negative-polarity input) in
the microcomputer.
73
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.11.5 Memory for OSD
There are 2 types of memory for OSD : OSD ROM used to store
character dot data and OSD RAM used to specify the characters and
colors to be displayed.
<M37272M6/M8-XXXSP/FP, M37272E8SP/FP>
OSD ROM : addresses 140016 to 3BFF16
OSD RAM : addresses 080016 to 087F16
<M37272MA-XXXSP, M37272EFSP>
OSD ROM : addresses 1140016 to 13BFF16
OSD RAM : addresses 080016 to 087F16
Fig. 8.11.15 Character Font Data Storing Address
O
S
D
R
O
M
a
d
d
r
e
s
s
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a
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a
A
D
1
5 A
D
1
4 A
D
1
3 A
D
1
2 A
D
1
1 A
D
1
0 A
D
9 A
D
8 A
D
7 A
D
6 A
D
5 A
D
4 A
D
3 A
D
2 A
D
1A
D
0
L
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F
o
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t
b
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t
“
0
A1
6”
t
o
“
1
D1
6”
“
0
01
6”
t
o
“
F
F1
6”
(
“
7
F1
6”
a
n
d
“
8
01
6”
c
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)
0
:
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f
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:
R
i
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h
t
a
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R
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M
a
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s
s
b
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0
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0
0
01
6
7
F
F
01
6
7
F
F
81
6
6
0
1
C
1
6
6
0
0
C
1
6
6
0
0
C
1
6
6
0
0
C
1
6
6
0
0
C
1
6
1
1
0
B
0
C
0
D
0
E
0
F
1
0
1
26
0
1
C
1
6
7
F
F
81
6
7
F
F
01
6
6
3
0
01
6
6
3
8
01
6
6
1
C
01
6
6
0
E
01
6
6
0
7
01
6
1
9
1
3
1
4
1
5
1
6
1
7
1
8
6
0
3
81
6
6
0
1
C
1
6
6
0
0
C
1
6
0
0
0
01
6
1
D
1
A
1
B
1
C
b
0
b
7b
0
b
7
L
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n
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0
A
D
1
6
1
(
N
o
t
e
)
N
o
t
e
:
O
n
l
y
M
3
7
2
7
2
M
A
-
X
X
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M
3
7
2
7
2
E
F
S
P
h
a
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A
D
1
6
.
(1) OSD ROM (addresses 140016 to 3BFF16)
The dot pattern data for OSD characters is stored in OSD ROM. To
specify the kinds of the character font, it is necessary to write the
character code into the OSD RAM.
Data of the character font is specified shown in Figure 8.11.15.
74
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Notes 1 : The 80-byte addresses corresponding to the character code “7F16”
and “8016” in OSD ROM are the test data storing area. Set data to
the area as follows.
<Test data storing area>
■ M37272M6/M8-XXXSP/FP, M37272E8SP/FP
addresses 100016 + (4 + 2n) ✕ 10016 + FE16 to
100016 + (5 + 2n) ✕ 10016 + 0116
(n = 0 to 19)
■ M37272MA-XXXSP, M37272EFSP
addresses 1100016 + (4 + 2n) ✕ 10016 + FE16 to
1100016 + (5 + 2n) ✕ 10016 + 0116
(n = 0 to 19)
(1)Mask version (M37272M6/M8-XXXSP/FP, M37272MA-XXXSP)
Set “FF16” to the area (We stores the test data to this area and the different
data from “FF16” is stored for the actual products.) When using our font
editor, the test data is written automatically.
(2)EPROM version (M37272E8SP/FP, M37272EFSP)
Set the test data to the area. When using our font editor, the test data
is written automatically.
…
…
150016 (9016), 150116 (A116)
170016 (0016), 170116 (A216)
190016 (4816), 190116 (A316)
1B0016 (0016), 1B0116 (A416)
1D0016 (2416), 1D0116 (A516)
1F0016 (0016), 1F0116 (A616)
210016 (1216), 210116 (A716)
230016 (0016), 230116 (A816)
250016 (0916), 250116 (A916)
270016 (0016), 270116 (AA16)
290016 (8116), 290116 (AB16)
2B0016 (1816), 2B0116 (AC16)
2D0016 (0016), 2D0116 (AD16)
2F0016 (4216), 2F0116 (AE16)
310016 (2416), 310116 (AF16)
330016 (0016), 330116 (B016)
350016 (8116), 350116 (B116)
370016 (0C16), 370116 (B216)
390016 (0616), 390116 (B316)
3B0016 (0016), 3B0116 (B416)
1150016 (9016), 1 150116 (A116)
1170016 (0016), 1 1701 16 (A216)
1190016 (4816), 1 1901 16 (A316)
11B0016 (0016), 11B0116 (A416)
11D0016 (2416), 1 1D0116 (A5 16)
11F0016 (0016), 1 1F0116 (A6 16)
1210016 (1216), 1210116 (A716)
1230016 (0016), 1230116 (A816)
1250016 (0916), 1250116 (A916)
1270016 (0016), 1270116 (AA16)
1290016 (8116), 1290116 (AB16)
12B0016 (1816), 12B0116 (AC16)
12D0016 (0016), 12D0116 (AD16)
12F0016 (4216), 12F0116 (AE16)
1310016 (2416), 1310116 (AF16)
1330016 (0016), 1330116 (B016)
1350016 (8116), 1350116 (B116)
1370016 (0C16), 1370116 (B216)
1390016 (0616), 1390116 (B316)
13B0016 (0016), 13B0116 (B416)
2 : The character code “0916” is used for “transparent space” when
displaying Closed Caption.
Therefore, set “0016” to the 40-byte addresses corresponding to the
character code “0916.”
<Transparent space font data storing area>
■ M37272M6/M8-XXXSP/FP, M37272E8SP/FP
addresses 100016 + (4 + 2n) ✕ 10016 + 1216 to
100016 + (4 + 2n) ✕ 10016 + 1316
(n = 0 to 19)
addresses 141216 and 141316
addresses 161216 and 161316
addresses 381216 and 381316
addresses 3A1216 and 3A1316
■ M37272MA-XXXSP, M37272EFSP
addresses 1100016 + (4 + 2n) ✕ 10016 + 1216 to
1100016 + (4 + 2n) ✕ 10016 + 1316
(n = 0 to 19)
addresses 1141216 and 1141316
addresses 1161216 and 1161316
addresses 1381216 and 1381316
addresses 13A1216 and 13A1316
14FE16 (0916), 14FF16 (5116)
16FE16 (0016), 16FF16 (5216)
18FE16 (1216), 18FF16 (5316)
1AFE16 (0016), 1AFF16 (5416)
1CFE16 (2416), 1CFF16 (5516)
1EFE16 (0016), 1EFF16 (5616)
20FE16 (8816), 20FF16 (5716)
22FE16 (0016), 22FF16 (5816)
24FE16 (9016), 24FF16 (5916)
26FE16 (4816), 26FF16 (5A16)
28FE16 (2416), 28FF16 (5B16)
2AFE16 (0016), 2AFF16 (5C16)
2CFE16 (2416), 2CFF16 (5D16)
2EFE16 (4816), 2EFF16 (5E16)
30FE16 (0016), 30FF16 (5F16)
32FE16 (4816), 32FF16 (5016)
34FE16 (9016), 34FF16 (5116)
36FE16 (0016), 36FF16 (5216)
38FE16 (0116), 38FF16 (5316)
3AFE16 (8016), 3AFF16 (5416)
<“FF16”> address (test data)
■M37272E8SP/FP <“8016”> address (test data)
114FE16 (0916), 1 14FF 16 (5116)
116FE16 (0016), 116FF16 (5216)
118FE16 (1216), 118FF16 (5316)
11AFE16 (0016), 11AFF16 (5416)
11CFE16 (2416), 11CFF16 (5516)
11EFE16 (0016), 11EFF16 (5616)
120FE16 (8816), 120FF16 (5716)
122FE16 (0016), 122FF16 (5816)
124FE16 (9016), 124FF16 (5916)
126FE16 (4816), 126FF16 (5A16)
128FE16 (2416), 128FF16 (5B16)
12AFE16 (0016), 12AFF16 (5C16)
12CFE16 (2416), 12CFF16 (5D16)
12EFE16 (4816), 12EFF16 (5E16)
130FE16 (0016), 130FF16 (5F16)
132FE16 (4816), 132FF16 (5016)
134FE16 (9016), 134FF16 (5116)
136FE16 (0016), 136FF16 (5216)
138FE16 (0116), 138FF16 (5316)
13AFE16 (8016), 13AFF16 (5416)
<“7F16”> address (test data)
■M37272EFSP <“8016”> address (test data)
75
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Table 8.11.3 Contents of OSD RAM
Block Character Code Specification Color Code Specification
31st character
3rd character
:
30th character
2nd character
32nd character
31st character
3rd character
:
30th character
1st character
2nd character
32nd character
081E16
080216
:
081D16
080116
081F16
085E16
084216
:
085D16
084016
084116
085F16
083E16
082216
:
083D16
082116
083F16
087E16
086216
:
087D16
086016
086116
087F16
Block 1
Display Position (from left)
Block 2
1st character 080016 082016
(2) OSD RAM
The RAM for OSD is allocated at addresses 080016 to 087F16, and
is divided into a display character code specification part, color code
1 specification part, and color code 2 specification part for each block.
Table 8.11.3 shows the contents of the OSD RAM.
For example, to display 1 character position (the left edge) in block
1, write the character code in address 080016, write the color code 1
at 082016.
The structure of the OSD RAM is shown in Figure 8.11.16.
76
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.11.16 Bit structure of OSD RAM
Bit name
Control of
character color R
Control of
character color G
Control of
character color B
OUT1/OUT2 control
Flash control
Underline control
Italic control
Bit
RF0
RF1
RF2
RF3
RF4
RF5
RF6
RF7
RA0
RA1
RA2
RA3
RA4
RA5
RA6
Function
Character code in
OSD ROM
0: Color signal output OFF
1: Color signal output ON
0: Flash OFF
1: Flash ON
0: Underline OFF
1: Underline ON
0: Italic OFF
1: Italic ON
Bit name
Control of
character color R
Control of
character color G
Control of
character color B
OUT1/OUT2 control
Control of
background color R
Control of
background color G
Control of
background color B
CC mode Function
Character code in
OSD ROM
0: Color signal output OFF
1: Color signal output ON
0: Color signal output OFF
1: Color signal output ON
OSD mode
Notes 1: Read value of bits 7 of the color code is “0.”
2: For OUT1/OUT2 control, refer to “8.11.8 OUT1/OUT2 signal.”
3: “7F16” and “8016” cannot be used as character code.
Character code Character code
(See note 2) (See note 2)
R
A
6 R
A
5 R
A
4 R
A
3 R
A
2 R
A
1 R
A
0 R
F
7 R
F
6 R
F
5 R
F
4 R
F
3 R
F
2 R
F
1R
F
0
b
0b
7b
0b
7
B
l
o
c
k
s
1
,
2
C
h
a
r
a
c
t
e
r
c
o
d
e
(
S
e
e
n
o
t
e
3
)C
o
l
o
r
c
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d
e
1
(
S
e
e
n
o
t
e
1
)
77
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.11.7 Character background color
The character background color can be displayed in the character
display area only in the OSD mode. The character background color
for each character is specified by the color code.
<7 kinds>
Specified by bits 4 (R), 5 (G), and 6 (B) of the color code
Note : The character background color is displayed in the following part :
(character display area)–(character font)–(border).
Accordingly, the character background color does not mix with these
color signal.
8.11.6 Character color
The color for each character is displayed by the color code.
<7 kinds>
Specified by bits 0 (R), 1 (G), and 2 (B) of the color code
78
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.11.8 OUT1, OUT2 signals
The OUT1, OUT2 signals are used to control the luminance of the
video signal. The output waveform of the OUT1, OUT2 signals is
controlled by display mode, bit 5 of the block control register i (refer
to Figure 8.11.4) and RA3 of OSD RAM. The setting values for
Fig. 8.11.17 Setting Value for Controlling OUT1, OUT2 and Corresponding Output Waveform
controlling OUT1, OUT2 and the corresponding output waveform is
shown in Figure 8.11.17.
Note : When OUT2 signal is output, set bit 7 of OSD port control register (refer
to Figure 8.11.28) to “1.”
0
(
O
U
T
1
o
u
t
p
u
t
i
s
c
o
n
t
r
o
l
l
e
d
b
y
R
A
3
)
1
O
U
T
1
=
F
O
N
T
/
B
O
R
D
E
R
D
i
s
p
l
a
y
M
o
d
e
O
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T
1
/
O
U
T
2
O
u
t
p
u
t
C
o
n
t
r
o
l
B
i
t
(
b
5
)
O
U
T
1
/
O
U
T
2
C
o
n
t
r
o
lO
u
t
p
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W
a
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f
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m
(
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A
'
)
O
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C
C
1
(
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2
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A
3
)
0
1
0
1
0
1
0
O
U
T
2
=
“
L
”
O
U
T
1
=
A
R
E
A
O
U
T
2
=
“
L
”
O
U
T
1
=
F
O
N
T
/
B
O
R
D
E
R
O
U
T
2
=
“
L
”
O
U
T
1
=
F
O
N
T
/
B
O
R
D
E
R
O
U
T
2
=
A
R
E
A
O
U
T
1
=
F
O
N
T
O
U
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2
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79
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.1 1.9 Attribute
The attributes (border, flash, underline, italic) are controlled to the
character font. The attributes to be controlled are different depend-
ing on each mode.
CC mode ..................... Flash, underline, italic (per character unit)
OSD mode .................. Border (per character unit)
(1) Under line
The underline is output at the 23th and 24th dots in vertical direction
only in the CC mode. The underline is controlled by RA5 of OSD
RAM. The color of underline is the same color as that of the charac-
ter font.
(2) Flash
The character font and the underline are flashed only in the CC mode.
The flash is controlled by RA4 of OSD RAM. As for character font
part, the character output part is flashed, the character background
part is not flashed. The flash cycle bases on the VSYNC count.
• VSYNC cycle ✕ 48 ≈ 800 ms (at display ON)
• VSYNC cycle ✕ 16 ≈ 267 ms (at display OFF)
(3) Italic
The italic is made by slanting the font stored in OSD ROM to the right
only in the CC mode. The italic is controlled by RA6 of OSD RAM.
The display example of the italic and underline is shown in Figure
8.11.8. In this case, “R” is displayed.
Notes 1: When setting both the italic and the flash, the italic character flashes.
2: The boundary of character color is displayed in italic. However, the
boundary of character background color is not affected by the italic
(refer to Figure 8.11.19).
3: The adjacent character (one side or both side) to an italic character is
displayed in italic even when the character is not specified to display
in italic (refer to Figure 8.11.19).
Fig. 8.11.18 Example of Attribute Display (in CC Mode)
C
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6
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R
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h
80
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.4
81
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.11.19 Example of Italic Display
10 0 1 1 0 1
(
R
e
f
e
r
t
o
“
8
.
1
1
.
9
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2
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t
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r
82
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
(4) Border
The border is output around of character font (all bordered) in the
OSD mode. The border ON/OFF is controlled by bit 0 and 1 of the
block control register i (refer to Figure 8.11.4).
The OUT1 signal is used for border output.
The horizontal size (x) of border is 1TC (OSD clock cycle divided in
pre-divide circuit) regardless of the character font dot size. The verti-
cal size (y) different depending on the screen scan mode and the
vertical dot size of character font.
Notes 1 : The border dot area is the shaded area as shown in Figure 8.11.20.
2 : When the border dot overlaps on the next character font, the charac-
ter font has priority (refer to Figure 8.11.22 A).
When the border dot overlaps on the next character back ground, the
border has priority (refer to Figure 8.11.22 B).
3 : The border in vertical out of character area is not displayed (refer to
Figure 8.11.22).
Fig. 8.11.20 Example of Border Display
Fig. 8.11.21 Horizontal and Vertical Size of Border
A
l
l
b
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)
83
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.11.22 Border Priority
Character boundary
BCharacter boundary
ACharacter boundary
B
84
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.11.10 Multiline Display
This microcomputer can ordinarily display 2 lines on the CRT screen
by displaying 2 blocks at different vertical positions. In addition, it can
display up to 16 lines by using OSD interrupts.
An OSD interrupt request occurs at the point at which display of each
block has been completed. In other words, when a scanning line
reaches the point of the display position (specified by the vertical
position registers) of a certain block, the character display of that
block starts, and an interrupt occurs at the point at which the scan-
ning line exceeds the block.
Notes 1: An OSD interrupt does not occur at the end of display when the block
is not displayed. In other words, if a block is set to off display by the
display control bit of the block control register (addresses 00D216,
00D316), an OSD interrupt request does not occur (refer to Figure
8.11.23 (A)).
2: When another block display appeares while one block is displayed,
an OSD interrupt request occurs only once at the end of the another
block display (refer to Figure 8.11.23 (B)).
3: On the screen setting window, an OSD interrupt occurs even at the
end of the CC mode block (off display) out of window (refer to Figure
8.11.23 (C)).
Fig. 8.11.23 Note on Occurence of OSD Interrupt
(B) (C)
Block 1 (on display)
Block 2 (on display)
Block 1’ (on display)
Block 2’ (on display)
Block 1 (on display)
Block 2 (on display)
Block 1’ (off display)
Block 2’ (off display)
“OSD interrupt request”
“OSD interrupt request”
“OSD interrupt request”
“OSD interrupt request”
“OSD interrupt request”
“OSD interrupt request”
No
“OSD interrupt request”
Block 1
Block 2 “OSD interrupt request”
“OSD interrupt request”
“OSD interrupt request”
“OSD interrupt request”
Block 1
Block 2
Block 1’
On display (OSD interrupt request occurs
at the end of block display) Off display (OSD interrupt request does
not occur at the end of block display)
In CC mode
Window
No
“OSD interrupt request”
No
“OSD interrupt request”
(A)
85
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Notes : The character code “0916” is used for “transparent space” when dis-
playing Closed Caption.
Therefore, set “0016” to the 40-byte addresses corresponding to the
character code “0916.”
<Transparent space font data storing area>
■ M37272M6/M8-XXXSP/FP, M37272E8SP/FP
addresses 100016 + (4 + 2n) ✕ 10016 + 1216 to
100016 + (4 + 2n) ✕ 10016 + 1316
(n = 0 to 19)
addresses 141216 and 141316
addresses 161216 and 161316
addresses 381216 and 381316
addresses 3A1216 and 3A1316
■ M37272MA-XXXSP, M37272EFSP
addresses 1100016 + (4 + 2n) ✕ 10016 + 1216 to
1100016 + (4 + 2n) ✕ 10016 + 1316
(n = 0 to 19)
addresses 1141216 and 1141316
addresses 1161216 and 1161316
addresses 1381216 and 1381316
addresses 13A1216 and 13A1316
8.11.11 Automatic Solid Space Function
This function generates automatically the solid space (OUT1 or OUT2
blank output) of the character area in the CC mode.
The solid space is output in the following area :
• Any character area except character code “0916 ”
• Character area on the left and right sides of the above character
This function is turned on and off by bit 1 of the OSD control register
(refer to Figure 8.11.3).
Fig. 8.11.24 Display Screen Example of Automatic Solid Space
…
0
50
90
90
90
60
6
1
61
61
61
61
61
6
0
60
9
1
61
6
•
•
•
•
•
•
0
9
1
6
0
6
1
6
W
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1
6
”
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,
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1
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.
(
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3
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1
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.
…
86
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.11.12 Window Function
This function sets the top and bottom boundary of display limit on a
screen. The window function is valid only in the CC mode. The top
boundary is set by the window registers 1 and bit 7 of block control
register 1. The bottom boundary is set by window registers 1 and bit
7 of block control register 2. This function is turned on and off by bit
2 of the OSD control register (refer to Figure 8.11.3).
The window registers 1 and 2 is shown in Figures 8.1 1.26 and 8.1 1.27.
Fig. 8.11.25 Example of Window Function
OSD mode
Window
FGHIJ
CC mode
KLMNO
CC mode
PQRST
CC mode
OSD mode Bottom
boundary
of window
Top
boundary
of window
Screen
ABCDE
UVWXY
87
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.11.26 Window Register 1
Fig. 8.11.27 Window Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
to
7
R W
Window Register 1
Window register 1 (WN1) [Address 00D6
16
]
BName Functions After reset RW
Inderterminate
Window top boundary
control bits
(WN10 to WN17)
Window top border position =
T
H
✕ (BC17 ✕ 16
2
+ n)
(n: setting value, T
H
: H
SYNC
cycle,
BC17: bit 7 of block control register 1)
Notes 1: Set values except “00
16
” to WN1 when BC17 is “0.”
2: Set values fit for the following condition: WN1 < WN2.
b7 b6 b5 b4 b3 b2 b1 b0
0
to
7
R W
Window Register 2
Window register 2 (WN2) [Address 00D716]
BName Functions After reset RW
Inderterminate
Window bottom boundary
control bits
(WN20 to WN27)
Window bottom border position =
TH ✕ (BC27 ✕ 162 + n)
(n: setting value, TH: HSYNC cycle,
BC27: bit 7 of block control register 2)
Note: Set values fit for the following condition: WN1 < WN2.
88
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.11.13 OSD Output Pin Control
The OSD output pins R, G, B and OUT1 can also function as ports
P52–P55. Set corresponding bit of the OSD port control register (ad-
dress 00CB16) to “0” to specify these pins as OSD output pins, or set
it to “1” to specify it as a general-purpose port P5.
The OUT2 can also function as port P10. Set bit 0 of the port P1
direction register (address 00C316) to “1” (output mode). After that,
set bit 7 of the OSD port control register to “1” to specify the pin as
OSD output pin, or set it to “0” to specify as port P10.
The input polarity of the HSYNC, VSYNC and output polarity of signals
R, G, B, OUT1 and OUT2 can be specified with the I/O polarity con-
trol register (address 00D8) . Set a bit to “0” to specify positive polar-
ity; set it to “1” to specify negative polarity (refer to Figure 8.11.13).
The structure of the OSD port control register is shown in Figure
8.11.28.
Fig. 8.11.28 OSD Port Control Register
b
7b
6b
5b
4b
3b
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89
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.11.14 Raster Coloring Function
An entire screen (raster) can be colored by setting the bits 4 to 0 of
the raster color register . Since each of the R, G, B, OUT1, and OUT2
pins can be switched to raster coloring output, 8 raster colors can be
obtained.
When the character color/the character background color overlaps
with the raster color, the color (R, G, B, OUT1, OUT2), specified for
the character color/the character background color, takes priority of
the raster color. This ensures that character color/character back-
ground color is not mixed with the raster color.
The raster color register is shown in Figure 8.11.29, the example of
raster coloring is shown in Figure 8.11.30.
Fig. 8.11.29 Raster Color Register
b7b6b5b4b3b2b1b0 Raster color register (RC) [Address 00D9
16
]
B Name Functions
After reset
RW
Raster Color Register
0 Raster color R
control bit (RC0) 0 : No output
1 : Output 0
1Raster color G
control bit (RC1) 0 : No output
1 : Output 0
20 : No output
1 : Output 0
0
4 Raster color OUT2
control bit (RC4) 0
Raster color B
control bit (RC2)
RW
RW
RW
RW
RW
30 : No output
1 : Output
Raster color OUT1
control bit (RC3)
5, 6
0 : No output
1 : Output
7
Fix these bits to “0.” 0RW
0RW
0
Note: Either OSD clock source or 32 kHz oscillating clock is
selected by bits 5 and 6 of the OSD control register.
0
Port function
selection bit (RC7) 0 : OSC1/X
CIN
,
OSC2/X
COUT
1 : P2
6
, P2
7
90
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig. 8.11.30 Example of Raster Coloring
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91
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig.8.12.1 Sequence at Detecting Software Runaway Detection
8.12 SOFTWARE RUNAWAY DETECT FUNCTION
This microcomputer has a function to decode undefined instructions
to detect a software runaway.
When an undefined op-code is input to the CPU as an instruction
code during operation, the following processing is done.
➀The CPU generates an undefined instruction decoding signal.
➁The device is internally reset because of occurrence of the unde-
fined instruction decoding signal.
➂As a result of internal reset, the same reset processing as in the
case of ordinary reset operation is done, and the program restarts
from the reset vector.
Note, however, that the software runaway detecting function cannot
be invalid.
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92
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.13. RESET CIRCUIT
When the oscillation of a quartz-crystal oscillator or a ceramic reso-
nator is stable and the power source voltage is 5 V ± 10 %, hold the
RESET pin at LOW for 2 µs or more, then return is to HIGH. Then, as
shown in Figure 8.13.2, reset is released and the program starts form
the address formed by using the content of address FFFF16 as the
high-order address and the content of the address FFFE16 as the
low-order address. The internal state of microcomputer at reset are
shown in Figures 8.2.3 to 8.2.6.
An example of the reset circuit is shown in Figure 8.13.1.
The reset input voltage must be kept 0.9 V or less until the power
source voltage surpasses 4.5 V.
Fig.8.13.2 Reset Sequence
Fig.8.13.1 Example of Reset Circuit
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93
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
8.14 CLOCK GENERATING CIRCUIT
This microcomputer has 2 built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance with
the resonator manufacturer’s recommended values. No external re-
sistor is needed between XIN and XOUT since a feed-back resistor
exists on-chip. However, an external feed-back resistor is needed
between XCIN and XCOUT. When using XCIN-XCOUT as sub-clock,
clear bits 5 and 6 of the OSD control register to “0.” To supply a clock
signal externally, input it to the XIN (XCIN) pin and make the XOUT
(XCOUT) pin open. When not using XCIN clock, connect the XCIN to
VSS and make the XCOUT pin open.
After reset has completed, the internal clock φ is half the frequency of
XIN. Immediately after poweron, both the XIN and XCIN clock start
oscillating. To set the internal clock φ to low-speed operation mode,
set bit 7 of the CPU mode register to “1.”
8.14.1 OSCILLATION CONTROL
(1) Stop Mode
The built-in clock generating circuit is shown in Figure 120. When the
STP instruction is executed, the internal clock φ stops at HIGH. At
the same time, timers 3 and 4 are connected by hardware and “FF16”
is set in timer 3 and “0716” is set in timer 4. Select f(XIN)/16 or f(XCIN)/
16 as the timer 3 count source (set both bit 0 of the timer mode
register 2 and bit 6 at address 00C716 to “0” before the execution of
the STP instruction). Moreover, set the timer 3 and timer 4 interrupt
enable bits to disabled (“0”) before execution of the STP instruction.
The oscillator restarts when external interrupt is accepted. However ,
the internal clock φ keeps its HIGH level until timer 4 overflows, al-
lowing time for oscillation stabilization when a ceramic resonator or a
quartz-crystal oscillator is used.
(2) Wait Mode
When the WIT instruction is executed, the internal clock φ stops in
the HIGH level but the oscillator continues running. This wait state is
released at reset or when an interrupt is accepted (See note). Since
the oscillator does not stop, the next instruction can be executed at
once.
Note: In the wait mode, the following interrupts are invalid.
• VSYNC interrupt
• OSD interrupt
• All timer interrupts using external clock input from port pin as count
source
• All timer interrupts using f(XIN)/2 or f(XCIN)/2 as count source
• All timer interrupts using f(XIN)/4096 or f(XCIN)/4096 as count source
• f(XIN)/4096 interrupt
• Multi-master I2C-BUS interface interrupt
• Data slicer interrupt
• A-D conversion interrupt
Fig.8.14.1 Ceramic Resonator Circuit Example
Fig.8.14.2 External Clock Input Circuit Example
(3) Low-speed Mode
If the internal clock is generated from the sub-clock (XCIN), a low
power consumption operation can be realized by stopping only the
main clock XIN. To stop the main clock, set bit 6 (CM6) of the CPU
mode register (00FB16) to “1.” When the main clock XIN is restarted,
the program must allow enough time to for oscillation to stabilize.
Note that in low-power-consumption mode the XCIN-XCOUT drivability
can be reduced, allowing even lower power consumption. To reduce
the XCIN-XCOUT drivability, clear bit 5 (CM5) of the CPU mode regis-
ter (00FB16) to “0.” At reset, this bit is set to “1” and strong drivability
is selected to help the oscillation to start. When an STP instruction is
executed, set this bit to “1” by software before executing.
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94
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig.8.14.3 Clock Generating Circuit Block Diagram
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95
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig.8.14.4 State Transitions of System Clock
R
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96
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
RESET
Vss
Vcc
Circuit example 1
RESET
Vss
Vcc
Circuit example 2
Note : Make the level change from “L” to “H” at the point at
which the power source voltage exceeds the specified
voltage.
8.15 DISPLAY OSCILLATION CIRCUIT
The OSD oscillation circuit has a built-in clock oscillation circuits, so
that a clock for OSD can be obtained simply by connecting an LC, a
ceramic resonator , or a quartz-crystal oscillator across the pins OSC1
and OSC2. Which of the sub-clock or the OSD oscillation circuit is
selected by setting bits 5 and 6 of the OSD control register (address
00D016).
8.17 ADDRESSING MODE
The memory access is reinforced with 17 kinds of addressing modes.
Refer to SERIES 740 <Software> User’s Manual for details.
8.18 MACHINE INSTRUCTIONS
There are 71 machine instructions. Refer to SERIES 740 <Soft- ware>
User’s Manual for details.
9. PROGRAMMING NOTES
• The divide ratio of the timer is 1/(n+1).
• Even though the BBC and BBS instructions are executed imme-
diately after the interrupt request bits are modified (by the pro-
gram), those instructions are only valid for the contents before
the modification. At least one instruction cycle is needed (such as
an NOP) between the modification of the interrupt request bits
and the execution of the BBC and BBS instructions.
• After the ADC and SBC instructions are executed (in the decimal
mode), one instruction cycle (such as an NOP) is needed before
the SEC, CLC, or CLD instruction is executed.
• An NOP instruction is needed immediately after the execution of
a PLP instruction.
• In order to avoid noise and latch-up, connect a bypass capacitor
(≈ 0.1µF) directly between the VCC pin–VSS pin, AVCC pin–VSS
pin, and the VCC pin–CNVSS pin, using a thick wire.
Fig.8.15.1 Display Oscillation Circuit
8.16 AUTO-CLEAR CIRCUIT
When a power source is supplied, the auto-clear function will oper-
ate by connecting the following circuit to the RESET pin.
Fig.8.16.1 Auto-clear Circuit Example
OSC2OSC1
L
C1 C2
Symbol Parametear
10. ABSOLUTE MAXIMUM RATINGS
11. RECOMMENDED OPERATING CONDITIONS (Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Ratings
–0.3 to 6
–0.3 to 6
–0.3–VCC + 0.3
–0.3–VCC + 0.3
–0.3 to 13
0 to 1 (See note 1)
0 to 2 (See note 2)
0 to 6 (See note 2)
0 to 1 (See note 2)
0 to 10 (See note 3)
550
–10 to 70
–40 to 125
Parametear
Power source voltage
VCC, AVCC
Input voltage CNVSS
Input voltage P00–P07, P10–P17, P2 0–P27,
P3
0
,
P3
1
, P5
0
, P5
1
, X
IN
, RESET, CV
IN
Output voltage P06, P07, P10–P17, P20–P27,
P30, P31, P52–P55, XOUT
Output voltage P00–P05
Circuit current P10–P17, P20–P27, P30, P31
P52–P55
Circuit current P06, P07, P10, P15–P17, P20–P23,
P26, P27, P52–P55
Circuit current P11–P14
Circuit current P00–P05
Circuit current P24, P25, P30, P31
Power dissipation
Operating temperature
Storage temperature
Conditions
All voltages are based
on VSS.
Output transistors are
cut off.
Ta = 25 °C
Unit
V
V
V
V
V
mA
mA
mA
mA
mA
mW
°C
°C
Symbol
VCC, AVCC
VI
VI
VO
VO
IOH
IOL1
IOL2
IOL3
IOL4
Pd
Topr
Tstg
Min.
4.5
0
0.8 VCC
0.7 VCC
0
0
0
7.9
29
26.5
15.262
1.5
Typ.
5.0
0
8.0
32
27.0
15.734
2.0
Max.
5.5
0
VCC
VCC
0.4 VCC
0.3 VCC
0.2 VCC
1
2
6
1
10
8.1
35
27.0
100
1
400
16.206
2.5
Limits
VCC, AVCC
VSS
VIH1
VIH2
VIL1
VIL2
VIL3
IOH
IOL1
IOL2
IOL3
IOL4
f(XIN)
f(XCIN)
fOSC
fhs1
fhs2
fhs3
fhs4
VI
Power source voltage (See note 4)
Power source voltage
HIGH Input voltage P00–P07, P10–P17, P20–P27, P30, P31, P50, P51,
RESET, XIN
HIGH Input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS)
LOW Input voltage P00–P07, P10–P17, P20–P27, P30, P31
LOW Input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS)
LOW Input voltage (See note 6) P50, P51, RESET, XIN, OSC1, TIM2,
TIM3, INT1, INT2, INT3, SIN, SCLK
HIGH average output current (See note1)
P10–P17, P20–P27, P30, P31, P52–P55
LOW average output current (See note 2)
P06, P07, P10, P15–P17, P20–P23,
P26, P27, P52–P55
LOW average output current (See note 2)
P11–P14
LOW average output current (See note 2)
P00–P05
LOW average output current (See note 3)
P24, P25, P30, P31
Oscillation frequency (for CPU operation) (See note 5) XIN
Oscillation frequency (for sub-clock operation) XCIN
Oscillation frequency (for OSD) OSC1
Input frequency TIM2, TIM3, INT1, INT2, INT3
Input frequency SCLK
Input frequency SCL1, SCL2
Input frequency Horizontal sync. signal of video signal
Input amplitude video signal CVIN
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
MHz
kHz
MHz
kHz
MHz
kHz
kHz
V
Unit
97
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.4
Max.
30
45
200
4
100
10
0.4
3.0
0.4
0.6
1.3
5
5
10
130
VCC = 5.5V,
f(XIN) = 8MHz
VCC = 5.5V, f(XIN) = 0,
f(XCIN) = 32kHz,
OSD OFF, Data slicer OFF,
Low-power dissipation mode set
(CM5 = “0”, CM6 = “1”)
VCC = 5.5 V, f(XIN) = 8 MHz
VCC = 5.5 V, f(XIN) = 0,
f(XCIN) = 32 kHz,
Low-power dissipation mode set
(CM5 = “0”, CM6 = “1”)
VCC = 5.5V, f(XIN) = 0,
f(XCIN) = 0
VCC = 4.5 V
IOH = –0.5 mA
VCC = 4.5 V
IOL = 0.5 mA
VCC = 4.5 V
IOL = 10.0 mA
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VI = 5.5 V
VCC = 5.5 V
VI = 0 V
VCC = 5.5 V
VI = 12 V
VCC = 4.5 V
12. ELECTRIC CHARACTERISTICS (VCC = 5 V ± 10 %, V SS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted)
Notes 1:The total current that flows out of the IC must be 20 mA or less.
2:The total input current to IC (IOL1 + IOL2 + IOL3) must be 30 mA or less.
3:The total average input current for ports P30, P31, P24 and P25 and AVCC–VSS to IC must be 20 mA or less.
4:Connect 0.1 µF or more capacitor externally between the power source pins VCC–VSS and A VCC–VSS so as to reduce power source noise.
Also connect 0.1 µF or more capacitor externally between the pins VCC–CNVSS.
5:Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz.
6:P06, P07, P15, P23, P24 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P11–P14 have the hysteresis when these
pins are used as multi-master I2C-BUS interface ports. P20–P22 have the hysteresis when these pins are used as serial I/O pins.
7:Pin names in each parameter is described as below.
(1) Dedicated pins: dedicated pin names.
(2) Duble-/triple-function ports
• When the same limits: I/O port name.
• When the limits of functins except ports are different from I/O port limits: function pin name.
HIGH output voltage P10–P17, P20–P27,
P30, P31, P52–P55,
LOW output voltage P00–P07, P10,
P15–P17, P20–P23,
P26, P27, P52–P55
LOW output voltage P24, P25, P30, P31
LOW output voltage P11–P14
Hysteresis (See note 6)
RESET, P50, P51, INT1, INT2,
INT3, TIM2, TIM3, SIN, SCLK, SCL1,
SCL2, SDA1, SDA2
HIGH input leak current
P06, P07, P10–P17, P20–P27,
P30, P31, RESET, P50, P51,
HIGH input leak current
P00–P07, P10–P17, P20–P27, P30,
P31, P50, P51, RESET
HIGH output leak current
P00–P05
I2C-BUS • BUS switch connection resistor
(between SCL1 and SCL2, SDA1 and SDA2)
ICC
Symbol Parametear Test conditions
OSD OFF
Data slicer OFF
OSD ON
Data slicer ON
Stop mode
Wait mode
System operation
Power source current
VOH
VOL
VT+ –VT–
IIZH
IIZL
IOZH
RBS
Test
circuit
1
Min.
2.4
Limits
IOL = 3 mA
IOL = 6 mA
Typ.
15
30
60
2
25
1
0.5
2
3
4
5
6
4
Unit
mA
µ
A
mA
µ
A
V
V
V
µ
A
µ
A
µ
A
Ω
98
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.4
99
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Fig.12.1 Measure Circuits
1
3
5
2
4
6
V
s
s
V
c
c
VV
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.
100
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
13. A-D CONVERTER CHARACTERISTICS
(VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted)
Resolution
Non-linearity error
Differencial non-linearity error
Zero transition error
Full-scale transition error
Max.
6
±1
±0.9
2
–2
bits
LSB
LSB
LSB
LSB
Min. Limits UnitTest conditionsParameterSymbol
—
—
—
V0T
VFST
IOL (SUM) = 0 mA
Typ.
14. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS
Bus free time
Hold time for START condition
LOW period of SCL clock
Rising time of both SCL and SDA signals
Data hold time
HIGH period of SCL clock
Falling time of both SCL and SDA signals
Data set-up time
Set-up time for repeated START condition
Set-up time for STOP condition
tBUF
tHD; STA
tLOW
tR
tHD; DAT
tHIGH
tF
tSU; DAT
tSU; STA
tSU; STO
Max.
1000
300
Min.
1.3
0.6
1.3
20+0.1Cb
0
0.6
20+0.1Cb
100
0.6
0.6
Max.
300
0.9
300
µs
µs
µs
ns
µs
µs
ns
ns
µs
µs
Unit
Standard clock mode High-speed clock mode
ParameterSymbol
Note: Cb = total capacitance of 1 bus line
Fig.14.1 Definition Diagram of Timing on Multi-master I2C-BUS
Min.
4.7
4.0
4.7
0
4.0
250
4.7
4.0
S
D
A
S
C
LP
t
B
U
F
S
t
H
D
;
S
T
A
t
L
O
W
t
R
t
H
D
;
D
A
T
t
H
I
G
H
t
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t
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U
;
D
A
T
t
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;
S
T
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rP
t
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U
;
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T
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t
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D
;
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r
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:
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t
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r
t
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t
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e
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t
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t
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n
:
S
t
o
p
c
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n
d
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t
i
o
n
101
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
15. PROM PROGRAMMING METHOD
The built-in PROM of the One Time PROM version (blank) and the
built-in EPROM version can be read or programmed with a general-
purpose PROM programmer using a special programming adapter.
The PROM of the One Time PROM version (blank) is not tested or
screened in the assembly process nor any following processes. To
ensure proper operation after programming, the procedure shown in
Figure 15.1 is recommended to verify programming.
Fig. 15.1 Programming and Testing of One Time PROM Version
Programming with
PROM programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in target device
Caution : The screening temperature is far higher
than the storage temperature. Never
expose to 150°C exceeding 100 hours.
Name of Programming Adapter
PCA7429G02
PCA7429G02
PCA7427
Product
M37272EFSP
M37272E8SP
M37272E8FP
16. DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
• Mask ROM Order Confirmation Form
• Mark Specification Form
• Data to be written to ROM, in EPROM form (three identical copies)
or FDK
When using EPROM:
<M37272M6/M8-XXXSP/FP, M37272E8SP/FP>
28-pin DIP Type 27512
<M37272MA-XXXSP, M37272EFSP>
32-pin DIP Type 27C101
102
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.4
103
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
17. MASK CONFIRMATION FORM
GZZ–SH55–37B < 91A0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37272M6-XXXSP/FP
MITSUBISHI ELECTRIC
Mask ROM number
Receipt
Date:
Section head
signature Supervisor
signature
✽Customer
Company
name TEL
( )
Date :
Date
issued
Issuance
signature
Note : Please fill in all items marked ✽.
Submitted by Supervisor
✽1. Confirmation
Specify the name of the product being ordered.
Three EPROMs are required for each pattern if this order is performed by EPROMs.
One floppy disk is required for each pattern if this order is performed by a floppy disk.
Ordering by EPROMs
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce
differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM (hexadecimal notation)
EPROM type (indicate the type used)
(1) Set “FF16” in the shaded area.
Microcomputer name : M37272M6-XXXSP M37272M6-XXXFP
EPROM address
Product nameASCII code:
'M37272M6-'
2 7 5 1 2
000016
000F16
1234567890123456
1
23456789012345
6
1
23456789012345
6
1234567890123456
OSDROM
Data ROM
(24K)
140016
3BFF16
1234567890123456
1
23456789012345
6
1
23456789012345
6
1234567890123456
A00016
FFFF16
1/3
104
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
2/3
GZZ–SH55–37B < 91A0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37272M6-XXXSP/FP
MITSUBISHI ELECTRIC
Addresses 000016 to 000F16 store the product
name.
ASCII codes ‘M37272M6-’ are listed on the right.
The addresses and data are in hexadecimal nota-
tion.
Note: If the name of the product contained in the
EPROMs does not match the name on the mask
ROM confirmation form, the ROM processing is
disabled. Please make sure the data is written
correctly.
Ordering by floppy disk
We will produce masks based on the mask files generated by the mask file generating utility. We shall assume
the responsibility for errors only if the mask ROM data on the products we produce differs from this mask file.
Thus, extreme care must be taken to verify the mask file in the submitted floppy disk.
The submitted floppy disk must be 3.5-inch 2HD type and DOS/V format. And the number of the mask files
must be 1 in one floppy disk.
File code (hexadecimal notation)
Mask file name .MSK (equal or less than eight characters)
✽2. Mark specification
Mark specification must be submitted using the correct form for the type of package being ordered. Fill the
appropriate mark specification form (42P4B for M37272M6-XXXSP , 42P2R for M37272M6-XXXFP) and attach
to the mask ROM confirmation form.
✽3. Comments
(2) Write the ASCII codes that indicate the product name of “M37272M6–” to addresses 000016 to 000F16.
Address
000016 ‘M’ = 4D16
000116 ‘3’ = 3316
000216 ‘7’ = 3716
000316 ‘2’ = 3216
000416 ‘7’ = 3716
000516 ‘2’ = 3216
000616 ‘M’ = 4D16
000716 ‘6’ = 3616
Address
000816 ‘–’ = 2D16
000916 FF16
000A16 FF16
000B16 FF16
000C16 FF16
000D16 FF16
000E16 FF16
000F16 FF16
105
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
3/3
GZZ–SH55–37B < 91A0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37272M6-XXXSP/FP
MITSUBISHI ELECTRIC
AD15 AD14AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
0
0A
16
0B
16
0C
16
0D
16
0E
16
0F
16
10
16
11
16
12
16
13
16
14
16
15
16
16
16
17
16
18
16
19
16
1A
16
1B
16
1C
16
1D
16
DB7 DB6 DB5DB4 DB3 DB2DB1 DB0 DB7 DB6 DB5DB4 DB3 DB2DB1 DB0
0
Notes 1 : The 80-byte addresses corresponding to the character code “7F 16” and “8016” in OSD ROM are the test
data storning area. Set “FF16” to the area (We stores the test data to this area and the different data
from “FF16” is stored for the actual products.)
The test data storing area :
addresses 100016 + (4 + 2n) ✕ 10016 + FE16 to 100016 + (5 + 2n) ✕ 10016 + 0116 (n = 0 to 19)
2 : The character code “0916” is used for “transparent space” when displaying Closed Caption.
Therefore, set “0016” to the 40-byte addresses corresponding to the character code “09 16.”
The transparent space font data storing area :
addresses 100016 + (4 + 2n) ✕ 10016 + 1216 to 100016 + (4 + 2n) ✕ 10016 + 1316 (n = 0 to 19)
Font data must be stored in the proper OSD ROM address according to the following table.
OSD ROM address of character font data
Line number = 0A16 to 1D16
Character code = 0016 to FF16 (Do not set 7F16 and 8016.)
Font bit = 0: Left font
1: Right font
OSD ROM address bit
Line number / Character code /
Font bit Font
bit
Line number Character code
Example) The font data “60” (shaded area ) of the character code “AA 16” is stored in address
0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 0 2 =255416.
Left font Right font
Line number
Character code “AA16”
addresses 14FE16 to 150116
addresses 16FE16 to 170116
addresses 38FE16 to 390116
addresses 3AFE16 to 3B0116
•
•
•
addresses 141216 and 141316
addresses 161216 and 161316
addresses 381216 and 381316
addresses 3A1216 and 3A1316
•
•
•
106
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
1/3
GZZ–SH55–38B < 91A0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37272M8-XXXSP/FP
MITSUBISHI ELECTRIC
Mask ROM number
Receipt
Date:
Section head
signature Supervisor
signature
✽Customer
Company
name TEL
( )
Date :
Date
issued
Issuance
signature
Note : Please fill in all items marked ✽.
Submitted by Supervisor
✽1. Confirmation
Specify the name of the product being ordered.
Three EPROMs are required for each pattern if this order is performed by EPROMs.
One floppy disk is required for each pattern if this order is performed by a floppy disk.
Ordering by EPROMs
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce
differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM (hexadecimal notation)
EPROM type (indicate the type used)
(1) Set “FF16” in the shaded area.
Microcomputer name : M37272M8-XXXSP M37272M8-XXXFP
EPROM address
Product nameASCII code:
'M37272M8-'
2 7 5 1 2
000016
000F16
1234567890123456
1
23456789012345
6
1
23456789012345
6
1234567890123456
OSDROM
Data ROM
(32K)
140016
3BFF16
1234567890123456
1
23456789012345
6
1
23456789012345
6
1234567890123456
800016
FFFF16
107
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
2/3
GZZ–SH55–38B < 91A0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37272M8-XXXSP/FP
MITSUBISHI ELECTRIC
Addresses 000016 to 000F16 store the product
name.
ASCII codes ‘M37272M8-’ are listed on the right.
The addresses and data are in hexadecimal nota-
tion.
Note: If the name of the product contained in the
EPROMs does not match the name on the mask
ROM confirmation form, the ROM processing is
disabled. Please make sure the data is written
correctly.
Ordering by floppy disk
We will produce masks based on the mask files generated by the mask file generating utility. W e shall assume
the responsibility for errors only if the mask ROM data on the products we produce differs from this mask file.
Thus, extreme care must be taken to verify the mask file in the submitted floppy disk.
The submitted floppy disk must be 3.5-inch 2HD type and DOS/V format. And the number of the mask files must
be 1 in one floppy disk.
File code (hexadecimal notation)
Mask file name .MSK (equal or less than eight characters)
✽2. Mark specification
Mark specification must be submitted using the correct form for the type of package being ordered. Fill the
appropriate mark specification form (42P4B for M37272M8-XXXSP , 42P2R for M37272M8-XXXFP) and attach
to the mask ROM confirmation form.
✽3. Comments
(2) Write the ASCII codes that indicate the product name of “M37272M8–” to addresses 000016 to 000F16.
Address
000016 ‘M’ = 4D16
000116 ‘3’ = 3316
000216 ‘7’ = 3716
000316 ‘2’ = 3216
000416 ‘7’ = 3716
000516 ‘2’ = 3216
000616 ‘M’ = 4D16
000716 ‘8’ = 3816
Address
000816 ‘–’ = 2D16
000916 FF16
000A16 FF16
000B16 FF16
000C16 FF16
000D16 FF16
000E16 FF16
000F16 FF16
108
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
3/3
GZZ–SH55–38B < 91A0 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37272M8-XXXSP/FP
MITSUBISHI ELECTRIC
AD15 AD14AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
0
0A16
0B16
0C16
0D16
0E16
0F16
1016
1116
1216
1316
1416
1516
1616
1716
1816
1916
1A16
1B16
1C16
1D16
DB7 DB6 DB5DB4 DB3 DB2DB1 DB0 DB7 DB6 DB5DB4 DB3 DB2DB1 DB0
0
Notes 1 : The 80-byte addresses corresponding to the character code “7F
16
” and “80
16
” in OSD ROM are the test
data storning area. Set “FF
16
” to the area (We stores the test data to this area and the different data
from “FF
16
” is stored for the actual products.)
The test data storing area :
addresses 1000
16
+ (4 + 2n) ✕ 100
16
+ FE
16
to 1000
16
+ (5 + 2n) ✕ 100
16
+ 01
16
(n = 0 to 19)
2 : The character code “09
16
” is used for “transparent space” when displaying Closed Caption.
Therefore, set “00
16
” to the 40-byte addresses corresponding to the character code “09
16
.”
The transparent space font data storing area :
addresses 1000
16
+ (4 + 2n) ✕ 100
16
+ 12
16
to 1000
16
+ (4 + 2n) ✕ 100
16
+ 13
16
(n = 0 to 19)
addresses 14FE
16
to 1501
16
addresses 16FE
16
to 1701
16
addresses 38FE
16
to 3901
16
addresses 3AFE
16
to 3B01
16
•
•
•
addresses 1412
16
and 1413
16
addresses 1612
16
and 1613
16
addresses 3812
16
and 3813
16
addresses 3A12
16
and 3A13
16
•
•
•
Font data must be stored in the proper OSD ROM address according to the following table.
OSD ROM address of character font data
Line number = 0A
16
to 1D
16
Character code = 00
16
to FF
16
(Do not set 7F
16
and 80
16
.)
Font bit = 0: Left font
1: Right font
OSD ROM address bit
Line number / Character code /
Font bit Font
bit
Line number Character code
Example) The font data “60” (shaded area ) of the character code “AA
16
” is stored in address
0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 0
2
=2554
16
.
Left font Right font
Line number
Character code “AA
16
”
1/3
109
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.5
GZZ–SH56–32B < 91A1 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37272MA-XXXSP
MITSUBISHI ELECTRIC
Mask ROM number
Receipt
Date:
Section head
signature Supervisor
signature
✽Customer
Company
name TEL
( )
Date :
Date
issued
Issuance
signature
Note : Please fill in all items marked ✽.
Submitted by Supervisor
✽1. Confirmation
Three EPROMs are required for each pattern if this order is performed by EPROMs.
One floppy disk is required for each pattern if this order is performed by a floppy disk.
Ordering by EPROMs
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on
this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce
differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM (hexadecimal notation)
EPROM type (indicate the type used)
(1) Set “FF16” in the shaded area.
EPROM address
Product nameASCII code:
'M37272MA-'
2 7 C 1 0 1
000016
000F16
12345678901234567
1
234567890123456
7
12345678901234567
OSDROM
Data ROM
(40K)
600016
FFFF16
12345678901234567
1
234567890123456
7
12345678901234567
1140016
1FFFF16
12345678901234567
1
234567890123456
7
1
234567890123456
7
12345678901234567
13BFF16
2/3
110
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.5
GZZ–SH56–32B < 91A1 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37272MA-XXXSP
MITSUBISHI ELECTRIC
Addresses 000016 to 000F16 store the product name.
ASCII codes ‘M37272MA-’ are listed on the right.
The addresses and data are in hexadecimal notation.
Note: If the name of the product contained in the EPROMs does
not match the name on the mask ROM confirmation form,
the ROM processing is disabled. Please make sure the
data is written correctly.
Address
000016 ‘M’ = 4D16
000116 ‘3’ = 3316
000216 ‘7’ = 3716
000316 ‘2’ = 3216
000416 ‘7’ = 3716
000516 ‘2’ = 3216
000616 ‘M’ = 4D16
000716 ‘A’ = 4116
Address
000816 ‘–’ = 2D16
000916 FF16
000A16 FF16
000B16 FF16
000C16 FF16
000D16 FF16
000E16 FF16
000F16 FF16
Ordering by floppy disk
We will produce masks based on the mask files generated by the mask file generating utility. We shall assume
the responsibility for errors only if the mask ROM data on the products we produce differs from this mask file.
Thus, extreme care must be taken to verify the mask file in the submitted floppy disk.
The submitted floppy disk must be 3.5-inch 2HD type and DOS/V format. And the number of the mask files must
be 1 in one floppy disk.
File code (hexadecimal notation)
Mask file name .MSK (equal or less than eight characters)
✽2. Mark specification
Mark specification must be submitted using the correct form for the type of package being ordered. Fill the
appropriate mark specification form (42P4B for M37272MA-XXXSP) and attach to the mask ROM confirmation
form.
✽3. Comments
(2) Write the ASCII codes that indicate the product name of “M37272MA–” to addresses 000016 to 000F16.
3/3
111
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.5
GZZ–SH56–32B < 91A1 >
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37272MA-XXXSP
MITSUBISHI ELECTRIC
A
D
1
5A
D
1
4A
D
1
3A
D
1
2A
D
1
1A
D
1
0A
D
9A
D
8A
D
7A
D
6A
D
5A
D
4A
D
3A
D
2A
D
1A
D
0
0
0
A
1
6
0
B
1
6
0
C
1
6
0
D
1
6
0
E
1
6
0
F
1
6
1
0
1
6
1
1
1
6
1
2
1
6
1
3
1
6
1
4
1
6
1
5
1
6
1
6
1
6
1
7
1
6
1
8
1
6
1
9
1
6
1
A
1
6
1
B
1
6
1
C
1
6
1
D
1
6
D
B
7D
B
6D
B
5D
B
4D
B
3D
B
2D
B
1D
B
0
D
B
7D
B
6D
B
5D
B
4D
B
3D
B
2D
B
1D
B
0
0
A
D
1
6
1
F
o
n
t
d
a
t
a
m
u
s
t
b
e
s
t
o
r
e
d
i
n
t
h
e
p
r
o
p
e
r
O
S
D
R
O
M
a
d
d
r
e
s
s
a
c
c
o
r
d
i
n
g
t
o
t
h
e
f
o
l
l
o
w
i
n
g
t
a
b
l
e
.
O
S
D
R
O
M
a
d
d
r
e
s
s
o
f
c
h
a
r
a
c
t
e
r
f
o
n
t
d
a
t
a
O
S
D
R
O
M
a
d
d
r
e
s
s
b
i
t
L
i
n
e
n
u
m
b
e
r
/
C
h
a
r
a
c
t
e
r
c
o
d
e
/
F
o
n
t
b
i
tF
o
n
t
b
i
t
L
i
n
e
n
u
m
b
e
rC
h
a
r
a
c
t
e
r
c
o
d
e
L
i
n
e
n
u
m
b
e
r
=
0
A
1
6
t
o
1
D
1
6
C
h
a
r
a
c
t
e
r
c
o
d
e
=
0
0
1
6
t
o
F
F
1
6
(
D
o
n
o
t
s
e
t
7
F
1
6
a
n
d
8
0
1
6
.
)
F
o
n
t
b
i
t
=
0
:
:
L
e
f
t
f
o
n
t
1
:
:
R
i
g
h
t
f
o
n
t
E
x
a
m
p
l
e
)
T
h
e
f
o
n
t
d
a
t
a
“
6
0
”
(
s
h
a
d
e
d
a
r
e
a
)
o
f
t
h
e
c
h
a
r
a
c
t
e
r
c
o
d
e
“
A
A
1
6
”
i
s
s
t
o
r
e
d
i
n
a
d
d
r
e
s
s
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
0
2
=
1
2
5
5
4
1
6
.
L
e
f
t
f
o
n
tR
i
g
h
t
f
o
n
t
L
i
n
e
n
u
m
b
e
r
C
h
a
r
a
c
t
e
r
c
o
d
e
“
A
A
1
6
”
2
:
T
h
e
c
h
a
r
a
c
t
e
r
c
o
d
e
“
0
9
1
6
”
i
s
u
s
e
d
f
o
r
“
t
r
a
n
s
p
a
r
e
n
t
s
p
a
c
e
”
w
h
e
n
d
i
s
p
l
a
y
i
n
g
C
l
o
s
e
d
C
a
p
t
i
o
n
.
T
h
e
r
e
f
o
r
e
,
s
e
t
“
0
0
1
6
”
t
o
t
h
e
4
0
-
b
y
t
e
a
d
d
r
e
s
s
e
s
c
o
r
r
e
s
p
o
n
d
i
n
g
t
o
t
h
e
c
h
a
r
a
c
t
e
r
c
o
d
e
“
0
9
1
6
.
”
T
h
e
t
r
a
n
s
p
a
r
e
n
t
s
p
a
c
e
f
o
n
t
d
a
t
a
s
t
o
r
i
n
g
a
r
e
a
:
a
d
d
r
e
s
s
e
s
1
1
0
0
0
1
6
+
(
4
+
2
n
)
✕
1
0
0
1
6
+
1
2
1
6
t
o
1
1
0
0
0
1
6
+
(
4
+
2
n
)
✕
1
0
0
1
6
+
1
3
1
6
(
n
=
0
t
o
1
9
)
a
d
d
r
e
s
s
e
s
1
1
4
F
E
1
6
t
o
1
1
5
0
1
1
6
a
d
d
r
e
s
s
e
s
1
1
6
F
E
1
6
t
o
1
1
7
0
1
1
6
a
d
d
r
e
s
s
e
s
1
3
8
F
E
1
6
t
o
1
3
9
0
1
1
6
a
d
d
r
e
s
s
e
s
1
3
A
F
E
1
6
t
o
1
3
B
0
1
1
6
•
•
•
a
d
d
r
e
s
s
e
s
1
1
4
1
2
1
6
a
n
d
1
1
4
1
3
1
6
a
d
d
r
e
s
s
e
s
1
1
6
1
2
1
6
a
n
d
1
1
6
1
3
1
6
a
d
d
r
e
s
s
e
s
1
3
8
1
2
1
6
a
n
d
1
3
8
1
3
1
6
a
d
d
r
e
s
s
e
s
1
3
A
1
2
1
6
a
n
d
1
3
A
1
3
1
6
•
•
•
N
o
t
e
s
1
:T
h
e
8
0
-
b
y
t
e
a
d
d
r
e
s
s
e
s
c
o
r
r
e
s
p
o
n
d
i
n
g
t
o
t
h
e
c
h
a
r
a
c
t
e
r
c
o
d
e
“
7
F
1
6
”
a
n
d
“
8
0
1
6
”
i
n
O
S
D
R
O
M
a
r
e
t
h
e
t
e
s
t
d
a
t
a
s
t
o
r
n
i
n
g
a
r
e
a
.
S
e
t
“
F
F
1
6
”
t
o
t
h
e
a
r
e
a
(
W
e
s
t
o
r
e
s
t
h
e
t
e
s
t
d
a
t
a
t
o
t
h
i
s
a
r
e
a
a
n
d
t
h
e
d
i
f
f
e
r
e
n
t
d
a
t
a
f
r
o
m
“
F
F
1
6
”
i
s
s
t
o
r
e
d
f
o
r
t
h
e
a
c
t
u
a
l
p
r
o
d
u
c
t
s
.
)
T
h
e
t
e
s
t
d
a
t
a
s
t
o
r
i
n
g
a
r
e
a
:
a
d
d
r
e
s
s
e
s
1
1
0
0
0
1
6
+
(
4
+
2
n
)
✕
1
0
0
1
6
+
F
E
1
6
t
o
1
1
0
0
0
1
6
+
(
5
+
2
n
)
✕
1
0
0
1
6
+
0
1
1
6
(n
=
0
t
o
1
9
)
112
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
18. MARK SPECIFICATION FORM
113
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
113
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
20. APPENDIX
Pin Configuration (TOP VIEW)
Outline 42P4B
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
P
06/
I
N
T
2
/
A
D
4
XO
U
T
P
50/
HS
Y
N
C
P
51/
VS
Y
N
C
P
00/
P
W
M
0
P
01/
P
W
M
1
P
02/
P
W
M
2
P
03/
P
W
M
3
P
04/
P
W
M
4
P
05/
P
W
M
5
P
07/
I
N
T
1
P
23/
T
I
M
3
P
24/
T
I
M
2
P
25
A
VC
C
H
L
F
VH
O
L
D
C
VI
N
C
N
VS
S
XI
N
VS
S
P
52/
R
P
53/
G
P
54/
B
P
55/
O
U
T
1
P
20/
SC
L
K
P
21/
SO
U
T
P
22/
SI
N
P
10/
O
U
T
2
P
11/
S
C
L
1
P
12/
S
C
L
2
P
13/
S
D
A
1
P
14/
S
D
A
2
P
15/
A
D
1
/
I
N
T
3
P
16/
A
D
2
P
30/
A
D
5
P
31/
A
D
6
R
E
S
E
T
P
26/
O
S
C
1
/
XC
I
N
P
27/
O
S
C
2
/
XC
O
U
T
VC
C
P
17/
A
D
3
M
3
7
2
7
2
M
6
/
M
8
/
M
A
-
X
X
X
S
P
M
3
7
2
7
2
E
8
/
E
F
S
P
Outline 42P2R-A/E
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
P
0
6
/
I
N
T
2
/
A
D
4
X
O
U
T
P
5
0
/
H
S
Y
N
C
P
5
1
/
V
S
Y
N
C
P
0
0
/
P
W
M
0
P
0
1
/
P
W
M
1
P
0
2
/
P
W
M
2
P
0
3
/
P
W
M
3
P
0
4
/
P
W
M
4
P
0
5
/
P
W
M
5
P
0
7
/
I
N
T
1
P
2
3
/
T
I
M
3
P
2
4
/
T
I
M
2
P
2
5
A
V
C
C
H
L
F
V
H
O
L
D
C
V
I
N
C
N
V
S
S
X
I
N
V
S
S
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
P
5
2
/
R
P
5
3
/
G
P
5
4
/
B
P
5
5
/
O
U
T
1
P
2
0
/
S
C
L
K
P
2
1
/
S
O
U
T
P
2
2
/
S
I
N
P
1
0
/
O
U
T
2
P
1
1
/
S
C
L
1
P
1
2
/
S
C
L
2
P
1
3
/
S
D
A
1
P
1
4
/
S
D
A
2
P
1
5
/
A
D
1
/
I
N
T
3
P
1
6
/
A
D
2
P
3
0
/
A
D
5
P
3
1
/
A
D
6
R
E
S
E
T
P
2
6
/
O
S
C
1
/
X
C
I
N
P
2
7
/
O
S
C
2
/
X
C
O
U
T
V
C
C
P
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8
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115
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.4
Memory Map
0
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116
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.4
117
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
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118
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.4
119
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
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120
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
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121
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Internal State of Processor Status Register and
Program Counter at Reset
b
7b
0b
7b
0
1
R
e
g
i
s
t
e
r
P
r
o
c
e
s
s
o
r
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
P
S
)
B
i
t
a
l
l
o
c
a
t
i
o
nS
t
a
t
e
i
m
m
e
d
i
a
t
e
l
y
a
f
t
e
r
r
e
s
e
t
P
r
o
g
r
a
m
c
o
u
n
t
e
r
(
P
C
H
)
P
r
o
g
r
a
m
c
o
u
n
t
e
r
(
P
C
L
)
C
o
n
t
e
n
t
s
o
f
a
d
d
r
e
s
s
F
F
F
F
1
6
C
o
n
t
e
n
t
s
o
f
a
d
d
r
e
s
s
F
F
F
E
1
6
I Z CDBTVN???????
:
F
i
x
t
o
t
h
i
s
b
i
t
t
o
“
0
”
(
d
o
n
o
t
w
r
i
t
e
t
o
“
1
”
)
:
<
B
i
t
a
l
l
o
c
a
t
i
o
n
><
S
t
a
t
e
i
m
m
e
d
i
a
t
e
l
y
a
f
t
e
r
r
e
s
e
t
>
F
u
n
c
t
i
o
n
b
i
t
:
N
o
f
u
n
c
t
i
o
n
b
i
t
:
F
i
x
t
o
t
h
i
s
b
i
t
t
o
“
1
”
(
d
o
n
o
t
w
r
i
t
e
t
o
“
0
”
)
N
a
m
e
:
:
“
0
”
i
m
m
e
d
i
a
t
e
l
y
a
f
t
e
r
r
e
s
e
t
:
I
n
d
e
t
e
r
m
i
n
a
t
e
i
m
m
e
d
i
a
t
e
l
y
a
f
t
e
r
r
e
s
e
t
0
1
?
:
“
1
”
i
m
m
e
d
i
a
t
e
l
y
a
f
t
e
r
r
e
s
e
t
1
0
122
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Structure of Register
The figure of each register structure describes its functions, contents
at reset, and attributes as follows:
V
a
l
u
e
s
i
m
m
e
d
i
a
t
e
l
y
a
f
t
e
r
r
e
s
e
t
r
e
l
e
a
s
e
B
i
t
a
t
t
r
i
b
u
t
e
s
(
N
o
t
e
1
)
(
N
o
t
e
2
)
B
i
t
p
o
s
i
t
i
o
n
2
:
B
i
t
a
t
t
r
i
b
u
t
e
s
•
•
•
•
•
•
T
h
e
a
t
t
r
i
b
u
t
e
s
o
f
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
b
i
t
s
a
r
e
c
l
a
s
s
i
f
i
e
d
i
n
t
o
3
t
y
p
e
s
:
r
e
a
d
-
o
n
l
y
,
w
r
i
t
e
-
o
n
l
y
a
n
d
r
e
a
d
a
n
d
w
r
i
t
e
.
I
n
t
h
e
f
i
g
u
r
e
,
t
h
e
s
e
a
t
t
r
i
b
u
t
e
s
a
r
e
r
e
p
r
e
s
e
n
t
e
d
a
s
f
o
l
l
o
w
s
:
:
B
i
t
i
n
w
h
i
c
h
n
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
N
o
t
e
s
1
:
V
a
l
u
e
s
i
m
m
e
d
i
a
t
e
l
y
a
f
t
e
r
r
e
s
e
t
r
e
l
e
a
s
e
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
“
0
”
a
f
t
e
r
r
e
s
e
t
r
e
l
e
a
s
e
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
“
1
”
a
f
t
e
r
r
e
s
e
t
r
e
l
e
a
s
e
I
n
d
e
t
e
r
m
i
n
a
t
e
•
•
•
I
n
d
e
t
e
r
m
i
n
a
t
e
a
f
t
e
r
r
e
s
e
t
r
e
l
e
a
s
e
•
•
•
•
•
•
R
e
a
d
e
n
a
b
l
e
d
•
•
•
•
•
•
R
e
a
d
d
i
s
a
b
l
e
d
R
–
R•
•
•
•
•
•
R
e
a
d•
•
•
•
•
•
W
r
i
t
e
e
n
a
b
l
e
d
•
•
•
•
•
•
W
r
i
t
e
d
i
s
a
b
l
e
d
•
•
•
•
•
•
“
0
”
c
a
n
b
e
s
e
t
b
y
s
o
f
t
w
a
r
e
,
b
u
t
“
1
”
c
a
n
n
o
t
b
e
s
e
t
.
W•
•
•
•
•
•
W
r
i
t
e
W
–
✽
b
7b
6 b
5b
4b
3 b
2b
1b
0
BA
f
t
e
r
r
e
RW
C
P
U
M
o
d
e
R
e
g
i
s
t
e
r
0
,
1
2
3
,
4
0
1
N
a
m
eF
u
n
c
t
i
o
n
s
P
r
o
c
e
s
s
o
r
m
o
d
e
b
i
t
s
(
C
M
0
,
C
M
1
)0
0
:
S
i
n
g
l
e
-
c
h
i
p
m
o
d
e
0
1
:
1
0
:
N
o
t
a
v
a
i
l
a
b
l
e
1
1
:
F
i
x
t
h
e
s
e
b
i
t
s
t
o
“
1
.
”
1
S
t
a
c
k
p
a
g
e
s
e
l
e
c
t
i
o
n
b
i
t
(
S
e
e
n
o
t
e
)
(
C
M
2
)
1
b
1
b
0
0
:
0
p
a
g
e
1
:
1
p
a
g
e
1
0
0
5
1N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
T
h
i
s
b
i
t
i
s
w
r
i
t
e
d
i
s
a
b
l
e
b
i
t
.
W
h
e
n
t
h
i
s
b
i
t
i
s
r
e
a
d
o
u
t
,
t
h
e
v
a
l
u
e
i
s
“
1
.
”
6
,
7
0
C
l
o
c
k
s
w
i
t
c
h
b
i
t
s
(
C
M
6
,
C
M
7
)0
0
:
f
(
XI
N)
=
8
M
H
z
0
1
:
f
(
XI
N)
=
1
2
M
H
z
1
0
:
f
(
XI
N)
=
1
6
M
H
z
1
1
:
D
o
n
o
t
s
e
t
b
7
b
6
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
(
C
P
U
M
)
(
C
M
)
[
A
d
d
r
e
s
s
0
0
F
B1
6]
R
W
RW
RW
R
W
RW
<
E
x
a
m
p
l
e
>
123
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
b7 b6 b5 b4 b3 b2 b1 b0
Port P3 direction register (P3D) [Address 00C7
16
]
B Name Functions After reset RW
Port P3 Direction Register
0 0 : Port P3
0
input mode
1 : Port P3
0
output mode 0
10 : Port P3
1
input mode
1 : Port P3
1
output mode 0
2 0 : CMOS output
1 : N-channel open-drain output 0
0
Port P3 direction register
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
RW
RW
RW
R—4, 5,
7
Port P3
0
output structure
selection bit (P30C)
30 : CMOS output
1 : N-channel open-drain output 0RWPort P3
1
output structure
selection bit (P30C)
6Refer to Timer section.Timer 3 count source
selection bit (T3SC) 0RW
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i=0,1,2) [Addresses 00C1
16,
00C3
16
, 00C5
16
]
B Name Functions After reset RW
Port Pi Direction Register
0 0 : Port Pi
0
input mode
1 : Port Pi
0
output mode 0
10 : Port Pi
1
input mode
1 : Port Pi
1
output mode 0
20 : Port Pi
2
input mode
1 : Port Pi
2
output mode 0
3 0 : Port Pi
3
input mode
1 : Port Pi
3
output mode 0
4 0 : Port Pi
4
input mode
1 : Port Pi
4
output mode 0
5 0 : Port Pi
5
input mode
1 : Port Pi
5
output mode 0
6 0 : Port Pi
6
input mode
1 : Port Pi
6
output mode 0
70 : Port Pi
7
input mode
1 : Port Pi
7
output mode 0
Port Pi direction register RW
RW
RW
RW
RW
RW
RW
RW
Address 00C116, 00C316, 00C516
Address 00C716
124
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
b7b6b5b4b3b2b1b0 OSD control register (OC) [Address 00D016]
B Name Functions After reset RW
OSD Control Register
0 OSD control bit
(OC0) (See note) 0 : All-blocks display off
1 : All-blocks display on 0
1Automatic solid space
control bit (OC1) 0 : OFF
1 : ON 0
20 : OFF
1 : ON 0
0
4 OSD mode clock
selection bit (OC4) 0
Window control bit
(OC2)
RW
RW
RW
RW
RW
30 : Data slicer clock
1 : Clock from OSC1 pin
CC mode clock
selection bit (OC3)
5, 6 OSC1 clock
selection bit
(OC5, OC6)
0 0: 32 kHz oscillating
0 1: Do not set.
1 0: LC oscillating,
Ceramic oscillating
1 1: Do not set.
b6 b5
0 : Data slicer clock
1 : Clock from OSC1 pin
7 Fix this bit to “0.”
0RW
0RW
0
Note: Even this bit is switched during display, the display screen
remains unchanged until a rising (falling) of the next V SYNC.
b
7b
6b
5b
4b
3b
2b
1b
0
O
S
D
p
o
r
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
F
)
[
A
d
d
r
e
s
s
0
0
C
B
1
6
]
BN
a
m
e
F
u
n
c
t
i
o
n
s
A
f
t
e
r
r
e
s
e
t
RW
O
S
D
P
o
r
t
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
0
20
30
:
G
s
i
g
n
a
l
o
u
t
p
u
t
1
:
P
o
r
t
P
5
3
o
u
t
p
u
t0
0
F
i
x
t
h
e
s
e
b
i
t
s
t
o
“
0
.
”R—
RW
RW
RW
0
,
1
P
o
r
t
P
5
3
o
u
t
p
u
t
s
i
g
n
a
l
s
e
l
e
c
t
i
o
n
b
i
t
(
P
F
3
)
40
:
B
s
i
g
n
a
l
o
u
t
p
u
t
1
:
P
o
r
t
P
5
4
o
u
t
p
u
t0RW
P
o
r
t
P
5
4
o
u
t
p
u
t
s
i
g
n
a
l
s
e
l
e
c
t
i
o
n
b
i
t
(
P
F
4
)
0RW
0
:
R
s
i
g
n
a
l
o
u
t
p
u
t
1
:
P
o
r
t
P
5
2
o
u
t
p
u
t
P
o
r
t
P
5
2
o
u
t
p
u
t
s
i
g
n
a
l
s
e
l
e
c
t
i
o
n
b
i
t
(
P
F
2
)
50
:
O
U
T
1
s
i
g
n
a
l
o
u
t
p
u
t
1
:
P
o
r
t
P
5
3
o
u
t
p
u
t
P
o
r
t
P
5
5
o
u
t
p
u
t
s
i
g
n
a
l
s
e
l
e
c
t
i
o
n
b
i
t
(
P
F
5
)
70
:
P
o
r
t
P
1
0
o
u
t
p
u
t
1
:
O
U
T
2
s
i
g
n
a
l
o
u
t
p
u
t
P
o
r
t
P
1
0
o
u
t
p
u
t
s
i
g
n
a
l
s
e
l
e
c
t
i
o
n
b
i
t
(
P
F
7
)
00
0
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
T
h
i
s
b
i
t
i
s
w
r
i
t
e
d
i
s
a
b
l
e
b
i
t
.
W
h
e
n
t
h
i
s
b
i
t
i
s
r
e
a
d
o
u
t
,
t
h
e
v
a
l
u
e
i
s
“
0
.
”R—
6
Address 00CB16
Address 00D016
125
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
b7b6b5b4b3b2b1b0 Block control register i (BCi) (i=1, 2) [Addresses 00D2
16
and 00D3
16
]
Block Control register i
0, 1 Display mode
selection bits
(BCi0, BCi1)
(See note 1)
Indeterminate
2, 3 Dot size selection
bits (BCi2, BCi3)
b4 b3 b2 Pre-divide Ratio Dot Size
4 Pre-divide ratio
selection bit (BCi4)
5
7 Window top/bottom
boundary control bit
(BCi7)
Notes 1: Bit RA3 of OSD RAM controls OUT1 output when bit 5 is “0.”
Bit RA3 of OSD RAM controls OUT2 output when bit 5 is “1.”
2: Tc is OSD clock cycle divided in pre-divide circuit.
3: H is H
SYNC
.
OUT1/OUT2 output control
bit (BCi5) (See note 1) 0: OUT1 output control
1: OUT2 output control
6Vertical display start
position control bit
(BCi6)
BC16: Block 1
BC26: Block 1
b1 b0
0 0: Display OFF
0 1: CC mode
1 0: OSD mode (Border OFF)
1 1: OSD mode (Border ON)
00
01
10
11
00
01
10
11
0
1
✕ 2
✕ 3
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
BC17: Window top boundary
BC27: Window bottom boundary
B Name Functions
After reset
RW
RW
Indeterminate
RW
Indeterminate
RW
Indeterminate
RW
Indeterminate
RW
Indeterminate
RW
Address 00D116
Address 00D216, 00D316
b7b6b5b4b3b2b1b0 Horizontal position register (HP) [Address 00D1
16
]
B Name
Horizontal Position Register
7
Horizontal display start
position control bits
(HP0 to HP6)
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
Functions After reset R W
Horizontal display start positions
128 steps (00
16
to 7F
16
)
(1 step is 4T
OSC
)
0
0
RW
R—
0
to
6
Note: The setting value synchronizes with the V
SYNC
.
126
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
Address 00D416, 00D516
Address 00D616
Address 00D716
b7 b6 b5 b4 b3 b2 b1 b0
0
to
7
R W
Vertical Position Register i
Vertical position register i (VPi) (i = 1 and 2) [Addresses 00D4
16
, 00D5
16
]
BName Functions After reset RW
InderterminateVertical display start
position control bits
(VPi0 to VPi7)
(See note)
Vertical display start position =
T
H
✕ (BCi6 ✕ 16
2
+ n)
(n: setting value, T
H
: H
SYNC
cycle,
BCi6: bit 6 of block control register i)
Note: Set values except “00
16
” to VPi when BCi6 is “0.”
b7 b6 b5 b4 b3 b2 b1 b0
0
to
7
R W
Window Register 1
Window register 1 (WN1) [Address 00D6
16
]
BName Functions After reset RW
Inderterminate
Window top boundary
control bits
(WN10 to WN17)
Window top border position =
T
H
✕ (BC17 ✕ 16
2
+ n)
(n: setting value, T
H
: H
SYNC
cycle,
BC17: bit 7 of block control register 1)
Notes 1: Set values except “00
16
” to WN1 when BC17 is “0.”
2: Set values fit for the following condition: WN1 < WN2.
b7 b6 b5 b4 b3 b2 b1 b0
0
to
7
R W
Window Register 2
Window register 2 (WN2) [Address 00D7
16
]
BName Functions After reset RW
Inderterminate
Window bottom boundary
control bits
(WN20 to WN27)
Window bottom border position =
T
H
✕ (BC27 ✕ 16
2
+ n)
(n: setting value, T
H
: H
SYNC
cycle,
BC27: bit 7 of block control register 2)
Note: Set values fit for the following condition: WN1 < WN2.
127
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
0 : “ ” at even field
“ ” at odd field
1 : “ ” at even field
“ ” at odd field
b7 b6 b5 b4 b3 b2 b1 b0
I/O polarity control register (PC) [Address 00D8
16
]
B Name Functions
After reset
RW
I/O Polarity Control Register
0H
SYNC
input polarity
switch bit (PC0) 0 : Positive polarity input
1 : Negative polarity input 0
10 : Positive polarity input
1 : Negative polarity input 0
2 R, G, B output polarity
switch bit (PC2) 0 : Positive polarity output
1 : Negative polarity output 0
3 OUT1 output polarity
switch bit (PC3) 0 : Positive polarity output
1 : Negative polarity output 0
4 OUT2 output polarity
switch bit (PC4) 0 : Positive polarity output
1 : Negative polarity output 0
5 Display dot line selection
bit (PC5) (See note) 0
6 Field determination flag
(PC6) 0 : Even field
1 : Odd field 1
70
V
SYNC
input polarity
switch bit (PC1)
RW
RW
RW
RW
RW
RW
R—
RWFix this bit to “0.”
Note: Refer to the corresponding figure (8.11.14).
0
Address 00D916
Address 00D816
b7b6b5b4 b3b2b1 b0 Raster color register (RC) [Address 00D9
16
]
B Name Functions
After reset
RW
Raster Color Register
0 Raster color R
control bit (RC0) 0 : No output
1 : Output 0
1Raster color G
control bit (RC1) 0 : No output
1 : Output 0
20 : No output
1 : Output 0
0
4 Raster color OUT2
control bit (RC4) 0
Raster color B
control bit (RC2)
RW
RW
RW
RW
RW
30 : No output
1 : Output
Raster color OUT1
control bit (RC3)
5, 6
0 : No output
1 : Output
7
Fix these bits to “0.” 0RW
0RW
0
Note: Either OSD clock source or 32 kHz oscillating clock is
selected by bits 5 and 6 of the OSD control register.
0
Port function
selection bit (RC7) 0 : OSC1/X
CIN
,
OSC2/X
COUT
1 : P2
6
, P2
7
128
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt input polarity register (RE) [Address 00DC16]
B Name Functions After reset R W
Interrupt Input Polarity Register
INT1 polarity switch bit
(INT1)
0
0
0
0 : Positive polarity
1 : Negative polarity
0
4
0 : Positive polarity
1 : Negative polarity
5
4
to
7
INT2 polarity switch bit
(INT2)
INT3 polarity switch bit
(INT3)
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
0RW
RW
RW
R—
0 : Positive polarity
1 : Negative polarity
b
7b
6b
5b
4b
3b
2b
1b
0D
a
t
a
s
l
i
c
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
D
S
C
1
)
[
A
d
d
r
e
s
s
0
0
E
0
1
6
]
D
a
t
a
S
l
i
c
e
r
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
1
00
RW
0RW
2R
e
f
e
r
e
n
c
e
c
l
o
c
k
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
D
S
C
1
2
)0
:
V
i
d
e
o
s
i
g
n
a
l
1
:
H
S
Y
N
C
s
i
g
n
a
l0R
W
0RW
0
RW
11
0
:
S
t
o
p
p
e
d
1
:
O
p
e
r
a
t
i
n
g
D
a
t
a
s
l
i
c
e
r
a
n
d
t
i
m
i
n
g
s
i
g
n
a
l
g
e
n
e
r
a
t
i
n
g
c
i
r
c
u
i
t
c
o
n
t
r
o
l
b
i
t
(
D
S
C
1
0
)
F
i
x
t
h
e
s
e
b
i
t
s
t
o
“
0
.
”
3
,
4
000
10
:
F
2
1
:
F
1
S
e
l
e
c
t
i
o
n
b
i
t
o
f
d
a
t
a
s
l
i
c
e
r
e
f
e
r
e
n
c
e
v
o
l
t
a
g
e
g
e
n
e
r
a
t
i
n
g
f
i
e
l
d
(
D
S
C
1
1
)
F
i
x
t
h
e
s
e
b
i
t
s
t
o
“
1
.
”
5
,
6
D
e
f
i
n
i
t
i
o
n
o
f
f
i
e
l
d
s
1
(
F
1
)
a
n
d
2
(
F
2
)
H
s
e
p
V
s
e
p
F
1
:
H
s
e
p
V
s
e
p
F
2
:
B
A
f
t
e
r
r
e
s
e
t
R
W
N
a
m
eF
u
n
c
t
i
o
n
s
0RWF
i
x
t
h
i
s
b
i
t
t
o
“
0
.
”
7
Address 00DC16
Address 00E016
129
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
b7 b6 b5 b4 b3 b2 b1 b0
Clock run-in detect register (CRD) [Address 00E4
16
]
RW
Clock Run-in Detect Register
0
to
2
0R—
Test bits
3
to
7
Number of reference clocks to
be counted in one clock run-in
pulse period.
Clock run-in detection bit
(CRD3 to CRD7) 0R—
Read-only
B After resetFunctionsName
b
7b
6b
5b
4b
3b
2b
1b
0
D
a
t
a
s
l
i
c
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
(
D
S
C
2
)
[
A
d
d
r
e
s
s
0
0
E
11
6]
R
W
D
a
t
a
S
l
i
c
e
r
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
2
0I
n
d
e
t
e
r
m
i
n
a
t
eR—
10R
W
I
n
d
e
t
e
r
m
i
n
a
t
eR —
I
n
d
e
t
e
r
m
i
n
a
t
eR —
01
0
:
D
a
t
a
i
s
n
o
t
l
a
t
c
h
e
d
y
e
t
a
n
d
a
c
l
o
c
k
-
r
u
n
-
i
n
i
s
n
o
t
d
e
t
e
r
m
i
n
e
d
.
1
:
D
a
t
a
i
s
l
a
t
c
h
e
d
a
n
d
a
c
l
o
c
k
-
r
u
n
-
i
n
i
s
d
e
t
e
r
m
i
n
e
d
.
C
a
p
t
i
o
n
d
a
t
a
l
a
t
c
h
c
o
m
p
l
e
t
i
o
n
f
l
a
g
1
(
D
S
C
2
0
)
F
i
x
t
h
i
s
b
i
t
t
o
“
1
.
”
2R
e
a
d
-
o
n
l
y
T
e
s
t
b
i
t
30
:
F
2
1
:
F
1
F
i
e
l
d
d
e
t
e
r
m
i
n
a
t
i
o
n
f
l
a
g
(
D
S
C
2
3
)
40
:
M
e
t
h
o
d
(
1
)
1
:
M
e
t
h
o
d
(
2
)
V
e
r
t
i
c
a
l
s
y
n
c
h
r
o
n
o
u
s
s
i
g
n
a
l
(
Vs
e
p)
g
e
n
e
r
a
t
i
n
g
m
e
t
h
o
d
s
e
l
e
c
t
i
o
n
b
i
t
(
D
S
C
2
4
)
0RW
50
:
M
a
t
c
h
1
:
M
i
s
m
a
t
c
h
V
-
p
u
l
s
e
s
h
a
p
e
d
e
t
e
r
m
i
n
a
t
i
o
n
f
l
a
g
(
D
S
C
2
5
)I
n
d
e
t
e
r
m
i
n
a
t
eR—
60RWF
i
x
t
h
i
s
b
i
t
t
o
“
o
.
”
B
A
f
t
e
r
r
e
s
e
t
F
u
n
c
t
i
o
n
sN
a
m
e
D
e
f
i
n
i
t
i
o
n
o
f
f
i
e
l
d
s
1
(
F
1
)
a
n
d
2
(
F
2
)
Hs
e
p
Vs
e
p
F
1
:
Hs
e
p
Vs
e
p
F
2
:
R—
7R
e
a
d
-
o
n
l
y
T
e
s
t
b
i
tI
n
d
e
t
e
r
m
i
n
a
t
e
Address 00E416
Address 00E116
130
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
b
7b
6b
5b
4b
3b
2b
1b
0
D
a
t
a
c
l
o
c
k
p
o
s
i
t
i
o
n
r
e
g
i
s
t
e
r
(
D
P
S
)
[
A
d
d
r
e
s
s
0
0
E
5
1
6
]
D
a
t
a
C
l
o
c
k
P
o
s
i
t
i
o
n
R
e
g
i
s
t
e
r
01
RW
F
i
x
t
h
i
s
b
i
t
t
o
“
0
.
”
1F
i
x
t
h
i
s
b
i
t
t
o
“
1
.
”0RW
100
B
A
f
t
e
r
r
e
s
e
t
F
u
n
c
t
i
o
n
s
N
a
m
eRW
3D
a
t
a
c
l
o
c
k
p
o
s
i
t
i
o
n
s
e
t
b
i
t
s
(
D
P
S
3
t
o
D
P
S
7
)1RW
4
t
o
7
0
2F
i
x
t
h
i
s
b
i
t
t
o
“
0
.
”0RW
b
7b
6b
5b
4b
3b
2b
1b
0
C
a
p
t
i
o
n
P
o
s
i
t
i
o
n
R
e
g
i
s
t
e
r
(
C
P
S
)
[
A
d
d
r
e
s
s
0
0
E
6
1
6
]
C
a
p
t
i
o
n
P
o
s
i
t
i
o
n
R
e
g
i
s
t
e
r
0
t
o
4
0RW
0R
W
C
a
p
t
i
o
n
p
o
s
i
t
i
o
n
b
i
t
s
(
C
P
S
0
t
o
C
P
S
4
)
6
,
7R
e
f
e
r
t
o
t
h
e
c
o
r
r
e
s
p
o
n
d
i
n
g
T
a
b
l
e
(
T
a
b
l
e
8
.
1
0
.
1
)
.
S
l
i
c
e
l
i
n
e
m
o
d
e
s
p
e
c
i
f
i
c
a
t
i
o
n
b
i
t
s
(
i
n
1
f
i
e
l
d
)
(
C
P
S
6
,
C
P
S
7
)
50
:
D
a
t
a
i
s
n
o
t
l
a
t
c
h
e
d
y
e
t
a
n
d
a
c
l
o
c
k
-
r
u
n
-
i
n
i
s
n
o
t
d
e
t
e
r
m
i
n
e
d
.
1
:
D
a
t
a
i
s
l
a
t
c
h
e
d
a
n
d
a
c
l
o
c
k
-
r
u
n
-
i
n
i
s
d
e
t
e
r
m
i
n
e
d
.
C
a
p
t
i
o
n
d
a
t
a
l
a
t
c
h
c
o
m
p
l
e
t
i
o
n
f
l
a
g
2
(
C
P
S
5
)
I
n
d
e
t
e
r
m
i
n
a
t
e
R—
B
A
f
t
e
r
r
e
s
e
t
F
u
n
c
t
i
o
n
sN
a
m
e
RW
b7 b6 b5 b4 b3 b2 b1 b0
Sync pulse counter register (HC) [Address 00E9
16
]
RW
Sync Pulse Counter Register
0
to
4
0R—
6, 7 0 R —
Count value (HC0 to HC4)
50RWCount source (HC5) 0: H
SYNC
signal
1: Composite sync signal
BAfter resetFunctionsName
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
Address 00E516
Address 00E616
Address 00E916
131
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
b
7b
6 b
5b
4b
3 b
2b
1b
0S
e
r
i
a
l
I
/
O
m
o
d
e
r
e
g
i
s
t
e
r
(
S
M
)
[
A
d
d
r
e
s
s
0
0
E
B1
6]
BN
a
m
eF
u
n
c
t
i
o
n
s
A
f
t
e
r
r
e
s
e
t
RW
S
e
r
i
a
l
I
/
O
M
o
d
e
R
e
g
i
s
t
e
r
0
,
1I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
s
(
S
M
0
,
S
M
1
)
b
1
b
0
0
0
:
f
(
XI
N)
/
4
o
r
f
(
XC
I
N)
/
4
0
1
:
f
(
XI
N)
/
1
6
o
r
f
(
XC
I
N)
/
1
6
1
0
:
f
(
XI
N)
/
3
2
o
r
f
(
XC
I
N)
/
3
2
1
1
:
f
(
XI
N)
/
6
4
o
r
f
(
XC
I
N)
/
6
4
2S
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
(
S
M
2
)
3P
o
r
t
f
u
n
c
t
i
o
n
s
e
l
e
c
t
i
o
n
b
i
t
(
S
M
3
)
4
5T
r
a
n
s
f
e
r
d
i
r
e
c
t
i
o
n
s
e
l
e
c
t
i
o
n
b
i
t
(
S
M
5
)
0
0
:
P
20,
P
21
1
:
SC
L
K,
SO
U
T
0
:
E
x
t
e
r
n
a
l
c
l
o
c
k
1
:
I
n
t
e
r
n
a
l
c
l
o
c
k
0
:
L
S
B
f
i
r
s
t
1
:
M
S
B
f
i
r
s
t
6
F
i
x
t
h
i
s
b
i
t
t
o
“
0
.
”
0
0
0
0
0
0
T
r
a
n
s
f
e
r
c
l
o
c
k
i
n
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
(
S
M
6
)0
:
I
n
p
u
t
s
i
g
n
a
l
f
r
o
m
SI
N
p
i
n
1
:
I
n
p
u
t
s
i
g
n
a
l
f
r
o
m
S
O
U
T
p
i
n
RW
RW
RW
R
W
RW
RW
0
7F
i
x
t
h
i
s
b
i
t
t
o
“
0
.
”0R
W
b
7b
6b
5b
4b
3b
2b
1b
0
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
(
A
D
1
)
[
A
d
d
r
e
s
s
0
0
E
C
1
6
]
B
A
f
t
e
r
r
e
s
e
t
RW
A
-
D
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
1
0
t
o
2
A
n
a
l
o
g
i
n
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
s
(
A
D
C
1
0
t
o
A
D
C
1
2
)
N
a
m
eF
u
n
c
t
i
o
n
s
b
2
b
1
b
0
0
0
0
:
A
D
1
0
0
1
:
A
D
2
0
1
0
:
A
D
3
0
1
1
:
A
D
4
1
0
0
:
A
D
5
1
0
1
:
A
D
6
1
1
0
:
1
1
1
:
4
S
t
o
r
a
g
e
b
i
t
o
f
c
o
m
p
a
r
i
s
o
n
r
e
s
u
l
t
(
A
D
C
1
4
)
0
:
I
n
p
u
t
v
o
l
t
a
g
e
<
r
e
f
e
r
e
n
c
e
v
o
l
t
a
g
e
1
:
I
n
p
u
t
v
o
l
t
a
g
e
>
r
e
f
e
r
e
n
c
e
v
o
l
t
a
g
e
0
I
n
d
e
t
e
r
m
i
n
a
t
e
0
D
o
n
o
t
s
e
t
.
3T
h
i
s
b
i
t
i
s
a
w
r
i
t
e
d
i
s
a
b
l
e
b
i
t
.
W
h
e
n
t
h
i
s
b
i
t
i
s
r
e
a
d
o
u
t
,
t
h
e
v
a
l
u
e
i
s
“
0
.
”
RW
RW
R—
0
5
t
o
7
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
T
h
i
s
b
i
t
s
a
r
e
w
r
i
t
e
d
i
s
a
b
l
e
b
i
t
s
.
W
h
e
n
t
h
e
s
e
b
i
t
s
a
r
e
r
e
a
d
o
u
t
,
t
h
e
v
a
l
u
e
s
a
r
e
“
0
.
”
R—
Address 00EC16
Address 00EB16
132
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register 2 (AD2) [Address 00ED
16
]
BAfter reset RW
A-D Control Register 2
0
to
5
6, 7
0
0
Name Functions
D-A converter set bits
(ADC20 to ADC25) b0b1b2 b3 b4 b5
Nothing is assigned. These bits are write disable bits.
When these bits are reed out, the values are “ 0.”
1
000000
00000
0
0000
0
0
111
1
1
11111
1
111111
: 3/128Vcc
: 5/128Vcc
: 123/128Vcc
: 125/128Vcc
: 127/128Vcc
: 1/128Vcc RW
R—
b7b6 b5b4b3 b2b1b0 Timer mode register 1 (TM1) [Address 00F4
16
]
B
After reset
W
Timer Mode Register 1
0
1
2
3
4
Name Functions
Timer 1 count source
selection bit 1 (TM10) 0: f(X
IN
)/16 or f(X
CIN
)/16 (See note)
1: Count source selected by bit 5 of TM1
Timer 2 count source
selection bit 1 (TM11) 0: Count source selected by bit 4 of TM1
1: External clock from TIM2 pin
Timer 1 count
stop bit (TM12) 0: Count start
1: Count stop
Timer 2 count stop
bit (TM13) 0: Count start
1: Count stop
Timer 2 count source
selection bit 2
(TM14)
R
0
0
0
0
0
WR
WR
WR
WR
WR
0: f(X
IN
)/16 or f(X
CIN
)/16 (See note)
1: Timer 1 overflow
5Timer 1 count source
selection bit 2 (TM15) 0: f(X
IN
)/4096 or f(X
CIN
)/4096 (See note)
1: External clock from TIM2 pin 0WR
6Timer 5 count source
selection bit 2 (TM16) 0: Timer 2 overflow
1: Timer 4 overflow 0WR
7 Timer 6 internal count
source selection bit
(TM17)
0WR0: f(X
IN
)/16 or f(X
CIN
)/16 (See note)
1: Timer 5 overflow
Note: Either f(X
IN
) or f(X
CIN
) is selected by bit 7 of the CPU mode register.
Address 00ED16
Address 00F416
133
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
b7b6 b5b4b3 b2b1b0 Timer mode register 2 (TM2) [Address 00F5
16
]
B
After reset
RW
Timer Mode Register 2
0Name Functions
Timer 3 count source
selection bit (TM20) 0RW
1, 4 Timer 4 count source
selection bits
(TM21, TM24)
0RW
2
3
0
Timer 3 count
stop bit (TM22) 0: Count start
1: Count stop
Timer 4 count stop bit
(TM23) 0: Count start
1: Count stop 0
0
5Timer 5 count stop bit
(TM25) 0: Count start
1: Count stop 0
6Timer 6 count stop bit
(TM26) 0: Count start
1: Count stop 0
RW
RW
RW
RW
RW
7Timer 5 count source
selection bit 1
(TM27)
0: f(X
IN
)/16 or f(X
CIN
)/16 (See note)
1: Count source selected by bit 6
of TM1
b0
0 0 : f(X
IN
)/16 or f(X
CIN
)/16 (See note)
0 1 : f(X
CIN
)
1 0 :
11 :
(b6 at address 00C7
16
)
External clock from TIM3 pin
b4 b1
0 0 : Timer 3 overflow signal
0 1 : f(X
IN
)/16 or f(X
CIN
)/16 (See note)
1 0 : f(X
IN
)/2 or f(X
CIN
)/2 (See note)
1 1 : f(X
CIN
)
Note: Either f(X
IN
) or f(X
CIN
) is selected by bit 7 of the CPU mode register.
Address 00F516
Address 00F616
b
7b
6b
5b
4b
3b
2b
1b
0
I
C
d
a
t
a
s
h
i
f
t
r
e
g
i
s
t
e
r
1
(
S
0
)
[
A
d
d
r
e
s
s
0
0
F
6
1
6
]
B
F
u
n
c
t
i
o
n
s
A
f
t
e
r
r
e
s
e
tRW
I
C
D
a
t
a
S
h
i
f
t
R
e
g
i
s
t
e
r
0
t
o
7
T
h
i
s
i
s
a
n
8
-
b
i
t
s
h
i
f
t
r
e
g
i
s
t
e
r
t
o
s
t
o
r
e
r
e
c
e
i
v
e
d
a
t
a
a
n
d
w
r
i
t
e
t
r
a
n
s
m
i
t
d
a
t
a
.I
n
d
e
t
e
r
m
i
n
a
t
e
2
2
N
o
t
e
:
2
T
o
w
r
i
t
e
d
a
t
a
i
n
t
o
t
h
e
I
C
d
a
t
a
s
h
i
f
t
r
e
g
i
s
t
e
r
a
f
t
e
r
s
e
t
t
i
n
g
t
h
e
M
S
T
b
i
t
t
o
“
0
”
(
s
l
a
v
e
m
o
d
e
)
,
k
e
e
p
a
n
i
n
t
e
r
v
a
l
o
f
8
m
a
c
h
i
n
e
c
y
c
l
e
s
o
r
m
o
r
e
.
N
a
m
e
D
0
t
o
D
7RW
134
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
b
7b
6b
5b
4b
3b
2b
1b
0
0R
e
a
d
/
w
r
i
t
e
b
i
t
(
R
B
W
)
1
t
o
7
S
l
a
v
e
a
d
d
r
e
s
s
(
S
A
D
0
t
o
S
A
D
6
)
<
O
n
l
y
i
n
1
0
-
b
i
t
a
d
d
r
e
s
s
i
n
g
(
i
n
s
l
a
v
e
)
m
o
d
e
>
T
h
e
l
a
s
t
s
i
g
n
i
f
i
c
a
n
t
b
i
t
o
f
a
d
d
r
e
s
s
d
a
t
a
i
s
c
o
m
p
a
r
e
d
.
0
:
W
a
i
t
t
h
e
f
i
r
s
t
b
y
t
e
o
f
s
l
a
v
e
a
d
d
r
e
s
s
a
f
t
e
r
S
T
A
R
T
c
o
n
d
i
t
i
o
n
(
r
e
a
d
s
t
a
t
e
)
1
:
W
a
i
t
t
h
e
f
i
r
s
t
b
y
t
e
o
f
s
l
a
v
e
a
d
d
r
e
s
s
a
f
t
e
r
R
E
S
T
A
R
T
c
o
n
d
i
t
i
o
n
(
w
r
i
t
e
s
t
a
t
e
)
<
I
n
b
o
t
h
m
o
d
e
s
>
T
h
e
a
d
d
r
e
s
s
d
a
t
a
i
s
c
o
m
p
a
r
e
d
.
I
2
C
A
d
d
r
e
s
s
R
e
g
i
s
t
e
r
I
2
C
a
d
d
r
e
s
s
r
e
g
i
s
t
e
r
(
S
0
D
)
[
A
d
d
r
e
s
s
0
0
F
7
1
6
]
B
N
a
m
e
F
u
n
c
t
i
o
n
s
0
0
A
f
t
e
r
r
e
s
e
t
R
W
R—
R
W
b
7b
6b
5b
4b
3b
2b
1b
0
I
2
C
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
S
1
)
[
A
d
d
r
e
s
s
0
0
F
8
1
6
]
I
2
C
S
t
a
t
u
s
R
e
g
i
s
t
e
r
0
3
4
5
6
,
7
b
7
b
6
0
0
:
S
l
a
v
e
r
e
c
i
e
v
e
m
o
d
e
0
1
:
S
l
a
v
e
t
r
a
n
s
m
i
t
m
o
d
e
1
0
:
M
a
s
t
e
r
r
e
c
i
e
v
e
m
o
d
e
1
1
:
M
a
s
t
e
r
t
r
a
n
s
m
i
t
m
o
d
e
1
2
0
0
0
1
0
B
N
a
m
e
F
u
n
c
t
i
o
n
s
A
f
t
e
r
r
e
s
e
t
R
W
C
o
m
m
u
n
i
c
a
t
i
o
n
m
o
d
e
s
p
e
c
i
f
i
c
a
t
i
o
n
b
i
t
s
(
T
R
X
,
M
S
T
)
0
:
B
u
s
f
r
e
e
1
:
B
u
s
b
u
s
y
B
u
s
b
u
s
y
f
l
a
g
(
B
B
)
0
:
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
e
d
1
:
N
o
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
e
d
I
2
C
-
B
U
S
i
n
t
e
r
f
a
c
e
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
(
P
I
N
)
0
:
N
o
t
d
e
t
e
c
t
e
d
1
:
D
e
t
e
c
t
e
d
A
r
b
i
t
r
a
t
i
o
n
l
o
s
t
d
e
t
e
c
t
i
n
g
f
l
a
g
(
A
L
)
(
S
e
e
n
o
t
e
)
0
:
A
d
d
r
e
s
s
m
i
s
m
a
t
c
h
1
:
A
d
d
r
e
s
s
m
a
t
c
h
S
l
a
v
e
a
d
d
r
e
s
s
c
o
m
p
a
r
i
s
o
n
f
l
a
g
(
A
A
S
)
(
S
e
e
n
o
t
e
)
0
:
N
o
g
e
n
e
r
a
l
c
a
l
l
d
e
t
e
c
t
e
d
1
:
G
e
n
e
r
a
l
c
a
l
l
d
e
t
e
c
t
e
d
G
e
n
e
r
a
l
c
a
l
l
d
e
t
e
c
t
i
n
g
f
l
a
g
(
A
D
0
)
(
S
e
e
n
o
t
e
)
0
:
L
a
s
t
b
i
t
=
“
0
”
1
:
L
a
s
t
b
i
t
=
“
1
”
L
a
s
t
r
e
c
e
i
v
e
b
i
t
(
L
R
B
)
(
S
e
e
n
o
t
e
)
N
o
t
e
:
T
h
e
s
e
b
i
t
s
a
n
d
f
l
a
g
s
c
a
n
b
e
r
e
a
d
o
u
t
,
b
u
t
c
a
n
n
n
o
t
b
e
w
r
i
t
t
e
n
.
I
n
d
e
t
e
r
m
i
n
a
t
e
R—
R—
R—
R—
RW
R
W
0
R
W
(
S
e
e
n
o
t
e
)
(
S
e
e
n
o
t
e
)
(
S
e
e
n
o
t
e
)
(
S
e
e
n
o
t
e
)
Address 00F716
Address 00F816
135
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
b
7b
6b
5b
4b
3b
2b
1b
0
0
t
o
2
B
i
t
c
o
u
n
t
e
r
(
N
u
m
b
e
r
o
f
t
r
a
n
s
m
i
t
/
r
e
c
i
e
v
e
b
i
t
s
)
(
B
C
0
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2
2
R
W
R
W
R
W
R
W
R
W
b7 b6 b5 b4 b3 b2 b1 b0
I
2
C clock control register (S2 : address 00FA
16
)
I
2
C Clock Control Register
0
to
4
SCL frequency control
bits
(CCR0 to CCR4)
7
5
6
SCL mode
specification bit
(FAST MODE)
0: Standard clock mode
1: High-speed clock mode
0
Standard clock
mode
B Name Functions
After reset
RW
0
0
0
ACK bit
(ACK BIT)
ACK clock bit
(ACK)
0: ACK is returned.
1: ACK is not returned.
0: No ACK clock
1: ACK clock
High speed
clock mode
Setup disabled Setup disabled
00 to 02
Setup disabled
33303
Setup disabled
25004 100
400 (See note)
05 83.3 16606
500/CCR value 1000/CCR value
...
17.2 34.5
1D 16.6 33.3
1E 16.1 32.3
1F (at
φ
= 4 MHz, unit : kHz)
Note: At 4000kHz in the high-speed clock mode, the duty is as below .
“0” period : “1” period = 3 : 2
In the other cases, the duty is as below.
“0” period : “1” period = 1 : 1
Setup value
of CCR4–
CCR0
RW
RW
RW
RW
Address 00F916
Address 00FA16
136
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
b
7b
6 b
5b
4b
3 b
2b
1b
0I
n
t
e
r
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p
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(
I
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Q
1
)
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A
d
d
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e
s
s
0
0
F
C
1
6
]
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a
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1
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r
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b
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(
T
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1
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0✽
0✽
0✽
0✽
0✽
0✽
0✽
✽:
“
0
”
c
a
n
b
e
s
e
t
b
y
s
o
f
t
w
a
r
e
,
b
u
t
“
1
”
c
a
n
n
o
t
b
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t
.
—
R
R
R
R
R
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h
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v
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s
“
0
.
”
b
7b
6 b
5b
4b
3 b
2b
1b
0
B
A
f
t
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r
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t
RW
C
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,
1
2
3
,
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M
0
,
C
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1
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:
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:
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:
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:
1
p
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M
a
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n
C
l
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k
(
X
I
N
–
X
O
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T
)
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(
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6
)
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P
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r
(
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)
[
A
d
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s
s
0
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F
B
1
6
]
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W
RW
R
W
R
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C
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d
r
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v
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b
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b
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(
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5
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:
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v
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:
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0
:
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1
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t
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d
7
0
I
n
t
e
r
n
a
l
s
y
s
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m
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
(
C
M
7
)
RW
0
:
X
I
N
–
X
O
U
T
s
e
l
e
c
t
e
d
(
h
i
g
h
-
s
p
e
e
d
m
o
d
e
)
1
:
X
C
I
N
–
X
C
O
U
T
s
e
l
e
c
t
e
d
(
h
i
g
h
-
s
p
e
e
d
m
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e
)
N
o
t
e
:
T
h
i
s
b
i
t
i
s
s
e
t
t
o
“
1
”
a
f
t
e
r
t
h
e
r
e
s
e
t
r
e
l
e
a
s
e
.
Address 00FB16
Address 00FC16
137
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
b
7b
6
b
5b
4b
3 b
2b
1b
0I
n
t
e
r
r
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p
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(
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)
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R
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f
(
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4
0
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6
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Address 00FD16
Address 00FE16
138
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
b
7b
6 b
5b
4b
3 b
2b
1b
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“
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”
R—
Address 00FF16
Address 020816
139
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
b7b6 b5b4b3 b2b1b0 PWM mode register 2 (PM2) [Address 0209 16]
BAfter reset RW
PWM Mode Register 2
0
1
2
3
4
0
Name Functions
P00/PWM0 output
selection bit (PM20) 0 : P00 output
1 : PWM0 output
P02/PWM2 output
selection bit (PM22) 0 : P02 output
1 : PWM2 output
P03/PWM3 output
selection bit (PM23) 0 : P03 output
1 : PWM3 output
P04/PWM4 output
selection bit (PM24) 0 : P04 output
1 : PWM4 output
5P05/PWM5 output
selection bit (PW25) 0: P05 output
1: PWM5 output
6, 7 Fix these bits to “0.”
P01/PWM1 output
selection bit (PM21) 0 : P01 output
1 : PWM1 output
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
00
b7 b6 b5 b4 b3 b2 b1 b0
ROM correction enable register (RCR) [Address 020E
16
]
B
After reset
RW
ROM Correction Enable Register
0 Vector 1 enable bit (RC0)
Name Functions
0: Disabled
1: Enabled
1 Vector 2 enable bit (RC1) 0: Disabled
1: Enabled
2
to
7
Nothing is assigned. These bits are write disable bits. When
these bits are read out, the values are “0.”
0
0
0
RW
RW
R—
Address 020916
Address 020E16
21. PACKAGE OUTLINE
SDIP42-P-600-1.78 Weight(g)
–
JEDEC Code 4.1
EIAJ Package Code Lead Material
Alloy 42/Cu Alloy
42P4B
Plastic 42pin 600mil SDIP
Symbol Min Nom Max
A
A
2
b
b
1
b
2
c
E
D
L
Dimension in Millimeters
A
1
0.51 – –
–3.8–
0.35 0.45 0.55
0.9 1.0 1.3
0.63 0.73 1.03
0.22 0.27 0.34
36.5 36.7 36.9
12.85 13.0 13.15
– 1.778 –
– 15.24 –
3.0 – –
0°–15°
– – 5.5
e
e
1
42 22
21
1
E
c
e
1
A
2
A
1
b
b
1
b
2
e
LA
SEATING PLANE
D
SSOP42-P-450-0.80 Weight(g)
–
JEDEC Code 0.63
EIAJ Package Code Lead Material
Alloy 42
42P2R-A/E
Plastic 42pin 450mil SSOP
Symbol Min Nom Max
A
A
2
b
c
D
E
L
L
1
y
Dimension in Millimeters
H
E
A
1
I
2
–
–
.250
.050
.130.317.28–
.6311.30–
–
–
.271
–
–
.02.30.150.517.48.80.9311.50.7651
–
.4311–
–
.42
–
.40.20.717.68–
.2312.70–
.150
–
b
2
–.50–
–
0°–10°
e
e
1
42 22
21
1
H
E
E
D
ey
F
A
A
2
A
1
L
1
L
c
eb
2
e
1
I
2
Recommended Mount Pad
Detail F
z
Z
1
Detail G
–
–
Z
1
0.75
––
0.9
z
b
G
140
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37273M8–XXXSP, M37273MF–XXXSP
M37273E8SP, M37273EFSP
MITSUBISHI MICROCOMPUTERS
© 1999 MITSUBISHI ELECTRIC CORP.
New publication, effective Dec. 1999.
Specifications subject to change without notice.
Notes regarding these materials
• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
contained in these materials.
• All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by
Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
• When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision
on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved
destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
Rev. Rev.
No. date
1.0 First Edition of PDF File 990201
1.1 • Delete “PRELIMINALY” 9907
• Correct product name (head of P141).
1.3 Updated to Rev.1.3 (all pages) 9912
ROM correction memory is included to RAM (P1, 5, 12, 13)
ROM correction memory “Block” changed to “Vector” (P5, 12, 13, 48)
P42/TIM2 pin changed to TIM2 pin (P23)
Clock Run-in Detect Register (address 00EA16) changed to (address 00E416) (P56)
OSD Control Register (OC) “f(XIN)” changed to “Do not set.” at OC5, OC6 = “1”, “1” (P63)
Changed and added of Notes of OSD memory (P74)
OSC1/XIN, OSC2/XOUT changed to OSC1/XCIN, OSC2/XCOUT at RC7 = “0” (P89)
1.4 Updated to Rev.1.4 (Top page and version up pages) 0003
PIN DESCRIPTION Outline 42P2R-A changed to 42P2R-A/E(P3, 115)
PIN DESCRIPTION RESET ____________
RESET changed to RESET (P7)
P52/R Functions “Ports P52-P57 are a 6-bit” changed to “Ports
P52-P55 are a 4-bit” (P8)
Figure 7.2 I/O Pin Block Diagram P52-P57, P6 changed to P52-P55 (P10)
Figure 8.2.3 SFR1 Area CC16 Port P6 is delated. Add Note 1 (P14, 118)
Figure 8.11.18 Color code is changed (P80)
____________
10.ABSOLUTE MAXIMUM RATINGS VI RESET changed to RESET (P97)
____________
11.RECOMMENDED OPERATING CONDITIONS VIL3 RESET changed to RESET (P97)
____________
12.ELECTRIC CHARACTERISTICS VT+-VT- RESET changed to RESET (P98)
____________
IIZL RESET changed to RESET (P98)
16.DATA REQUIRED FOR MASK ORDERS “M37272M6/M8-XXXSP, ” changed to
“M37272M6/M8-XXXSP/FP, ” (P102)
21.PACKAGE OUTLINE 42P2R-A changed to 42P2R-A/E(P140)
1.5 Updated to Rev.1.5 (Top page and version up pages) 0008
Mask confirmation form of M37272MA is updated (P109 to 111).
(1/1)
Revision Description
REVISION DESCRIPTION LIST
M37272M6/M8-XXXSP/FP, M37272MA-XXXSP,
M37272E8SP/FP, M37272EFSP
DATA SHEET