a FEATURES Specified for VDD of 2.7 V to 5.25 V 1.75 MSPS for AD7470 (10-Bit) 1.5 MSPS for AD7472 (12-Bit) Low Power AD7470: 3.34 mW Typ at 1.5 MSPS with 3 V Supplies 7.97 mW Typ at 1.75 MSPS with 5 V Supplies AD7472: 3.54 mW Typ at 1.2 MSPS with 3 V Supplies 8.7 mW Typ at 1.5 MSPS with 5 V Supplies Wide Input Bandwidth 70 dB Typ SNR at 500 kHz Input Frequency Flexible Power/Throughput Rate Management No Pipeline Delays High Speed Parallel Interface Sleep Mode: 50 nA Typ 24-Lead SOIC and TSSOP Packages 1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs AD7470/AD7472 FUNCTIONAL BLOCK DIAGRAM AVDD VIN T/H REF IN VDRIVE 10-/12-BIT SUCCESSIVE APPROXIMATION ADC OUTPUT DRIVERS DVDD The conversion process and data acquisition are controlled using standard control inputs, allowing easy interfacing to microprocessors or DSPs. The input signal is sampled on the falling edge of CONVST, and conversion is also initiated at this point. BUSY goes high at the start of conversion and goes low 531.66 ns after falling edge of CONVST (AD7472 with a clock frequency of 26 MHz) to indicate that the conversion is complete. There are no pipeline delays associated with the parts. The conversion result is accessed via standard CS and RD signals over a high speed parallel interface. The AD7470/AD7472 use advanced design techniques to achieve very low power dissipation at high throughput rates. With 3 V supplies and 1.5 MSPS throughput rates, the AD7470 typically consumes, on average, just 1.1 mA. With 5 V supplies and 1.75 MSPS, the average current consumption is typically 1.6 mA. The part also offers flexible power/throughput rate management. Operating the AD7470 with 3 V supplies and 500 kSPS throughput reduces the current consumption to 713 A. At 5 V supplies and 500 kSPS, the part consumes 944 A. DB0 CLK IN CONVST CONTROL LOGIC CS RD BUSY AD7470/AD7472 AGND GENERAL DESCRIPTION The AD7470/AD7472 are 10-bit/12-bit high speed, low power, successive approximation ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1.5 MSPS for the 12-bit AD7472 and up to 1.75 MSPS for the 10-bit AD7470. The parts contain a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 1 MHz. DB9 (DB11) DGND AD7470 IS A 10-BIT PART WITH DB0 TO DB9 AS OUTPUTS. AD7472 IS A 12-BIT PART WITH DB0 TO DB11 AS OUTPUTS. It is also possible to operate the parts in an auto sleep mode, where the part wakes up to do a conversion and automatically enters sleep mode at the end of conversion. This method allows very low power dissipation numbers at lower throughput rates. In this mode, the AD7472 can be operated with 3 V supplies at 100 kSPS, and consume an average current of just 124 A. At 5 V supplies and 100 kSPS, the average current consumption is 171 A. The analog input range for the part is 0 V to REF IN. The 2.5 V reference is applied externally to the REF IN pin. The conversion rate is determined by the externally-applied clock. PRODUCT HIGHLIGHTS 1. High Throughput with Low Power Consumption. The AD7470 offers 1.75 MSPS throughput and the AD7472 offers 1.5 MSPS throughput rates with 4 mW power consumption. 2. Flexible Power/Throughput Rate Management. The conversion rate is determined by an externally-applied clock allowing the power to be reduced as the conversion rate is reduced. The part also features an auto sleep mode to maximize power efficiency at lower throughput rates. 3. No Pipeline Delay. The part features a standard successive approximation ADC with accurate control of the sampling instant via a CONVST input and once off conversion control. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. AD7470/AD7472 V2, REF IN = 2.5 V, fCLKIN = 30 MHz @ 5 V and 24 MHz @ 3 V; 1 (VDD = 2.7 V to 5.25 3 AD7470-SPECIFICATIONS A Version1 Parameter DYNAMIC PERFORMANCE Signal to Noise + Distortion (SINAD) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion (IMD) Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance REFERENCE INPUT REF IN Input Voltage Range DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS VDD IDD5 Normal Mode Quiescent Current Normal Mode Quiescent Current Sleep Mode Power Dissipation5 Normal Mode Sleep Mode TA = TMIN to TMAX , unless otherwise noted.) Unit Test Conditions/Comments 5V 60 60 60 60 -83 -75 -85 -75 3V 60 60 60 60 -83 -75 -85 -75 dB min dB min dB min dB min dB typ dB max dB typ dB max fS = 1.75 MSPS @ 5 V, fS = 1.5 MSPS @ 3 V fIN = 500 kHz Sine Wave fIN = 100 kHz Sine Wave fIN = 500 kHz Sine Wave fIN = 100 kHz Sine Wave fIN = 500 kHz Sine Wave fIN = 100 kHz Sine Wave fIN = 500 kHz Sine Wave fIN = 100 kHz Sine Wave -79 -75 -77 -75 5 15 20 -75 -75 -75 -75 5 15 20 dB typ dB max dB typ dB max ns typ ps typ MHz typ 10 1 0.9 2.5 1 10 1 0.9 2.5 1 Bits LSB max LSB max LSB max LSB max 0 to REF IN 1 33 0 to REF IN 1 33 V A max pF typ 2.5 1 10/20 2.5 1 10/20 V A max pF typ 2.4 0.4 1 10 2.4 0.4 1 10 V min V max A max pF max VDRIVE - 0.2 VDRIVE - 0.2 0.4 0.4 10 10 10 10 Straight (Natural) Binary V min V max A max pF max 12 135 1.75 CLK IN Cycles (max) ns min MSPS max 12 135 1.5 +2.7/+5.25 V min/max 2.4 900 1.5 800 1 mA max A max mA max A max A max 12 4.5 5 3 mW max mW max W max W max fIN = 500 kHz Sine Wave fIN = 100 kHz Sine Wave fIN = 500 kHz Sine Wave fIN = 100 kHz Sine Wave @ 3 dB fS = 1.75 MSPS @ 5 V; fS = 1.5 MSPS @ 3 V Guaranteed No Missed Codes to 10 Bits 1% for Specified Performance Track-and-Hold Mode Typically 10 nA, VIN = 0 V or VDD ISOURCE = 200 A ISINK = 200 A VDD = 2.7 V to 5.25 V Conversion Time + Acquisition Time CLK IN of 30 MHz @ 5 V and 24 MHz @ 3 V Digital Inputs = 0 V or DVDD VDD = 4.75 V to 5.25 V; fS = 1.75 MSPS; Typ 2 mA VDD = 4.75 V to 5.25 V; fS = 1.75 MSPS VDD = 2.7 V to 3.3 V; fS = 1.5 MSPS; Typ 1.3 mA VDD = 2.7 V to 3.3 V; fS = 1.5 MSPS CLK IN = 0 V or DVDD Digital Inputs = 0 V or DVDD VDD = 5 V VDD = 3 V VDD = 5 V; CLK IN = 0 V or DVDD VDD = 3 V; CLK IN = 0 V or DVDD NOTES 1 Temperature ranges as follows: A Version: -40C to +85C. 2 The AD7470 functionally works at 2.35 V. Typical specifications @ 25C for SNR (100 kHz) = 59 dB; THD (100 kHz) = -84 dB; INL 0.8 LSB. 3 The AD7470 will typically maintain A-grade performance up to 125C, with a reduced CLK of 20 MHz @ 5 V and 16 MHz @ 3 V. Typical sleep mode current @ 125C is 700 nA. 4 Sample tested @ 25C to ensure compliance. 5 See Power vs. Throughput Rate section. Specifications subject to change without notice. -2- REV. B AD7470/AD7472 V , REF IN = 2.5 V, A and B Versions: f AD7472-SPECIFICATIONS1 (V20 MHz= 2.7@ V3 toV, 5.25 T = T to T , unless otherwise noted.) 2 DD A Parameter A Version DYNAMIC PERFORMANCE 5V Signal to Noise + Distortion (SINAD) 69 68 Signal-to-Noise Ratio (SNR) 70 68 Total Harmonic Distortion (THD) -83 -83 -75 Peak Harmonic or Spurious Noise (SFDR) -86 -86 -76 Intermodulation Distortion (IMD) Second-Order Terms -77 -86 Third-Order Terms -77 -86 Aperture Delay 5 Aperture Jitter 15 Full Power Bandwidth 20 DC ACCURACY Resolution Integral Nonlinearity 1 B Version MIN 1 CLKIN MAX Unit Test Conditions/Comments 3V 69 68 70 68 -78 -84 -75 5V 69 68 70 68 -83 -83 -75 3V 69 68 70 68 -78 -84 -75 dB typ dB min dB typ dB min dB typ dB typ dB max fS = 1.5 MSPS @ 5 V, fS = 1.2 MSPS @ 3 V fIN = 500 kHz Sine Wave fIN = 100 kHz Sine Wave fIN = 500 kHz Sine Wave fIN = 100 kHz Sine Wave fIN = 500 kHz Sine Wave fIN = 100 kHz Sine Wave fIN = 100 kHz Sine Wave -81 -86 -76 -86 -86 -76 -81 -86 -76 dB typ dB typ dB max fIN = 500 kHz Sine Wave fIN = 100 kHz Sine Wave fIN = 100 kHz Sine Wave -77 -86 -77 -86 5 15 20 -77 -86 -77 -86 5 15 20 -77 -86 -77 -86 5 15 20 dB typ dB typ dB typ dB typ ns typ ps typ MHz typ fIN = 500 kHz Sine Wave fIN = 100 kHz Sine Wave fIN = 500 kHz Sine Wave fIN = 100 kHz Sine Wave 12 2 12 1 12 1 Bits LSB max Differential Nonlinearity 1.8 1.8 0.9 0.9 LSB max Offset Error Gain Error 10 2 10 2 10 2 10 2 LSB max LSB max ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance 0 to REF IN 0 to REF IN 1 1 33 33 0 to REF IN 0 to REF IN 1 1 33 33 V A max pF typ REFERENCE INPUT REF IN Input Voltage Range DC Leakage Current Input Capacitance 2.5 1 10/20 2.5 1 10/20 2.5 1 10/20 2.5 1 10/20 V A max pF typ LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 2.4 0.4 1 10 2.4 0.4 1 10 2.4 0.4 1 10 2.4 0.4 1 10 V min V max A max pF max LOGIC OUTPUTS Output High Voltage, V OH Output Low Voltage, V OL Floating-State Leakage Current Floating-State Output Capacitance Output Coding VDRIVE - 0.2 VDRIVE - 0.2 0.4 0.4 10 10 10 10 Straight (Natural) Binary VDRIVE - 0.2 VDRIVE - 0.2 0.4 0.4 10 10 10 10 Straight (Natural) Binary V min V max A max pF max CONVERSION RATE Conversion Time 14 14 14 14 135 1.5 135 1.2 135 1.5 135 1.2 CLK IN Cycles (max) ns min MSPS max POWER REQUIREMENTS VDD IDD4 Normal Mode Quiescent Current Normal Mode Quiescent Current Sleep Mode Power Dissipation4 Normal Mode Sleep Mode @ 3 dB fS = 1.5 MSPS @ 5 V , fS = 1.2 MSPS @ 3 V 12 2 Track-and-Hold Acquisition Time Throughput Rate +2.7/+5.25 +2.7/+5.25 V min/max 2.4 900 1.5 800 1 2.4 900 1.5 800 1 mA max A max mA max A max A max 12 4.5 5 3 12 4.5 5 3 mW max mW max W max W max Guaranteed No Missed Codes to 11 Bits (A Version) Guaranteed No Missed Codes to 12 Bits (B Version) 1% for Specified Performance Track-and-Hold Mode Typically 10 nA, VIN = 0 V or VDD ISOURCE = 200 A ISINK = 200 A VDD = 2.7 V to 5.25 V Conversion Time + Acquisition Time Digital Inputs = 0 V or DV DD VDD = 4.75 V to 5.25 V; Typ 2 mA; f S = 1.5 MSPS VDD = 4.75 V to 5.25 V; fS = 1.5 MSPS VDD = 2.7 V to 3.3 V; Typ 1.3 mA; fS = 1.2 MSPS VDD = 2.7 V to 3.3 V; fS = 1.2 MSPS CLK IN = 0 V or DVDD Digital Inputs = 0 V or DV DD VDD = 5 V VDD = 3 V VDD = 5 V; CLK IN = 0 V or DV DD VDD = 3 V; CLK IN = 0 V or DV DD NOTES 1 Temperature ranges as follows: A and B Versions: -40C to +85C. 2 The AD7472 functionally works at 2.35 V. Typical specifications @ 25C for SNR (100 kHz) = 68 dB; THD (100 kHz) = -84 dB; INL 0.8 LSB. 3 Sample tested @ 25C to ensure compliance. 4 See Power vs. Throughput Rate section. Specifications subject to change without notice. REV. B = 26 MHz @ 5 V and -3- AD7470/AD7472 2 = 2.7 V to 5.25 V , REF IN = 2.5 V,Y Version: fCLKIN = 20 MHz @ 5 V and 1 (V14DDMHz @ 3 V; T = T to T , unless otherwise noted.) AD7472-SPECIFICATIONS Y Version1 Parameter DYNAMIC PERFORMANCE Signal to Noise + Distortion (SINAD) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion (IMD) Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance REFERENCE INPUT REF IN Input Voltage Range DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS VDD IDD4 Normal Mode Quiescent Current Normal Mode Quiescent Current Sleep Mode Power Dissipation4 Normal Mode Sleep Mode A MIN MAX Unit Test Conditions/Comments fS = 1.2 MSPS @ 5 V, fS = 875 kSPS @ 3 V fIN = 500 kHz Sine Wave fIN = 100 kHz Sine Wave fIN = 500 kHz Sine Wave fIN = 100 kHz Sine Wave fIN = 500 kHz Sine Wave fIN = 100 kHz Sine Wave fIN = 100 kHz Sine Wave fIN = 500 kHz Sine Wave fIN = 100 kHz Sine Wave fIN = 100 kHz Sine Wave 5V 69 68 70 68 -83 -83 -75 -86 -86 -76 3V 69 68 70 68 -78 -84 -75 -81 -86 -76 dB typ dB min dB typ dB min dB typ dB typ dB max dB typ dB typ dB max -77 -86 -77 -86 5 15 20 -77 -86 -77 -86 5 15 20 dB typ dB typ dB typ dB typ ns typ ps typ MHz typ 12 2 1.8 10 2 12 2 1.8 10 2 Bits LSB max LSB max LSB max LSB max 0 to REF IN 1 33 0 to REF IN 1 33 V A max pF typ 2.5 1 10/20 2.5 1 10/20 V A max pF typ 2.4 0.4 1 10 2.4 0.4 1 10 V min V max A max pF max VDRIVE - 0.2 VDRIVE - 0.2 0.4 0.4 10 10 10 10 Straight (Natural) Binary V min V max A max pF max 14 140 1200 CLK IN Cycles (max) ns min kSPS max 14 140 875 +2.7/+5.25 V min/max 2.4 900 1.5 800 2 mA max A max mA max A max A max 12 4.5 10 6 mW max mW max W max W max fIN = 500 kHz Sine Wave fIN = 100 kHz Sine Wave fIN = 500 kHz Sine Wave fIN = 100 kHz Sine Wave @ 3 dB fS = 1.2 MSPS @ 5 V; fS = 875 kSPS @ 3 V Guaranteed No Missed Codes to 11 Bits 1% for Specified Performance Track-and-Hold Mode Typically 10 nA, VIN = 0 V or VDD ISOURCE = 200 A ISINK = 200 A VDD = 2.7 V to 5.25 V Conversion Time + Acquisition Time Digital Inputs = 0 V or DVDD VDD = 4.75 V to 5.25 V; fS = 1.2 MSPS; Typ 2 mA VDD = 4.75 V to 5.25 V; fS = 1.2 MSPS VDD = 2.7 V to 3.3 V; fS = 875 kSPS; Typ 1.3 mA VDD = 2.7 V to 3.3 V; fS = 875 kSPS CLK IN = 0 V or DVDD Digital Inputs = 0 V or DVDD VDD = 5 V VDD = 3 V VDD = 5 V; CLK IN = 0 V or DVDD VDD = 3 V; CLK IN = 0 V or DVDD NOTES 1 Temperature ranges as follows: Y Version: -40C to +125C. 2 The AD7472 functionally works at 2.35 V. Typical specifications @ 25C for SNR (100 kHz) = 68 dB; THD (100 kHz) = -84 dB; INL 0.8 LSB. 3 Sample tested @ 25C to ensure compliance. 4 See Power vs. Throughput Rate section. Specifications subject to change without notice. -4- REV. B AD7470/AD7472 TIMING SPECIFICATIONS1 (V DD Parameter fCLK 2 tCONVERT tWAKEUP t1 t2 AD7470 Unit Description 10 26 531.66 1 10 kHz min MHz max ns min s max ns min 10 10 15 30 35 0 0 20 15 8 0 ns max ns max ns max ns max ns max ns max ns min ns min ns max ns max 135 140 100 ns max ns max ns min 0 0 20 15 8 0 135 t10 Limit at TMIN, TMAX AD7472 10 30 436.42 1 10 30 t3 t4 3 t5 t6 3 t7 4 t8 t9 = 2.7 V to 5.25 V, REF IN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.) 100 tCLK = 1/fCLK IN Wake-Up Time CONVST Pulse Width CONVST to BUSY Delay, VDD = 5 V, A and B Versions VDD = 5 V, Y Version VDD = 3 V, A and B Versions VDD = 3 V, Y Version BUSY to CS Setup Time CS to RD Setup Time RD Pulse Width Data Access Time After Falling Edge of RD Bus Relinquish Time After Rising Edge of RD CS to RD Hold Time Acquisition Time A and B Versions Y Version Quiet Time NOTES 1 Sample tested at 25C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. See Figure 1. 2 Mark/Space ratio for the CLK inputs is 40/60 to 60/40. First CLK pulse should be 10 ns min from falling edge of CONVST. 3 Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V. 4 t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 7, quoted in the timing characteristics, is the true bus relinquish time of the part and is independent of the bus loading. Specifications subject to change without notice. 200A TO OUTPUT PIN IOL 1.6V CL 50pF 200A IOH Figure 1. Load Circuit for Digital Output Timing Specifications REV. B -5- AD7470/AD7472 ABSOLUTE MAXIMUM RATINGS 1 Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150C JA Thermal Impedance . . . . . . . . . . . . . . . 75C/W (SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115C/W (TSSOP) JC Thermal Impedance . . . . . . . . . . . . . . . 25C/W (SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35C/W (TSSOP) Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 kV (TA = 25C unless otherwise noted.) AVDD to AGND/DGND . . . . . . . . . . . . . . . . . -0.3 V to +7 V DVDD to AGND/DGND . . . . . . . . . . . . . . . . . -0.3 V to +7 V VDRIVE to AGND/DGND . . . . . . . . . . . . . . . . -0.3 V to +7 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V VDRIVE to DVDD . . . . . . . . . . . . . . . -0.3 V to DVDD + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V Analog Input Voltage to AGND . . . . -0.3 V to AVDD + 0.3 V Digital Input Voltage to DGND . . . . -0.3 V to DVDD + 0.3 V REF IN to AGND . . . . . . . . . . . . . . . -0.3 V to AVDD + 0.3 V Input Current to Any Pin Except Supplies2 . . . . . . . . 10 mA Operating Temperature Range Commercial (A and B Versions) . . . . . . . . . -40C to +85C Industrial (Y Version) . . . . . . . . . . . . . . . -40C to +125C Storage Temperature Range . . . . . . . . . . . -65C to +150C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. ORDERING GUIDE Model AD7470ARU AD7470ARU-REEL AD7470ARU-REEL7 AD7472AR AD7472AR-REEL AD7472AR-REEL7 AD7472ARU AD7472ARU-REEL AD7472ARU-REEL7 AD7472BR AD7472BR-REEL AD7472BRU AD7472BRU-REEL AD7472BRU-REEL7 AD7472YR AD7472YR-REEL AD7472YRU AD7472YRU-REEL AD7472YRU-REEL7 EVAL-AD7470CB2 EVAL-AD7472CB2 EVAL CONTROL BRD23 Temperature Range Resolution (Bits) Package Options1 Package Description -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C 10 10 10 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 RU-24 RU-24 RU-24 R-24 R-24 R-24 RU-24 RU-24 RU-24 R-24 R-24 RU-24 RU-24 RU-24 R-24 R-24 RU-24 RU-24 RU-24 TSSOP TSSOP TSSOP SOIC SOIC SOIC TSSOP TSSOP TSSOP SOIC SOIC TSSOP TSSOP TSSOP SOIC SOIC TSSOP TSSOP TSSOP Evaluation Board Evaluation Board Controller Board NOTES 1 R = SOIC; RU = TSSOP. 2 This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes. 3 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, you need to order the specific ADC evaluation board, for example, EVAL-AD7472CB, the EVAL CONTROL BRD2, and a 12 V ac transformer. See the relevant evaluation board application note for more information. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7470/AD7472 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -6- REV. B