June 30, 2008
LM111QML
Voltage Comparator
General Description
The LM111 is a voltage comparator that has input currents
nearly a thousand times lower than devices such as the
LM106 or LM710. It is also designed to operate over a wider
range of supply voltages: from standard ±15V op amp sup-
plies down to the single 5V supply used for IC logic. The
output is compatible with RTL, DTL and TTL as well as MOS
circuits. Further, it can drive lamps or relays, switching volt-
ages up to 50V at currents as high as 50 mA.
Both the inputs and the output of the LM111 can be isolated
from system ground, and the output can drive loads referred
to ground, the positive supply or the negative supply. Offset
balancing and strobe capability are provided and outputs can
be wire OR'ed. Although slower than the LM106 and LM710
(200 ns response time vs 40 ns) the device is also much less
prone to spurious oscillations. The LM111 has the same pin
configuration as the LM106 and LM710.
Features
■Available with radiation guaranteed
—High Dose Rate 50 krad(Si)
—Low Dose and ELDRS Free 100 krad(Si)
■Operates from single 5V supply
■Input current: 200 nA max. over temperature
■Offset current: 20 nA max. over temperature
■Differential input voltage range: ±30V
■Power consumption: 135 mW at ±15V
■Power supply voltage, single 5V to ±15V
■Offset voltage null capability
■Strobe capability
Ordering Information
NS PART NUMBER SMD PART NUMBER NS PACKAGE NUMBER PACKAGE DESCRIPTION
LM111E-SMD 5962-8687701Q2A E20A 20LD Leadless Chip Carrier
LM111H-SMD 5962-8687701QGA H08C 8LD TO-99 Metal Can
LM111J-8-SMD 5962-8687701QPA J08A 8LD CERDIP
LM111WG-SMD 5962-8687701QZA WG10A 10LD Ceramic SOIC
LM111E/883 E20A 20LD Leadless Chip Carrier
LM111H/883 H08C 8LD TO-99 Metal Can
LM111J-8/883 J08A 8LD CERDIP
LM111J/883 J14A 14LD CERDIP
LM111W/883 W10A 10LD CERPACK
LM111WG/883 WG10A 10LD Ceramic SOIC
LM111HLQMLV (Note 12)
High Dose Rate ONLY
5962L0052401VGA
50k rd(Si)
H08C 8LD TO-99 Metal Can
LM111J-8LQMLV (Note 12)
High Dose Rate ONLY
5962L0052401VPA
50k rd(Si)
J08A 8LD CERDIP
LM111WGLQMLV (Note 12)
High Dose Rate ONLY
5962L0052401VZA
50k rd(Si)
WG10A 10LD Ceramic SOIC
LM111WLQMLV (Note 12)
High Dose Rate ONLY
5962L0052401VHA
50k rd(Si)
W10A 10LD CERPACK
LM111HRLQMLV (Note 14)
ELDRS Free ONLY
5962R0052402VGA
100k rd(Si)
H08C 8LD TO-99 Metal Can
LM111J-8RLQMLV (Note 14)
ELDRS Free ONLY
5962R0052402VPA
100k rd(Si)
J08A 8LD CERDIP
LM111WGRLQMLV (Note 14)
ELDRS Free ONLY
5962R0052402VZA
100k rd(Si)
WG10A 10LD Ceramic SOIC
LM111WRLQMLV (Note 14)
ELDRS Free ONLY
5962R0052402VHA
100k rd(Si)
W10A 10LD CERPACK
© 2008 National Semiconductor Corporation 201285 www.national.com
LM111QML Voltage Comparator
Connection Diagrams
Metal Can Package
20128506
Note: Pin 4 connected to case
Top View
See NS Package Number H08C
Dual-In-Line Package
20128534
Top View
See NS Package Number J08A
Dual-In-Line Package
20128535
Top View
See NS Package Number J14A
20128533
See NS Package Number W10A, WG10A
20128573
See NS Package NumberE20A
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LM111QML
Absolute Maximum Ratings (Note 2)
Positive Supply Voltage +30.0V
Negative Supply Voltage -30.0V
Total Supply Voltage 36V
Output to Negative Supply Voltage 50V
GND to Negative Supply Voltage 30V
Differential Input Voltage ±30V
Sink Current 50mA
Input Voltage (Note 3) ±15V
Power Dissipation (Note 4)
8 LD CERDIP 400mW @ 25°C
8 LD Metal Can 330mW @ 25°C
10 LD CERPACK 330mW @ 25°C
10 LD Ceramic SOIC 330mW @ 25°C
20 LD LCC 500mW @ 25°C
Output Short Circuit Duration 10 seconds
Maximum Strobe Current 10mA
Operating Temperature Range -55°C ≤ TA ≤ 125°C
Thermal Resistance
θJA
8 LD CERDIP (Still Air @ 0.5W) 134°C/W
8 LD CERDIP (500LF/Min Air flow @ 0.5W) 76°C/W
8 LD Metal Can (Still Air @ 0.5W) 162°C/W
8 LD Metal Can (500LF/Min Air flow @ 0.5W) 92°C/W
10 Ceramic SOIC (Still Air @ 0.5W) 231°C/W
10 Ceramic SOIC (500LF/Min Air flow @ 0.5W) 153°C/W
10 CERPACK (Still Air @ 0.5W) 231°C/W
10 CERPACK (500LF/Min Air flow @ 0.5W) 153°C/W
14 LD CERDIP (Still Air @ 0.5W) 97°C/W
14 LD CERDIP (500LF/Min Air flow @ 0.5W) 65°C/W
20 LD LCC (Still Air @ 0.5W) 90°C/W
20 LD LCC (500LF/Min Air flow @ 0.5W) 65°C/W
θJC
8 LD CERDIP 21°C/W
8 LD Metal Can Pkg 50°C/W
10 LD Ceramic SOIC 24°C/W
10 LD CERPACK 24°C/W
14 LD CERDIP 20°C/W
20 LD LCC 21°C/W
Storage Temperature Range -65°C ≤ TA ≤ 150°C
Maximum Junction Temperature 175°C
Lead Temperature (Soldering, 60 seconds) 300°C
Voltage at Strobe Pin V+ = -5V
Package Weight (Typical)
8 LD Metal Can 965mg
8 LD CERDIP 1100mg
10 LD CERPACK 250mg
10 LD Ceramic SOIC 225mg
14 LD CERDIP TBD
20 LD LCC TBD
ESD Rating (Note 5) 300V
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LM111QML
Recommended Operating Conditions
Supply Voltage VCC = ±15VDC
Operating Temperature Range -55°C ≤ TA ≤ 125°C
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup Description Temperature (°C)
1 Static tests at +25
2 Static tests at +125
3 Static tests at -55
4 Dynamic tests at +25
5 Dynamic tests at +125
6 Dynamic tests at -55
7 Functional tests at +25
8A Functional tests at +125
8B Functional tests at -55
9 Switching tests at +25
10 Switching tests at +125
11 Switching tests at -55
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LM111QML
LM111/883 Electrical Characteristics
DC Parameters
The following conditions apply, unless otherwise specified. V56 = 0, RS = 0 Ω, VCC = ±15V, VCM = 0, VO = 1.4V WRT −VCC
The pin assignments are based on the 8 pin package configuration. (Note 7)
Symbol Parameter Conditions Notes Min Max Unit Sub-
groups
IIO Input Offset Current VCM = 13.5V, RS = 50KΩ -10 10 nA 1
-20 20 nA 2, 3
VCM = 13.5V, V85 = V86 = 0V, RS =
50KΩ(Note 7) -30 30 nA 1
VCM = -14.5V, RS= 50KΩ -10 10 nA 1
-20 20 nA 2, 3
VCM = -14.5V, V85 = V86 = 0V,
RS= 50KΩ(Note 7) -30 30 nA 1
RS = 50KΩ -10 10 nA 1
-20 20 nA 2, 3
V85 = V86 = 0V, RS = 50KΩ(Note 7) -30 30 nA 1
IIB Input Bias Current VCM = 13.5V, RS = 50KΩ 100 nA 1
150 nA 2, 3
VCM = -14.5V, RS = 50KΩ 100 nA 1
150 nA 2, 3
RS = 50KΩ 100 nA 1
150 nA 2, 3
IOL Output Leakage Current VCC = ± 18V, I5 + I6 = 5mA,
VO = 35V WRT -VCC
(Note 7) 10 nA 1
(Note 7) 500 nA 2, 3
IGL Ground Leakage Current VCC = ± 18V, I5 + I6 = 5mA,
VO = 50V WRT -VCC
(Note 7) 25 nA 1
(Note 7) 500 nA 2
VSat Saturation Voltage VI = -5mV, I7 = 50mA (Note 7) 1.5 V 1, 2, 3
VI = -6mV, I7 = 8mA (Note 7) 0.4 V 1, 2, 3
-ICC Negative Supply Current 5.0 mA 1, 2
15 mA 3
+ICC Positive Supply Current 6.0 mA 1, 2
15 mA 3
IL1 Input Leakage Current VCC = ± 18V, V28 = 1V,
V38 = 30V, I5 + I6 = 5mA
VO = 50V WRT -VCC
(Note 7) 10 nA 1
(Note 7) 30 nA 2
IL2 Input Leakage Current VCC = ± 18V, V38 = 1V,
V28 = 30V, I5 + I6 = 5mA
VO = 50V WRT -VCC
(Note 7) 10 nA 1
(Note 7) 30 nA 2
VOSt Collector Output Voltage (Strobe) 14 V 1
ISt = 3mA 14 V 1
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LM111QML
Symbol Parameter Conditions Notes Min Max Unit Sub-
groups
VIO Input Offset Voltage VCM = 13.5V -3.0 3.0 mV 1
-4.0 4.0 mV 2, 3
VCM = 13.5V, V85 = V86= 0V (Note 7) -3.0 3.0 mV 1
VCM = -14.5V -3.0 3.0 mV 1
-4.0 4.0 mV 2, 3
VCM = -14.5V, V85 = V86 = 0V (Note 7) -3.0 3.0 mV 1
-3.0 3.0 mV 1
-4.0 4.0 mV 2, 3
V85 = V86 = 0V (Note 7) -3.0 3.0 mV 1
VO = 0.4V, +VCC = 4.5V,
-VCC = 0V, VCM = 3V
-5.0 5.0 mV 1
-6.0 6.0 mV 2, 3
VO = 4.5V, +VCC = 4.5V,
-VCC = 0V, VCM = 3V
-3.0 3.0 mV 1
-4.0 4.0 mV 2, 3
VO = 0.4V, +VCC = 4.5V,
-VCC = 0V, VCM = 0.5V
-5.0 5.0 mV 1
-6.0 6.0 mV 2, 3
VO = 4.5V, +VCC = 4.5V,
-VCC = 0V, VCM = 0.5V
-3.0 3.0 mV 1
-4.0 4.0 mV 2, 3
AVS Large Signal Gain -12V ≤ VO ≤ 35V, RL = 1KΩ(Note 6) 40 V/mV 4
(Note 6) 30 V/mV 5, 6
AC Parameters
The following conditions apply, unless otherwise specified. V56 = 0, RS = 0 Ω, VCC = ±15V, VCM = 0, VO = 1.4V WRT −VCC
The pin assignments are based on the 8 pin package configuration. (Note 7)
Symbol Parameter Conditions Notes Min Max Unit Sub-
groups
tR Response Time 400 nS 7
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LM111QML
LM111-SMD Electrical Characteristics SMD 5962-8687701
DC Parameters
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Symbol Parameter Conditions Notes Min Max Unit Sub-
groups
VIO Input Offset Voltage VI = 0V, RS = 50Ω -3.0 +3.0 mV 1
-4.0 +4.0 mV 2, 3
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50Ω
-3.0 +3.0 mV 1
-4.0 +4.0 mV 2, 3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50Ω
-3.0 +3.0 mV 1
-4.0 +4.0 mV 2, 3
+VCC = +2.5V, -VCC = -2.5V,
VI = 0V,
RS = 50Ω
-3.0 +3.0 mV 1
-4.0 +4.0 mV 2, 3
VIO R Raised Input Offset Voltage VI = 0V, RS = 50Ω (Note 15) -3.0 +3.0 mV 1
-4.5 +4.5 mV 2, 3
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50Ω
(Note 15)
-3 +3 mV 1
-4.5 +4.5 mV 2, 3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V, RS = 50Ω (Note 15) -3.0 +3.0 mV 1
-4.5 +4.5 mV 2, 3
IIO Input Offset Current VI = 0V, RS = 50KΩ -10 +10 nA 1, 2
-20 +20 nA 3
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50KΩ
-10 +10 nA 1, 2
-20 +20 nA 3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50KΩ
-10 +10 nA 1, 2
-20 +20 nA 3
IIOR Raised Input Offset Current VI = 0V, RS = 50KΩ(Note 15) -25 +25 nA 1, 2
-50 +50 nA 3
±IIB Input Bias Current VI = 0V, RS = 50KΩ -100 0.1 nA 1, 2
-150 0.1 nA 3
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50KΩ
-150 0.1 nA 1, 2
-200 0.1 nA 3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50KΩ
-150 0.1 nA 1, 2
-200 0.1 nA 3
VOSt Collector Output Voltage (Strobe) +VI = Gnd, -VI = 15V,
ISt = -3mA, RS = 50Ω
(Notes 8,
13) 14 V 1, 2, 3
CMRR Common Mode Rejection Ratio -28V ≤ -VCC ≤ -0.5V, RS = 50Ω,
2V ≤ +VCC ≤ 29.5V, RS = 50Ω,
-14.5V ≤ VCM ≤ 13V, RS = 50Ω
80 dB 1, 2, 3
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LM111QML
Symbol Parameter Conditions Notes Min Max Unit Sub-
groups
VOL Low Level Output Voltage +VCC = 4.5V, -VCC = Gnd,
IO = 8mA, ±VI = 0.71V,
VID = -6mV
0.4 V 1, 2, 3
+VCC = 4.5V, -VCC = Gnd,
IO = 8mA, ±VI = −1.75V,
VID = -6mV
0.4 V 1, 2, 3
IO = 50mA, ±VI = 13V,
VID = -5mV 1.5 V 1, 2, 3
IO = 50mA, ±Vl= -14V,
VID = -5mV 1.5 V 1, 2, 3
ICEX Output Leakage Current +VCC = 18V, -VCC = -18V,
VO = 32V
-1.0 10 nA 1
-1.0 500 nA 2
ILInput Leakage Current +VCC = 18V, -VCC = -18V,
+VI = +12V, -VI = -17V (Note 11) -5.0 500 nA 1, 2, 3
+VCC = 18V, -VCC = -18V,
+VI = -17V, -VI = +12V (Note 11) -5.0 500 nA 1, 2, 3
+ICC Power Supply Current 6.0 mA 1, 2
7.0 mA 3
-ICC Power Supply Current -5.0 mA 1, 2
-6.0 mA 3
Δ VIO / ΔTTemperature Coefficient Input
Offset Voltage
25°C ≤ T ≤ 125°C (Notes 11,
13) -25 25 µV/°C 2
-55°C ≤ T ≤ 25°C (Notes 11,
13) -25 25 µV/°C 3
Δ IIO / ΔTTemperature Coefficient Input
Offset Current
25°C ≤ T ≤ 125°C (Notes 11,
13) -100 100 pA/°C 2
-55°C ≤ T ≤ 25°C (Notes 11,
13) -200 200 pA/°C 3
IOS Short Circuit Current VO = 5V, t ≤ 10mS, -VI = 0.1V,
+VI = 0V
(Note 10) 200 mA 1
(Note 10) 150 mA 2
(Note 10) 250 mA 3
+VIO adj. Input Offset Voltage (Adjustment) VO = 0V, VI = 0V, RS = 50Ω 5.0 mV 1
-VIO adj. Input Offset Voltage (Adjustment) VO = 0V, VI = 0V, RS = 50Ω -5.0 mV 1
±AVE Voltage Gain (Emitter) RL = 600Ω (Note 6) 10 V/mV 4
(Note 6) 8.0 V/mV 5, 6
AC Parameters SMD 5962-8687701
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Symbol Parameter Conditions Notes Min Max Unit Sub-
groups
tRLHC Response Time (Collector
Output)
VOD(Overdrive) = -5mV,
CL = 50pF, VI = -100mV
(Note 13) 300 nS 7, 8B
(Note 13) 640 nS 8A
tRHLC Response Time (Collector
Output)
VOD(Overdrive) = 5mV,
CL = 50pF, VI = 100mV
(Note 13) 300 nS 7, 8B
(Note 13) 500 nS 8A
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LM111QML
LM111 RADIATION Electrical Characteristics SMD 5962L0052401
DC Parameters (Note 12)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Symbol Parameter Conditions Notes Min Max Unit Sub-
groups
VIO Input Offset Voltage VI = 0V, RS = 50Ω -3.0 +3.0 mV 1
-4.0 +4.0 mV 2, 3
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50Ω
-3.0 +3.0 mV 1
-4.0 +4.0 mV 2, 3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50Ω
-3.0 +3.0 mV 1
-4.0 +4.0 mV 2, 3
+VCC = +2.5V, -VCC = -2.5V,
VI = 0V, RS = 50Ω
-3.0 +3.0 mV 1
-4.0 +4.0 mV 2, 3
VIO R Raised Input Offset Voltage VI = 0V, RS = 50Ω (Note 15) -3.0 +3.0 mV 1
-4.5 +4.5 mV 2, 3
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50Ω
(Note 15)
-3.0 +3.0 mV 1
-4.5 +4.5 mV 2, 3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50Ω
(Note 15)
-3.0 +3.0 mV 1
-4.5 +4.5 mV 2, 3
IIO Input Offset Current VI = 0V, RS = 50KΩ -10 +10 nA 1, 2
-20 +20 nA 3
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50KΩ
-10 +10 nA 1, 2
-20 +20 nA 3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50KΩ
-10 +10 nA 1, 2
-20 +20 nA 3
IIOR Raised Input Offset Current VI = 0V, RS = 50KΩ(Note 15) -25 +25 nA 1, 2
-50 +50 nA 3
±IIB Input Bias Current VI = 0V, RS = 50KΩ -100 0.1 nA 1, 2
-150 0.1 nA 3
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50KΩ
-150 0.1 nA 1, 2
-200 0.1 nA 3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50KΩ
-150 0.1 nA 1, 2
-200 0.1 nA 3
VOSt Collector Output Voltage (Strobe) +VI = Gnd, -VI = 15V,
ISt = -3mA, RS = 50Ω
(Notes 8,
13) 14 V 1, 2, 3
CMRR Common Mode Rejection Ratio -28V ≤ -VCC ≤ -0.5V, RS = 50Ω,
2V ≤ +VCC ≤ 29.5V, RS = 50Ω,
-14.5V ≤ VCM ≤ 13V, RS = 50Ω
80 dB 1, 2, 3
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LM111QML
Symbol Parameter Conditions Notes Min Max Unit Sub-
groups
VOL Low Level Output Voltage +VCC = 4.5V, -VCC = Gnd,
IO = 8mA, ±VI = 0.5V,
VID = -6mV
0.4 V 1, 2, 3
+VCC = 4.5V, -VCC = Gnd,
IO = 8mA, ±VI = 3V,
VID = -6mV
0.4 V 1, 2, 3
IO = 50mA, ±VI = 13V,
VID = -5mV 1.5 V 1, 2, 3
IO = 50mA, ±VI = -14V,
VID = -5mV 1.5 V 1, 2, 3
ICEX Output Leakage Current +VCC = 18V, -VCC = -18V,
VO = 32V
-1.0 10 nA 1
-1.0 500 nA 2
ILInput Leakage Current +VCC = 18V, -VCC = -18V,
+VI = +12V, -VI = -17V (Note 11) -5.0 500 nA 1, 2, 3
+VCC = 18V, -VCC = -18V,
+VI = -17V, -VI = +12V (Note 11) -5.0 500 nA 1, 2, 3
+ICC Power Supply Current 6.0 mA 1, 2
7.0 mA 3
-ICC Power Supply Current -5.0 mA 1, 2
-6.0 mA 3
ΔVIO / ΔTTemperature Coefficient Input
Offset Voltage
25°C ≤ T ≤ 125°C -25 25 µV/°C 2
-55°C ≤ T ≤ 25°C -25 25 µV/°C 3
Δ IIO / ΔTTemperature Coefficient Input
Offset Current
25°C ≤ T ≤ 125°C -100 100 pA/°C 2
-55°C ≤ T ≤ 25°C -200 200 pA/°C 3
IOS Short Circuit Current VO = 5V, t ≤ 10mS, -VI = 0.1V,
+VI = 0V
(Note 10) 200 mA 1
(Note 10) 150 mA 2
(Note 10) 250 mA 3
+VIO adj. Input Offset Voltage (Adjustment) VO = 0V, VI = 0V, RS = 50Ω 5.0 mV 1
-VIO adj. Input Offset Voltage (Adjustment) VO = 0V, VI = 0V, RS = 50Ω -5.0 mV 1
±AVE Voltage Gain (Emitter) RL = 600Ω (Note 6) 10 V/mV 4
(Note 6) 8.0 V/mV 5, 6
AC Parameters SMD 5962L0052401 (Note 12)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Symbol Parameter Conditions Notes Min Max Unit Sub-
groups
tRLHC Response Time (Collector
Output)
VOD(Overdrive) = -5mV,
CL = 50pF, VI = -100mV (Note 13) 300 nS 7, 8B
640 nS 8A
tRHLC Response Time (Collector
Output)
VOD(Overdrive) = 5mV,
CL = 50pF, VI = 100mV (Note 13) 300 nS 7, 8B
500 nS 8A
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LM111QML
DC DELTA Parameters SMD 5962L0052401 (Note 12)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Delta calculations performed on QMLV devices at group B , subgroup 5.
Symbol Parameter Conditions Notes Min Max Unit Sub-
groups
VIO Input Offset Voltage VI = 0V, RS = 50Ω -0.5 0.5 mV 1
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50Ω
-0.5 0.5 mV 1
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50Ω
-0.5 0.5 mV 1
±IIB Input Bias Current VI = 0V, RS = 50KΩ -12.5 12.5 nA 1
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50KΩ
-12.5 12.5 nA 1
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50KΩ
-12.5 12.5 nA 1
ICEX Output Leakage Current +VCC = 18V, -VCC = -18V,
VO = 32V -5.0 5.0 nA 1
Post Radiation Parameters SMD 5962L0052401 (Note 12)
The following conditions apply, unless otherwise specified
Symbol Parameter Conditions Notes Min Max Unit Sub-
groups
IIO Input Offset Current +VCC = 29.5V, −VCC = −0.5V, VI =
0V, VCM = −14.5V,
RS = 50KΩ
−50 +50 nA 1
+VCC = 2V, −VCC = −28V,
VI = 0V, VCM = +13V, RS = 50KΩ
−50 +50 nA 1
±IIB Input Bias Current VI = 0V, RS = 50KΩ −150 0.1 nA 1
+VCC = 29.5V, −VCC = −0.5V, VI =
0V, VCM = −14.5V,
RS = 50KΩ
−175 0.1 nA 1
ICEX Output Leakage Current +VCC = 18V, −VCC = −18V,
VO = 32V
−25 +25 nA 1
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LM111QML
LM111 RADIATION Electrical Characteristics SMD 5962R0052402
DC Parameters (Note 14)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Symbol Parameter Conditions Notes Min Max Unit Sub-
groups
VIO Input Offset Voltage VI = 0V, RS = 50Ω -3.0 +3.0 mV 1
-4.0 +4.0 mV 2, 3
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50Ω
-3.0 +3.0 mV 1
-4.0 +4.0 mV 2, 3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50Ω
-3.0 +3.0 mV 1
-4.0 +4.0 mV 2, 3
+VCC = +2.5V, -VCC = -2.5V,
VI = 0V, RS = 50Ω
-3.0 +3.0 mV 1
-4.0 +4.0 mV 2, 3
VIO R Raised Input Offset Voltage VI = 0V, RS = 50Ω (Note 15) -3.0 +3.0 mV 1
-4.5 +4.5 mV 2, 3
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50Ω
(Note 15)
-3.0 +3.0 mV 1
-4.5 +4.5 mV 2, 3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50Ω
(Note 15)
-3.0 +3.0 mV 1
-4.5 +4.5 mV 2, 3
IIO Input Offset Current VI = 0V, RS = 50KΩ -10 +10 nA 1, 2
-20 +20 nA 3
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50KΩ
-10 +10 nA 1, 2
-20 +20 nA 3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50KΩ
-10 +10 nA 1, 2
-20 +20 nA 3
IIOR Raised Input Offset Current VI = 0V, RS = 50KΩ(Note 15) -25 +25 nA 1, 2
-50 +50 nA 3
±IIB Input Bias Current VI = 0V, RS = 50KΩ -100 0.1 nA 1, 2
-150 0.1 nA 3
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50KΩ
-150 0.1 nA 1, 2
-200 0.1 nA 3
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50KΩ
-150 0.1 nA 1, 2
-200 0.1 nA 3
VOSt Collector Output Voltage (Strobe) +VI = Gnd, -VI = 15V,
ISt = -3mA, RS = 50Ω
(Notes 8,
13) 14 V 1, 2, 3
CMRR Common Mode Rejection Ratio -28V ≤ -VCC ≤ -0.5V, RS = 50Ω,
2V ≤ +VCC ≤ 29.5V, RS = 50Ω,
-14.5V ≤ VCM ≤ 13V, RS = 50Ω
80 dB 1, 2, 3
13 www.national.com
LM111QML
Symbol Parameter Conditions Notes Min Max Unit Sub-
groups
VOL Low Level Output Voltage +VCC = 4.5V, -VCC = Gnd,
IO = 8mA, ±VI = 0.5V,
VID = -6mV
0.4 V 1, 2, 3
+VCC = 4.5V, -VCC = Gnd,
IO = 8mA, ±VI = 3V,
VID = -6mV
0.4 V 1, 2, 3
IO = 50mA, ±VI = 13V,
VID = -5mV 1.5 V 1, 2, 3
IO = 50mA, ±VI = -14V,
VID = -5mV 1.5 V 1, 2, 3
ICEX Output Leakage Current +VCC = 18V, -VCC = -18V,
VO = 32V
-1.0 10 nA 1
-1.0 500 nA 2
ILInput Leakage Current +VCC = 18V, -VCC = -18V,
+VI = +12V, -VI = -17V (Note 11) -5.0 500 nA 1, 2, 3
+VCC = 18V, -VCC = -18V,
+VI = -17V, -VI = +12V (Note 11) -5.0 500 nA 1, 2, 3
+ICC Power Supply Current 6.0 mA 1, 2
7.0 mA 3
-ICC Power Supply Current -5.0 mA 1, 2
-6.0 mA 3
ΔVIO / ΔTTemperature Coefficient Input
Offset Voltage
25°C ≤ T ≤ 125°C -25 25 µV/°C 2
-55°C ≤ T ≤ 25°C -25 25 µV/°C 3
Δ IIO / ΔTTemperature Coefficient Input
Offset Current
25°C ≤ T ≤ 125°C -100 100 pA/°C 2
-55°C ≤ T ≤ 25°C -200 200 pA/°C 3
IOS Short Circuit Current VO = 5V, t ≤ 10mS, -VI = 0.1V,
+VI = 0V
(Note 10) 200 mA 1
(Note 11) 150 mA 2
(Note 11) 250 mA 3
+VIO adj. Input Offset Voltage (Adjustment) VO = 0V, VI = 0V, RS = 50Ω 5.0 mV 1
-VIO adj. Input Offset Voltage (Adjustment) VO = 0V, VI = 0V, RS = 50Ω -5.0 mV 1
±AVE Voltage Gain (Emitter) RL = 600Ω (Note 7) 10 V/mV 4
(Note 7) 8.0 V/mV 5, 6
AC Parameters SMD 5962R0052402 (Note 14)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Symbol Parameter Conditions Notes Min Max Unit Sub-
groups
tRLHC Response Time (Collector
Output)
VOD(Overdrive) = -5mV,
CL = 50pF, VI = -100mV (Note 13) 300 nS 7, 8B
640 nS 8A
tRHLC Response Time (Collector
Output)
VOD(Overdrive) = 5mV,
CL = 50pF, VI = 100mV (Note 13) 300 nS 7, 8B
500 nS 8A
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LM111QML
DC DELTA Parameters SMD 5962R0052402 (Note 14)
The following conditions apply, unless otherwise specified. VCC = ±15V, VCM = 0
Delta calculations performed on QMLV devices at group B , subgroup 5.
Symbol Parameter Conditions Notes Min Max Unit Sub-
groups
VIO Input Offset Voltage VI = 0V, RS = 50Ω -0.5 0.5 mV 1
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50Ω
-0.5 0.5 mV 1
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50Ω
-0.5 0.5 mV 1
±IIB Input Bias Current VI = 0V, RS = 50KΩ -12.5 12.5 nA 1
+VCC = 29.5V, -VCC = -0.5V,
VI = 0V, VCM = -14.5V,
RS = 50KΩ
-12.5 12.5 nA 1
+VCC = 2V, -VCC = -28V,
VI = 0V, VCM = +13V,
RS = 50KΩ
-12.5 12.5 nA 1
ICEX Output Leakage Current +VCC = 18V, -VCC = -18V,
VO = 32V -5.0 5.0 nA 1
Post Radiation Parameters SMD 5962R0052402 (Note 14)
The following conditions apply, unless otherwise specified
Symbol Parameter Conditions Notes Min Max Unit Sub-
groups
IIOR Raised Input Offset Current VI = 0V, RS = 50KΩ(Note 15) −100 +100 nA 1
±IIB Input Bias Current VI = 0V, RS = 50KΩ −180 0.1 nA 1
+VCC = 29.5V, −VCC = −0.5V, VI =
0V, VCM = −14.5V, RS = 50KΩ
−225 0.1 nA 1
ICEX Output Leakage Current +VCC = 18V, −VCC = −18V,
VO = 32V
−1.0 +25 nA 1
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 3: This rating applies for ±15V supplies. The positive input voltage limits is 30 V above the negative supply. The negative input voltage limits is equal to the
negative supply voltage or 30V below the positive supply, whichever is less.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package
junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/
θJA or the number given in the Absolute Maximum Ratings, whichever is lower.
Note 5: Human body model, 1.5 kΩ in series with 100 pF.
Note 6: Datalog reading in K=V/mV.
Note 7: Pin names based on an 8 pin package configuration. When using higher pin count packages then: Pin 2 & 3 are Inputs, Pin 5 is Balance, Pin 6 is
Balance / Strobe, Pin 7 is Output, and Pin 8 is V+. For example: V56is the Voltage between the Balance and Balance / Strobe pins
Note 8: IST = −2mA at −55°C
Note 9: Calculated parameter.
Note 10: Actual min. limit used is 5mA due to test setup.
Note 11: VID is voltage difference between inputs.
Note 12: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table.
These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters
are guaranteed only for the conditions as specified in Mil-Std-883, Method 1019, Condition A.
Note 13: Group A sample ONLY
Note 14: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table.
These parts may be sensitive in a high dose environment. Low dose rate testing has been performed on a wafer-by-wafer basis, per test method 1019 condition
D of MIL-STD-883, with no enhanced low dose rate sensitivity (ELDRS) effect.
Note 15: Subscript (R) indicates tests which are performed with input stage current raised by connecting BAL and BAL/STB terminals to +VCC.
15 www.national.com
LM111QML
LM111 Typical Performance Characteristics
Input Bias Current
20128543
Input Bias Current
20128544
Input Bias Current
20128545
Input Bias Current
20128546
Input Bias Current
20128547
Input Bias Current
20128548
www.national.com 16
LM111QML
Input Bias Current
Input Overdrives
20128549
Input Bias Current
Input Overdrives
20128550
Input Bias Current
20128551
Response Time for Various
Input Overdrives
20128552
Response Time for Various
Input Overdrives
20128553
Output Limiting Characteristics
20128554
17 www.national.com
LM111QML
Supply Current
20128555
Supply Current
20128556
Leakage Currents
20128557
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LM111QML
Application Hints
CIRCUIT TECHNIQUES FOR AVOIDING
OSCILLATIONS IN COMPARATOR APPLICATIONS
When a high-speed comparator such as the LM111 is used
with fast input signals and low source impedances, the output
response will normally be fast and stable, assuming that the
power supplies have been bypassed (with 0.1 μF disc capac-
itors), and that the output signal is routed well away from the
inputs (pins 2 and 3) and also away from pins 5 and 6.
However, when the input signal is a voltage ramp or a slow
sine wave, or if the signal source impedance is high (1 kΩ to
100 kΩ), the comparator may burst into oscillation near the
crossing-point. This is due to the high gain and wide band-
width of comparators like the LM111. To avoid oscillation or
instability in such a usage, several precautions are recom-
mended, as shown in Figure 1 below.
1. The trim pins (pins 5 and 6) act as unwanted auxiliary
inputs. If these pins are not connected to a trim-pot, they
should be shorted together. If they are connected to a
trim-pot, a 0.01 μF capacitor C1 between pins 5 and 6
will minimize the susceptibility to AC coupling. A smaller
capacitor is used if pin 5 is used for positive feedback as
in Figure 1.
2. Certain sources will produce a cleaner comparator
output waveform if a 100 pF to 1000 pF capacitor C2 is
connected directly across the input pins.
3. When the signal source is applied through a resistive
network, RS, it is usually advantageous to choose an RS
′ of substantially the same value, both for DC and for
dynamic (AC) considerations. Carbon, tin-oxide, and
metal-film resistors have all been used successfully in
comparator input circuitry. Inductive wire wound resistors
are not suitable.
4. When comparator circuits use input resistors (e.g.
summing resistors), their value and placement are
particularly important. In all cases the body of the resistor
should be close to the device or socket. In other words
there should be very little lead length or printed-circuit foil
run between comparator and resistor to radiate or pick
up signals. The same applies to capacitors, pots, etc. For
example, if RS=10 kΩ, as little as 5 inches of lead
between the resistors and the input pins can result in
oscillations that are very hard to damp. Twisting these
input leads tightly is the only (second best) alternative to
placing resistors close to the comparator.
5. Since feedback to almost any pin of a comparator can
result in oscillation, the printed-circuit layout should be
engineered thoughtfully. Preferably there should be a
ground plane under the LM111 circuitry, for example, one
side of a double-layer circuit card. Ground foil (or,
positive supply or negative supply foil) should extend
between the output and the inputs, to act as a guard. The
foil connections for the inputs should be as small and
compact as possible, and should be essentially
surrounded by ground foil on all sides, to guard against
capacitive coupling from any high-level signals (such as
the output). If pins 5 and 6 are not used, they should be
shorted together. If they are connected to a trim-pot, the
trim-pot should be located, at most, a few inches away
from the LM111, and the 0.01 μF capacitor should be
installed. If this capacitor cannot be used, a shielding
printed-circuit foil may be advisable between pins 6 and
7. The power supply bypass capacitors should be located
within a couple inches of the LM111. (Some other
comparators require the power-supply bypass to be
located immediately adjacent to the comparator.)
6. It is a standard procedure to use hysteresis (positive
feedback) around a comparator, to prevent oscillation,
and to avoid excessive noise on the output because the
comparator is a good amplifier for its own noise. In the
circuit of Figure 2, the feedback from the output to the
positive input will cause about 3 mV of hysteresis.
However, if RS is larger than 100Ω, such as 50 kΩ, it
would not be reasonable to simply increase the value of
the positive feedback resistor above 510 kΩ. The circuit
of Figure 3 could be used, but it is rather awkward. See
the notes in paragraph 7 below.
7. When both inputs of the LM111 are connected to active
signals, or if a high-impedance signal is driving the
positive input of the LM111 so that positive feedback
would be disruptive, the circuit of Figure 1 is ideal. The
positive feedback is to pin 5 (one of the offset adjustment
pins). It is sufficient to cause 1 to 2 mV hysteresis and
sharp transitions with input triangle waves from a few Hz
to hundreds of kHz. The positive-feedback signal across
the 82Ω resistor swings 240 mV below the positive
supply. This signal is centered around the nominal
voltage at pin 5, so this feedback does not add to the
VOS of the comparator. As much as 8 mV of VOS can be
trimmed out, using the 5 kΩ pot and 3 kΩ resistor as
shown.
8. These application notes apply specifically to the LM111
and are applicable to all high-speed comparators in
general, (with the exception that not all comparators have
trim pins).
19 www.national.com
LM111QML
20128529
Pin connections shown are for LM111H in the H08 hermetic package
FIGURE 1. Improved Positive Feedback
20128530
Pin connections shown are for LM111H in the H08 hermetic package
FIGURE 2. Conventional Positive Feedback
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LM111QML
20128531
FIGURE 3. Positive Feedback with High Source Resistance
21 www.national.com
LM111QML
Typical Applications (Note 18)
Offset Balancing
20128536
Strobing
20128537
Note: Do Not Ground Strobe Pin. Output is turned off when current is pulled from
Strobe Pin.
Increasing Input Stage Current (Note Increases typical
common mode slew from 7.0V/μs to 18V/μs. )
20128538
Note 16: Increases typical common mode slew from 7.0V/μs to 18V/μs.
Detector for Magnetic Transducer
20128539
Digital Transmission Isolator
20128540
Relay Driver with Strobe
20128541
*Absorbs inductive kickback of relay and protects IC from severe voltage tran-
sients on V++ line.
Note: Do Not Ground Strobe Pin.
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LM111QML
Strobing off Both Input and Output Stages (Note Typical input current is 50 pA with inputs strobed off. )
20128542
Note: Do Not Ground Strobe Pin.
Note 17: Typical input current is 50 pA with inputs strobed off.
Note 18: Pin connections shown on schematic diagram and typical applications are for H08 metal can package.
Positive Peak Detector
20128523
*Solid tantalum
Zero Crossing Detector Driving MOS Logic
20128524
Typical Applications for H08 Package
(Pin numbers refer to H08 package)
Zero Crossing Detector Driving MOS Switch
20128513
100 kHz Free Running Multivibrator
20128514
*TTL or DTL fanout of two
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LM111QML
10 Hz to 10 kHz Voltage Controlled Oscillator
20128515
*Adjust for symmetrical square wave time when VIN = 5 mV
†Minimum capacitance 20 pF Maximum frequency 50 kHz
Driving Ground-Referred Load
20128516
*Input polarity is reversed when using pin 1 as output.
Using Clamp Diodes to Improve Response
20128517
TTL Interface with High Level Logic
20128518
*Values shown are for a 0 to 30V logic swing and a 15V threshold.
†May be added to control speed and reduce susceptibility to noise spikes.
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LM111QML
Crystal Oscillator
20128519
Comparator and Solenoid Driver
20128520
Precision Squarer
20128521
*Solid tantalum
†Adjust to set clamp level
Low Voltage Adjustable Reference Supply
20128522
*Solid tantalum
25 www.national.com
LM111QML
Positive Peak Detector
20128523
*Solid tantalum
Zero Crossing Detector Driving MOS Logic
20128524
Negative Peak Detector
20128525
*Solid tantalum
Precision Photodiode Comparator
20128526
*R2 sets the comparison level. At comparison, the photodiode has less than 5 mV across it, decreasing leakages by an order of magnitude.
www.national.com 26
LM111QML
Switching Power Amplifier
20128527
27 www.national.com
LM111QML
Switching Power Amplifier
20128528
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LM111QML
Revision History
Released Revision Section Originator Changes
10/11/05 A New Release, Corporate format L. Lytle 3 MDS data sheets converted into one Corp.
data sheet format. MNLM111-X Rev 0A0,
MDLM111-X Rev. 0B0, and MRLM111-X-RH
Rev 0E1. The drift table was eliminated from
the 883 section since it did not apply; Note #3
was removed from RH & QML datasheets with
SG verification that it no longer applied. Added
NSID's for 50k Rad and Post Radiation Table.
MDS data sheets will be archived.
12/14/05 B Ordering Information Table R. Malone Removed NSID reference LM111J-8PQMLV,
5962P0052401VPA
30k rd(Si). Reason: NSID on LTB, Inventory
exhausted. Added following NSID's:
LM111HPQMLV, LM111WPQMLV and
LM111WGPQMLV. Reason: Still have
Inventory. LM111QML, Revision A will be
archived.
06/26/08 C Features, Ordering Information Table,
Electrical section Notes.
Larry McGee Added Radiation reference, ELDRS NSID's
and Note 14 and 15, Low Dose Electrical
Table. Deleted 30k rd(Si) NSID's:
LM111HPQMLV, LM111WPQMLV and
LM111WGPQMLV. Reason: EOL 9/06/05.
Revision B will be archived.
29 www.national.com
LM111QML
Physical Dimensions inches (millimeters) unless otherwise noted
Metal Can Package (H)
NS Package Number H08C
Cavity Dual-In-Line Package (J)
NS Package Number J08A
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LM111QML
Dual-In-Line Package (J)
NS Package Number J14A
Leadless Chip Carrier (E)
NS Package Number E20A
31 www.national.com
LM111QML
Cerpack Package (W)
NS Package Number W10A
Cerpack Gull Wing Package (WG)
NS Package Number WG10A
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LM111QML
Notes
33 www.national.com
LM111QML
Notes
LM111QML Voltage Comparator
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