DATASHEET CA3260, CA3260A FN1266 Rev.7.00 Dec 10, 2009 4MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output CA3260A and CA3260 are integrated circuit operational amplifiers that combine the advantage of both CMOS and bipolar transistors on a monolithic chip. The CA3260 series circuits are dual versions of the popular CA3160 series. Gate protected P-Channel MOSFET (PMOS) transistors are used in the input circuit to provide very high input impedance, very low input current, and exceptional speed performance. The use of PMOS field effect transistors in the input stage results in common mode input voltage capability down to 0.5V below the negative supply terminal, an important attribute in single supply applications. A complementary symmetry MOS (CMOS) transistor pair, capable of swinging the output voltage to within 10mV of either supply voltage terminal (at very high values of load impedance), is employed as the output circuit. The CA3260 Series circuits operate at supply voltages ranging from 4V to 16V, or 2V to 8V when using split supplies. The CA3260A offers superior input characteristics over those of the CA3260. Features * MOSFET Input Stage provides - Very High ZI = 1.5T (1.5 x 1012) (Typ) - Very Low II . . . . . . . . . . . . 5pA (Typ) at 15V Operation . . . . . . . . . . . . . . . . . . . . . . 2pA (Typ) at 5V Operation * Ideal for Single Supply Applications * Common Mode Input Voltage Range Includes Negative Supply Rail; Input Terminals Can be Swung 0.5V Below Negative Supply Rail * CMOS Output Stage Permits Signal Swing to Either (Or Both) Supply Rails * Pb-Free Available (RoHS Compliant) Applications * Ground Referenced Single Supply Amplifiers * Fast Sample-Hold Amplifiers * Long Duration Timers/Monostables * Ideal Interface with Digital CMOS Ordering Information PART NUMBER PART MARKING TEMP. RANGE (C) * High Input Impedance Wideband Amplifiers PACKAGE PKG. DWG. # * Voltage Followers (e.g. Follower for Single Supply D/A Converter) * Voltage Regulators (Permits Control of Output Voltage Down to 0V) CA3260E CA3260E -55 to +125 8 Ld PDIP E8.3 CA3260EZ (Note) CA3260EZ -55 to +125 8 Ld PDIP* (Pb-free) E8.3 CA3260AE CA3260AE -55 to +125 8 Ld PDIP E8.3 -55 to +125 8 Ld PDIP* (Pb-free) E8.3 CA3260AEZ 3260AEZ (Note) * Wien Bridge Oscillators *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. * Voltage Controlled Oscillators * Photo Diode Sensor Amplifiers Pinout CA3260, CA3260A (8 LD PDIP) TOP VIEW OUTPUT (A) 1 8 V+ 7 OUTPUT (B) 6 INV. INPUT (B) 5 NON INV. INPUT (B) A INV. INPUT (A) 2 - + B FN1266 Rev.7.00 Dec 10, 2009 NON INV. INPUT (A) 3 V- 4 + - Page 1 of 4 CA3260, CA3260A Absolute Maximum Ratings Thermal Information DC Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . 16V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V) Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite Thermal Resistance (Typical, Note 2) JA (C/W) JC (C/W) PDIP Package* . . . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . -65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = +25C, Typical Values Intended Only for Design Guidance. TYPICAL VALUES PARAMETER SYMBOL TEST CONDITIONS CA3260A CA3260 UNITS Input Resistance RI VS = 7.5V 1.5 1.5 T Input Capacitance CI f = 1MHz, VS = 7.5V 4.3 4.3 pF Unity Gain Crossover Frequency fT VS = 7.5V 4 4 MHz SR VS = 7.5V Slew Rate Transient Response Rise Time tr Overshoot OS Settling Time (to <0.1, VIN = 4VP-P) tS 10 10 V/s CL = 25pF, RL = 2k AV = +1, VS = 7.5V 0.09 0.09 s 10 10 % CL = 25pF, RL = 2k AV = +1, VS = 7.5V 1.8 1.8 s Input Offset Voltage VIO V+ = 5V, V- = 0V 2 6 mV Input Offset Current IIO V+ = 5V, V- = 0V 0.1 0.1 pA II V+ = 5V, V- = 0V 2 2 pA CMRR V+ = 5V, V- = 0V 70 60 dB VO = 4VP-P, RL = 20k V+ = 5V, V- = 0V 100 100 kV/V 100 100 dB 0 to 2.5 0 to 2.5 V 1 1 mA Input Current Common Mode Rejection Ratio Large Signal Voltage Gain AOL Common Mode Input Voltage Range VICR Supply Current I+ Power Supply Rejection Ratio Electrical Specifications PARAMETER PSRR V+ = 5V, V- = 0V VO = 5V, RL = V+ = 5V, V- = 0V VO = 2.5V, RL = V+ = 5V, V- = 0V 1.2 1.2 mA VIO/V+, V+ = 5V, V- = 0V 200 200 V/V For Each Amplifier at TA = +25C, V+ = 15V, V- = 0V, Unless Otherwise Specified. SYMBOL TEST CONDITIONS CA3260A CA3260 MIN TYP MAX MIN TYP MAX UNITS Input Offset Voltage |VIO| VS = 7.5V - 2 5 - 6 15 mV Input Offset Current |IIO| VS = 7.5V - 0.5 20 - 0.5 30 pA II VS = 7.5V Input Current Large Signal Voltage Gain Common Mode Rejection Ratio FN1266 Rev.7.00 Dec 10, 2009 AOL CMRR VO = 10VP-P, RL = 10k - 5 30 - 5 50 pA 50 320 - 50 320 - kV/V 94 110 - 94 110 - dB 80 95 - 70 90 - dB Page 2 of 4 CA3260, CA3260A For Each Amplifier at TA = +25C, V+ = 15V, V- = 0V, Unless Otherwise Specified. (Continued) Electrical Specifications PARAMETER CA3260A TEST CONDITIONS SYMBOL CA3260 MIN TYP MAX MIN TYP MAX UNITS 0 -0.5 to 12 10 0 -0.5 to 12 10 V Common Mode Input Voltage Range VlCR Power Supply Rejection Ratio PSRR VIO/V+ V+ = 17.5V - 32 150 - 32 320 V/V Maximum Output Voltage VOM+ RL = 10k 11 13.3 - 11 13.3 - V - 0.002 0.01 - 0.002 0.01 V 14.99 15 - 14.99 15 - V VOMRL = VOM+ - 0 0.01 - 0 0.01 V IOM+ Source VOMVO = 0V 12 22 45 12 22 45 mA IOM- Sink VO = 15V 12 20 45 12 20 45 mA VO (Amplifier A) = 7.5V VO (Amplifier B) = 7.5V - 9 15.5 - 9 15.5 mA VO (Amplifier A) = 0V VO (Amplifier B) = 0V - 1.2 3 - 1.2 3 mA VO (Amplifier A) = 0V VO (Amplifier B) = 7.5V - 5 8.5 - 5 8.5 mA - 6 - - 8 - V/C - 120 - - 120 - dB Maximum Output Current Total Supply Current RL = I+ VIO/T Input Offset Voltage Temperature Drift Crosstalk f = 1kHz Schematic Diagram 8 V+ AMPLIFIER A Q11 AMPLIFIER B Q7 Q6 Q10 D2 D4 R5 2K Q1 Q2 Q14 R6 200k Q13 FN1266 Rev.7.00 Dec 10, 2009 C2 30pF R11 1k Q16 Q15 2 1 7 6 Q26 R10 Q27 1k Q18 R9 1k Q24 D8 Q19 R2 1k Q25 D7 D5 R12 2k Q4 R1 1k 3 D6 Q22 Q5 Q3 R7 300k Q8 C1 30pF R4 1k R3 1k Q20 Q9 Q23 D3 D1 Q12 Q21 Q17 Q28 R14 300 R8 1k 5 R13 200k 4 Page 3 of 4 CA3260, CA3260A Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. eB - L 0.115 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 0.355 10.16 N 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 8 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 8 6 10.92 7 3.81 4 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). (c) Copyright Intersil Americas LLC 1998-2009. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN1266 Rev.7.00 Dec 10, 2009 Page 4 of 4