MICRON TECHNOLOGY, INC. ADVANCE 16 MEG x 72 REGISTERED SDRAM DIMM SYNCHRONOUS DRAM MODULE MT18LSD11672 For the latest dala sheet revisions, please refer to the Micron Web site: www. micron.commii/msp/himi/datasheet himl FEATURES * JEDEC-standard 168-pin, dual in-line memory module (DIMM) * Registered inputs with one-clock delay * Phase-lock loop (PLL) clock driver to reduce loading * Utilizes 100 MHz and 125 MHz SDRAM components * ECC-optimized pinout * 128MB * Single +3.3V +0.3V power supply * Fully synchronous; all signals registered on positive edge of PLL clock * Internal pipelined operation; column address can be changed every clock cycle * Internal SDRAM banks for hiding row access/ precharge * Programmable burst lengths: 1,2, 4, 8 or full page * Auto Precharge and Auto Refresh Modes * Self Refresh * 64ms, 4,096-cycle, quad-row refresh (15.6,8/row) * LVTTL-compatible inputs and outputs * Serial presence-detect (SPD) * Two-clock WRITE recovery (WR) version; one-clock ("WR) not supported OPTIONS MARKING * Package 168-pin DIMM (gold) G * Frequency/CAS Latency* 100 MH2/CL = 3 (8ns, 125 MHzSDRAMs) -10C 100 MH2/CL = 3 (8ns, 125 MHz SDRAMs) -10B * Component Revision Designator Alpha character Factory Defined * Printed Circuit Board Revision Designator Numeric character Factory Defined *Device latency only; extra clock cycle required due to input register. KEY SDRAM COMPONENT TIMING PARAMETERS MODULE SPEED ACCESS SETUP HOLD MARKING GRADE TIME TIME TIME -10BA10C | -8B/8C 6ns 2ns 1ns PIN ASSIGNMENT (Front View) 168-Pin DIMM HUET PIN SYMBOL PIN | SYMBOL PIN SYMBQL PIN SYMBOL 1 Vs 43 Vs 85 Vs5 127 Vss 2 pad 44 DNU 86 DQ32 126 CKEO 3 Do 45 $2# 87 DO33 129 [RS VD(S34) 4 Doe 46 DOMB2 88 DO34 130 DOMBE6 5 pas 47 DQMB3 89 DQ35 131 DQM B7 6 Voc 48 DNU 90 Veo 132 RFU 7 DQ4 49 Voc 91 0036 133 Veo 8 pgs 50 NG 92 Das? 134 NG 9 DQ6 54 NC 93 DQ38 135 NG 10 Da? 52 CB2 94 pa39 136 CB6 11 Das 53 CB3 95 DG40 137 CB? 12 Vas 54 Vag 96 Vs5 138 Ves 13 pas 55 DO16 a7 DO41 139 DQ48 i4 DO10 56 DOW 98 DQ42 140 nQ49 15 Dat 57 DQ18 99 DQ43 14 DQ50 16 DQ12 58 DQ19 100 DO44 142 Das 17 DQ13 59 Voc 101 DQ45 143 Veo 18 Voc 60 Da20 102 Voo 144 DQs2 19 DQ14 61 NG 103 DO46 145 PLLBYP 20 DQ15 62 NG 104 DQ47 146 NG a4 CBO 63 RSVD(CKEt)| 105 CB4 147 REGE 22 CBI 64 Vsg 106 CBS 148 Vs5 23 Vss 65 DQ21 107 Vss 149 DQ53 24 NC 66 DQ22 108 NC 150 DQ54 25 NG 67 D023 109 NG 151 DQS5 26 Veo 68 Vss 110 Veo 152 Ves oT WE# 69 DQ24 111 Case 153 DO56 26 DQMBO 70 DQ25 112 | DOMB4 154 0Q57 29 DQMB1 7 DQ26 113 | DOMBS 155 DQ58 30 S0# 72 DQ27 114 [RSVD(S1#)] 156 DQs9 31 DNU 73 Vee 115 RAS# 157 Veo 32 Viss 74 D028 116 Vss 158 DQ60 33 AQ 75 DQ29 17 Al 159 DQ61 a4 AQ 76 pa30 118 Ag 160 DQ62 35 Ad 77 pa31 119 AS 161 DQ63 36 AG 78 Ves 120 AT 162 Ves 37 Ag 79 Gk2 121 AQ 163 cK3 38 A1Q/AP 80 NG 122 BAO 164 NG 39 Bat 81 WP 123 Ait 165 SA0 40 Vee 82 SDA 124 Voc 166 Sai 4 Voc 83 SCL 125 CK1 167 $A2 42 CKO 84 Voc 126 RFU 168 Voc NOTE: Symbols in parenthesis are not used on this module but may be used for other modules in this product family. They are jor reference only. 16 Meg x 72 Registered SDRAM DIMM 2M11 p65 Rev 4/98 Micron Technology, Inc, reserves the right to change products or specitications without notice 1998, Micron Technology, IncMICRON TECHNOLOGY, INC. ADVANCE 16 MEG x 72 REGISTERED SDRAM DIMM PART NUMBER PART NUMBER CONFIGURATION |SYSTEM BUS SPEED M118LSD11672G-10C___| 16 Meg x 72 100 MHz MT18LSD1T1672G-10B__ | 16 Meg x 72 100 MHz NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Examiple: MT18LSDT472G-10BC1 GENERAL DESCRIPTION The MT18LSDT1672 is a high-speed CMOS, dynamic random-access, 128MB solid-state memorie organized in a x72 configuration. This module uses internally configured quad-bank SDRAMs with a synchronous interface (all sig- nals are registered on the positive edge of clock signal CKO). Read and write accesses to the SORAM module are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an AC- TIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BAO, BA] select the bank, AO-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The module provides for programmable read or write burst lengths of 1,2,40r8 locations, or full page, witha burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The module uses an internal pipelined architecture to achieve high-speed operation. This architecture is compat- ible with the 2#rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seam- less, high-speed, random-access operation. The module is designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVITTL-compatible. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to synchronously burst data ata high data rate withautomatic column-address generation, the ability to interleave be- tween internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. For more informa- tion regarding SDRAM operation, refer to the 64 Meg: x4, x8, x16 SDRAM data sheet. PLL AND REGISTER OPERATION The module can be operated in either registered mode (REGE pin HIGH), where the control/ address input signals are latched in the register on one rising clock edge and sent to the SDRAM devices on the following rising clock edge (data access is delayed by one clock), or in buffered mode (REGE pin LOW) where the input signals pass through the register/ buffer to the SDRAM devices on thesame clock. A phase-lock loop (PLL) on the module is used to re-drive the clock signals to the SDRAM devices to minimize system clock loading (CKO is connected to the PLL, and CK1, CK? and CK3 are terminated). SERIAL PRESENCE-DETECT OPERATION This module incorporates serial presence-detect (SPD). TheSPD function is implemented using a?,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various DRAM organizations and timing parameters. The remaining 128 bytes of storage are avail- able for use by the customer. System READ/ WRITE opera- tions between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC bus using the DIMMs SCL (clock) and SDA (data) signals, together with SA(2:0), which provide eight unique DIMM/ EEPROM addresses. 16 Meg x 72 Registered SDRAM DIMM 2M11 p65 Rev 4/98 Micron Technology, Inc, reserves the right to change products or specitications without notice 1998, Micron Technology, IncMICRON TECHNOLOGY, INC. ADVANCE 16 MEG x 72 REGISTERED SDRAM DIMM SPD CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figures 1 and 2). SPD START CONDITION Allcommands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD STOP CONDITION All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. scl. / \ / \ SDA / \ | | | | | x | | | DATA STABLE | DATA GHANGE DATA STABLE Figure 1 DATA VALIDITY SPD ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW toacknowledge that it received the eight bits of data (Figure 3). The SPD device will always respond with an acknowl edge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowl- edge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to trans- mit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the step condition to return to standby power mode. Figure 2 DEFINITION OF START AND STOP SCL from Master ee ey A - ey A ee ee Data Output fram Receiver | | | Data Output \ from Transmitter | [ x | | | | | | | | Xx /\ | | | Acknowledge Figure 3 ACKNOWLEDGE RESPONSE FROM RECEIVER 16 Meg x 72 Registered SDRAM DIMM 2M11 p65 Rev 4/98 Micron Technology, Inc, reserves the right to change products or specitications without notice 1998, Micron Technology, IncMICRON TECHNOLOGY, INC. ADVANCE 16 MEG x 72 REGISTERED SDRAM DIMM RSo# RS2# FUNCTIONAL BLOCK DIAGRAM MT18LSDT1672 (128MB) RDGMBO, RDQMB4 | DOM CS# BOM CS# Bao -~-}Da0 Das2 4 Dao Dai 4{Da1 Uo Dass-4ba1 Ug DQ2 -v7}DO2 DG34 | DQ2 DQ3s ---}DQ3 DQ35 -v4 Ds l | | DQM CS# DOM CS# DQ4 -4DQ0 Dass 4 DQG DQ5 -40G1 lt bas? v4 DG1 U0 Das --4DGz2 Dass 4 DAZ DQ7 -v4 DOs Dass 4 Das RDGMB1_, RDQMB5 DOM CS# DOM CS# Bas -4 DOO DG40 | DQO pag }DGI Ue DQ41 {D1 U11 DQ10 ~--4 Dae DQ41 -4 Doe Dan + Das DG43 --] DG3 I l | DQM CS# DOM CS# DQ12 - DOO Da44 +4 Dao DaIg-~4DO1 US DO4E 4 DOL U2 DQ14 -v4 DOF DO46 w4 DG2 DQ15 ~4 DOs DG47 -~4 DGS | DOM CS# DQM CS# CBO -v- DGQO CB4 -we]DQ0 CH DG U4 CBS --4DG1 L13 CB2 -v- DOF CBB -4 Daz CBS -4 DOS CB7 . D038 ROQMB2 RDQMBB} DQM CS# DQM CS# Da16 -4 Dao DO48 4 DOO DQIF--4DGQ1 US Doss DOT 14 Daeg 4 DG DaQs0 .4 Dae Dag 4 Das DQS1 4 DAS l DQM CS# DOM CS# DQz0 -4 BG DQS2 4 DG0 Daa 4 Dai Us DQ53 DG U5 DQ22 >re DO2 DQs4 -.4 DG2 DQz3 4 DGS DQS5 -] D8 RDQMB3s!4 ROQMB7 DQM CS# DOM CS# DQ24 -w4 DGo DQs6 -4 DAO DQZ5~4DQ1 U7 Das? --4DQ1 Wis DQ26 -r DQ? DasE -4 Daz DG27 -"4 DOS Dass v4 DO3 | I | BOM CS# DOM CS# bQe28 - DAG DGeo --4 DAG DG29-4DG1 Us DQe1 --4 DOI Li? BQs0 -~ BaF DQe2 4 Daz bast --4 Das DQ6S 4 DAS RAS# R RRAS# SDRAMs Lio-L17 CAS# E RCAS# SDRAMs LIO-L17 CKEO RCKEO SDRAMs L0-Lit7 SDRAM x 4 G SDRAM x4 WE# | RWE# SDRAMs Lio-Li17 SDRAM x4 AO-AI1 RAC-RAI1 SDRAMs UO-Ui7 = CKO wy PLL SDRAM x 4 $s BAD T RBAO SDRAMs Lo-Li17 SDRAM x2 BAI 5 RBA1 SDRAMs Lio-LI17 Tr 20pl REGISTER x2 SO# S2# ASow RSzv - DGMBO - DOMB7 R RDGMEBo - RDQMB7 CK1I-CKS _ 10K = 30pt Voz sR + REGE PLL CLK Vos +_+ SDRAMs LIO-LI17 47K Vss [___+ SDRAMs U0-L17 1 SAD SAI SA? NOTE ALL RESISTOR VALUES ARE 10 OHMS Ub-LU17 = MT48LC1 6M4A2TG SDRAMs UNLESS OTHERWISE SPECIFIED 16 Meg x 72 Registered SDRAM DIMM 4 Micron Technology, Inc, reserves the right to change products or specitications without notice 2M11 p65 Rev 4/98 1998, Micron Technology, IncMICRON TECHNOLOGY, INC. ADVANCE 16 MEG x 72 REGISTERED SDRAM DIMM PIN DESCRIPTIONS PIN NUMBERS SYMBOL TYPE DESCRIPTION 115, 111, 27 RAS#, CAS#, WE# Input Command Inputs: RAS#, CAS# and WE# (along with S0#, S2#) define the command being entered. 42, 79, 125, 163 CKO-CK3 Input Clock: CKO-CK3 are driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. CK also increments the internal burst counter and controls the output registers. 128 CKEO Input Clock Enable: CKEO activates (HIGH) and deactivates (LOW) the CKO-3 signals. Deactivating the clock provides POWER-DOWN and SELF REFRESH operaticn (all banks idle}, or CLOCK SUSPEND operation (burst access in progress). CKEO is synchronous except after the device enters power-down and self refresh modes, where CKEO becomes asynchronous until after exiting the same mode. The input butters, including CKO-3, are disabled during power-down and self refresh modes, providing low standby power, 30, 45 SO#, S2# Input Chip Select: SO#, S2# enable (registered LOW) and disable (registered HIGH) the command decoder. All commands are masked when SO#, S2# are registered HIGH. SO#, S2# are considered part of the command ccde. 28-29, 46-47, 112-113, 130-131 DQMB0-DQMB7 Input Input/Output Mask: DQMB is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQMB is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency} when DQMB is sampled HIGH during a READ cycle. 39,122 BAO, BA1 Input Bank Address: BAO and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. 33-38, 117-121,128 AO-A11 Input Address Inputs: AO-A11 are sampled during the ACTIVE command (row-address AO-A11) and READ/WRITE command (column-address AO-A8, with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if both banks are to be precharged (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE REGISTER command. 2-5, 7-11, 13-17, 19-20, 55-58, 60, 65-67, 69-72, 74-77, 86-89, 91-95, 97-101, 103-104, 139-142, 144, 149-151, 153-156, 158-161 DQo-DQ63 Input! Output Data I/O: Data bus. 21, 22, 52, 53, 105, 106, 136, 137 CBO-CB7 Input/ Output Check Bits. 16 Meg x 72 Registered SDRAM DIMM 2M11 p65 Rev 4/98 Micron Technology, Inc, reserves the right to change products or specitications without notice 1998, Micron Technology, IncMICRON TECHNOLOGY, INC. ADVANCE 16 MEG x 72 REGISTERED SDRAM DIMM PIN DESCRIPTIONS (continued) PIN NUMBERS SYMBOL TYPE DESCRIPTION 6, 18, 26, 40, 41, 49, 59, Vcc Supply Power Supply: +8.8V +0.3V. 73, 84, 90, 102, 110, 124, 133, 148, 157, 168 1,12, 28, 32, 48, 54, 64, Vss Supply Ground. 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 31 WP Input Write Protect: Serial presence-detect hardware write protect. 82 SDA Input/Output] Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. 83 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. 165-167 SA0-SA2 Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. 147 REGE Input Register Enable. 126, 132 RFU Reserved for Future Use: These pins should be lett unconnected. 31, 44, 48 DNU Do Not Use: These pins are not connected on this module but are assigned pins on the compatible DRAM version. 63, 114, 129 RSVD - Reserved: These pins are not connected on this module (CKE1, 51#, S3#) but are assigned pins on other SDRAM versions. 16 Meg x 72 Registered SDRAM DIMM 2M11 p65 Rev 4/98 Micron Technology, Inc, reserves the right to change products or specitications without notice 1998, Micron Technology, IncADVANCE MICRON 16 MEG x 72 TECHNOLOGY, Ne REGISTERED SDRAM DIMM SERIAL PRESENCE-DETECT MATRIX BYTE DESCRIPTION ENTRY (VERSION) |SYMBOL |BIT? | BIT6| BITS | BIT4] BITS | BITZ] BIT1 | BITO| HEX 0 NUMBER OF BYTES USED BY MICRON 126 1 0 0 0 0 0 0 0 80 1 TOTAL NUMBER OF SPD MEMORY BYTES 256 0 0 0 0 1 0 0 0 08 2 MEMORY TYPE SDRAM 0 0 0 0 0 1 0 0 04 a NUMBER OF ROW ADDRESSES 12 0 0 0 0 1 1 0 0 oc 4 NUMBER OF COLUMN ADDRESSES 10 0 0 0 0 1 0 1 0 10 NUMBER OF BANKS 1 0 0 0 0 0 0 0 1 O41 6 MODULE DATA WIDTH 72 0 1 0 0 1 0 0 0 48 ? MODULE DATA WIDTH (continued) 0 0 0 0 0 0 0 0 Q 00 8 MODULE VOLTAGE INTERFACE LEVELS LVTTL 0 0 0 0 0 0 0 1 O41 9 SDRAM CYCLE TIME 8 CK 1 0 0 0 Q 0 0 0 B0 (CAS LATENCY = 3) 10 | SDRAM ACCESS FROM CLOCK 6 'ac 0 1 1 0 0 0 0 0 60 (CAS LATENCY = 3} "1 MODULE CONFIGURATION TYPE ECC 0 0 Q 0 0 0 1 0 02 12 | REFRESH RATE/TYPE 15.6us SELF 1 0 0 0 0 0 0 0 80 13 | SDRAM WIDTH (PRIMARY SDRAM} 4 0 0 0 0 0 1 0 0 04 14 | ERROR GHECKING SDRAM DATA WIDTH 4 0 0 Q 0 0 1 0 0 04 15 | MIN. CLOCK DELAY FROM BACK TO BACK 1 'ccb 0 0 0 0 0 0 0 1 1 RANDOM COLUMN ADDRESSES 16 | BURST LENGTHS SUPPORTED 1,2, 4, 8, PAGE 1 0 0 0 1 1 1 1 8F 17__| NUMBER OF BANKS ON SDRAM DEVICE 4 0 0 0 0 Q 1 0 0 04 18 | CAS#LATENCIES SUPPORTED 2,3 0 0 0 0 0 1 1 0 06 19 | CS#LATENCY 0 0 0 0 0 0 0 0 1 1 20 | WE#LATENCY 0 0 0 0 0 Q 0 0 1 01 a4 SDRAM MODULE ATTRIBUTES REGISTERED, PLL 0 0 0 1 0 1 1 0 16 22 | SDRAM DEVICE ATTRIBUTES: GENER AL OE 0 0 0 0 1 1 1 0 OE 23 | SDRAM CYCLE TIME 13 ick 1 1 0 1 0 0 0 0 Do (CAS LATENCY = 2} 24 | SDRAM ACCESS FROM CLK 9 AC 1 0 0 1 0 0 0 0 90 (CAS LATENCY = 2} 25 SDRAM CYCLE TIME CK 0 0 0 0 Q 0 0 0 00 (CAS LATENCY = 1) 26 | SDRAM ACCESS FROM CLK ac o} oo] 0] 0 o}/of]o] 0 00 (CAS LATENCY = 1} 27 | MINIMUM ROW PREGHARGE TIME ('RP} 40 'RP 0 0 0 1 1 1 1 0 1E 23 | MINIMUM ROW ACTIVE TO ROW ACTIVE 20 'RRD 0 0 0 1 Q 1 0 0 14 29 | MINIMUM RAS#TO GAS# DELAY 20 'koD 0 0 0 1 0 1 0 0 14 40 | MINIMUM RAS#PULSE WIDTH 50 RAS 0 0 1 1 0 0 1 0 42 a MODULE BANK DENSITY 128MB 0 0 1 0 Q 0 0 0 20 42 COMMAND AND ADDRESS SETUP TIME 2 AS,'CMS| 0 0 1 0 Q 0 0 0 20 44 | COMMAND AND ADDRESS HOLD TIME 1 AH CMH] 0 0 0 1 0 0 0 0 10 34 | DATA SIGNAL INPUT SETUP TIME 2 ins 0 0 1 0 Q 0 0 0 20 a5 | DATA SIGNAL INPUT HOLD TIME 1 'DH 0 0 0 1 0 0 0 0 10 46-61 | RESERVED 0 0 0 0 0 0 0 0 00 62 | SPD REVISION REV. 1.2 0 0 0 1 Q 0 1 0 12 63 __| CHECKSUM FOR BYTES 0-62 128MB 1 0 Q Q 1 Q 1 Q BA NOTE: 1. 1/0": Serial Data, driven to HIGH" / driven ta LOW." 16 Meg x 72 Registered SDRAM CIMM 7 Micron Technology, Inc, reserves the right to change products or specitications without notice p65 Rev fos 1998, Micron Technology, IncADVANCE MICRON 16 MEG x72 TECHNOLOGY, Ne REGISTERED SDRAM DIMM SERIAL PRESENCE-DETECT MATRIX (continued) BYTE DESCRIPTION ENTRY (VERSION) | SYMBOL |BIT?7 | BITG| BITS | BIT4 | BITS | BIT2 | BIT1 | BITO | HEX 64 MANUFACTURER'S JEDEC ID CODE MICRON 0 i] 1 0 1 1 i] 0 20 65-71 | MANUFACTURER'S JEDEC ID CODE (CONT.) 1 1 1 1 1 1 1 1 FF 72 MANUFACTURING LOCATION 0 i] 0 0 0 0 i] 1 01 0 0 0 0 0 0 1 0 02 0 i} 0 0 0 0 1 1 nk 0 0 0 0 0 1 0 0 04 0 0 0 0 0 1 0 1 05 0 0 0 0 0 1 1 0 06 73-90 | MODULE PART NUMBER (ASCII) x x x x x x x x x 91 PCB REVSION CODE A 0 0 0 0 0 0 0 1 o1 B 0 i} 0 0 0 0 1 0 a C 0 0 0 0 0 0 1 1 03 D 0 0 0 0 0 1 0 0 04 92 REVISION CODE (CONT.} 0 0 0 0 0 0 0 0 0 00 93 YEAR OF MANUFACTURE IN BCD x x x x x x x x x 94 WEEK OF MANUFACTURE IN BCD x x x x x x x x x 95-98 | MODULE SERIAL NUMBER x x x x x x x x x 99-125 | MANUFACTURE SPECIFIC DATA (RSVD) . 126 SYSTEM FREQUENCY 100 MHz 0 1 1 0 0 1 i] 0 64 127) | SDRAM COMPONENT & CLOCK DETAIL 1 i} 0 0 1 1 i} 1 80 16 Mog 72 Royster SDRAM DIMM 8 Micron Technology, Inc, reserves the right fo change produets or apeerestenewthaut natiMICRON TECHNOLOGY, INC. ADVANCE 16 MEG x 72 REGISTERED SDRAM DIMM COMMANDS Truth Table 1 provides a general reference of available commands. For a more detailed description of commands and operations, refer to the 64 Meg: x4, x8, x16 SDRAM data sheet. TRUTH TABLE 1 - Commands and DQMB Operation (Notes: 1) NAME (FUNCTION) CS# |RAS# |CAS# | WE# |DQMB]| ADDR DQs |NOTES COMMAND INHIBIT (NOP) H X X X X X X NO OPERATION (NOP) L H H H X X xX ACTIVE (Select bank and activate row) L L H H X |Bank/Row] xX 3 READ (Select bank and column, and start READ burst) L H L H X |Bank/Col| xX 4 WRITE (Select bank and column, and start WRITE burst) L H L L X | Bank/Col | Valid 4 BURST TERMINATE L H H L Xx x Active PRECHARGE (Deactivate row in bank or banks) L L H L Xx Code xX 5 AUTO REFRESH or L L L H X X xX 6, 7 SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER L L L L X |Opcode}] X 2 Write Enable/Output Enable L Active 8 Write Inhibit/Output High-2 - - - - H - High-Z| 8 NOTE: . CKE is HIGH for all commands shown except SELF REFRESH. . AO-A11 define the op-code written to the Mode Register. 1 2 3. AQ-A11 provide row address, and BAO/BA1 determine which bank is made active. 4 . AQ-A8 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BAO/BA1 determine which bank is being read from or written to. 5. A10 LOW: BAO/BA1 determine which bank is being precharged. A10 HIGH: both banks are precharged and BAO/BA1 are Dont Care. 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. N Internal refresh counter controls row addressing; all inputs and I/Os are Dont Care except for GKE. 8. Activates or deactivates the DQs during WRITEs (Zero-clock delay) and READs (two-clock delay). 16 Meg x 72 Registered SDRAM DIMM 2M11 p65 Rev 4/98 Micron Technology, Inc, reserves the right to change products or specitications without notice 1998, Micron Technology, IncMicCR ON TECHNOLOGY, INC. ADVANCE 16 MEG x 72 REGISTERED SDRAM DIMM All AIO AS AB A? AG AS Ad AS AZ At AO Address Bus PVT Pry yyy 3 lode Register (Mx) |Reservect | WE | Op Mode GAS Latency [er | Burst Length Should program M11, M10 = 0, 0 io ensure compatibility with future devices Burst Length M2 M1 MO M3 =0 M3 = 1 o 0 1 1 oO 0 1 2 2 oO 1 0 4 4 oo1 1 8 8 1 co 0 Reserved Reserved 101 Reserved Reserved 191 0 Reserved Reserved 19101 Full Page Reserved M3 Burst Type 0 Sequential 1 Interleaved M6 MS M4 GAS Latency oo 08 Reserved oO 1 0 2 o1 4 3 160 06 Reserved 1 0 1 Reserved 131 ~=0 Reserved 161 1 Reserved Ma Ma? Mo-Mo Operating Mode a 0 Defined Standard Operation Allother states reserved LE Write Burst Moce Programmed Burst Length Single Location Access Figure 4 MODE REGISTER DEFINITION Table 1 BURST DEFINITION Order of Accesses Within a Burst Burst Starting Column Length Address: Type = Sequential | Type = Interleaved AQ 2 0 0-1 0-1 1 1-0 1-0 Al AQ 0 60 0-1-2-3 0-1-2-3 A Oo 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 Ae Ai AO 0 0.0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 Oo oO 1 1-2-3-4-5-6-7-0 | 1-0-3-2-5-4-7-6 Oo 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-54 1 O O 4-5-6-7-0-1-2-3 | 4-5-6-7-0-1-2-3 1 oO 1 5-6-7-0-1-2-3-4 | 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 | 7-6-5-4-3-2-1-0 Full n AO-AQ Cn, Cn4+1, Cn+2 Page |(location 0-1,023) Cn+3, Cnt4... Not supported (1,024) . Cn, Cn... NOTE: 1. For aburst length of two, A1-A9 select the block of two burst; AO selects the starting column within the block. . For a burst length of four, A2-A9 select the block of four burst; AO-A1 select the starting column within the block. . For a burst length of eight, A3-A9 select the block of eight burst; AO-A2 select the starting column within the block. . For a full-page burst, the full row is selected and AO-A9 select the starting column. 5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. For a burst length of one, AO-AS select the unique column to be accessed, and Mode Register bit M3 is ignored. 16 Meg x 72 Registered SDRAM DIMM 2M11 p65 Rev 4/98 Micron Technology, Inc, reserves the right to change products or specitications without notice 1998, Micron Technology, IncMICRON TECHNOLOGY, INC. ADVANCE 16 MEG x 72 REGISTERED SDRAM DIMM ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Supply Relative to Vss........... -1V to +4.6V Voltage on Inputs, NC or I/O Pins Relative tO V6 ..ecesceseseeeeseeneeeeseeeneeeneneees 1V to +4.6V Operating Temperature, T, (ambient) .......... OPC to 470C Storage Temperature (plastic)... 55C to +125C Power Dissipation ......cscssssesssseessessssenssseeessesssseens 18W *Stresses greater than those listed under " Absolute Maxi- mum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 6) (Vcc = +3.3V 0.3V}) PARAMETER /CONDITION SYMBOL MIN MAX |UNITS | NOTES Supply Voltage Vcc 3.0 3.6 Vv Input High (Logic 1) Voltage, all inputs VIH 2.0 |VWoco+0.3] V 25 Input Low (Logic 0) Voltage, all inputs VIL -0.5 0.8 Vv 25 INPUT LEAKAGE CURRENT In 6 5 pA 22 Any input OV = Vin s Vcc (All other pins not under test = OV) OUTPUT LEAKAGE CURRENT loz 6 5 pA (DQs are disabled; OV < Vout = Vcc) OUTPUT LEVELS VoH 2.4 Vv Output High Voltage (lout = -4mA) Output Low Voltage (lout = 4mA) VoL 0.4 Vv Icc OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes: 1, 6, 13) (Vcc = +3.8V +0.3V) MAX PARAMETER CONDITION SYMBOL |-10C/-108] UNITS | NOTES OPERATING CURRENT: Active Mode; Icct 1,170 mA | 3, 18, Burst = 2; READ or WRITE; 'RC ='RC (MIN); 19 CAS latency = 3; CK = 10ns STANDBY CURRENT: Power-Down Mode; Icc2 36 mA iCK = 10ns: CKE = LOW; All banks idle STANDBY CURRENT: CS# = HIGH; Icc3 630 mA | 12,19 ICK = 10ns; CKE = HIGH; All banks active after RCD met; No accesses in progress OPERATING CURRENT: Burst Mode; Continuous burst; Icc4 2,340 mA 8, 18, READ or WRITE; 'CK = 1Gns; All banks active; 19 Addresses transition once per clock cycle; CAS latency = 3 AUTO REFRESH CURRENT: 'RC 2 'RC (MIN); lecs 3,780 mA | 3, 18, CAS latency = 3 19 AUTO REFRESH CURRENT: 'RCG = 15.625yS; Ioce 630 mA | 3, 18, CAS latency = 3 19 SELF REFRESH CURRENT: CKE s 0.2V lec? 18 mA 4 16 Meg x 72 Registered SDRAM DIMM 1 1 2M11 p65 Rev 4/98 Micron Technology, Inc, reserves the right to change products or specitications without notice 1998, Micron Technology, IncMICRON TECHNOLOGY, INC. ADVANCE 16 MEG x 72 REGISTERED SDRAM DIMM CAPACITANCE PARAMETER SYMBOL | MAX | UNITS | NOTES Input Capacitance: AO-A11, BAO, BA1, RAS#, CAS#, WE# cn pF 2 Input Capacitance: SO#, S2#, CKEO, DQMBO#-DQMB7# Cie 8 pF 2 Input Capacitance: CKO Ce 6 pF 2 Input Capacitance: REGE C4 5 pF 2 Input/Output Capacitance: SCL, SAO-SA2, SDA C5 12 pF 2 Input/Output Capacitance: DQ0-DQ63, CBO-CB7 Cio a pF 2 SDRAM COMPONENT* AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 8, 9, 11, 24) AC CHARACTERISTICS -10C -10B PARAMETER SYMBOL] MIN MAX MIN MAX UNITS |NOTES Access time from CLK (pos. edge) CL=3 'AC 6 6 ns 24 CL=2 TAC 9 9g ns 24 Address hold time TAH 1 1 ns Address setup time tAS 2 2 ns CLK high-level width CH 3 3 ns CLK low-level width CL 3 3 ns Clock cycle time CL=3 CK 8 8 ns CL=2 CK 13 13 ns CKE hold time 'CKH 1 1 ns CKE setup time 'CKS 2 2 ns CS#, RAS#, CAS#, WE#, DOM hold time CMH 1 1 ns CS#, RAS#, CAS#, WE#, DOM setup time 'CMS 2 2 ns Data-in hold time 'DH 1 1 ns Data-in setup time ips 2 2 ns Data-out high-impedance time CL=3 tHZ 6 6 ns 10 CL=2 'HZ 7 7 ns 10 Data-out low-impedance time LZ 1 1 ns Data-out hold time OH 3 3 ns ACTIVE to PRECHARGE command 'RAS 50 120K 50 120K ns AUTO REFRESH, ACTIVE command period RC 70 80 ns ACTIVE to READ or WRITE delay RCD 20 20 ns Refresh period - 4,096 rows 'REF 64 64 ms PRECHARGE command period iRP 20 24 ns ACTIVE bank A to ACTIVE bank B command 'RRD 20 20 ns Transition time T 0.3 1.2 0.3 1.2 ns 7 WRITE recovery time WR 1 CLK + 1CLK+ _ 27 8ns 8ns 15 15 ns 28 Exit SELF REFRESH to ACTIVE command 'XSR 80 80 ns 20 J.Moy 372 Regitered SDRAM CIMM { 5 Micron Technology, Inc, reserves the right to change Products or epectieatons without teeADVANCE MICRON 16 MEG x72 TECHNOLOGY, Ne REGISTERED SDRAM DIMM AC FUNCTIONAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 11, 24) PARAMETER SYMBOL -10B UNITS NOTES READ/WRITE command to READAVRITE command ScD 1 cK 17 CKE to clock disable or power-down entry mode iCKED 1 CK 14 CKE to clock enable or power-down exit setup mode PED 1 CK 14 DQM to input data delay Dab 0 cK 17 DOM to data mask during WRITEs (DQM 0 iCK 17 DQM to data high-impedance during READs Daz 2 cK 17 WRITE command to input data delay 'DWD 0 CK 17 Data-in to ACTIVE command 'DAL 5 iCK 15, 21 Data-in to PRECHARGE command 'DPL 2 CK 16 Last data-in to burst STOP command BDL 1 cK 17 Last data-in to new READ/WRITE command 'CDL 1 iCK 17 Last data-in to PRECHARGE command 'RDL 2 CK 16 LOAD MODE REGISTER command to ACTIVE or REFRESH command MRD 2 cK 17 Data-out to high-impedance from PRECHARGE command CL=3 |] 'ROH 3 CK 17 CL=2 ] 'ROH 2 cK 17 SDRAM COMPONENT ELECTRICAL TIMING CHARACTERISTICS BETWEEN -8 SPEED OPTIONS (Notes: 5, 6, 8, 9, 11) (OC < Ty s +70C) AC CHARACTERISTICS BE -8D 80 OB BA PARAMETER SYM [MIN |MAX|MIN [MAX] MIN [MAX [MIN |MAX [MIN |MAX | UNITS [NOTES Access time from CLK (pos. edge} CL=3 TAC 6 6 6 6 6 ns 26 CL=2 | AC 6 7 9 9 9 | ns | 26 CL=1 'AC af 27 af 27 27 ns 26 Clock cycle time CcL=3 | CK | 8 8 8 8 8 ns 26 cL=2 | 'ck | 10 10 12 12 12 ns 26 CL=1 cK | 30 30 30 30 30 ns 26 ACTIVE to READ or WRITE delay RCD | 20 20 20 20 24 ns 26 PRECHARGE command period RP | 20 20 20 24 24 ns 26 AUTO REFRESH, ACTIVE command period tro | 70 70 70 80 80 ns 26 WRITE recovery time WR | 2 2 2 2 2 CK 100 MHz Speed Reference (CL+RCD-RP) 2-2-2 2-2-2 3-2-2 3-2-3 3-3-3 | CLKs 16 Meg x 72 Registered SDRAM DIMM 1 3 Micron Technology, Inc, reserves the right to change products or specitications without notice 2M11 p65 Rev 4/98 1998, Micron Technology, IncMICRON TECHNOLOGY, INC. ADVANCE 16 MEG x72 REGISTERED SDRAM DIMM SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS (Notes: 1) (Vcc = +3.8V 0.3V) PARAMETER /CONDITION SYMBOL MIN MAX UNITS Supply Voltage Vcc 3.0 3.6 V Input High (Logic 1) Voltage, all inputs VIH Voc x .7 | Voc +.5 Vv Input Low (Logic 0} Voltage, all inputs VIL -1.0 | Vccx.3 Vv OUTPUT LOW VOLTAGE, lout = 8mA VoL 0.4 Vv INPUT LEAKAGE CURRENT, Vin = GND to Vcc IL 10 HA OUTPUT LEAKAGE CURRENT, Vout = GND to Vcc ILo 10 HA STANDBY CURRENT IsB 30 pA SCL = SDA = Vcc -0.8V, All other inputs = GND or 3.8V +10% POWER SUPPLY CURRENT Icc 2 mA SCL clock frequency = 100 KHz SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS (Notes: 1) (Vcc = +8.8V +0.3V) PARAMETER /CONDITION SYMBOL MIN MAX UNITS NOTES SCL LOW to SDA data-out valid TAA 0.3 3.5 us Time the bus must be free before a new transition can start BUF 47 us Data-out hold time 'DH 300 ns SDA and SCL fall time IF 300 ns Data-in hold time 'HD:DAT 0 us Start condition hold time 'HD:STA 4 us Clock HIGH period tHIGH 4 us Noise suppression time constant at SCL, SDA inputs ty 100 ns Clock LOW period 'LOW 47 ws SDA and SCL rise time 'R 1 us SCL clock frequency ISCL 100 KHz Data-in setup time 'SU:DAT | 250 ns Start condition setup time 'SU:STA A7 us Stop condition setup time 'SU:STO AZ us WAITE cycle time WRC 10 ms 23 16 Meg x 72 Registered SDRAM DIMM 1 4 2M11 p65 Rev 4/98 Micron Technology, Inc, reserves the right to change products or specitications without notice 1998, Micron Technology, IncMICRON TECHNOLOGY, INC. ADVANCE 16 MEG x 72 REGISTERED SDRAM DIMM NOTES 1. 2 a 10. 11. 13. 14. All voltages referenced to Vss. This parameter is sampled. Vcc = +3.3V +0.3V; f= 1MHz. Icc is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. Enables on-chip refresh and address counters. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0C <T, 70C) is ensured. An initial pause of 100ps is required after power-up, followed by two AUTO REFRESH commands before proper device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the 'REF refresh requirement is exceeded. AC characteristics assume T = Ins. In addition to meeting the transition rate specifica- tion, the clock and CKE must transit between Vin and Vit (or between ViL and Vin) in a monotonic manner. Outputs measured at 1.5V with equivalent load: oF} 50pF L HZ defines the time at which the output achieves the open circuit condition; it is not a reference to Vou or VoL. The last valid data element will meet OH before going High-Z. AC timing tests have Vit = OV and Vin = 3V with timing referenced to 1.5V crossover point. . Other input signals are allowed to transition no more than once in any 20ns period and are otherwise at valid Vin or Vin levels. Icc specifications are tested after the device is properly initialized. Timing actually specified by "CKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by 'WR plus 'RP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by WR. 17. Clocks required are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The Icc current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS latency is reduced. 19. Address transitions average one transition every 20ns. 20. CLK must be toggled a minimum of two times during this period. 21. Based on 'CK = 100 MHz. 22. Input leakage values based on register electrical characteristics, Vee = 3.6V. 23. The SPD EEPROM WRITE cycle time (WRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/ program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 24, There will be an added one-clock latency at the system level due to the register requiring an added clock cycle. 25. Vin overshoot: Vin (MAX) = VccQ + 2.0V for a pulse width < 10ns, and the pulse width cannot be greater than one third of the cycle rate. Vi, undershoot: VIL (MIN) = -2.0V for a pulse width < 10ns, and the pulse width cannot be greater than one third of the cycle rate. 26. These five parameters vary between speed grades and define the differences between the -8 SDRAM speeds: -8A, -8B, -8C, -8D, and -8E. All other -8 timing parameters remain constant. 27. Auto precharge mode only. The precharge timing budget ('RP) begins 8ns after the first clock delay, after the last WRITE is executed. 28. Manual precharge mode only. 16 Meg x 72 Registered SDRAM DIMM 2M11 p65 Rev 4/98 Micron Technology, Inc, reserves the right to change products or specitications without notice 1998, Micron Technology, IncMICRON TECHNOLOGY, INC. ADVANCE 16 MEG x 72 REGISTERED SDRAM DIMM SPD EEPROM t 1 t Fy, | = HIGH om Ay t Low |) { SCL | / \ \ } Le tSU STA}ese}| bere] THO STA THD DAT |-o 1SU DAT tsusTo SDA IN / oo tAA tbH SDA OUT tBUF DOA AAA AAA AAA ANAAAA Soe ss eS, RY UNDEFINED SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS SYM 16 Meg x 72 Registered SDRAM DIMM 2M11 p65 Rev 4/98 16 Micron Technology, Inc, reserves the right to change products or specitications without notice 1998, Micron Technology, IncADVANCE MICRON 16 MEG x72 TECHNOLOGY, Ne REGISTERED SDRAM DIMM 168-PIN DIMM FRONT VIEW 157 (4 00) MAX 5 260 (133 80) 5 240 (133 10} TauaE TauaE AARNE Taaaw CCCCOLEEL O78 (2 oN 1710 (43 44) 1 650 (42 93) CCCCCCEET ELEC CE LEER TCE) nag io WaT io Hae 4 io Cd Tae ARAAQA HGRA) A) GGG 0 A) ABB BANE 118 (3 00) TEGVEERHTEE 700 (17 78) (2X) oN, FTES ELE | neeontye Tamm . COT) TOOT ooo] ae} fe \= (6.35) TYP \O _. _ \ 118 {3 00) PIN 1 088 (1 00) FAX) oni 02} O50 (1 27) PIN 84 TYP TYP TYP 4550 (115 57) BACK VIEW i a E i e o E o a E i o : a E a o o 5 ; C 7 ry y 7 128 (825) sayy 118 (3 00} \ a_ 1661(42 18) __, \ je (8G 88) PIN 168 TD PIN 65 MISRON Technology that works for you. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900, Micron DataFax: 208-368-5800 E-mail: prodmktg@micron.com, Internet: http:/Avww.micron.com, Customer Comment Line: 800-932-4992 16 Meg x 72 Registered SDRAM DIMM 1 7 Micron Technology, Inc, reserves the right to change products or specitications without notice 2M11 p65 Rev 4/98 1998, Micron Technology, Inc