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Introduction
The CONEXANT RP56D, RP336D, and RP144D
Modem Data Pump (MDP) families support data/fax
modem, voice coding/decoding, optional full-duplex
speakerphone, and optional AudioSpan (Table 1). Low
voltage and small size support desktop applications.
Downloadable architecture allows upgrading of MDP code
from the host/DTE.
In V.90/K56flex mode (RP56), the MDP can receive data
at speeds up to 56 kbps from a digitally connected V.90-
or K56flex-compatible central site modem. These MDPs
take advantage of the PSTN which is primarily digital
except for the client modem to central office local loop and
are ideal for applications such as remote access to an
Internet service provider (ISP), on-line service, or
corporate site. The MDP can send upstream data at
speeds up to V.34 rates.
In V.34 data mode (RP56 and RC336), the MDP can
connect at the highest data rate the channel can support
from 33.6 kbps to 2400 bps with auto-fallback to V.32 bis.
In V.32 bis mode, the MDP can connect at the highest
data rate the channel can support from 14.4 kbps to 4800
bps with optional auto-fallback to lower rate modulations.
Internal HDLC support eliminates the need for an external
serial input/output (SIO) device in the DTE for products
incorporating error correction and T.30 protocols.
Voice mode includes an Adaptive Differential Pulse Code
Modulation (ADPCM) voice coder and decoder (codec).
The codec compresses and decompresses voice signals
for efficient digital storage of voice messages. The codec
operates at 28.8k, 21.6k, or 14.4k bps (4-bit, 3-bit, or 2-bit
quantization, respectively) with a 7.2 kHz or 8.0 kHz
sample rate.
A voice pass-through mode allows the host to transmit
and receive uncompressed voice samples in 16-bit linear
form at 7.2 kHz, 8.0 kHz, or 11.025 kHz sample rate, or in
8-bit A-Law/µ-Law PCM form at 8.0 kHz sample rate.
SP models support position-independent full-duplex
speakerphone (FDSP) operation using a dual internal
integrated analog circuit to interface with the telephone
line and the audio input/out (i.e., a headset, handset, or a
microphone with external speaker).
SP models also support AudioSpan (analog simultaneous
audio/voice and data) operation at a data rate of 4.8 kbps.
The MDP operates over the public switched telephone
network (PSTN) through the appropriate line termination.
Features
• Downloadable MDP code from the host/DTE
• 2-wire full-duplex
− V.90 and K56flex (RP56 models)
− V.34 (33.6 kbps) (RP56 and RP336 models)
− V.32 bis, V.32, V.22 bis, V.22, V.23, and V.21
− Bell 212 and 103
• 2-wire half-duplex
− V.34 fax, V.17, V.33, V.29, V.27 ter, and V.21 ch 2
− Bell 208
− Short train option in V.17 and V.27 ter
• Serial synchronous and asynchronous data
• Parallel synchronous and asynchronous data
• Parallel synchronous SDLC/HDLC support
• In-band secondary channel (V.34 and V.32 bis)
• Automatic mode selection (AMS)
• Automatic rate adaption (ARA)
• Digital near-end and far-end echo cancellation
• Bulk delay for satellite transmission
• ADPCM voice mode (7.2 kHz or 8.0 kHz)
• Voice pass-through mode (7.2 kHz, 8.0 kHz, or 11.025 kHz)
• Full-duplex speakerphone (SP models)
− Acoustic and line echo cancellation
− Programmable microphone AGC
− Microphone volume selection and muting
− Speaker volume control and muting; room monitor
• AudioSpan (SP models)
− ITU-T V.61 modulation (4.8 kbps data plus audio)
− Handset, headset, or half-duplex speakerphone
• TTL and CMOS compatible DTE interface
− ITU-T V.24 (EIA/TIA-232-E) (data/control)
− Microprocessor bus (data/configuration/control)
• Dynamic range: -9 dBm to -43 dBm
• Adjustable speaker output to monitor received signal
• DMA support interrupt lines
• Transmit and receive (16+128)-byte FIFO data buffers
• NRZI encoding/decoding
• 511 pattern generation/detection
• V.8 and V.8 bis signaling
• V.13 signaling
• Diagnostic capability
− V.54 inter-DCE signaling
− V.54 local analog and remote digital loopback
• +3.3V operation with +5V tolerant inputs
− +5V analog operation
• Power consumption:
− Normal Mode = 280 mW; Sleep Mode = 53 mW
• Low profile, small footprint package
− 100-pin PQFP
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Information provided by CONEXANT SYSTEMS, INC. ( CONEXANT) is believed to be accurate and reliable. However, no responsibility is assumed by CONEXANT
for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent rights of CONEXANT other than for circuitry embodied in CONEXANT products. CONEXANT reserves the right to change circuitry at any time without notice.
This document is subject to change without notice.
K56flex is a trademark of CONEXANT SYSTEMS, INC. and Lucent Technologies.
CONEXANT and “What's Next in Communications Technologies” are trademarks of CONEXANT SYSTEMS, INC.
©1998, CONEXANT SYSTEMS, INC.
Printed in U.S.A.
All Rights Reserv ed
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Technical Description
The MDP functional interface is illustrated in Figure 1.
Configurations and Rates
The selectable MDP configurations, signaling rates, and
data rates are listed in Table 2.
MD218F1 FID
RS0-RS4
TELEPHONE LINE/
TELEPHONE/
AUDIO INTERFACE
INTERFACE
TELEPHONE
LINE
~RLYA
~RLYB
RINGD
RIN
TXA1
TXA2
MICM
SPK
SPKMD
MICV/NC*
TELIN/NC*
TELOUT/NC*
RXA
TXA
VCC (+3.3V)
AGND
DGND
POWER
SUPPLY
HOST
PROCESSOR DECODER ~CS
~READ
~WRITE
DATA BUS (8) D0-D7
ADDRESS BUS (5) A0-A4
~RESET
IRQ
MIC/
SPEAKER
SPKR
MIC
TELEPHONE
LINE
TELOUT
TELIN
V.24
SERIAL
DTE
INTERFACE
~RDCLK
TDCLK
XTCLK
TXD
RXD
~RTS
~CTS
~DTR
~DSR
~RLSD
~RI
MODEM DATA PUMP
(MDP)
R6764:100-PIN PQFP]
VGG (+5V )
CLOCK
CIRCUIT
CLKIN
VAA (+5V)
* PINS ARE INTERNAL NO CONNECT (NC) ON NON-SP MODELS.
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V.90/K5 6flex PCM* PCM – 56000R/V.34ratesT4 8000 Dynamic – –
V.34 33600 TCM** TCM Note 2 33600 Note 2 Note 2 Note 2 Note 2
V.34 31200 TCM** TCM Note 2 31200 Note 2 Note 2 Note 2 Note 2
V.34 28800 TCM** TCM Note 2 28800 Note 2 Note 2 Note 2 Note 2
V.34 26400 TCM** TCM Note 2 26400 Note 2 Note 2 Note 2 Note 2
V.34 24000 TCM** TCM Note 2 24000 Note 2 Note 2 Note 2 Note 2
V.34 21600 TCM** TCM Note 2 21600 Note 2 Note 2 Note 2 Note 2
V.34 19200 TCM** TCM Note 2 19200 Note 2 Note 2 Note 2 Note 2
V.34 16800 TCM** TCM Note 2 16800 Note 2 Note 2 Note 2 Note 2
V.34 14400 TCM** TCM Note 2 14400 Note 2 Note 2 Note 2 Note 2
V.34 12000 TCM** TCM Note 2 12000 Note 2 Note 2 Note 2 Note 2
V.34 9600 TCM** TCM Note 2 9600 Note 2 Note 2 Note 2 Note 2
V.34 7200 TCM** TCM Note 2 7200 Note 2 Note 2 Note 2 Note 2
V.34 4800 TCM** TCM Note 2 4800 Note 2 Note 2 Note 2 Note 2
V.34 2400 TCM** TCM Note 2 2400 Note 2 Note 2 Note 2 Note 2
V.32 bis 14400 TCM TCM 1800 14400 2400 6 1 128
V.32 bis 12000 TCM TCM 1800 12000 2400 5 1 64
V.32 bis 9600 TCM TCM 1800 9600 2400 4 1 32
V.32 bis 7200 TCM TCM 1800 7200 2400 3 1 16
V.32 bis 4800 QAM 1800 4800 2400 2 0 4
V.32 9600 TCM TCM 1800 9600 2400 4 1 32
V.32 9600 QAM 1800 9600 2400 4 0 16
V.32 4800 QAM 1800 4800 2400 2 0 4
V.22 bis 2400 QAM 1200/2400 2400 600 4 0 16
V.22 bis 1200 DPSK 1200/2400 1200 600 2 0 4
V.22 1200 DPSK 1200/2400 1200 600 2 0 4
V.22 600 DPSK 1200/2400 600 600 1 0 4
V.23 1200/75 FSK 1700/420 1200/75 1200 1 0 –
V.21 FSK 1080/1750 0–300 300 1 0 –
Bell 208 4800 DPSK 1800 4800 1600 3 0 8
Bell 212A DPSK 1200/2400 1200 600 2 0 4
Bell 103 FSK 1170/2125 0–300 300 1 0 –
V.23 1200/75 FSK 1700/420 1200/75 1200 1 0 –
V.21 FSK 1080/1750 0–300 300 1 0 –
V.17 14400 TCM/V.333 TCM 1800 14400 2400 6 1 128
V.17 12000 TCM/V.333 TCM 1800 12000 2400 5 1 64
V.17 9600 TCM3 TCM 1800 9600 2400 4 1 32
V.17 7200 TCM3 TCM 1800 7200 2400 3 1 16
V.29 96003 QAM 1700 9600 2400 4 0 16
V.29 72003 QAM 1700 7200 2400 3 0 8
V.29 48003 QAM 1700 4800 2400 2 0 4
V.27 48003 DPSK 1800 4800 1600 3 0 8
V.27 24003 DPSK 1800 2400 1200 2 0 4
V.21 Channel 23 FSK 1750 300 300 1 0 –
Tone Transmit – – – – – – –
Notes:
1. Modulation legend: TCM: Trellis-Coded Modulation QAM: Quadrature Amplitude Modulation
FSK: Frequency Shift Keying DPSK: Differential Phase Shift Keying
2. Adaptive; established during handshake:
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3. Models with fax support only.
4. Maximum data rate.
* RP56 models only.
** RP56 and RP336 models only.
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Automatic Mode Selection
When automatic mode selection (AMS) is enabled, the
MDP configures itself to the highest compatible data rate
supported by the remote modem (AUTO bit). Automode
operation is supported in V.90, K56flex, V.34, V.32 bis,
V.32 V.22 bis, V.22, V.21, V.23, Bell 212A, and Bell 103
modes.
Automatic Rate Adaption (ARA)
In V.90, K56flex, V.34, and V.32 bis modes, automatic
rate adaption (ARA) can be enabled to select the highest
data rate possible based on the measured eye quality
monitor (EQM) (EARC bit). This selection occurs during
handshake/retrain and rate renegotiation.
Tone Generation
The MDP can generate single or dual voice-band tones
from 0 Hz to 3600 Hz with a resolution of 0.15 Hz and an
accuracy of ± 0.01%. Tones over 3000 Hz are attenuated.
DTMF tone generation allows the MDP to operate as a
programmable DTMF dialer.
Data Encoding
The data encoding conforms to ITU-T recommendations
V.90, V.34, V.32 bis, V.32, V.17, V.33, V.29, V.27 ter,
V.22 bis, V.22, V.23, or V.21, and is compatible with Bell
208, 212A, or 103, depending on the model and selected
configuration.
RTS - CTS Response Time
The response times of CTS relative to a corresponding
transition of RTS are listed in Table 3.
Transmit Level
The transmitter output level is selectable from 0 dBm to
-15 dBm (VAA = +5V) in 1 dB steps and is accurate to
±0.5 dB when used with an external hybrid. The output
level can also be fine tuned by changing a gain constant
in MDP DSP RAM. The maximum V.34/V.32 bis/V.32
transmit level for acceptable receive performance should
not exceed -9 dBm.
Note: In V.34 mode, the transmit level may be
automatically changed during the handshake. This
automatic adjustment of the transmit level may be
disabled via a parameter in DSP RAM.
Transmitter Timing
Transmitter timing is selectable between internal
(±0.01%), external, or slave.
Scrambler/Descrambler
A self-synchronizing scrambler/descrambler is used in
accordance with the selected configuration.
Answer Tone
When the NV25 bit is a zero, the MDP generates a 2100
Hz answer tone at the beginning of the answer handshake
for 5.0 seconds (V.8) or 3.6 seconds (V.32 bis, V.32, V.22
bis, V.22, V.23, and V.21). The answer tone has 180°
phase reversals every 0.45 second to disable network
echo cancellers (V.8, V.32 bis, V.32).
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RTS-CTS Resp o n se 1
Configuration Constant
Carrier Controlled
Carrier Turn-Off
Sequence3
V.90, K 56flex, V .34,
V.32 bis , V.32 ± 2 ms N/A N/A
V.33/V.17 Long N/A 1393 ms215 ms 4
V.33/V .17 Short N/ A 142 ms215 ms 4
V.29 N/A 253 ms212 ms
V.27 4800 Long N/A 708 ms27 ms4
V.27 4800 Short N/A 50 ms27 m s4
V.27 2400 Long N/A 943 ms210 ms4
V.27 2400 Short N/A 67 ms210 m s4
V.22 bis , V.22,
Bell 212A ± 2 ms 270 ms N/A
V.21 500 ms 500 ms N/A
V.23, B e l l 103 210 ms 210 ms N/ A
Notes:
1. Times listed are CTS turn-on. The CTS OFF-to-ON
response t i m e i s host program m abl e i n DSP RAM. (Full-
duplex modes onl y.)
2. Add echo protector tone duration plus 20 m s when echo
protector tone is us ed duri ng turn-on.
3. Turn-off sequence consi sts of transmi ssion of rem ai ni ng
data and sc ram bl ed ones for cont rol l ed carrier operation.
CTS turn-off is less than 2 ms for all configurati ons.
4. Plus 20 m s of no trans m i tted energy.
5. N/A = not appl i cable.
Receive Level
The MDP satisfies performance requirements for received
line signal levels from –9 dBm to –43 dBm measured at
the Receiver Analog (RXA) (TIP and RING) input (-15
dBm at RIN).
Note: A 6 dB pad is required between TIP and RING and
the RIN input.
Receiver Timing
The timing recovery circuit can track a frequency error in
the associated transmit timing source of ±0.035% (V.22
bis) or ±0.01% (other configurations).
Carrier Recovery
The carrier recovery circuit can track a ±7 Hz frequency
offset in the received carrier.
Clamping
Received Data (RXD) is clamped to a constant mark
whenever the Received Line Signal Detector (~RLSD) is
off. ~RLSD can be clamped off (RLSDE bit).
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Echo Canceller
A data echo canceller with near-end and far-end echo
cancellation is included for 2-wire full-duplex
V.34/V.32 bis/V.32 operation. The combined echo span of
near and far cancellers can be up to 40 ms. The
proportion allotted to each end is automatically
determined by the MDP. The delay between near-end and
far-end echoes can be up to 1.2 seconds.
V.90 and K56flex echo cancellation is also provided.
ADPCM Voice Mode
The Adaptive Differential Pulse Code Modulation
(ADPCM) voice coder and decoder (codec) compresses
and decompresses voice signals for efficient digital
storage of voice messages. The codec operates at 28.8k,
21.6k, or 14.4k bps (4-bit, 3-bit, or 2-bit quantization,
respectively) with a 7.2 kHz or 8.0 kHz sample rate.
Transmit Voice. 16-bit compressed transmit voice can be
sent to the MDP ADPCM codec for decompression then to
the digital-to-analog converter (DAC) by the host.
Receive Voice. 16-bit received voice samples from the
MDP analog-to-digital converter (ADC) can be sent to the
ADPCM codec for compression, and then be read by the
host.
Voice Pass-Through Mode
Voice pass-through mode allows the host to transmit and
receive uncompressed voice samples in 16-bit linear form
at 7.2 kHz, 8.0 kHz, or 11.025 kHz sample rate, or in 8-bit
A-Law/µ-Law PCM form at 8.0 kHz sample rate.
Transmit Voice. Transmit voice samples can be sent to
the MDP DAC from the host.
Receive Voice. Received voice samples from the MDP
ADC can be read by the host.
Speakerphone Voice/Audio Paths (SP Models)
The MDP incorporates a dual integrated analog interface.
The voice/audio transmit and receive signals can be
routed through several paths. The voice/audio paths are
available in the speakerphone mode configuration and are
selected through DSP RAM.
The voice/audio input can be taken from one of four
different sources: telephone line input (RIN), handset
(TELIN), microphone (MICM or MICV).
The speaker output (SPK) can originate from one of five
different sources: RIN, TELIN, MICM or MICV or from the
MDP’s internal voice playback mode.
The voice/audio output may be routed to the telephone
line output (TXA1 and TXA2) or handset (TELOUT).
The voice paths can be switched to allow an audio input
to be routed to the telephone line output through a
variable gain for applications such as music-on-hold.
The “room monitor” mode allows the MDP to receive
audio from its surroundings and concurrently transmit the
audio to a remote site.
AudioSpan Mode (SP Models)
AudioSpan provides full-duplex analog simultaneous
audio/voice and data over a single telephone line at a
data rate with audio of 4800 bps using V.61 modulation.
AudioSpan can send any type of audio waveform,
including music. Data can be sent with or without error
correction. The audio/voice interface can be in the form of
a headset, handset, or a microphone and speaker (half-
duplex speakerphone). Handset echo cancellation is
provided.
Data Formats
Serial Synchronous Data
Data rate: 300-56000 bps (RP56), 300-33600 bps
(RP56 and RP336), or 300-14400 bps,
±0.01%.
Selectable clock: Internal, external, or slave.
Serial Asynchronous Data
Data rate: 300-56000 bps (RP56), 300-33600 bps
(RP56 and RP336), or 300-14400 bps,
+1% (or +2.3%), -2.5%;
0-300 bps (V.21 and Bell 103);
1200/75 bps (V.23).
Bits per character: 7, 8, 9, 10, or 11.
Parallel Synchronous Data
Normal sync: 8-bit data for transmit and receive
Data rate: 300-56000 bps (RP56), 300-33600 bps
(RP56 and RP336), or 300-14400 bps,
±0.01%.
SDLC/HDLC support:
Transmitter: Flag generation, 0 bit stuffing,
CRC-16 or CRC-32 generation.
Receiver: Flag detection, 0 bit deletion,
CRC-16 or CRC-32 check ing.
Parallel Asynchronous Data
Data rate: 300-56000 bps (RP56), 300-33600 bps
(RP56 and RP336), or 300-14400 bps,
+1% (or 2.3%), -2.5%;
1200, 300, or 75 bps (FSK).
Data bits per character: 5, 6, 7, or 8.
Parity generation/checking: Odd, even, or 9th data bit.
Async/Sync and Sync/Async Conversion
An asynchronous-to-synchronous converter is provided in
the transmitter and a synchronous-to-asynchronous
converter is provided in the receiver. The converters
operate in both serial and parallel modes. The
asynchronous character format is 1 start bit, 5 to 8 data
bits, an optional parity bit, and 1 or 2 stop bits. Valid
character size, including all bits, is 7, 8, 9, 10, or 11 bits
per character. Two ranges of signaling rates are provided:
• Basic range: +1% to –2.5%
• Extended overspeed range: +2.3% to –2.5%
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When the transmitter's converter is operating at the basic
signaling rate, no more than one stop bit will be deleted
per 8 consecutive characters. When operating at the
extended rate, no more than one stop bit will be deleted
per 4 consecutive characters. Break handling is
performed as described in V.14.
Asynchronous characters are accepted on the TXD serial
input and are issued on the RXD serial output.
V.54 Inter-DCE Signaling
The MDP supports V.54 inter-DCE signaling procedures
in synchronous and asynchronous configurations.
Transmission and detection of the preparatory,
acknowledgment, and termination phases as defined in
V.54 are provided. Three control bits in the transmitter
allow the host to send the appropriate bit patterns (V54T,
V54A, and V54P bits). Three control bits in the receiver
are used to enable one of three bit pattern detectors
(V54TE, V54AE, and V54PE bits). A status bit indicates
when the selected pattern detector has found the
corresponding bit pattern (V54DT bit).
V.13 Remote RTS Signaling
The MDP supports V.13 remote RTS signaling.
Transmission and detection of signaling bit patterns in
response to a change of state in the RTS bit or the ~RTS
input signal are provided. The RRTSE bit enables V.13
signaling. The RTSDE bit enables detection of V.13
patterns. The RTSDT status bit indicates the state of the
remote RTS signal. This feature may be used to
clamp/unclamp the local ~RLSD and RXD signals in
response to a change in the remote RTS signal in order to
simulate controlled carrier operation in a constant carrier
environment. The MDP automatically clamps and
unclamps ~RLSD.
Dialing and Answering
The host can dial and answer using supported
DTMF/pulse dialing and tone detection functions. The
major parameters are host programmable.
Supervisory Tone Detection
Three parallel tone detectors (A, B, and C) are provided
for supervisory tone detection. The signal path to these
detectors is separate from the main received signal path.
Each tone detector consists of two cascaded second
order IIR biquad filters. The coefficients are host
programmable. Each fourth order filter is followed by a
level detector which has host programmable turn-on and
turn-off thresholds allowing hysteresis. Tone detector C is
preceded by a prefilter and squarer. This circuit is useful
for detecting a tone with frequency equal to the difference
between two tones that may be simultaneously present on
the line. The squarer may be disabled by the SQDIS bit
causing tone detector C to be an eighth order filter. The
tone detectors are disabled in data mode.
The tone detection sample rate is 9600 Hz in V.8 and
V.34 modes and is 7200 Hz in non-V.34 modes. The
default call progress filter coefficients are based on a
7200 Hz sampling rate and apply to non-V.34 modes only.
The maximum detection bandwidth is equal to one-half
the sample rate.
The default bandwidths and thresholds of the tone
detectors are:
Tone Detector Bandwidth Turn-On
Threshold Turn-Off
Threshold
A 245 – 650 Hz –25 dBm –31 dBm
B 360 – 440 Hz –25 dBm –31 dBm
C Prefilter 0 – 500 Hz N/ A N/A
C 50 – 110 Hz * *
* Tone Detector C will detect a difference tone within its
bandwidth when the t wo tones present are i n the range –1 dBm
to –26 dBm.
511 Pattern Generation/Detection
In synchronous mode, a 511 pattern can be generated
and detected (control bit S511). Use of this bit pattern
during self-test eliminates the need for external test
equipment.
In-Band Secondary Channel
A full-duplex in-band secondary channel is provided in
V.34 (all speeds) and V.32 bis/V.32 (7200 bps and above)
modes. Control bit SECEN enables and disables the
secondary channel operation. The secondary channel
operates in parallel data mode with independent transmit
and receive interrupts and data buffers. The main channel
may operate in parallel or serial mode.
In V.34 modes, the secondary channel rate is 200 bps.
In V.32 bis/V.32 modes, the secondary channel rate is
150 bps. This rate is also host programmable in V.32
bis/V.32 modes.
Transmit and Receive FIFO Data Buffers
Two (16+128)-byte first-in first-out (FIFO) data buffers
allow the DTE/host to rapidly output up to 144 bytes of
transmit data and input up to 144 bytes of accumulated
received data. The receiver FIFO is always enabled. The
transmitter FIFO is enabled by the FIFOEN control bit.
TXHF and RXHF bits operate off the lower 16 bits and
indicate the corresponding FIFO buffer half full (8 or more
bytes loaded) status. TXFNF and RXFNE bits indicate the
TXFIFO buffer not full and RXFIFO buffer not empty
status, respectively. An interrupt mask register allows an
interrupt request to be generated whenever the TXFNF,
RXFNE, RXHF, or TXHF status bit changes state. The
128-byte FIFO extensions are enabled by default and can
be disabled by clearing a bit in RAM.
DMA Support Interrupt Request Lines
DMA support is available in synchronous, asynchronous,
and HDLC parallel data modes. Control bit DMAE enables
and disables DMA support. When DMA support is
enabled, the MDP ~RI and ~DSR lines are assigned to
Transmitter Request (TXRQ) and Receiver Request
(RXRQ) hardware output interrupt request lines,
respectively. The TXRQ and RXRQ signals follow the
assertion of the TDBE and RDBF interrupt bits thus
allowing the DTE/host to respond immediately to the
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interrupt request without masking out status bits to
determine the interrupt source.
NRZI Encoding/Decoding
NRZI data encoding/decoding may be selected in
synchronous and HDLC modes instead of the default NRZ
(control bit NRZIEN). In NRZ encoding, a 1 is represented
by a high level and a 0 is represented by a low level. In
NRZI encoding, a 1 is represented by no change in level
and a 0 is represented by a change in level.
ITU-T CRC-32 Support
ITU-T CRC-32 generation/checking may be selected
instead of the default ITU-T CRC-16 in HDLC mode using
DSP RAM access.
Caller ID Demodulation
Caller ID information can be demodulated in V.23 1200
receive configuration and presented to the host/DTE in
serial (RXD) and parallel (RBUFFER) form.
Telephone Line Interface
Line Transformer Interface. V.90/K56flex/V.34/V.32
bis/V.32 places high requirements upon the Data Access
Arrangement (DAA) to the telephone line. Any non-linear
distortion generated by the DAA in the transmit direction
cannot be canceled by the MDP's echo canceller and
interferes with data reception. The designer must,
therefore, ensure that the total harmonic distortion seen at
the RXA input to the MDP be at least 65 dB below the
minimum level of received signal. Due to the wider
bandwidth requirements in V.90, K56flex, and V.34, the
DAA must maintain linearity from 10 Hz to 4000 Hz.
Relay Control. Direct control of the off-hook and talk/data
relays is provided. Internal relay drivers allow direct
connection to the off-hook (RLYA) and talk/data (RLYB)
relays. The talk/data relay output can optionally be used
for pulse dial.
Speaker Interface
An analog speaker output (SPK) is provided with on/off
and volume control logic incorporated in the MDP. An
external amplifier is recommended if driving non-amplified
speakers.
A digital speaker output (SPKMD) is provided which
reflects the received analog input signal digitized to TTL
high or low level by an internal comparator to create a PC
Card (PCMCIA)-compatible signal.
Additional Information
Additional information is provided in the RP56D, RP336D,
and RP144D Modem Designer's Guide (Order No. 1155).
Hardware Interface Signals
A functional interconnect diagram showing the typical
MDP connection in a system is illustrated in Figure 2. Any
point that is active low is represented by a small circle at
the signal point.
Edge triggered inputs are denoted by a small triangle
(e.g., TDCLK). An active low signal is indicated by a tilde
preceding the signal name (e.g., ~RESET).
A clock intended to activate logic on its rising edge (low-
to-high trans ition) is c alled active low (e.g., ~RDCLK),
while a clock intended to activate logic on its falling edge
(high-to-low transition) is called active high (e.g., TDCLK).
When a clock input is associated with a small circle, the
input activates on a falling edge. If no circle is shown, the
input activates on a rising edge.
The 100-pin PQFP MDP hardware interface signals are
shown Figure 2.
The 100-pin PQFP MDP signal pin assignments are
shown Figure 3 and are listed in Table 4.
The MDP hardware interface signals are described in
Table 5.
The digital interface characteristics are defined in Table 6.
The analog interface characteristics are defined Table 7.
The power requirements are defined in Table 8.
The absolute maximum ratings are defined in Table 9.
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75
76
88
89
90
91
92
93
94
95
96
97
2
3
4
5
6
7
80
9
36
17
47
79
35
30
31
26
27
34
37
29
38
~RLYA
RINGD
RIN
TXA1
TXA2
TELIN/NC*
TELOUT/NC*
MICV/NC*
MICM
SPK
SPKMD
NOTES:
1. TOLERANCES AND RATINGS (UNLESS OTHERWISE
SPECIFIED):
RESISTOR VALUES IN OHMS; 5%, 1/8W
CAPACITOR VALUES IN MICROFARADS; 10%, 20V
2. DENOTES ANALOG GROUND.
3. DENOTES DIGITAL GROUND.
TELEPHONE LINE/
TELEPHONE/
AUDIO
INTERFACE
AGND
AGND
AGND
YCLK
XCLK
D0
D1
D2
D3
D4
D5
D6
D7
RS0
RS1
RS2
RS3
RS4
~CS
~WRITE
~READ
IRQ
~WKRES
~RES2
~RES1
MCU: ~WKRESOUT
MCU
EXTERNAL
BUS
MCU: IRQ
MCLKIN
MTXSIN
MRXOUT
MSTROBE
MSCLK
MCNTRLSIN
SR1IO
IA1CLK
SA1CLK
SR4IN
SR4OUT
CLKOUT
SR3OUT
SR3IN
SA2CLK
SR2CLK
SR2IO
VCNTRLSIN/NC*
VSCLK/NC*
VSTROBE/NC*
VRXOUT/NC*
VTXSIN/NC*
VCLKIN/NC*
42
43
45
46
44
41
62
24
23
20
18
22
19
21
59
10
60
55
52
50
51
53
54
SLEEPO
IASLEEP
69
56
10 0.1 CER
VREF 32
10 0.1 CER
VC 33
14
15
1
57
61
66
70
72
73
74
77
83
84
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
AVDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
40
63
68
85
16
65
81
99
49
+3.3V
0.1 10
0.022 10
25
39
48
10µH AVAA
28
GPO0
~RDCLK
TDCLK
XTCLK
TXD
RXD
~RLSD
~RI
82
8
12
64
13
67
11
78
SERIAL
DTE
INTERFACE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PLLVDD
PLLGND
98
100
MD218F4-HIS-100PQFP
+5V
58
71
RESERVED
VGG
MCU: ~RESET
86
87
CLKIN
NC
28.224 MHz CLOCK
NC
* PINS ARE INTERNAL NO CONNECT (NC)
ON NON-SP MODELS.
NC
+5V
PROVIDE DIRECT CONNECTION OR
FERRITE BEAD BETWEEN GND AND AGND,
WHICHEVER ACHIEVES LOWEST NOISE
FLOOR.
0.1
10 +3.3V (VDD)
10
DAA FOR EXTERNAL VC USE
10µH
10µH10µH
FERRITE BEADS (70 OHM @ 100 MHZ TYPE
WITH A MAX DC RESISTANCE OF 0.5 OHM
AND A RATED CURRENT OF 200 mA).
FB
FB
FB
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
PLLGND
GND
PLLVDD
RS1
RS0
D7
D6
D5
D4
D3
D2
D1
D0
NC
CLKIN
VDD
RESERVED
RESERVED
GP00
GND
TXA2
VREF
VC
MICV/NC*
RIN
~RES2
MICM
SPKMD
AGND
AVDD
MCNTRLSIN
MCLKIN
MTXSIN
MSCLK
MRXOUT
MSTROBE
~RLYA
AGND
GND
VSTROBE/NC*
IRQ
RINGD
~RI
RESERVED
XCLK
YCLK
RESERVED
RESERVED
RESERVED
VGG
RESERVED
SLEEPO
VDD
RXD
RESERVED
GND
XTCLK
VDD
SR1IO
RESERVED
SR2IO
SA2CLK
RESERVED
RESERVED
IASLEEP
VCNTRLSIN/NC*
VCLKIN/NC*
VTXSIN/NC*
VSCLK/NC*
VRXOUT/NC*
RESERVED
RS2
RS3
RS4
~CS
~WRITE
~READ
~RDCLK
~WKRES
SR2CLK
~RLSD
TDCLK
TXD
RESERVED
RESERVED
GND
~RES1
SR4OUT
SR3OUT
SR4IN
SR3IN
CLKOUT
SA1CLK
IA1CLK
AGND
TELIN/NC*
TELOUT/NC*
AVAA
SPKR
TXA1
* NC on non-SP models.
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Pin Signal Label I/O Type Interface3Pin Signal Label I/O Type Interface
1 RESERVED NC 51 VRXOUT/NC* DI To SR3IN (21)
2 RS2 IA Host Parallel Interface 52 VSCLK/NC* DI To SR2CLK (10)
3 RS3 IA Host Parallel Interface 53 VTXSIN/NC* DI To SR3OUT (19)
4 RS4 IA Host Parallel Interface 54 VCLKIN/NC* DI To CLKOUT (22)
5 ~CS IA Host Parallel Interface 55 VCNTRLSIN/NC* DI To SR2IO (60)
6 ~WRITE IA Host Parallel Interface 56 IASLEEP DI To SLEEPO (69)
7 ~READ IA Host Parallel In terface 57 RESERVED NC
8 ~RDCLK OA DTE Serial Interface 58 RESERVED NC
9 ~WKRES IA MCU: READY/~WKRESO UT 59 SA2CLK DI To VSTROBE (50)
10 SR2CLK DI To VSCLK (52) 60 SR2IO DI To VCNTRLSIN (55)
11 ~RLSD OA DTE Serial Interface 61 RESERVED NC
12 TDCLK OA DTE Serial Interface 62 SR1IO DI To MCNTRLSIN (41)
13 TXD IA DTE Serial Interface 63 VDD PWR +3.3V
14 RESERVED NC 64 XT CLK IA DTE Serial Interface
15 RESERVED NC 65 GND GND DGND
16 GND GND DGND 66 RESERVED NC
17 ~RES1 PIF: ~RESET
SIF: Reset circuit 67 RXD OA DTE Serial Interface
18 SR4OUT DI To MTXSIN (43) 68 VDD PWR +3.3V
19 SR3OUT DI To VTXSIN (53) 69 SLEEPO DI To IASLEEP (56)
20 SR4IN DI To MRXOUT (45) 70 RESERVED NC
21 SR3IN DI To VRXOUT (51) 71 VGG REF +5V
22 CLKOUT DI To MCLKIN (42) & VCLKIN
(54) 72 RESERVED NC
23 SA1CLK DI To MSTROBE (4 6) 73 RESERVED NC
24 IA1CLK DI To MSCLK (44 ) 74 RESERVED NC
25 AGND GND Analog Ground 75 YCLK OA NC
26 TELIN/NC* I(DA) Line/Audio Interface 76 XCLK OA NC
27 TELOUT /NC* O(DD) Line/Audio Interface 77 RESERVED NC
28 AVAA PWR +5VA 78 ~RI OA DTE Serial In terfa ce
29 SPK O(DF) Line/Audio Interface 79 RINGD IA Line/Audio Interface
30 TXA1 O(DD) Line/Audio Interface 80 IRQ IA Host Parallel Interface
31 TXA2 O(DD) Line/Audio Interface 81 GND GND DGND
32 VREF REF VC through capacitors 8 2 GP00 DI To ~RDCLK (8)
33 VC REF DAA through FB; GND
through capacitors and FB 83 RESERVED NC
34 MICV/NC* I(DA) Line/Audio In terfac e 84 RESERVED NC
35 RIN I(DA) Line/Audio Interface 85 VDD PWR +3.3V
36 ~RES2 PIF: ~RESET
SIF: Reset circuit 86 CLKIN I Clock Circuit
37 MICM I(DA) Line/Audio Interface 87 NC NC
38 SPKMD OA Line/Audio Interface 88 D0 IA/OB Host Parallel In terface
39 AGND GND Analog Ground 89 D1 IA/OB Host Parallel Interface
40 AVDD PWR +3.3V 90 D2 IA/OB Host Par allel Interface
41 MCNTRLSIN DI To SR1IO (62) 91 D3 IA/OB Host Parallel Interface
42 MCLKIN DI To CLKOUT (2 2) 92 D4 IA/OB Host Par allel Interface
43 MTXSIN DI To SR4OUT (18) 93 D5 IA/OB Host Parallel Interface
44 MSCLK DI To IA1CLK (24) 94 D6 IA/OB Host Parallel Interface
45 MRXOUT DI To SR4IN (20) 95 D7 IA/OB Host Parallel Interface
46 MSTROBE DI To SA1CLK (23) 96 RS0 IA Host Parallel Interface
47 ~RLYA OD NC 97 RS1 IA Host Parallel Interface
48 AGND GND AGND 98 PLLVDD PLL To +3.3 (VDD) through 10 Ω
and to DGND through 10 µF.
49 GND GND DGND 99 GND GND DGND
50 VSTROBE/NC* DI To SA2CLK ( 59) 100 PLLGND PLL DGND
Notes:
1. I/O types:
IA, IB = Digital input; OA, OB = Digital output.
I(DA) = Analog input; O(DD), O(DF) = Analog output.
DI = Device interconnect.
2. NC = No external connection allowed (may have internal connection).
3. Interface Legend:
MDP = Modem Data Pump
DTE = Data Terminal Equipment
PIF = Parallel host interfa c e
SIF = Seri al DTE interface.
* NC on non-SP models.
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Label I/O Type Signal/Definition
OVERHEAD SIGNALS
CLKIN I Clock In. Connec t to an external 28.224 MHz clock circuit .
~RES1,
~RES2 IA Reset. ~RESET low holds the MDP in the reset state. ~RESET going high releases the MDP from the reset
state and init iat es normal operation using power turn-on (default) values. ~RESET must be held low for at least
3 µs. The MDP is ready to use 400 ms after the low-to-high transition of ~RESET. ~RES1 and ~RES2 are
typically connected to t he MCU ~RESET input and to the host bus ~RESET (or RESET through an inverter) line
(parallel host) or reset circuit (serial DTE i nterface) whi ch resets both the MCU and MDP upon power turn-on.
~RES1 and ~RES 2 have acti ve internal pull-up resistors.
~WKRES IA Wake-up Reset. ~WKRES is connected internally to ~RESET but will not drive the MDP ~RESET pins.
Asserting ~WKRES performs the same reset function as the MDP ~RESET and typically used by the MCU to
wake up the MDP from SLEEP Mode when the MDP ~RESET lines cannot be ass erted (because they are also
connected to t he MCU ~RESET input). For a s erial DTE or parallel host MCU conf igurat ion, connect ~WKRES to
the MCU ~WKRE S OUT output. ~WK RE S has an act i ve internal pul l -up resist or.
VDD PWR +3.3V Digital Circuit Power Supply. Connect to +3. 3V through digit al circuit power supply filter.
AVDD PWR +3.3V Analog Circuit Digital Power Supply. Connect to +3.3V t hrough di gi tal circuit power s uppl y filter.
AVAA PWR Analog Circuit Analog Power Supply. Connect to +5V through anal og circuit power supply filter.
VGG REF Input Reference Voltage. Reference voltage f or +5V tolerant i nput pins. Connect to +5V .
GND GND Digital Ground. Connect to digital ground.
AGND GND Analog Ground. Connect to analog ground.
XCLK OA X Clock. Out put clock at 56.448 MHz (P LL di sabled) or 63.5045 (P LL enabl ed), whi ch runs during M DP Norm al
Mode and is t urned off during Sl eep M ode.
YCLK OA Y Clock. Out put clock at 28.224 MHz , whi ch runs during M DP Norm al M ode and i s turned off during Sleep
Mode.
SYCLK OA S ystem Clock. Out put cloc k at 28.224 M Hz, which runs during MDP Norm al M ode and duri ng Sleep Mode.
PLLVDD PLL PLLVDD Connection. Connect t o +3.3V (VDD) t hrough 10 Ω and to DGND through 10 (+) µF.
PLLGND PLL PLLGND Connection. Connect t o DGND.
PARALLE L HOST INTERFACE
Address , data, control, and int errupt hardware interface signal s allow MDP connecti on to an 8086-compat i bl e m i croprocessor bus. With the
addition of external logi c, the i nt erface can be m ade compatibl e wi th a wide variety of ot her microprocessors such as t he 6502, 8086 or
68000. The mic roprocessor i nterface all o ws a microprocessor t o change MDP c onfiguration, read or wri te channel and diagnostic dat a, and
supervise MDP operati on by writing control bit s and reading st atus bit s.
D0–D7 IA/OB Data Lines. Eight bi di rectional dat a l i nes (D0–D7) provide parall el transfer of data between the hos t and the
MDP. The most si gni ficant bi t is D7. Dat a di rection is control l ed by the Read Enable and Wri te Enable si gnal s.
RS0–RS4 IA Register S el ect Lines. The fiv e active high register select l i nes (RS0–RS4) addres s interf ace memory regi sters
within the MDP interf ace memory. These lines are typi cally connected t o the fiv e l east signi ficant l i nes (A0–A4)
of the address bus.
The MDP decodes RS0 through RS4 t o address one of 32 internal interface memory regist ers (00–1F). The
most signifi cant address bit is RS4, while t he l east si gni ficant address bit i s RS0. The selected register c an be
read from or written into v i a the 8-bit parallel data bus (D0–D7). The m ost si gni ficant data bit is D7, while t he
least significant data bit is D0.
~CS IA Chip Select. ~CS selec ts the M DP for microprocessor bus operation. ~CS is t ypicall y generated by decoding
host addres s bus lines.
~READ IA Read Enable. During a read cycle (~READ asserted), data from the selected interface memory register is gated
onto the data bus by means of three-st ate drivers i n the MDP. These drivers f orce the data l i nes high for a one
bit, or low for a zero bit . When not being read, the three-st ate drivers assume t hei r hi gh-i m pedance (off) state.
~WRITE IA Write Enable. During a write cycle (~WRITE asserted), data from the data bus is copied into the selected MDP
interface memory regi ster, wi t h hi gh and low bus lev el s representi ng one and zero bit s t ates, respecti vely.
IRQ OA Interrupt Request. The MDP IRQ output may be connected t o the host proc essor int errupt request input i n
order to interrupt host program ex ecution for i m m edi ate MDP service. The IRQ output can be enabl ed i n the
MDP interf ace memory t o i ndi cate imm edi at e change of condi tions. The use of IRQ is optional dependi ng upon
MDP applic ation. The IRQ out put i s driven by a TTL-compatibl e CM OS dri ver.
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Label I/O Type Signal Name/Description
DTE SERIAL I NT ERFACE
Timing, dat a, control, and stat us signals provide a V.24-compat ibl e serial int erf ace. These signals are TTL compatible i n order to drive the
short wire l engths and ci rcuits norm al l y found within a printed ci rcuit board, stand-alone modem enclosures , or equipment cabinets . For
driving longer cables, these si gnal s can be easi l y converted to EI A /RS-232-D voltage levels.
TXD IA Transmi tted Data. The MDP obtai ns serial dat a to be transmi tted from the local DTE on the Transmit ted Data
(TXD) input.
RXD OA Received Data. The MDP presents received s eri al data to the local DTE on the Received Dat a (RX D) output.
~RTS IA Request to Send. Activating ~RTS causes the MDP to transmit data on TXD when ~CTS becomes active. The
~RTS pin is l ogi cally ORed with the RTS bit .
~CTS OA Clear To Send. ~CTS active indicates to the local DTE that the MDP will transmit any data present on TXD.
CTS response times from an acti ve condit i on of RTS are shown in Table 3.
~RLSD OA Received Line Signal Detector. ~RLSD act i ve indic at es to the l ocal DTE that energy above t he receive level
threshold i s present on t he receiver input, and that t he energy is not a training sequence.
One of four ~RLSD receive level thres hol d opt i ons can be sel ected (RTH bit s). A mi ni m um hyst eresis ac tion of
2 dB exis ts between t he actual of f -to-on and on-to-off transiti on l evels. The t hreshold level and hysteresis ac tion
are measured wit h a m odul ated signal appl i ed to the Recei ver Analog (RXA) input. Note that perf orm ance may
be degraded when the received signal l evel is l ess than -43 dB m . The ~RLSD on and off t hresholds are hos t
programmable in DSP RAM.
~DTR IA Data Term inal Ready. I n V.8, V.90, K56f l ex, V. 34, V.32 bis, V. 32, V.22 bis, V.22, or B ell 212A configuration,
activ ating ~DTR initi ates the handshake sequenc e. The DATA bit must be s et to compl ete the handshak e.
In V.21, V.23, or B el l 103 configurati on, activating ~DTR c auses the M DP t o enter the data s tate provi ded t hat
the DATA bi t i s a 1. If i n answer mode, t he M DP i m m edi ately s ends answer tone. I n these modes , if c ont rol l ed
carrier is enabl ed, carrier is control l ed by RTS.
During the data m ode, deactiv at i ng ~DTR causes t he transmitter and receiver to turn of f and return to t he i dl e
state.
The ~DTR input and the DTR c ontrol bit are logi cally ORed.
~DSR OA Data Set Ready. ~DSR ON indicates that the MDP i s i n the data trans f er state. ~DS R OFF i ndi cates t hat the
DTE is t o di sregard all si gnal s appearing on the interchange ci rcuits except Ri ng Indicator (~RI). ~DSR is OFF
when the MDP is in a tes t mode (i.e. , local anal og or rem ote digital l oopback).
The DSR status bit ref l ects the stat e of the ~DSR output.
~RI OA Ring Indicator. ~RI output foll ows the ringing signal present on the line wi th a low level (0 V) during the ON
time, and a hi gh l evel during the OFF t i me coinci dent with the ri ngi ng signal. The RI status bit refl ects t he state
of the ~RI output.
TDCLK OA Transmit Data Clock. The M DP outputs a s ynchronous Transmit Dat a Cl ock (TDCLK) f or USRT timing. The
TDCLK frequency is the data rate (±0.01%) with a duty cycle of 50±1%. The TDCLK source can be internal,
external (i nput on XTCLK), or slave (t o ~RDCLK) as sel ected by TXCLK bits in interface memory.
XTCLK IA External Transmi t Cl ock. In s ynchronous communic ation, an external trans m i t data clock can be connected to
the MDP XT CLK input. The clock supplied at X TCLK must exhibit t he same charac t eri stic s as TDCLK. The
XTCLK input is then reflect ed at the TDCLK output .
~RDCLK OA Receive Data Clock. The MDP outputs a sy nchronous Recei ve Data Clock (~RDCLK) f or USRT tim i ng. The
~RDCLK frequency is t he data rate (±0.01% ) wi th a duty cycle of 50±1%. The ~RDCLK low-to-high t ransitions
coinci de wi th the cent er of the recei ved data bits.
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Label I/O Type Signal Name/Description
TELEPHONE LI NE /TELE PHONE/AUDI O INTERFACE SIGNALS AND REFERENCE VOL T AGE
TXA1, TXA2 O(DF) Transmit Analog 1 and 2 Output. The TXA1 and TXA2 out put s are differential output s 180 degrees out of
phase with each other. E ach output c an dri ve a 300 Ω load. Typically, TXA1 and TXA2 are connected to the
telephone line i nterface or an opt i onal external hy bri d circuit.
RIN I(DA) Receive Analog I nput. RIN is a single-ended input with 70K Ω i nput impedance. Typicall y, RIN i s connect ed to
telephone line i nterface or an opt i onal external hy bri d circuit.
NOTE: If not used, do not tie directly to ground; this input has a bias voltage of +2.5V (VAA = +5V).
RINGD IA Ring Detect. The RINGD input is monitored for pul ses in t he range of 15 Hz to 68 Hz . The frequency detect i on
range may be changed by the host in DSP RAM. The circuit dri ving RINGD s houl d be a 4N35 optoisolator or
equivalent . The circui t dri ving RINGD s houl d not respond to m om entary burst s of ringing l ess than 125 m s in
duration, or less than 40 VRMS (15 Hz to 68 Hz) across TIP and RING. Detec ted ring signal s are reflec t ed on
the ~RI output signal as well as the RI bit.
~RLYA
(~OHRC,
~CALLID)
OD Relay A Control . The ~RLYA open drain output can direct l y drive a reed relay coil wi th a minimum resist ance of
360 ohms (9.2 m A m ax. @ +3.3V ). A clam p di ode, such as a 1N4148, should be i nstalled across t he rel ay coil.
An external transis tor can be used t o dri ve heavier l oads (e.g., el ectro-mec hani cal relays). ~RLYA i s control l ed
by host setting/resetting of the RA bit.
In a typi cal applic ation, ~RLYA is c onnected to t he norm al l y open Off-Hook rel ay (~OHRC). In t hi s case, ~RLYA
active clos es the relay to connect the MDP to the telephone line.
Alternat i vely, i n a typic al appl i cation, ~RLYA is connected to the normall y open Caller ID relay (~CALLID). When
the MDP detec ts a Calling Number Delivery (CND) message, t he ~RLY A output is asserted to close the Caller ID
relay in order t o AC couple t he CND i nformation t o t he MDP RIN input (without closing the off-hook relay and
allowing loop c urrent flow which would indic ate an off-hook condition).
~RLYB
(~TALK) OD Relay B Co n tro l. The ~RLYB open drai n output can directly dri ve a reed relay c oi l wi th a minimum resist ance of
360 ohms (9.2 m A max. @ 3. 3V ). A clamp diode, such as a 1N4148, should be inst al l ed across the relay c oi l . An
external t ransist or can be used to dri ve heavier loads (e.g., el ectro-mec hani cal relays). ~RLYB i s control l ed by
host s et ting/res etting of the RB bit.
In a typi cal applic at i on, ~RLYB is connect ed to the normally clos ed Tal k/Data relay (~TALK). In this c ase,
~RLYB active opens t he rel ay to dis connect t he handset from the telephone li ne.
MICM I(DA) Modem Microphone Input. MICM i s a single-ended m i crophone input. The i nput impedance i s > 70k Ω.
NOTE: If not used, do not tie directly to ground; this input has a bias voltage of +2.5V (VAA = +5V).
SPK O(DF) Speaker Analog Output. The SPK analog out put can originate from one of f ive different s ourc es: RIN, TELIN,
MICM or MICV or from the MDP’s internal voice playback mode. The SPK on/off and three levels of attenuation
are controlled by bits in DSP RAM. When the speaker is turned off, the SPK output is c lamped to the v oltage at
the VC pin. The SPK output can driv e an impedance as low as 300 ohms. In a typical applic at ion, the SPK
output is an i nput to an ext ernal LM386 audio power amplif i er.
SPKMD OA Modem Speaker Digital Output. The SPKMD digital output reflects the received analog input signal digitized to
TTL high or low level by an internal comparator t o create a PC Card (P CM CI A)-compat i bl e signal.
VREF REF High Voltage Reference. Connect to V C t hrough 10 µF (pol ari zed, + termi nal to VREF) and 0. 1 µF (ceramic) i n
parallel.
VC REF Low Voltage Reference. Connect to a ferrite bead and connect the other end of the f erri te bead to DGND
through 10 µF (polariz ed, + terminal t o V C) and 0. 1 µF (ceramic ) i n paral l el .
MICV/NC* I(DA) Voice Microphone Input. MICV is a single-ended microphone input. Typicall y, MICV is c onnected to a
microphone out put for recording v oi ce e.g., i n a speakerphone application.
NOTE: If not used, do not tie directly to ground; this input has a bias voltage of +2.5V (VAA = +5V).
TELIN/NC* I(DA) Telephone Analog Input. TELIN is a single-ended i nput with 70K Ω i nput i m pedance. Typically, TE LIN is
connect ed t o a telephone handset m i crophone circ ui t.
NOTE: If not used, do not tie directly to ground; this input has a bias voltage of +2.5V (VAA = +5V).
TELOUT/NC* O(DF) Telephone Analog Output. TELOUT is a single-ended out put that can drive a 300 Ω load. Typically, TE LOUT is
connect ed t o a telephone handset speaker ci rcuit.
MICBIAS REF Microphone Bias. Microphone bias reference voltage.
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Label I/O Type Signal Name/ Descri ption
MISCELLANEOUS
RESERVED Reserved Function. May be connec t ed t o int ernal c i rc uit . Leave open.
MDP INT ERCONNECT
GP00 DI T o ~RDCLK.
SLEEPO DI To IASLEEP.
IASLEEP DI To SLEEPO.
MSCLK DI To I A1CLK.
CLKOUT DI To MCLKIN & VCLKIN.
SR1IO DI To MCNTRLSIN.
SR3IN DI To VRXOUT.
IA1CLK DI T o M SCLK.
SA1CLK DI To MSTROBE.
SR4OUT DI To MTX S IN.
MCLKIN DI T o CLKOUT.
VCLKIN/NC* DI T o CLK O UT .
MSTROBE DI To SA1CLK.
VSTROBE/NC* DI To SA2CLK.
MCNTRLSIN DI To S R1IO.
VSCLK/NC* DI To SR2CLK.
VCNTRLSI N/NC* DI T o SR2IO.
MRXOUT DI To SR4IN.
VTXS IN/NC* DI T o SR3OUT.
VRXOUT/NC* DI To SR3IN.
MTXSIN DI To SR4OUT.
SR2IO DI To VCNTRLSIN.
SR4IN DI To MRXOUT.
SR2CLK DI To VSCLK.
SA2CLK DI To VSTROBE.
SR3OUT DI To VTXSIN.
* NC on non-SP models. External int erconnects as described can made for the NC pins on non-SP models in cas e S P models are ever
subst i t uted in the appli cation desi gn and SP support i s required.
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Parameter Symbol Min. Typ. Max. Units Test Conditions1
Input High Voltage VIH Vdc
Type IA 2.0 – VCC
Input High Current IIH – – 40 µA
Input Low Voltage VIL 0.3 0.8 VDC
Input Low Current IIL – – 40 µA
Input Leakage Current IIN – – ±100 µADC VIN = 0 to +3.3V, VCC = 3.6V
Output High V ol tage VOH ––VDC
Type OA 2.4 – VCC ILOAD = – 100 µA
Type OD ILOAD = 0 mA
Output Low Vol tage VOL VDC
Type OA – – 0.4 ILOAD = 1.6 mA
Type OD – – 0.75 ILOAD = 15 mA
Three-State (Of f) Current ITSI ±10 µADC VIN = 0.4 to VCC-1
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Signal Nam e Type Characteristic Value
RIN, TELIN, I (DA) Input Impedance > 70K Ω
MICM, M ICV AC Input V oltage Range 1.1 VP-P
Reference Voltage +2.5 VDC (VAA = +5V)
TXA1, TX A 2, O (DD) Minimum Load 300 Ω
TELOUT Maximum Capacitiv e Load 0 µF
Output Im pedance 10 Ω
AC Output Voltage Range 2.2 VP-P (VAA = +5V)
(with referenc e to ground and a 600 Ω load)
Reference Voltage +2.5 VDC (VAA = +5V)
DC Offset Voltage ± 200 mV
SPK O (DF) Mini m um Load 300 Ω
Maximum Capaciti ve Load 0.01 µF
Output Im pedance 10 Ω
AC Output Voltage Range 2.2 VP-P (VAA = +5V)
Reference Voltage +2.5 VDC (VAA = +5V)
DC Offset Voltage ± 20 mV
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Mode Typical
Current
(mA)
Maximum
Current
(mA)
Typical
Power
(mW)
Maximum
Power
(mW)
Notes
Normal Mode 85 90 280 325 f = 28.224 MHz
Sleep Mode 53 — 175 — f = 28. 224 M Hz
Notes:
1. Operating v ol tage: VDD = +3. 3V ± 0.3V.
2. Test conditions: VDD = +3.3V for typical values; VDD = +3.6V for maximum values.
3. Input Ripple ≤ 0.1 V peak-peak.
4. f = Internal frequency.
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Parameter Symbol Limits Units
Supply Voltage VDD -0.5 to +4.0 V
Input Voltage VIN V
Except XTLI -0.5 to (VGG +0.5)*
XTLI -0.5 to 3.9V
Operating Temperature Range TA-0 to +70 °C
Storage Temperat ure Range TSTG -55 to +125 °C
Analog Inputs VIN -0.3 to (VAA + 0.5) V
Voltage A ppl i ed t o Outputs i n Hi gh I mpedance (Off ) S tate VHZ -0.5 to (VGG +0.5)* V
DC Input Clam p Current IIK ±20 mA
DC Output Clam p Current IOK ±20 mA
Stati c Disc h arge V ol tage (25°C) VESD ±2500 V
Latch-up Current (25° C) ITRIG ±400 mA
* VGG = +5.0V ± 5%.
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