CY2DP818 1:8 Clock Fanout Buffer Features Description Low-voltage operation VDD = 3.3V 1:8 fanout The Cypress CY2DP818 fanout buffer features a single LVDS or a single ended LVTTL compatible input and eight LVPECL output pairs. Operation to 350 MHz Single input configurable for LVDS, LVPECL, or LVTTL 8 pair of LVPECL outputs Drives a 50 ohm load Low input capacitance Low output skew Low propagation delay (tpd = 4 ns, typical) Commercial and Industrial temperature ranges 38-Pin TSSOP Package Designed for data-communications clock management applications, the large fanout from a single input reduces loading on the input clock. The CY2DP818 is ideal for both level translations from single ended to LVPECL and/or for the distribution of LVPECL based clock signals. The Cypress CY2DP818 has configurable input functions. The input is user configurable via the InConfig pin for single ended or differential input. Logic Block Diagram Q1A Q1B Q2A Q2B Q3A Q3B INPUT (LVPECL / LVDS / LVTTL) Q4A INPUT A INPUT B Q4B Q5A InConfig Q5B Q6A Q6B Q7A Q7B Q8A Q8B OUTPUT (LVPECL) Cypress Semiconductor Corporation Document #: 38-07061 Rev. *B * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised August 5, 2009 [+] Feedback CY2DP818 Pinouts Pin Configuration GND VDD VDD VDD VDD VDD InConfig VDD GND INPUT A INPUT B GND VDD VDD VDD VDD VDD GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CY2DP818 Figure 1. 38-Pin TSSOP 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 GND Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B VDD Q5A Q5B Q6A Q6B Q7A Q7B Q8A Q8B GND Pin Description Pin Number Pin Name 1, 9, 12, 18, 19, 20, 38 GND 2, 3, 4, 5, 6, 8, 13, 14, 15, 16, 17, 29 VDD 10, 11 Input A, Input B Type POWER POWER Default: LVPECL/LDVS Optional: LVTTL/LVCMOS single pin 37, 36, 35, 34, 33, 32, 31, 30, 28, 27, 26, 25, 24, 23, 22, 21 7 LVPECL Q1(A,B), Q2(A,B) Q3(A,B), Q4(A,B) Q5(A,B), Q6(A,B) Q7(A,B), Q8(A,B) InConfig LVTTL/LVCMOS Description Ground Power Supply Clock Input. Either differential LVPECL/LVDS or single-ended LVTTL/LVCMOS, as determined by InConfig. See Table 1 and Table 2 for details. Differential Output Clocks Control Input. Selects input type: either differential LVPECL/LVDS or single-ended LVTTL/LVCMOS See Table 1 and Table 2 for details. Table 1. Input Receiver Configuration for Differential or LVTTL/LVCMOS InConfig (Pin 7) Input Receiver Family Input Receiver Type 1 LVTTL or LVCMOS Single ended, non-inverting or inverting, void of bias resistors 0 LVDS or LVPECL Differential, void of internal termination Table 2. Single ended LVTTL/LVCMOS Input Logic (InConfig = 1) Input A (+) Pin 10 Input B (-) Pin 11 Output Clock QnA Pins Input Ground True Input VDD Invert Ground Input Invert VDD Input True Document #: 38-07061 Rev. *B Page 2 of 7 [+] Feedback CY2DP818 Maximum Ratings[1] Ambient Temperature: .................................. -40C to +85C Supply Voltage to Ground Potential (Outputs only) ........................................ -0.3V to VDD + 0.3V Supply Voltage to Ground Potential DC Input Voltage ................................... -0.3V to VDD + 0.3V (Inputs and VDD only) .......................................-0.3V to 4.6V DC Output Voltage................................. -0.3V to VDD + 0.9V Storage Temperature: ................................ -65C to + 150C Power Dissipation....................................................... 0.75W. Table 3. Power Supply Characteristics Parameter Description Test Conditions Typ Max Unit 1.5 2.0 mA/ MHz VDD = Max Input toggling 50% Duty Cycle, Outputs 50 ohms fL=100 MHz 350 mA VDD = Max Input toggling 50% Duty Cycle, Outputs not connected to VTT fL=100 MHz 50 mA Max Unit 600 mV ICC Dynamic Power Supply Current VDD = Max Input toggling 50% Duty Cycle, Outputs Open IC Total Power Supply Current IC Core Core current when output loads are disabled Min DC Electrical Specifications Table 4. LVDS Input, VDD = 3.3V 5%, TA = 0C to 70C or -40C to 85C Parameter Description Conditions VID Magnitude of Differential Input Voltage VIC Common-mode of Differential Input VoltageIVIDI (min and max) VIH Input High Voltage Guaranteed Logic High Level VIL Input Low Voltage Guaranteed Logic Low Level IIH Input High Current VDD = Max, VIN = VDD IIL Input Low Current VDD = Max, VIN = VSS Min Typ 100 IVIDI/2 2.4-(IVIDI/2) 2 V V 0.8 V 10 20 A 10 20 A Typ Max Unit Table 5. LVPECL Input, VDD = 3.3V 5%, TA = 0C to 70C or -40C to 85C Parameter Description Conditions Min VID Differential Input Voltage p-p Guaranteed Logic High Level 400 2600 mV VIH Input High Voltage Guaranteed Logic High Level 2.15 2.4 V VIL Input Low Voltage Guaranteed Logic Low Level 1.5 1.8 V IIH Input High Current VDD = Max, VIN = VDD 10 20 A IIL Input Low Current VDD = Max, VIN = VSS 10 20 A VCM Common-mode Voltage 225 mV Max Unit Table 6. LVTTL/LVCMOS Input, VDD = 3.3V 5%, TA = 0C to 70C or -40C to 85C Parameter Description Conditions Min Typ VIH Input High Voltage VIL Input Low Voltage 0.8 V IIH Input High Current VDD = Max, VIN = 2.7V 1 A IIL Input Low Current VDD = Max, VIN = 0.5V -1 A 2 V Note 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Document #: 38-07061 Rev. *B Page 3 of 7 [+] Feedback CY2DP818 Table 6. LVTTL/LVCMOS Input, VDD = 3.3V 5%, TA = 0C to 70C or -40C to 85C Parameter Description Conditions II Input High Current VDD = Max, VIN = VDD(Max) VIK Clamp Diode Voltage VDD = Min, IIN = -18mA VH Input Hysteresis Min Typ -0.7 Max Unit 20 A -1.2 80 V mV Table 7. LVPECL Output, VDD = 3.3V 5%, TA = 0C to 70C or -40C to 85C Parameter Description Conditions Min VOD Driver Differential Output voltage p-p VDD = Min, VIN = VIH or VIL, RL = 50 VOC Driver common-mode p-p VDD = Min, VIN = VIH or VIL, RL = 50 tR Rise Time tF Fall Time Differential 20% to 80%, CL = 10 pF to GND, RL = 50 to GND Typ 1000 300 Max Unit 3600 mV 300 mV 1200 ps VOH Output High Voltage VDD = Min, VIN = VIH or VIL, IOH = -12 mA 2.1 3.0 V VOL[2] Output Low Voltage VDD = Min, VIN = VIH or VIL 0.8 1.3 V IOS Short Circuit Current VDD = Max, VOUT = GND -125 -150 mA AC Switching Characteristics Table 8. VDD = 3.3V 5%, TA = 0C to 70C or -40C to 85C Conditions Min Typ Max Unit tPLH Parameter Propagation Delay - Low to High Description VID = 100 mV 3 4 5 ns tPHL Propagation Delay - High to Low VID = 100 mV 3 4 tSK(0) Output Skew: Skew between outputs of the same package (in phase) tSK(p) Pulse Skew: Skew between opposite transitions of the same output (tPHL-tPLH) tSK(t) Package Skew: Skew between outputs of different packages at the same power supply voltage, temperature and package type. Same input signal level and output load. 5 ns 0.2 ns 0.2 VID = 100 mV ns 1 ns Max Unit 350 MHz Table 9. High frequency Parametrics Parameter Fmax Description Maximum frequency VDD = 3.3V Conditions Min Typ 45%-55% duty cycle Standard load circuit Note 2. VOL levels are dependent on the termination voltage VTT and termination resistance RTT. Changing either of these values will affect VOL. Document #: 38-07061 Rev. *B Page 4 of 7 [+] Feedback CY2DP818 Figure 2. Driver Design Figure 3. Standard Termination A TPA 150 Pulse 50 10pF Generator B 150 TPC VDD-2V 50 GND TPB Figure 4. Differential Receiver to Driver Propagation Delay and Driver Transition Time[3,4,5,6] 1.4 V INPUT A INPUT B 1.0 V QnA QnB tPLH tPHL 80% 0V Differential 20% QnA - QnB tR tF Figure 5. Test Circuit and Voltage Definitions for the Driver Common Mode Output Voltage[3,4,5,6] A TPA 150 Pulse Generator 50 TPC B 150 50 GND TPB VOC Standard Termination INPUT A 2.0V INPUT B 1.6V VOD Next Device Notes 3. All input pulses are supplied by a frequency generator with the following characteristics: tR and tF 1 ns; pulse rerate = 50 Mpps; pulse width = 10 0.2 ns. 4. RL = 50 ohm 1%; Zline = 50 ohm 6". 5. CL includes instrumentation and fixture capacitance within 6 mm of the UT. 6. TPA and B are used for prop delay and Rise/Fall measurements. TPC is used for VOC measurements only and is otherwise connected to VDD - 2V. Document #: 38-07061 Rev. *B Page 5 of 7 [+] Feedback CY2DP818 Ordering Information Part Number Package Type CY2DP818ZI 38-pin TSSOP Product Flow Industrial, -40 to 85C CY2DP818ZIT 38-pin TSSOP-Tape and Reel Industrial, -40 to 85C CY2DP818ZC 38-pin TSSOP Commercial, 0C to 70C CY2DP818ZCT 38-pin TSSOP-Tape and Reel Commercial, 0C to 70C CY2DP818ZXI 38-pin TSSOP Industrial, -40 to 85C CY2DP818ZXIT 38-pin TSSOP-Tape and Reel Industrial, -40 to 85C Pb-Free CY2DP818ZXC 38-pin TSSOP Commercial, 0C to 70C CY2DP818ZXCT 38-pin TSSOP-Tape and Reel Commercial, 0C to 70C Package Drawing and Dimensions Figure 6. 38-Pin TSSOP (4.40 mm Body) Z38 and ZZ38 51-85151-*A Document #: 38-07061 Rev. *B Page 6 of 7 [+] Feedback CY2DP818 Document History Page Document Title: CY2DP818 1:8 Clock Fanout Buffer Document Number: 38-07061 Revision ECN ** 107086 Orig. of Submission Change Date 06/07/01 Description of Change IKA New Data Sheet *A 115913 07/11/02 CTK IC, VCM, VOC, Rise/Fall Time Fmax (20) *B 2748606 08/05/09 KVM Deleted references to ComLink Minor edits to page 1 text Instances of VCC changed to VDD Changed table sequence to be more logical Edited Table 1 on page 2 and reformatted Table 2 on page 2 for clarity Added voltage and temperature specs to heading of all DC and AC tables Added commercial temp range to DC and AC table headings Clarified wording for IC Core Removed duplicate II (input high current) parameter from LVPECL & LVDS Removed TPE and TPD parameters from AC table Cleaned up waveform drawings Removed figures showing inputs for different InConfig values because Table 1 on page 2 and Table 2 on page 2 are more complete Added part numbers CY2DP818ZXC, CY2DP818ZXCT, CY2DP818ZXI and CY2DP818ZXIT to the ordering information table Revised Package Diagram Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers psoc.cypress.com clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors image.cypress.com (c) Cypress Semiconductor Corporation, 2001-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07061 Rev. *B Revised August 5, 2009 Page 7 of 7 PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC ExpressTM are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback