CY2DP818
1:8 Clock Fanout Buffer
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-07061 Rev. *B Revised August 5, 2009
Features
■Low-voltage operation VDD = 3.3V
■1:8 fanout
■Operation to 350 MHz
■Single input configurable for LVDS, LVPECL, or LVTTL
■8 pair of LVPECL outputs
■Drives a 50 ohm load
■Low input capacitance
■Low output skew
■Low propagation delay (tpd = 4 ns, typical)
■Commercial and Industrial te mperature ranges
■38-Pin TSSOP Package
Description
The Cypress CY2DP818 fanout buffer features a single L VDS or
a single ended L VTTL compatible input and eight L VPECL output
pairs.
Designed for data-communications clock management
applications, the large fanout from a single input reduces loading
on the input clock.
The CY2DP818 is ideal for both level translations from single
ended to LVPECL and/or for the distribution of LVPECL based
clock signals.
The Cypress CY2DP818 has configurable input functions. The
input is user configurable via the InConfig pin for single ended or
differential input.
Logic Block Diagram
INPUT
(LVPECL / LVDS / LVTTL)
OUTPUT
(LVPECL)
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
INPUT A
INPUT B
InConfig
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CY2DP818
Document #: 38-07061 Rev. *B Page 2 of 7
Pinouts
Pin Configuration
Figure 1. 38-Pin TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
GND
VDD
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4B
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
GND
Q4A
GND
VDD
GND
GND
VDD
InConfig
INPUT A
INPUT B
GND
GND
CY2DP818
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Pin Description
Pin Number Pin Name Type Description
1, 9, 12, 18, 19, 20, 38 GND POWER Ground
2, 3, 4, 5, 6, 8, 13, 14, 15, 16, 17, 29 VDD POWER Power Supply
10, 11 Input A, Input B Default: LVPECL/LDVS
Optional: LVTTL/LVCMOS
single pin
Clock Input. Either differential
LVPECL/LVDS or single-ended
LVTTL/LVCMOS, as determined by
InConfig. See Table 1 and Table 2 for
details.
37, 36, 35, 34,
33, 32, 31, 30,
28, 27, 26, 25,
24, 23, 22, 21
Q1(A,B), Q2(A,B)
Q3(A,B), Q4(A,B)
Q5(A,B), Q6(A,B)
Q7(A,B), Q8(A,B)
LVPECL Differential Output Clocks
7 InConfig LVTTL/LVCMOS Control Input. Selects input type: either
differential LVPECL/LVDS or
single-ended LVTTL/LVCMOS
See Table 1 and Table 2 for details.
Table 1. Input Receiver Configuration for Differential or LVTTL/LVCMOS
InConfig (Pin 7) Input Receiver Family Input Receiver Type
1 LVTTL or LVCMOS Single ended, non-inverting or inverting, void of bias resistors
0 LVDS or LVPECL Differential, void of internal termination
Table 2. Single ended LVTTL/LVCMOS Input Logic (InConfig = 1)
Input A (+) Pin 10 Input B (–) Pin 11 Output Clock QnA Pins
Input Ground True
Input VDD Invert
Ground Input Invert
VDD Input True
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CY2DP818
Document #: 38-07061 Rev. *B Page 3 of 7
Maximum Ratings[1]
Storage Temperature:........................... ... ..–65°C to + 150°C
Ambient Temperature:..................................–40°C to +85°C
Supply Voltage to Ground Potential
(Inputs and VDD only).......................................–0.3V to 4.6V
Supply Voltage to Ground Potential
(Outputs only).................. .. ................. ...–0.3V to VDD + 0.3V
DC Input Voltage ............. .. ................. ...–0.3V to VDD + 0.3V
DC Output Voltage...................... ... .. ... ...–0.3V to VDD + 0.9V
Power Dissipation....................................................... 0.75W.
DC Electrical Specifications
Table 3. Power Supply Characte ristics
Parameter Description Test Conditions Min Typ Max Unit
ICC Dynamic Power Supply Current VDD = Max
Input toggling 50% Duty Cycle,
Outputs Open
1.5 2.0 mA/
MHz
IC Total Power Supply Current VDD = Max
Input toggling 50% Duty Cycle,
Outputs 50 ohms
fL=100 MHz
350 mA
IC Core Core current when output loads are
disabled VDD = Max
Input toggling 50% Duty Cycle,
Outputs not connected to VTT
fL=100 MHz
50 mA
Tab le 4. LVDS Input, VDD = 3.3V ±5%, TA = 0°C to 70°C or –40°C to 85°C
Parameter Description Conditions Min Typ Max Unit
VID Magnitude of Differential Input Voltage 100 600 mV
VIC Common-mode of Differential Input
VoltageIVIDI (min and max) IVIDI/2 2.4–(IVIDI/2) V
VIH Input High Voltage Guaranteed Logic High Level 2 V
VIL Input Low Voltage Guaranteed Logic Low Level 0.8 V
IIH Input High Current VDD = Max, VIN = VDD ±10 ±20 μA
IIL Input Low Current VDD = Max, VIN = VSS ±10 ±20 μA
Table 5. LVPECL Input, VDD = 3.3V ±5%, TA = 0°C to 70°C or –40°C to 85°C
Parameter Description Conditions Min Typ Max Unit
VID Dif ferential Input Voltage p-p Guaranteed Logic High Level 400 2600 mV
VIH Input High Voltage Guaranteed Logic High Level 2.15 2.4 V
VIL Input Low Voltage Guaranteed Logic Low Level 1.5 1.8 V
IIH Input High Current VDD = Max, VIN = VDD ±10 ±20 μA
IIL Input Low Current VDD = Max, VIN = VSS ±10 ±20 μA
VCM Common-mode Voltage 225 mV
Table 6. LVTTL/LVCMOS Input, VDD = 3.3V ±5% , TA = 0°C to 70°C or –40°C to 85°C
Parameter Description Conditions Min Typ Max Unit
VIH Input High V oltage 2 V
VIL Input Low Voltage 0.8 V
IIH Input High Current VDD = Max, VIN = 2.7V 1 μA
IIL Input Low Current VDD = Max, VIN = 0.5V –1 μA
Note
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extende d periods may affect reliability.
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CY2DP818
Document #: 38-07061 Rev. *B Page 4 of 7
AC Switching Characteristics
IIInput High Current VDD = Max, VIN = VDD(Max) 20 μA
VIK Clamp Diode Voltage VDD = Min, IIN = –18mA –0.7 –1.2 V
VHInput Hysteresis 80 mV
Table 7. LVPECL Output, VDD = 3.3V ±5%, TA = 0°C to 70°C or –40°C to 85°C
Parameter Description Conditions Min Typ Max Unit
VOD Driver Differential Output
voltage p-p VDD = Min, VIN = VIH or VIL, RL = 50 Ω1000 3600 mV
VOC Driver common-mode p-p VDD = Min, VIN = VIH or VIL, RL = 50 Ω300 mV
tRRise T ime Differential 20% to 80%, CL = 10 pF to GND,
RL = 50 Ω to GND 300 1200 ps
tFFall Time
VOH Output High Voltage VDD = Min, VIN = VIH or VIL, IOH = –12 mA 2.1 3.0 V
VOL[2] Output Low Voltage VDD = Min, VIN = VIH or VIL 0.8 1.3 V
IOS Short Circuit Current VDD = Max, VOUT = GND –125 –150 mA
Tab le 8. VDD = 3.3V ±5%, TA = 0°C to 70°C or –40°C to 85°C
Parameter Description Conditions Min Typ Max Unit
tPLH Propagation Delay – Low to High VID = 100 mV 3 4 5 ns
tPHL Propagation Delay – High to Low VID = 100 mV 3 4 5 ns
tSK(0) Output Skew: Skew between outputs of the same package (in phase) 0.2 ns
tSK(p) Pulse Skew: Skew between opp osite transitions of the same output
(tPHL–tPLH)0.2 ns
tSK(t) Package Skew: Skew between outputs of different packages at the
same power supply voltage, temperature and package type. Same
input signal level and output load.
VID = 100 mV 1 ns
Table 6. LVTTL/LVCMOS Input, VDD = 3.3V ±5% , TA = 0°C to 70°C or –40°C to 85°C
Parameter Description Conditions Min Typ Max Unit
Note
2. VOL levels are dependent on the termination voltage VTT and termination resistance RTT. Changing either of these values will affect VOL.
Table 9. High frequency Parametric s
Parameter Description Conditions Min Typ Max Unit
Fmax Maximum frequency
VDD = 3.3V 45%–55% duty cycle
Standard load circuit 350 MHz
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CY2DP818
Document #: 38-07061 Rev. *B Page 5 of 7
Figure 2. Driver Design
Figure 3. Standard Termination
Figure 4. Differential Receiver to Driver Propagation Delay and Driver Transition Time[3,4,5,6]
Figure 5. Te st Circuit and Voltage Definitions for the Driver Common Mode Output Voltage[3,4,5,6]
TPA
TPC
TPB
50
50
GND
150
150
Pulse
Generator
A
B10pF VDD-2V
Notes
3. All input pulses are supplied by a frequency generator with the following characteristics: tR and tF ≤ 1 ns; pulse rerate = 50 Mpps; pulse width = 10 ± 0.2 ns.
4. RL = 50 ohm ± 1%; Zline = 50 ohm 6”.
5. CL includes instrumentation and fixture cap acitance within 6 mm of the UT.
6. TPA and B are used for prop delay and Rise/Fall measurements. TPC is used for VOC measurements only and is otherwise connected to VDD – 2V.
2.0V
1.6V
INPUT A
INPUT B
Next Device
VODVOC
TPA
TPC
TPB
50
50
GND
150
150
Standard Termination
Pulse
Generator
A
B
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CY2DP818
Document #: 38-07061 Rev. *B Page 6 of 7
Package Drawing and Dimensions
Figure 6. 38-Pin TSSOP (4.40 mm Body) Z38 and ZZ 3 8
Ordering Information
Part Number Package Type Product Flow
CY2DP818ZI 38-pin TSSOP Industrial, –40° to 85°C
CY2DP818ZIT 38-pin TSSOP–Tape and Reel Industrial, –40° to 85°C
CY2DP818ZC 38-pin TSSOP Commercial, 0°C to 70°C
CY2DP818ZCT 38-pin TSSOP–Tape and Reel Commercial, 0°C to 70°C
Pb-Free
CY2DP818ZXI 38-pin TSSOP Industrial, –40 ° to 85°C
CY2DP818ZXIT 38-pin TSSOP–Tape and Reel Industrial, –40° to 85°C
CY2DP818ZXC 38-pin TSSOP Commercial, 0°C to 70°C
CY2DP818ZXCT 38-pin TSSOP–Tape and Reel Commercial, 0°C to 70°C
51-85151-*A
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Document #: 38-07061 Rev. *B Revised August 5, 2009 Page 7 of 7
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp.
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY2DP818
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Document Title: CY2DP818 1:8 Clock Fanout Buffer
Document Number: 38-07061
Revision ECN Orig. of
Change Submission
Date Description of Change
** 107086 06/07/01 IKA New Data Sheet
*A 115913 07/11/02 CTK IC, VCM, VOC, Rise/Fall Time Fmax (20)
*B 2748606 08/05/09 KVM Deleted references to ComLin k
Minor edits to page 1 text
Instances of VCC changed to VDD
Changed table sequence to be mo re logical
Edited Table 1 on page 2 and reformatted Table 2 on page 2 for clarity
Added voltage and temperature specs to headi ng of all DC and AC tables
Added commercial te mp range to DC and AC table headings
Clarified wording for IC Core
Removed duplicate II (input high current) parameter from LVPECL & LVDS
Removed TPE and TPD parameters from AC table
Cleaned up waveform drawings
Removed figures showing inputs for different InConfig values because Table 1 on
page 2 and Table 2 on page 2 are more com pl e te
Added part numbers CY2DP818ZXC, CY2DP818ZXCT, CY2DP818ZXI and
CY2DP818ZXIT to the ordering information table
Revised Package Diagram
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