SGLS148 - DECEMBER 2002 D Qualification in Accordance With D PACKAGE (TOP VIEW) AEC-Q100 D Qualified for Automotive Applications D Customer-Specific Configuration Control D D D D D D 1B 2B 3B 4B 5B 6B 7B E Can Be Supported Along With Major-Change Approval ESD Protection Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) 500-mA Rated Collector Current (Single Output) High-Voltage Outputs . . . 50 V Output Clamp Diodes Inputs Compatible With Various Types of Logic Relay-Driver Applications 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1C 2C 3C 4C 5C 6C 7C COM Contact factory for details. Q100 qualification data available on request. description The ULQ2003A-Q1 and ULQ2004A-Q1 are high-voltage, high-current Darlington transistor arrays. Each consists of seven npn Darlington pairs that feature high-voltage outputs with common-cathode clamp diodes for switching inductive loads. The collector-current rating of a single Darlington pair is 500 mA. The Darlington pairs can be paralleled for higher current capability. Applications include relay drivers, hammer drivers, lamp drivers, display drivers (LED and gas discharge), line drivers, and logic buffers. The ULQ2003A-Q1 has a 2.7-k series base resistor for each Darlington pair, for operation directly with TTL or 5-V CMOS devices. The ULQ2004A-Q1 has a 10.5-k series base resistor to allow operation directly from CMOS devices that use supply voltages of 6 V to 15 V. The required input current of the ULQ2004A-Q1 is below that of the ULQ2003A-Q1. AVAILABLE OPTIONS D PACKAGES{ TA SMALL OUTLINE ULQ2003ATDQ1 ULQ2003ATDRQ1 40C to 105C -40C ULQ2004ATDQ1} ULQ2004ATDRQ1} The D package is available taped and reeled. Add the suffix R to device type (e.g., ULQ2003TDADRQ1). ULQ2004ATDQ1 and ULQ2004ATDRQ1 are Product Preview only. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated !"#$ #$%# #&'!%$# # (' $ # !'" $%# #" (%" & ")"*(!"#$+ " $%$ & "% ")" #%$" # $" (%,"-. ("&/#, $ "*"$'%* %'%$"'$+ POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SGLS148 - DECEMBER 2002 logic diagram 9 1B 2B 3B 4B 5B 6B 7B 1 16 2 15 3 14 4 13 5 12 6 11 7 10 COM 1C 2C 3C 4C 5C 6C 7C schematics (each Darlington pair) COM Input B ULQ2003A-Q1: RB = 2.7 k ULQ2004A-Q1: RB = 10.5 k Output C RB 7.2 k 3 k E ULQ2003A-Q1, ULQ2004A-Q1 All resistor values shown are nominal. absolute maximum ratings at 25C free-air temperature (unless otherwise noted) Collector-emitter voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V Clamp diode reverse voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V Input voltage, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V Peak collector current (see Figure 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Output clamp current, IOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Total emitter-terminal current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.5 A Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Package thermal impedance, JA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W Operating free-air temperature range, TA, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 105C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS148 - DECEMBER 2002 DISSIPATION RATING TABLE PACKAGE 25C TA = 25 C POWER RATING DERATING FACTOR ABOVE TA = 25C 85C TA = 85 C POWER RATING 105C TA = 105 C POWER RATING D 950 mW 7.6 mW/C 494 mW 342 mW electrical characteristics over recommended operating conditions (unless otherwise noted) ULQ2003A-Q1 PARAMETER TEST CONDITIONS MIN TYP IC = 125 mA IC = 200 mA VI(on) On state inp On-state inputt voltage, oltage See Fig Figure re 6 VCE(sat) ICEX C ll t itt saturation t ti voltage, lt Collector-emitter See Figure 5 C ll t cutoff t ff currentt Collector VF Clamp forward voltage, See Figure 8 II(off) Off state input Off-state inp t current, c rrent See Figure Fig re 3 II Input In ut current, see Figure 4 VCE = 2 V II = 250 A, II = 350 A, ULQ2004A-Q1 MAX MIN TYP MAX 5 2.7 IC = 250 mA IC = 275 mA 2.9 IC = 300 mA IC = 350 mA 3 6 7 0.9 1.2 0.9 1.1 1 1.4 1 1.3 II = 500 A, IC = 350 mA VCE = 50 V, II = 0, See Figure 1 1.2 1.7 1.2 1.6 100 V 50 II = 0 VI = 1 V 100 A A 500 IF = 350 mA VCE = 50 V, V VI = 3.85 V V 8 IC = 100 mA IC = 200 mA VCE = 50 V, See Figure 2 UNIT 1.7 IC = 500 A A 30 2.2 65 0.93 1.7 50 Clamp reverse current, Clam See Figure 7 VR = 50 V, VR = 50 V TA = 25C Ci Input capacitance VI = 0, f = 1 MHz V A A 65 1.35 VI = 5 V VI = 12 V IR 2 15 0.35 0.5 1 1.45 100 50 100 100 25 15 25 mA A A pF switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS ULQ2003A-Q1, ULQ2004A-Q1 MIN tPLH tPHL VOH Propagation delay time, low-to-high level output See Figure 9 Propagation delay time, high-to-low level output See Figure 9 High-level output voltage after switching VS = 50 V, See Figure 10 POST OFFICE BOX 655303 IO 300 mA, * DALLAS, TEXAS 75265 VS-500 UNIT TYP MAX 1 10 s 1 10 s mV 3 SGLS148 - DECEMBER 2002 PARAMETER MEASUREMENT INFORMATION Open Open VCE ICEX VCE ICEX Open VI Figure 1. ICEX Test Circuit Open Figure 2. ICEX Test Circuit VCE Open II(off) IC II(on) Open VI Figure 3. II(off) Test Circuit Figure 4. II Test Circuit Open Open IC hFE = II VCE II IC VI(on) VCE IC NOTE: II is fixed for measuring VCE(sat), variable for measuring hFE. Figure 5. hFE, VCE(sat) Test Circuit Figure 6. VI(on) Test Circuit VR IR VF Open Open Figure 7. IR Test Circuit 4 POST OFFICE BOX 655303 Figure 8. VF Test Circuit * DALLAS, TEXAS 75265 IF SGLS148 - DECEMBER 2002 PARAMETER MEASUREMENT INFORMATION 50% Input 50% tPHL tPLH 50% Output 50% VOLTAGE WAVEFORMS Figure 9. Propagation Delay-Time Waveforms VS 2 mH Open 1N3064 200 Pulse Generator (see Note A) Output ULQ2003A-Q1 ULQ2004A-Q1 CL = 15 pF (see Note B) TEST CIRCUIT 5 ns 10 ns 90% 1.5 V Input 10% VIH (see Note C) 90% 1.5 V 10% 40 s 0V VOH Output VOL VOLTAGE WAVEFORMS NOTES: A. The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 . B. CL includes probe and jig capacitance. C. For testing the ULQ2003A-Q1, VIH = 3 V; for the ULQ2004A-Q1, VIH = 8 V. Figure 10. Latch-Up Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SGLS148 - DECEMBER 2002 TYPICAL CHARACTERISTICS COLLECTOR-EMITTER SATURATION VOLTAGE vs TOTAL COLLECTOR CURRENT (TWO DARLINGTONS IN PARALLEL) 2.5 VCE(sat) VCE(sat) - Collector-Emitter Saturation Voltage - V VCE(sat) VCE(sat) - Collector-Emitter Saturation Voltage - V COLLECTOR-EMITTER SATURATION VOLTAGE vs COLLECTOR CURRENT (ONE DARLINGTON) TA = 25C 2 II = 250 A II = 350 A II = 500 A 1.5 1 0.5 0 0 100 200 300 400 500 600 700 2.5 TA = 25C II = 250 A 2 II = 350 A 1.5 II = 500 A 1 0.5 0 0 800 100 200 300 Figure 11 Figure 12 COLLECTOR CURRENT vs INPUT CURRENT 500 RL = 10 TA = 25C IIC C - Collector Current - mA 450 400 VS = 10 V 350 VS = 8 V 300 250 200 150 100 50 0 0 500 600 700 IC(tot) - Total Collector Current - mA IC - Collector Current - mA 25 50 75 100 125 150 II - Input Current - A Figure 13 6 400 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 175 200 800 SGLS148 - DECEMBER 2002 THERMAL INFORMATION MAXIMUM COLLECTOR CURRENT vs DUTY CYCLE IIC C - Maximum Collector Current - mA 600 500 N=1 N=4 400 N=3 300 N=2 N=6 N=7 N=5 200 100 TA = 70C N = Number of Outputs Conducting Simultaneously 0 0 10 20 30 40 50 60 70 80 90 100 Duty Cycle - % Figure 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SGLS148 - DECEMBER 2002 APPLICATION INFORMATION ULQ2004A-Q1 ULQ2003A-Q1 VCC VDD V V 1 16 1 16 2 15 2 15 3 14 3 14 4 13 4 13 5 12 5 12 6 11 6 11 7 10 7 10 8 9 8 9 CMOS Lamp Output Test TTL Output Figure 16. Buffer for Higher Current Loads Figure 15. TTL to Load ULQ2003A-Q1 VCC V 1 16 2 15 RP 3 14 4 13 5 12 6 11 7 10 8 9 TTL Output Figure 17. Use of Pullup Resistors to Increase Drive Current 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS148 - DECEMBER 2002 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0- 8 A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 MECHANICAL DATA MSOI002B - JANUARY 1995 - REVISED SEPTEMBER 2001 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0- 8 A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). 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