MC74HC373ANG - ON SEMICONDUCTOR - Datasheet.Directory

May, 2011 − Rev. 14

1Publication Order Number:

MC74HC373A/D

MC74HC373A

Octal 3-State Non-Inverting

Transparent Latch

High−Performance Silicon−Gate CMOS

The MC74HC373A is identical in pinout to the LS373. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

These latches appear transparent to data (i.e., the outputs change

asynchronously) when Latch Enable is high. When Latch Enable goes

low, data meeting the setup and hold time becomes latched.

The Output Enable input does not affect the state of the latches, but

when Output Enable is high, all device outputs are forced to the

high−impedance state. Thus, data may be latched even when the

outputs are not enabled.

The HC373A is identical in function to the HC573A which has the

data inputs on the opposite side of the package from the outputs to

facilitate PC board layout.

The HC373A is the non−inverting version of the HC533A.

Features

•Output Drive Capability: 15 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 mA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the JEDEC Standard No. 7.0 A Requirements

•Chip Complexity: 186 FETs or 46.5 Equivalent Gates

•These Devices are Pb−Free and are RoHS Compliant

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MARKING

DIAGRAMS

See detailed ordering and shipping information in the package

dimensions section on page 3 of this data sheet.

ORDERING INFORMATION

20

1

20

SOIC−20

DW SUFFIX

CASE 751D

HC373A

AWLYYWWG

HC

373A

ALYWG

G

TSSOP−20

DT SUFFIX

CASE 948E

SOEIAJ−20

F SUFFIX

CASE 967

74HC373A

AWLYWWG

1

20

1

20

PDIP−20

N SUFFIX

CASE 738

1

20

MC74HC373AN

AWLYYWWG

1

20

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or G= Pb−Free Package

(Note: Microdot may be in either location)

MC74HC373A

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2

DATA

INPUTS

D0

D1

D2

D3

D4

D5

D6

D7 18

17

14

13

8

7

4

3

1

OUTPUT ENABLE

19

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

16

15

12

9

6

5

2

PIN 20 = VCC

PIN 10 = GND

NONINVERTING

OUTPUTS

11

LATCH ENABLE

FUNCTION TABLE

Inputs Output

Output Latch

Enable Enable D Q

LHHH

LHLL

L L X No Change

HXXZ

X = Don’t Care

Z = High Impedance

Q2

D1

D0

Q0

OUTPUT

ENABLE

GND

Q3

D3

D2

Q1 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q6

D6

D7

Q7

VCC

LATCH

ENABLE

Q4

D4

D5

Q5

LOGIC DIAGRAM

PIN ASSIGNMENT

ÎÎÎÎÎÎÎÎÎÎÎ

Design Criteria

ÎÎÎÎ

Value

ÎÎÎ

Units

ÎÎÎÎÎÎÎÎÎÎÎ

Internal Gate Count*

ÎÎÎÎ

46.5

ÎÎÎ

ea

ÎÎÎÎÎÎÎÎÎÎÎ

Internal Gate Propagation Delay

ÎÎÎÎ

1.5

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎ

Internal Gate Power Dissipation

ÎÎÎÎ

5.0

ÎÎÎ

mW

ÎÎÎÎÎÎÎÎÎÎÎ

Speed Power Product

ÎÎÎÎ

0.0075

ÎÎÎ

pJ

*Equivalent to a two−input NAND gate.

MC74HC373A

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3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

V

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

V

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

V

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎ

±20

ÎÎÎ

mA

ÎÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎ

±35

ÎÎÎ

mA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎ

±75

ÎÎÎ

mA

ÎÎÎÎ

PD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎÎ

750

500

450

ÎÎÎ

mW

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

_C

ÎÎÎÎ

TL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC, SSOP or TSSOP Package)

ÎÎÎÎÎ

260

ÎÎÎ

_C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

V

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

0

ÎÎÎ

VCC

ÎÎÎ

V

ÎÎÎÎ

TA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

_C

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

0

ÎÎÎ

1000

500

400

ÎÎÎ

ns

ORDERING INFORMATION

Device Package Shipping†

MC74HC373ANG PDIP−20

(Pb−Free)

18 Units / Box

MC74HC373ADWG SOIC−20 WIDE

(Pb−Free)

38 Units / Rail

MC74HC373ADWR2G SOIC−20 WIDE

(Pb−Free)

1000 Units / Reel

MC74HC373ADTG TSSOP−20* 75 Units / Rail

MC74HC373ADTR2G TSSOP−20* 2500 Units / Reel

MC74HC373AFG SOEIAJ−20

(Pb−Free)

40 Units / Rail

MC74HC373AFELG SOEIAJ−20

(Pb−Free)

2000 Units / Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74HC373A

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4

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎ

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

V

ÎÎÎÎÎ

– 55 to 25_C

ÎÎÎÎ

v 85_C

ÎÎÎÎ

v 125_C

ÎÎ

Unit

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎ

Minimum High−Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = VCC – 0.1 V

|Iout| v 20 mA

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

1.5

2.1

3.15

4.2

ÎÎÎÎ

1.5

2.1

3.15

4.2

ÎÎÎÎ

1.5

2.1

3.15

4.2

ÎÎ

V

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V

|Iout| v 20 mA

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

0.5

0.9

1.35

1.8

ÎÎÎÎ

0.5

0.9

1.35

1.8

ÎÎÎÎ

0.5

0.9

1.35

1.8

ÎÎ

V

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎ

Minimum High−Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH

|Iout| v 20 mA

ÎÎÎ

2.0

4.5

6.0

ÎÎÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎ

V

ÎÎÎÎÎÎÎÎÎ

Vin = VIH |Iout| v 2.4 mA

|Iout| v 6.0 mA

|Iout| v 7.8 mA

ÎÎÎ

3.0

4.5

6.0

ÎÎÎÎÎ

2.48

3.98

5.48

ÎÎÎÎ

2.34

3.84

5.34

ÎÎÎÎ

2.2

3.7

5.2

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIL

|Iout| v 20 mA

ÎÎÎ

2.0

4.5

6.0

ÎÎÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎ

V

ÎÎÎÎÎÎÎÎÎ

Vin = VIL |Iout| v 2.4 mA

|Iout| v 6.0 mA

|Iout| v 7.8 mA

ÎÎÎ

3.0

4.5

6.0

ÎÎÎÎÎ

0.26

ÎÎÎÎ

0.33

ÎÎÎÎ

0.4

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎ

6.0

ÎÎÎÎÎ

±0.1

ÎÎÎÎ

±1.0

ÎÎÎÎ

±1.0

ÎÎ

mA

ÎÎÎÎ

IOZ

ÎÎÎÎÎÎÎÎÎ

Maximum Three−State

Leakage Current

ÎÎÎÎÎÎÎÎÎ

Output in High−Impedance State

Vin = VIL or VIH

Vout = VCC or GND

ÎÎÎ

6.0

ÎÎÎÎÎ

±0.5

ÎÎÎÎ

±5.0

ÎÎÎÎ

±10

ÎÎ

mA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply

Current (per Package)

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

Iout = 0 mA

ÎÎÎ

6.0

ÎÎÎÎÎ

4.0

ÎÎÎÎ

40

ÎÎÎÎ

160

ÎÎ

mA

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎ

Unit

ÎÎÎÎÎ

– 55 to 25_C

ÎÎÎÎ

v 85_C

ÎÎÎÎ

v 125_C

ÎÎÎÎ

tPLH

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Input D to Q

(Figures 1 and 5)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

125

80

25

21

ÎÎÎÎ

155

110

31

26

ÎÎÎÎ

190

130

38

32

ÎÎ

ns

ÎÎÎÎ

tPLH

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Latch Enable to Q

(Figures 2 and 5)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

140

90

28

24

ÎÎÎÎ

175

120

35

30

ÎÎÎÎ

210

140

42

36

ÎÎ

ns

ÎÎÎÎ

tPLZ

tPHZ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

150

100

30

26

ÎÎÎÎ

190

125

38

33

ÎÎÎÎ

225

150

45

38

ÎÎ

ns

ÎÎÎÎ

tPZL

tPZH

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

150

100

30

26

ÎÎÎÎ

190

125

38

33

ÎÎÎÎ

225

150

45

38

ÎÎ

ns

ÎÎÎÎ

tTLH

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition Time, Any Output

(Figures 1 and 5)

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎÎÎ

60

23

12

10

ÎÎÎÎ

75

27

15

13

ÎÎÎÎ

90

32

18

15

ÎÎ

ns

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎ

ÎÎÎÎÎ

10

ÎÎÎÎ

10

ÎÎÎÎ

10

ÎÎ

pF

ÎÎÎÎ

Cout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Three−State Output Capacitance

(Output in High−Impedance State)

ÎÎÎ

ÎÎÎÎÎ

15

ÎÎÎÎ

15

ÎÎÎÎ

15

ÎÎ

pF

CPD Power Dissipation Capacitance (Per Enabled Output)*

Typical @ 25°C, VCC = 5.0 V

pF

36

* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.

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5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Figure

ÎÎÎ

VCC

Volts

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎ

Unit

ÎÎÎÎÎ

– 55 to 25_C

ÎÎÎÎÎ

v 85_C

ÎÎÎÎÎ

v 125_C

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎ

tsu

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Setup Time, Input D to Latch Enable

ÎÎÎ

4

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

25

20

5.0

ÎÎÎ

30

25

6.0

ÎÎÎ

40

30

8.0

7.0

ÎÎÎ

ÎÎ

ns

ÎÎÎÎ

th

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Hold Time, Latch Enable to Input D

ÎÎÎ

4

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

5.0

ÎÎÎ

5.0

5 0

5.0

ÎÎÎ

5.0

ÎÎÎ

ÎÎ

ns

ÎÎÎÎ

tw

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Latch Enable

ÎÎÎ

2

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

60

23

12

10

ÎÎÎ

75

27

15

13

ÎÎÎ

90

32

18

15

ÎÎÎ

ÎÎ

ns

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall Times

ÎÎÎ

1

ÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

1000

800

500

400

ÎÎÎ

1000

800

500

400

ÎÎÎ

1000

800

500

400

ÎÎ

ns

SWITCHING WAVEFORMS

VCC

GND

tf

tr

INPUT D

Q

10%

50%

90%

10%

50%

90%

tTLH

tPLH tPHL

tTHL

VCC

GND

50%

LATCH ENABLE

tPLH tPHL

Q

tw

50%

Figure 1. Figure 2.

Figure 3. Figure 4.

50%

1.3 V

Q

tPZL tPLZ

tPZH tPHZ

10%

90%

VCC

GND

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

Q

OUTPUT

ENABLE

50%

INPUT D

LATCH ENABLE

VCC

GND

VALID

th

tsu

50%

MC74HC373A

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6

TEST CIRCUITS

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 5. Figure 6.

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ AND tPZH.

1 kW

D0

3

DQ

LE

2

Q0

11

1

D1

4

DQ

LE

5

Q1

D2

7

DQ

LE

6

Q2

D3

8

DQ

LE

9

Q3

D4

13

DQ

LE

12

Q4

D5

14

DQ

LE

15

Q5

D6

17

DQ

LE

16

Q6

D7

18

DQ

LE

19

Q7

Figure 7. EXPANDED LOGIC DIAGRAM

MC74HC373A

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7

PACKAGE DIMENSIONS

PDIP−20

N SUFFIX

PLASTIC DIP PACKAGE

CASE 738−03

ISSUE E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

M

L

J20 PL

M

B

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A25.66 27.171.010 1.070

B6.10 6.600.240 0.260

C3.81 4.570.150 0.180

D0.39 0.550.015 0.022

G2.54 BSC0.100 BSC

J0.21 0.380.008 0.015

K2.80 3.550.110 0.140

L7.62 BSC0.300 BSC

M0 15 0 15

N0.51 1.010.020 0.040

____

E

1.27 1.770.050 0.070

1

11

10

20

−A−

SEATING

PLANE

K

N

FG

D20 PL

−T−

M

A

M

0.25 (0.010) T

E

B

C

F

1.27 BSC0.050 BSC

SOIC−20

DW SUFFIX

CASE 751D−05

ISSUE G

20

1

11

10

B20X

H10X

C

L

18X A1

A

SEATING

PLANE

q

hX 45_

E

D

M

0.25 M

B

M

0.25 S

AS

B

T

eT

B

A

DIM MIN MAX

MILLIMETERS

A2.35 2.65

A1 0.10 0.25

B0.35 0.49

C0.23 0.32

D12.65 12.95

E7.40 7.60

e1.27 BSC

H10.05 10.55

h0.25 0.75

L0.50 0.90

q0 7

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF B

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

__

MC74HC373A

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8

PACKAGE DIMENSIONS

TSSOP−20

DT SUFFIX

CASE 948E−02

ISSUE C

DIM

A

MIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B4.30 4.50 0.169 0.177

C1.20 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.27 0.37 0.011 0.015

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION:

MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE

MOLD FLASH, PROTRUSIONS OR GATE

BURRS. MOLD FLASH OR GATE BURRS

SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION

SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

ÍÍÍÍ

110

1120

PIN 1

IDENT

A

B

−T−

0.100 (0.004)

C

DGH

SECTION N−N

K

K1

JJ1

N

M

F

−W−

SEATING

PLANE

−V−

−U−

S

U

M

0.10 (0.004) V S

T

20X REFK

L

L/2

2X

S

U0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E 6.40 0.252

--- ---

S

U0.15 (0.006) T

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

MC74HC373A

http://onsemi.com

9

PACKAGE DIMENSIONS

SOEIAJ−20

F SUFFIX

CASE 967−01

ISSUE A

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.15 0.25 0.006 0.010

12.35 12.80 0.486 0.504

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 0.81 --- 0.032

A1

HE

Q1

LE

_10 _0

_10 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

HE

A1

LE

Q1

_

c

A

Z

D

E

20

110

11

b

M

0.13 (0.005)

e

0.10 (0.004)

VIEW P

DETAIL P

M

L

A

b

c

D

E

e

L

M

Z

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

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