LM3481QMM/NOPB - Texas Instruments

LM3481

VIN

ISEN

COMP

AGND

UVLO VCC

PGND

FA/SYNC/SD

VIN = 5V

VOUT = 12V

121 k:

82 nF

390 pF

22.6 k:RF2

20 k:

RF1

169 k:

RFA

90.9 k:

RSEN

20 m:

CSEN

1 nF

1 PF

CIN1, CIN2

150 PF

6.8 PH

IOUT = 1.8A

COUT1, COUT2

150 PF

C9 D1

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Folder

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Buy

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM3481

LM3481-Q1

SNVS346F –NOVEMBER 2007–REVISED NOVEMBER 2014

LM3481 / -Q1 High-Efficiency Controller for Boost, SEPIC and Flyback DC-DC Converters

1 Features

1• LM3481QMM are Automotive-Grade Products

That are AEC-Q100 Grade 1 Qualified (–40°C to

+125°C Operating Junction Temperature)

• 10-Lead VSSOP Package

• Internal Push-Pull Driver With 1-A Peak Current

Capability

• Current Limit and Thermal Shutdown

• Frequency Compensation Optimized With a

Capacitor and a Resistor

• Internal Softstart

• Current Mode Operation

• Adjustable Undervoltage Lockout With Hysteresis

• Pulse Skipping at Light Loads

• Key Specifications

– Wide Supply Voltage Range of 2.97 V to 48 V

– 100-kHz to 1-MHz Adjustable and

Synchronizable Clock Frequency

– ±1.5% (Over Temperature) Internal Reference

– 10-µA Shutdown Current (Over Temperature)

• Create a Custom Design Using the LM3481 with

the WEBENCH Power Designer

2 Applications

• Automotive Start-Stop Applications

• Automotive ADAS Driver Information

• One Cell/Two Cell Li-ion Battery Powered

Portable Bluetooth Audio Systems

• Notebooks, PDAs, Digital Cameras, and Other

Portable Applications

• Offline Power Supplies

• Set-Top Boxes

• Boost for Audio Amplifiers

3 Description

The LM3481 device is a versatile Low-Side N-FET

high-performance controller for switching regulators.

The device is designed for use in Boost, SEPIC and

Flyback converters and topologies requiring a low-

side FET as the primary switch. The LM3481 device

can be operated at very high switching frequencies to

reduce the overall solution size. The switching

frequency of the LM3481 device can be adjusted to

any value between 100kHz and 1MHz by using a

single external resistor or by synchronizing it to an

external clock. Current mode control provides

superior bandwidth and transient response in addition

to cycle-by-cycle current limiting. Current limit can be

programmed with a single external resistor.

The LM3481 device has built-in protection features

such as thermal shutdown, short-circuit protection

and overvoltage protection. Power-saving shutdown

mode reduces the total supply current to 5 µA and

allows power supply sequencing. Internal soft-start

limits the inrush current at start-up. Integrated current

slope compensation simplifies the design and, if

needed for specific applications, can be increased

using a single resistor.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LM3481 VSSOP (10) 3.00 mm × 3.00 mm

LM3481-Q1

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Figure 1. LM3481 Typical 5V to 12V Boost Converter Application

LM3481

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SNVS346F –NOVEMBER 2007–REVISED NOVEMBER 2014

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 Handling Ratings: LM3481........................................ 4

6.3 Handling Ratings: LM3481-Q1.................................. 4

6.4 Recommended Operating Ratings............................ 4

6.5 Thermal Information.................................................. 5

6.6 Electrical Characteristics........................................... 5

6.7 Typical Characteristics.............................................. 8

7 Detailed Description............................................ 11

7.1 Overview................................................................. 11

7.2 Functional Block Diagram....................................... 12

7.3 Feature Description................................................. 12

7.4 Device Functional Modes........................................ 18

8 Application and Implementation ........................ 19

8.1 Application Information............................................ 19

8.2 Typical Applications ................................................ 19

9 Power Supply Recommendations...................... 30

10 Layout................................................................... 30

10.1 Layout Guidelines ................................................. 30

10.2 Layout Example .................................................... 31

11 Device and Documentation Support................. 32

11.1 Documentation Support ........................................ 32

11.2 Related Links ........................................................ 32

11.3 Trademarks........................................................... 32

11.4 Electrostatic Discharge Caution............................ 32

11.5 Glossary................................................................ 32

12 Mechanical, Packaging, and Orderable

Information........................................................... 33

4 Revision History

Changes from Revision E (April 2012) to Revision F Page

• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device

Functional Modes,Application and Implementation section, Power Supply Recommendations section, Layout

section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information

section ................................................................................................................................................................................... 1

LM3481

VIN

ISEN

COMP

AGND

UVLO VCC

PGND

FA/SYNC/SD

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LM3481-Q1

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SNVS346F –NOVEMBER 2007–REVISED NOVEMBER 2014

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5 Pin Configuration and Functions

10-Pin

VSSOP Package

Top View

Pin Functions

PIN I/O DESCRIPTION

NO. NAME

1 ISEN A Current sense input pin. Voltage generated across an external sense resistor is fed into this pin.

2 UVLO A Under voltage lockout pin. A resistor divider from VIN to ground is connected to the UVLO pin. The

ratio of these resistances determine the input voltage which allows switching and the hysteresis to

disable switching.

3 COMP A Compensation pin. A resistor and capacitor combination connected to this pin provides

compensation for the control loop.

4 FB A Feedback pin. Inverting input of the error amplifier.

5 AGND G Analog ground pin. Internal bias circuitry reference. Should be connected to PGND at a single

point.

6 FA/SYNC/SD I/A Frequency adjust, synchronization, and shutdown pin. A resistor connected from this pin to ground

sets the oscillator frequency. An external clock signal at this pin will synchronize the controller to

the frequency of the clock. A high level on this pin for ≥30 µs will turn the device off and the device

will then draw 5 µA from the supply typically.

7 PGND G Power ground pin. External power circuitry reference. Should be connected to AGND at a single

point.

8 DR O Drive pin of the IC. The gate of the external MOSFET should be connected to this pin.

9 VCC O Driver supply voltage pin. A bypass capacitor must be connected from this pin to PGND. See

Driver Supply Capacitor Selection section. Do not bias externally.

10 VIN P Power supply input pin.

LM3481

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SNVS346F –NOVEMBER 2007–REVISED NOVEMBER 2014

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(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Recommended Operating Ratings indicates

conditions for which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications

and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions.

(2) Part is MSL1-260C qualified

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VIN Pin Voltage –0.4 50 V

FB Pin Voltage –0.4 6 V

FA/SYNC/SD Pin Voltage –0.4 6 V

COMP Pin Voltage –0.4 6 V

UVLO Pin Voltage –0.4 6 V

VCC Pin Voltage –0.4 6.5 V

DR Pin Voltage –0.4 6 V

ISEN Pin Voltage –400 600 mV

Peak Driver Output Current 1 A

Power Dissipation Internally Limited

Junction Temperature 150 °C

Lead Temperature

(only applies to

operating conditions) DGS Package 220 °C

Peak Body

Temperature (2) 260 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 Handling Ratings: LM3481 MIN MAX UNIT

Tstg Storage temperature range –65 150 °C

V(ESD) Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins(1) –2000 +2000 V

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins(2) –750 +750

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Handling Ratings: LM3481-Q1 MIN MAX UNIT

Tstg Storage temperature range –65 150 °C

V(ESD) Electrostatic discharge

Human body model (HBM), per AEC Q100-002(1) –2000 +2000

Charged device model (CDM), per

AEC Q100-011

Corner pins (1, 5, 6,

and 10) –750 +750

Other pins –750 +750

6.4 Recommended Operating Ratings MIN MAX UNIT

Supply Voltage 2.97 48 V

Junction Temperature Range –40 125 °C

Switching Frequency Range 100 1 kHz/MHz

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(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Thermal Information

THERMAL METRIC(1) LM3481

UNITVSSOP

10 PINS

RθJA Junction-to-ambient thermal resistance 157.3

°C/W

RθJC(top) Junction-to-case (top) thermal resistance 51.1

RθJB Junction-to-board thermal resistance 76.9

ψJT Junction-to-top characterization parameter 5.0

ψJB Junction-to-board characterization parameter 75.6

RθJC(bot) Junction-to-case (bottom) thermal resistance -

(1) The drive pin voltage, VDR, is equal to the input voltage when input voltage is less than 6 V. VDR is equal to 6 V when the input voltage

is greater than or equal to 6 V.

(2) For this test, the FA/SYNC/SD Pin is pulled to ground using a 40-kΩresistor.

6.6 Electrical Characteristics

VIN= 12 V, RFA= 40 kΩ, TJ= 25°C, unless otherwise indicated.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VFB Feedback Voltage VCOMP = 1.4 V, 2.97 ≤VIN ≤48 V 1.275 V

VCOMP = 1.4 V, 2.97 ≤VIN ≤48 V,

–40°C ≤TJ≤125°C 1.256 1.294

ΔVLINE Feedback Voltage Line Regulation 2.97 ≤VIN ≤48 V 0.003 %/V

ΔVLOAD Output Voltage Load Regulation IEAO Source/Sink ±0.5 %/A

VUVLOSEN Undervoltage Lockout Reference

Voltage

VUVLO Ramping Down 1.430 V

VUVLO Ramping Down, –40°C ≤TJ≤

125°C 1.345 1.517

IUVLO UVLO Source Current Enabled 5 µA

Enabled, –40°C ≤TJ≤125°C 3 6

VUVLOSD UVLO Shutdown Voltage 0.55 0.7 0.82 V

ICOMP COMP pin Current Sink VFB = 0V 640 µA

VCOMP VFB = 1.275V 1 V

fnom Nominal Switching Frequency RFA = 40 kΩ475 kHz

RFA = 40 kΩ, –40°C ≤TJ≤125°C 406 550

Vsync-HI Threshold for Synchronization on

FA/SYNC/SD pin Synchronization Voltage Rising 1.4 V

Vsync-LOW Threshold for Synchronization on

FA/SYNC/SD pin Synchronization Voltage Falling 0.7 V

RDS1 (ON) Driver Switch On Resistance (top) IDR = 0.2A, VIN= 5 V 4 Ω

RDS2 (ON) Driver Switch On Resistance (bottom) IDR = 0.2A 2 Ω

VDR (max) Maximum Drive Voltage Swing(1) VIN < 6V VIN V

VIN ≥6V 6

Dmax Maximum Duty Cycle RFA=40 kΩ81% 85%

tmin (on) Minimum On Time 250 363 ns

worst case over temperature 571 ns

ISUPPLY Supply Current (switching) See(2) 3.7 mA

See(2), –40°C ≤TJ≤125°C 5.0

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SNVS346F –NOVEMBER 2007–REVISED NOVEMBER 2014

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Electrical Characteristics (continued)

VIN= 12 V, RFA= 40 kΩ, TJ= 25°C, unless otherwise indicated.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(3) For this test, the FA/SYNC/SD Pin is pulled to 3 V using a 40-kΩresistor.

(4) The overvoltage protection is specified with respect to the feedback voltage. This is because the overvoltage protection tracks the

feedback voltage. The overvoltage threshold can be calculated by adding the feedback voltage (VFB) to the overvoltage protection

specification.

(5) The FA/SYNC/SD pin should be pulled to VIN through a resistor to turn the regulator off. The voltage on the FA/SYNC/SD pin must be

above the max limit for the Output = High longer than 30 µs to keep the regulator off and must be below the minimum limit for Output =

Low to keep the regulator on.

IQQuiescent Current in Shutdown Mode

VFA/SYNC/SD = 3 V(3), VIN = 12 V 9

µA

VFA/SYNC/SD = 3 V(3), VIN = 12 V,

–40°C ≤TJ≤125°C 15

VFA/SYNC/SD = 3 V(3), VIN = 5 V 5

VFA/SYNC/SD = 3 V(3), VIN = 5 V, –40°C

≤TJ≤125°C 10

VSENSE Current Sense Threshold Voltage 160 mV

–40°C ≤TJ≤125°C 100 190

VSC Over Load Current Limit Sense Voltage 220 mV

–40°C ≤TJ≤125°C 157 275

VSL Internal Compensation Ramp Voltage 90 mV

VOVP Output Over-voltage Protection (with

respect to feedback voltage)(4) VCOMP = 1.4 V 85 mV

VCOMP = 1.4 V, –40°C ≤TJ≤125°C 26 135

VOVP(HYS) Output Over-Voltage Protection

Hysteresis VCOMP = 1.4 V 70 mV

VCOMP = 1.4 V, –40°C ≤TJ≤125°C 28 106

Gm Error Amplifier Transconductance VCOMP = 1.4 V 450 µmho

VCOMP = 1.4 V, –40°C ≤TJ≤125°C 216 690

AVOL Error Amplifier Voltage Gain

VCOMP = 1.4 V, IEAO = 100 µA

(Source/Sink) 60 V/V

VCOMP = 1.4 V, IEAO = 100 µA

(Source/Sink), –40°C ≤TJ≤125°C 35 66

IEAO Error Amplifier Output Current (Source/

Sink)

Source, VCOMP = 1.4 V, VFB = 1.1 V 640 µA

Source, VCOMP = 1.4 V, VFB = 1.1 V,

–40°C ≤TJ≤125°C 475 837

Sink, VCOMP = 1.4 V, VFB = 1.4 V 65 µA

Sink, VCOMP = 1.4 V, VFB = 1.4 V,

–40°C ≤TJ≤125°C 31 100

VEAO Error Amplifier Output Voltage Swing

Upper Limit: VFB = 0 V, COMP Pin

Floating 2.70 V

Upper Limit: VFB = 0 V, COMP Pin

Floating, –40°C ≤TJ≤125°C 2.45 2.93

Lower Limit: VFB = 1.4 V 0.60 V

Lower Limit: VFB = 1.4 V, –40°C ≤TJ

≤125°C 0.32 0.90

tSS Internal Soft-Start Delay VFB = 1.2 V, COMP Pin Floating 8.7 15 21.3 ms

trDrive Pin Rise Time Cgs = 3000 pf, VDR = 0 V to 3 V 25 ns

tfDrive Pin Fall Time Cgs = 3000 pf, VDR = 3 V to 0 V 25 ns

VSD Shutdown signal

threshold(5)FA/SYNC/SD pin

Output = High (Shutdown) 1.31 V

Output = High (Shutdown), –40°C ≤

TJ≤125°C 1.40

Output = Low (Enable) 0.68 V

Output = Low (Enable), –40°C ≤TJ≤

125°C 0.40

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SNVS346F –NOVEMBER 2007–REVISED NOVEMBER 2014

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Electrical Characteristics (continued)

VIN= 12 V, RFA= 40 kΩ, TJ= 25°C, unless otherwise indicated.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISD Shutdown Pin Current FA/SYNC/SD

pin VSD = 5 V −1µA

VSD = 0 V 20

TSD Thermal Shutdown 165 °C

Tsh Thermal Shutdown Hysteresis 10 °C

LM3481

LM3481-Q1

SNVS346F –NOVEMBER 2007–REVISED NOVEMBER 2014

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6.7 Typical Characteristics

Unless otherwise specified, VIN = 12 V, TJ= 25°C.

Figure 3. Comp Pin Voltage vs. Load Current Figure 4. Switching Frequency vs. RFA

Figure 5. Efficiency vs. Load Current (3.3 VIN and 12 VOUT)Figure 6. Efficiency vs. Load Current (5 VIN and 12 VOUT)

Figure 7. Efficiency vs. Load Current (9 VIN and 12 VOUT)Figure 8. Frequency vs. Temperature

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Typical Characteristics (continued)

Unless otherwise specified, VIN = 12 V, TJ= 25°C.

Figure 9. COMP Pin Source Current vs. Temperature Figure 10. ISupplyvs. Input Voltage (Nonswitching)

Figure 11. ISupply vs. Input Voltage (Switching) Figure 12. Shutdown Threshold Hysteresis vs. Temperature

Figure 13. Drive Voltage vs. Input Voltage Figure 14. Short Circuit Protection vs. VIN

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SNVS346F –NOVEMBER 2007–REVISED NOVEMBER 2014

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Typical Characteristics (continued)

Unless otherwise specified, VIN = 12 V, TJ= 25°C.

Figure 15. Current Sense Threshold vs. Input Voltage Figure 16. Compensation Ramp Amplitude vs. Input Voltage

Figure 17. Minimum On-Time vs. Temperature

PWM

Comparator

Oscillator Sets

the RS Latch

PWM Comparator resets

the RS latch

Blank-Out prevents false

reset

VSL

Tmin (on) Blank-Out time

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7 Detailed Description

7.1 Overview

The LM3481 device uses a fixed frequency, Pulse Width Modulated (PWM), current mode control architecture. In

a typical application circuit, the peak current through the external MOSFET is sensed through an external sense

resistor. The voltage across this resistor is fed into the ISEN pin. This voltage is then level shifted and fed into the

positive input of the PWM comparator. The output voltage is also sensed through an external feedback resistor

divider network and fed into the error amplifier (EA) negative input (feedback pin, FB). The output of the error

amplifier (COMP pin) is added to the slope compensation ramp and fed into the negative input of the PWM

comparator.

At the start of any switching cycle, the oscillator sets the RS latch using the SET/Blank-out and switch logic

blocks. This forces a high signal on the DR pin (gate of the external MOSFET) and the external MOSFET turns

on. When the voltage on the positive input of the PWM comparator exceeds the negative input, the RS latch is

reset and the external MOSFET turns off.

The voltage sensed across the sense resistor generally contains spurious noise spikes, as shown in Figure 18.

These spikes can force the PWM comparator to reset the RS latch prematurely. To prevent these spikes from

resetting the latch, a blank-out circuit inside the IC prevents the PWM comparator from resetting the latch for a

short duration after the latch is set. This duration, called the blank-out time, is typically 250 ns and is specified as

tmin (on) in the Electrical Characteristics section.

Under extremely light load or no-load conditions, the energy delivered to the output capacitor when the external

MOSFET is on during the blank-out time is more than what is delivered to the load. An overvoltage comparator

inside the LM3481 prevents the output voltage from rising under these conditions by sensing the feedback (FB

pin) voltage and resetting the RS latch. The latch remains in a reset state until the output decays to the nominal

value. Thus the operating frequency decreases at light loads, resulting in excellent efficiency.

Figure 18. Basic Operation of the PWM Comparator

FA/SYNC/SD

COMP

ISEN

AGND PGND

VIN

Shutdown Detect

SYNC/Fixed

Frequency detect

Soft-start

Slope

Compensation

Thermal

Shutdown

Set/Blankout

Switch

Logic

Switch

Driver

1.275V

Reference

Oscillator

220 mV

Level Shifter

One Shot

Bias

Voltages

Overvoltage

Comparator

Short-circuit

Comparator

Ramp

Adjust

V-I

Converter

I-V

Converter

PWM

Comparator R S

VCC

UVLO

40 éA

Vfb + Vovp -

LM3481

LM3481-Q1

SNVS346F –NOVEMBER 2007–REVISED NOVEMBER 2014

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7.2 Functional Block Diagram

Figure 19. LM3481 Simplified Functional Block Diagram

7.3 Feature Description

7.3.1 Overvoltage Protection

The LM3481 has overvoltage protection (OVP) for the output voltage. OVP is sensed at the feedback pin (FB). If

at anytime the voltage at the feedback pin rises to VFB + VOVP, OVP is triggered. See the Electrical

Characteristics section for limits on VFB and VOVP.

OVP will cause the drive pin (DR) to go low, forcing the power MOSFET off. With the MOSFET off, the output

voltage will drop. The LM3481 will begin switching again when the feedback voltage reaches VFB + (VOVP -

VOVP(HYS)). See the Electrical Characteristics section for limits on VOVP(HYS). The Error Amplifier is operationnal

during OVP events.

7.3.2 Bias Voltage

The internal bias of the LM3481 comes from either the internal bias voltage generator as shown in the block

diagram or directly from the voltage at the VIN pin. At input voltages lower than 6 V the internal IC bias is the

input voltage and at voltages above 6 V the internal bias voltage generator of the LM3481 provides the bias. The

voltage for the gate driver is output on the VCC pin for compensation by an external capacitor (0.47µF to 4.7µF

depending on the FET requirements). Biasing the VCC pin by an external voltage source should not be

attempted.

PWM

Comparator

Control Signal

-M2

DTS(1-D)TS

MC = 0

Steady State

Signal Vsamp

Perturbed Signal

Vsamp1

Vsamp0

'Vsamp1 = - M2

1-D 'Vsamp0

'Vsamp0 = -

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Feature Description (continued)

7.3.3 Slope Compensation Ramp

The LM3481 uses a current mode control scheme. The main advantages of current mode control are inherent

cycle-by-cycle current limit for the switch and simpler control loop characteristics. It is easy to parallel power

stages using current mode control because current sharing is automatic. However there is a natural instability

that will occur for duty cycles, D, greater than 50% if additional slope compensation is not addressed as

described below.

The current mode control scheme samples the inductor current, IL, and compares the sampled signal, Vsamp, to a

internally generated control signal, Vc. The current sense resistor, RSEN, as shown in Figure 23, converts the

sampled inductor current, IL, to the voltage signal, Vsamp, that is proportional to ILsuch that:

Vsamp = ILx RSEN (1)

The rising and falling slopes, M1and −M2respectively, of Vsamp are also proportional to the inductor current rising

and falling slopes, Mon and −Moff respectively. Where Mon is the inductor slope during the switch on-time and

−Moff is the inductor slope during the switch off-time and are related to M1and −M2by:

M1= Mon x RSEN (2)

−M2=−Moff x RSEN (3)

For the boost topology:

Mon = VIN / L (4)

−Moff = (VIN −VOUT) / L (5)

M1= [VIN / L] x RSEN (6)

−M2= [(VIN −VOUT) / L] x RSEN (7)

M2= [(VOUT −VIN) / L] x RSEN (8)

Current mode control has an inherent instability for duty cycles greater than 50%, as shown in Figure 20, where

the control signal slope, MC, equals zero. In Figure 20, a small increase in the load current causes the sampled

signal to increase by ΔVsamp0. The effect of this load change, ΔVsamp1, at the end of the first switching cycle is :

(9)

From Equation 9, when D > 0.5, ΔVsamp1 will be greater than ΔVsamp0. In other words, the disturbance is

divergent. So a very small perturbation in the load will cause the disturbance to increase. To ensure that the

perturbed signal converges we must maintain:

(10)

Figure 20. Subharmonic Oscillation for D>0.5

Control Signal

Compensation Ramp

without RSL

-MC

VSL

'VSL

Control Signal

Compensation Ramp

with RSL

M2 - MC

M1 + MC

M2 - MC

'Vsamp1 = - M1 + MC

'Vsamp0

PWM

Comparator

Control Signal

Compensation Ramp

-M2

-MC

DTS(1-D)TS

'Vsamp1

'Vsamp0

Steady State

Signal Vsamp

Perturbed Signal

VSL Control

Signal

Vsamp

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Feature Description (continued)

Figure 21. Compensation Ramp Avoids Subharmonic Oscillation

To prevent the subharmonic oscillations, a compensation ramp is added to the control signal, as shown in

Figure 21.

With the compensation ramp, ΔVsamp1 and the convergence criteria are expressed by,

(11)

(12)

The compensation ramp has been added internally in the LM3481. The slope of this compensation ramp has

been selected to satisfy most applications, and it's value depends on the switching frequency. This slope can be

calculated using the formula:

MC= VSL x fS(13)

In Equation 13, VSL is the amplitude of the internal compensation ramp and fSis the controller's switching

frequency. Limits for VSL have been specified in the Electrical Characteristics section.

To provide the user additional flexibility, a patented scheme has been implemented inside the IC to increase the

slope of the compensation ramp externally, if the need arises. Adding a single external resistor, RSL(as shown in

Figure 23) increases the amplitude of the compensation ramp as shown in Figure 22.

Figure 22. Additional Slope Compensation Added Using External Resistor RSL

Where,

ΔVSL = K x RSL (14)

K = 40 µA typically and changes slightly as the switching frequency changes. Figure 24 shows the effect the

current K has on ΔVSLand different values of RSL as the switching frequency changes.

A more general equation for the slope compensation ramp, MC, is shown below to include ΔVSL caused by the

resistor RSL.

MC= (VSL +ΔVSL) x fS(15)

RFA = fS

22 x 103- 5.74

LM3481

ISEN

RSEN

VIN

COUT

VOUT

RSL

CSEN

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Feature Description (continued)

It is good design practice to only add as much slope compensation as needed to avoid subharmonic oscillation.

Additional slope compensation minimizes the influence of the sensed current in the control loop. With very large

slope compensation the control loop characteristics are similar to a voltage mode regulator which compares the

error voltage to a saw tooth waveform rather than the inductor current.

Figure 23. Increasing the Slope of the Compensation Ramp

Figure 24. ΔVSL vs RSL

7.3.4 Frequency Adjust, Synchronization, and Shutdown

The switching frequency of the LM3481 can be adjusted between 100 kHz and 1 MHz using a single external

resistor. This resistor must be connected between the FA/SYNC/SD pin and ground, as shown in Figure 25.

Refer to the Typical Characteristics to determine the value of the resistor required for a desired switching

frequency.

Equation 16 can also be used to estimate the frequency adjust resistor.

Where fSis in kHz and RFA in kΩ.

(16)

FA/SYNC/SD >1.3V

10 k:

RFA

MOSFET State

On-Normal Operation

OFF- Shutdown

LM3481

FA/SYNC/SD

Freq. clock

100 kHz to 1 MHz

RFA

LM3481

FA/SYNC/SD

RFA

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Feature Description (continued)

The LM3481 can be synchronized to an external clock. The external clock must be connected between the

FA/SYNC/SD pin and ground, as shown in Figure 26. The frequency adjust resistor may remain connected while

synchronizing a signal, therefore if there is a loss of signal, the switching frequency will be set by the frequency

adjust resistor.

It is also necessary to have the width of the synchronization pulse wider than the duty cycle of the converter and

to have the synchronization pulse width ≥300 ns.

The FA/SYNC/SD pin also functions as a shutdown pin. If a high signal (refer to the Electrical Characteristics

section for definition of high signal) appears on the FA/SYNC/SD pin, the LM3481 stops switching and goes into

a low current mode. The total supply current of the IC reduces to 5 µA, typically, under these conditions.

Figure 27 and Figure 28 show an implementation of a shutdown function when operating in frequency adjust

mode and synchronization mode, respectively. In frequency adjust mode, connecting the FA/SYNC/SD pin to

ground forces the clock to run at a certain frequency. Pulling this pin high shuts down the IC. In frequency adjust

or synchronization mode, a high signal for more than 30 µs shuts down the IC.

Figure 25. Frequency Adjust

Figure 26. Frequency Synchronization

Figure 27. Shutdown Operation in Frequency Adjust Mode

UVLO

VIN

IUVLO

VUVLOSEN

R7 =

©-1

VEN

1.43V

R8 =

VEN ± 1.43V

IUVLO x

1.43V

FA/SYNC/SD 40 k:

30 Ps

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Feature Description (continued)

Figure 28. Shutdown Operation in Synchronization Mode

7.3.5 Undervoltage Lockout (UVLO) Pin

The UVLO pin provides user programmable enable and shutdown thresholds. The UVLO pin is compared to an

internal reference of 1.43 V (typical), and a resistor divider programs the enable threshold, VEN. When the IC is

enabled, a 5-μA current is sourced out of the UVLO pin, which effectively causes a hysteresis, and the UVLO

shutdown threshold, VSH, is now lower than the enable threshold. Setting these thresholds requires two resistors

connected from the VIN pin to the UVLO pin and from the UVLO pin to GND (see Figure 29). Select the desired

enable, VEN, and UVLO shutdown, VSH, threshold voltages and use the Equation 17 and Equation 18 to

determine the resistance values:

(17)

(18)

Figure 29. UVLO Pin Resistor Divider

If the system is designed to work over wide input voltages, the voltage at the UVLO pin could exceed the voltage

limit for the UVLO pin. In this case a zener diode can be connected between the UVLO pin and ground to

prevent the UVLO voltage from rising above the maximum value.

If the UVLO pin function is not desired, select R8 and R7 of equal magnitude greater than 100 kΩ. This will allow

VIN to be in control of the UVLO thresholds. The UVLO pin may also be used to implement the enable/disable

function. If a signal pulls the UVLO pin below the 1.43 V (typical) threshold, the converter will be disabled.

7.3.6 Short-Circuit Protection

When the voltage across the sense resistor (measured on the ISEN Pin) exceeds 220 mV, short-circuit current

limit gets activated. A comparator inside the LM3481 reduces the switching frequency by a factor of 8 and

maintains this condition until the short is removed.

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7.4 Device Functional Modes

The device is set to run as soon as the input voltage crosses above the UVLO set point and at a frequency set

according to the FA/SYNC/SD pin pull-down resistor or to run at a frequency set by the waveform applied to the

FA/SYNC/SD pin.

If the FA/SYNC/SD pin is pulled high, the LM3481 enters shut-down mode.

VOUT + VD1 - VQVIN - VQ

1-D

LM3481

VIN

ISEN

COMP

AGND

UVLO VCC

PGND

FA/SYNC/SD

VIN = 5V

VOUT = 12V

121 k:

82 nF

390 pF

22.6 k:RF2

20 k:

RF1

169 k:

RFA

90.9 k:

RSEN

20 m:

CSEN

1 nF

1 PF

CIN1, CIN2

150 PF

6.8 PH

IOUT = 1.8A

COUT1, COUT2

150 PF

C9 D1

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM3481 may be operated in either continuous or discontinuous conduction mode. The following applications

are designed for continuous conduction operation. This mode of operation has higher efficiency and lower EMI

characteristics than the discontinuous mode.

8.2 Typical Applications

8.2.1 Boost Converter

Figure 30. Typical High Efficiency Step-Up (Boost) Converter using LM3481

The most common topology for the LM3481 is the boost or step-up topology. The boost converter converts a low

input voltage into a higher output voltage. The basic configuration for a boost regulator is shown in Figure 31. In

continuous conduction mode (when the inductor current never reaches zero at steady state), the boost regulator

operates in two cycles. In the first cycle of operation, MOSFET Q is turned on and energy is stored in the

inductor. During this cycle, diode D1 is reverse biased and load current is supplied by the output capacitor, COUT.

In the second cycle, MOSFET Q is off and the diode is forward biased. The energy stored in the inductor is

transferred to the load and output capacitor. The ratio of these two cycles determines the output voltage. The

output voltage is defined as:

(19)

(ignoring the voltage drop across the MOSFET and the diode), or

(20)

where D is the duty cycle of the switch, VD1 is the forward voltage drop of the diode, and VQis the drop across

the MOSFET when it is on. The following sections describe selection of components for a boost converter.

+ +

PWM

VOUT

VIN

RLOAD

VOUT

VIN

RLOAD

VOUT

COUT

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Typical Applications (continued)

A. First Cycle of Operation

B. Second Cycle of Operation

Figure 31. Simplified Boost Converter Diagram

8.2.1.1 Design Requirements

To properly size the components for the application, the designer needs the following parameters: Input voltage

range, output voltage, output current range and required switching frequency. These four main parameters will

affect the choices of component available to achieve a proper system behavior.

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Custom Design with WEBENCH Tools

Click here to create a custom design using the LM3481 device with the WEBENCH®Power Designer.

1. Start by entering your VIN, VOUT and IOUT requirements.

2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and

compare this design with other possible solutions from Texas Instruments.

3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real

time pricing and component availability.

4. In most cases, you will also be able to:

– Run electrical simulations to see important waveforms and circuit performance,

– Run thermal simulations to understand the thermal performance of your board,

– Export your customized schematic and layout into popular CAD formats,

– Print PDF reports for the design, and share your design with colleagues.

5. Get more information about WEBENCH tools at www.ti.com/webench.

8.2.1.2.2 Power Inductor Selection

The inductor is one of the two energy storage elements in a boost converter. Figure 32 shows how the inductor

current varies during a switching cycle. The current through an inductor is quantified as:

(21)

'iLDVIN

2LfS

IL =IOUT

1-D

t (s)

IL_AVG

ISW_AVG

D*Ts Ts

IL (A)

ID (A) (a)

(b)

t (s)

D*Ts Ts

ISW (A)

(c)

ID_AVG

= IOUT_AVG

-VOUT

VIN

-VOUT

VIN

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Typical Applications (continued)

Figure 32. (a) Inductor Current (b) Diode Current (c) Switch Current

If VL(t) is constant, diL(t)/dt must be constant. Hence, for a given input voltage and output voltage, the current in

the inductor changes at a constant rate.

The important quantities in determining a proper inductance value are IL(the average inductor current) and ΔiL

(the inductor current ripple difference between the peak inductor current and the average inductor current). If ΔiL

is larger than IL, the inductor current drops to zero for a portion of the cycle and the converter operates in

discontinuous conduction mode. If ΔiLis smaller than IL, the inductor current stays above zero and the converter

operates in continuous conduction mode. All the analysis in this data sheet assumes operation in continuous

conduction mode. To operate in continuous conduction mode, the following conditions must be met:

IL>ΔiL(22)

(23)

(24)

Choose the minimum IOUT to determine the minimum L. A common choice is to set (2 x ΔiL) to 30% of IL.

Choosing an appropriate core size for the inductor involves calculating the average and peak currents expected

through the inductor. In a boost converter,

(25)

IL_peak = IL(max) + ΔiL(max) (26)

(27)

VOUT

ISEN

COUT

RF2

VIN

LM3481

RSEN

RF1

RSEN = VSENSE - (D x VSL)

IOUT(max)

(1-D) +(D x VIN)

(2 x fS x L)

Isw(peak) = IOUT(max)

(1-D) +(D x VIN)

(2 x fS x L)

VOUT = 1.275 (1+ RF1

RF2)

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Typical Applications (continued)

A core size with ratings higher than these values should be chosen. If the core is not properly rated, saturation

will dramatically reduce overall efficiency.

The LM3481 can be set to switch at very high frequencies. When the switching frequency is high, the converter

can operate with very small inductor values. With a small inductor value, the peak inductor current can be

extremely higher than the output currents, especially under light load conditions.

The LM3481 senses the peak current through the switch. The peak current through the switch is the same as the

peak current calculated above.

8.2.1.2.3 Programming the Output Voltage and Output Current

The output voltage can be programmed using a resistor divider between the output and the feedback pins, as

shown in Figure 33. The resistors are selected such that the voltage at the feedback pin is 1.275 V. RF1 and RF2

can be selected using the equation,

(28)

A 100-pF capacitor may be connected between the feedback and ground pins to reduce noise.

The maximum amount of current that can be delivered at the output can be controlled by the sense resistor,

RSEN. Current limit occurs when the voltage that is generated across the sense resistor equals the current sense

threshold voltage, VSENSE. Limits for VSENSE have been specified in the Electrical Characteristics section. This can

be expressed as:

Isw(peak) x RSEN = VSENSE- D x VSL (29)

The peak current through the switch is equal to the peak inductor current.

Isw(peak) = IL(max) + ΔiL(30)

Therefore for a boost converter,

(31)

Combining the two equations yields an expression for RSEN,

(32)

Evaluate RSEN at the maximum and minimum VIN values and choose the smallest RSEN calculated.

Figure 33. Adjusting the Output Voltage

VIN(MIN)

VOUT

DMAX =

IOUT(max) 2DMAXRDS(ON)

PCOND(MAX) =1 - DMAX

RSEN = IOUT(max)

(1-D) +(D x VIN)

(2 x fS x L)

VSENSE - D x (VSL+'VSL)

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Typical Applications (continued)

8.2.1.2.4 Current Limit With Additional Slope Compensation

If an external slope compensation resistor is used (see Figure 23) the internal control signal will be modified and

this will have an effect on the current limit.

If RSL is used, then this will add to the existing slope compensation. The command voltage, VCS, will then be

given by:

VCS = VSENSE −D x (VSL +ΔVSL) (33)

Where VSENSE is a defined parameter in the Electrical Characteristics section and ΔVSL is the additional slope

compensation generated as discussed in the Slope Compensation Ramp section. This changes the equation for

RSEN to:

(34)

Note that because ΔVSL = RSL x K as defined earlier, RSLcan be used to provide an additional method for setting

the current limit. In some designs RSL can also be used to help filter noise to keep the ISEN pin quiet.

8.2.1.2.5 Power Diode Selection

Observation of the boost converter circuit shows that the average current through the diode is the average load

current, and the peak current through the diode is the peak current through the inductor. The diode should be

rated to handle more than the inductor peak current. The peak diode current can be calculated using the formula:

ID(Peak) = [IOUT/ (1−D)] + ΔiL(35)

In Equation 35, IOUT is the output current and ΔiLhas been defined in Figure 32.

The peak reverse voltage for a boost converter is equal to the regulator output voltage. The diode must be

capable of handling this peak reverse voltage. To improve efficiency, a low forward drop Schottky diode is

recommended.

8.2.1.2.6 Power MOSFET Selection

The drive pin, DR, of the LM3481 must be connected to the gate of an external MOSFET. In a boost topology,

the drain of the external N-Channel MOSFET is connected to the inductor and the source is connected to the

ground. The drive pin voltage, VDR, depends on the input voltage (see Typical Characteristics). In most

applications, a logic level MOSFET can be used. For very low input voltages, a sub-logic level MOSFET should

be used.

The selected MOSFET directly controls the efficiency. The critical parameters for selection of a MOSFET are:

• Minimum threshold voltage, VTH(MIN)

• On-resistance, RDS(ON)

• Total gate charge, Qg

• Reverse transfer capacitance, CRSS

• Maximum drain to source voltage, VDS(MAX)

The off-state voltage of the MOSFET is approximately equal to the output voltage. VDS(MAX) of the MOSFET must

be greater than the output voltage. The power losses in the MOSFET can be categorized into conduction losses

and ac switching or transition losses. RDS(ON) is needed to estimate the conduction losses. The conduction loss,

PCOND, is the I2R loss across the MOSFET. The maximum conduction loss is given by:

(36)

where DMAX is the maximum duty cycle.

(37)

At high switching frequencies the switching losses may be the largest portion of the total losses.

'iLDVIN

2LfS

VIN VIN

RIN

CIN

CBYPASS

LM3481

ICIN(RMS) ='iL/3(VOUT - VIN)VIN

=VOUTLfS

RGate

tLH = VDR - Vgsth

Qgs

Qgd + x

PSW = ILmax x Vout

2x fSW x (tLH + tHL)

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Typical Applications (continued)

The switching losses are very difficult to calculate due to changing parasitics of a given MOSFET in operation.

Often, the individual MOSFET datasheet does not give enough information to yield a useful result. Equation 38

and Equation 39 give a rough idea how the switching losses are calculated:

(38)

(39)

8.2.1.2.7 Input Capacitor Selection

Due to the presence of an inductor at the input of a boost converter, the input current waveform is continuous

and triangular, as shown in Figure 32. The inductor ensures that the input capacitor sees fairly low ripple

currents. However, as the input capacitor gets smaller, the input ripple goes up. The rms current in the input

capacitor is given by:

(40)

The input capacitor should be capable of handling the rms current. Although the input capacitor is not as critical

in a boost application, low values can cause impedance interactions. Therefore a good quality capacitor should

be chosen in the range of 100 µF to 200 µF. If a value lower than 100 µF is used, then problems with impedance

interactions or switching noise can affect the LM3481. To improve performance, especially with VIN below 8 V, it

is recommended to use a 20Ωresistor at the input to provide a RC filter. This resistor is placed in series with the

VIN pin with only a bypass capacitor attached to the VIN pin directly (see Figure 34). A 0.1-µF or 1-µF ceramic

capacitor is necessary in this configuration. The bulk input capacitor and inductor will connect on the other side

of the resistor with the input power supply.

Figure 34. Reducing IC Input Noise

8.2.1.2.8 Output Capacitor Selection

The output capacitor in a boost converter provides all the output current when the inductor is charging. As a

result it sees very large ripple currents. The output capacitor should be capable of handling the maximum rms

current. The rms current in the output capacitor is:

(41)

Where

(42)

and D, the duty cycle is equal to (VOUT −VIN)/VOUT.

The ESR and ESL of the output capacitor directly control the output ripple. Use capacitors with low ESR and ESL

at the output for high efficiency and low ripple voltage. Surface mount tantalums, surface mount polymer

electrolytic and polymer tantalum, Sanyo- OSCON, or multi-layer ceramic capacitors are recommended at the

output.

8.2.1.2.9 Driver Supply Capacitor Selection

A good quality ceramic bypass capacitor must be connected from the VCC pin to the PGND pin for proper

operation. This capacitor supplies the transient current required by the internal MOSFET driver, as well as

filtering the internal supply voltage for the controller. A value of between 0.47 µF and 4.7 µF is recommended.

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Typical Applications (continued)

8.2.1.2.10 Compensation

For detailed explanation on how to select the right compensation components to attach to the compensation pin

for a boost topology please see AN-1286 Compensation for the LM3478 Boost Controller (SNVA067). When

calculating the Error Amplifier DC gain, AEA, ROUT = 152 kΩfor the LM3481.

8.2.1.3 Application Curve

Figure 35. Start-Up Pattern for a 5-Vin, 12-Vout Boost Converter Using LM3481 Boost Evaluation Module

(C1: Inductor Current, C2: Vin, C3:Vout)

LM3481

VIN

ISEN

COMP

AGND

UVLO VCC

PGND

FA/SYNC/SD

VIN = 3.0V to 24V

VOUT = 5V, 1A

CIN

15 PF, 35V x2

COUT

100 PF, 10V

1 PF, ceramic

RSEN

0.05:

10 PH

0.47 µFMBRS130LT3

RFA

40 k:

CSEN

1 nF

IRF7807

4.7 k:

0.1 PF

RF1

60 k:

RF2

20 k:

10 k:

5.1V

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Typical Applications (continued)

8.2.2 Typical SEPIC Converter

Figure 36. Typical SEPIC Converter using LM3481

Because the LM3481 controls a low-side N-Channel MOSFET, it can also be used in SEPIC (Single Ended

Primary Inductance Converter) applications. An example of SEPIC using the LM3481 is shown in Figure 36. As

shown in Figure 36, the output voltage can be higher or lower than the input voltage. The SEPIC uses two

inductors to step-up or step-down the input voltage. The inductors L1 and L2 can be two discrete inductors or

two windings of a coupled transformer because equal voltages are applied across the inductor throughout the

switching cycle. Using two discrete inductors allows use of catalog magnetics, as opposed to a custom

transformer. The input ripple can be reduced along with size by using the coupled windings of transformer for L1

and L2.

Due to the presence of the inductor L1 at the input, the SEPIC inherits all the benefits of a boost converter. One

main advantage of SEPIC over a boost converter is the inherent input to output isolation. The capacitor CS

isolates the input from the output and provides protection against shorted or malfunctioning load. Hence, the

SEPIC is useful for replacing boost circuits when true shutdown is required. This means that the output voltage

falls to 0V when the switch is turned off. In a boost converter, the output can only fall to the input voltage minus a

diode drop.

The duty cycle of a SEPIC is given by:

(43)

In Equation 43, VQis the on-state voltage of the MOSFET, Q1, and VDIODE is the forward voltage drop of the

diode.

8.2.2.1 Design Requirements

To properly size the components for the application, the designer needs the following parameters: Input voltage

range, output voltage, output current range and required switching frequency. These four main parameters will

affect the choices of component available to achieve a proper system behavior.

8.2.2.2 Detailed Design Procedure

8.2.2.2.1 Power MOSFET Selection

As in a boost converter, the parameters governing the selection of the MOSFET are the minimum threshold

voltage, VTH(MIN), the on-resistance, RDS(ON), the total gate charge, Qg, the reverse transfer capacitance, CRSS,

and the maximum drain to source voltage, VDS(MAX). The peak switch voltage in a SEPIC is given by:

VSW(PEAK) = VIN + VOUT + VDIODE (44)

The selected MOSFET should satisfy the condition:

VDS(MAX) > VSW(PEAK) (45)

'VOUT = IOUT

1-D +

'IL2

( ) ESR

L2 > (VIN - VQ)D

2IOUTfS

L1 > (VIN - VQ)(1-D)

2IOUTfS

ISWPEAK = IL1(AVG) + IOUT +'IL1 + 'IL2

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Typical Applications (continued)

The peak switch current is given by:

(46)

Where ΔIL1 and ΔIL2 are the peak-to-peak inductor ripple currents of inductors L1 and L2 respectively.

The rms current through the switch is given by:

(47)

8.2.2.2.2 Power Diode Selection

The Power diode must be selected to handle the peak current and the peak reverse voltage. In a SEPIC, the

diode peak current is the same as the switch peak current. The off-state voltage or peak reverse voltage of the

diode is VIN + VOUT. Similar to the boost converter, the average diode current is equal to the output current.

Schottky diodes are recommended.

8.2.2.2.3 Selection of Inductors L1 and L2

Proper selection of the inductors L1 and L2 to maintain constant current mode requires calculations of the

following parameters.

Average current in the inductors:

(48)

IL2AVE = IOUT (49)

Peak-to-peak ripple current, to calculate core loss if necessary:

(50)

(51)

Maintaining the condition IL>ΔIL/2 to ensure continuous conduction mode yields the following minimum values

for L1 and L2:

(52)

(53)

Peak current in the inductor, to ensure the inductor does not saturate:

(54)

(55)

IL1PK must be lower than the maximum current rating set by the current sense resistor.

The value of L1 can be increased above the minimum recommended value to reduce input ripple and output

ripple. However, once ΔIL1 is less than 20% of IL1AVE, the benefit to output ripple is minimal.

By increasing the value of L2 above the minimum recommendation, ΔIL2 can be reduced, which in turn will

reduce the output ripple voltage:

(56)

where ESR is the effective series resistance of the output capacitor.

ICIN(RMS) ='IL1/12 VIN - VQ

(L1)fS

CS tL1 IOUT2

(VIN - VQ)2

'IL1 =(VIN - VQ) D

(L1)fS

CS'VS2 = (L1)'IL12

ISWPEAK

VSENSE - D x (VSL+'VSL)

RSEN =

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If L1 and L2 are wound on the same core, then L1 = L2 = L. All the equations above will hold true if the

inductance is replaced by 2L. A good choice for transformer with equal turns is Coiltronics CTX series Octopack.

8.2.2.2.4 Sense Resistor Selection

The peak current through the switch, ISWPEAK, can be adjusted using the current sense resistor, RSEN, to provide

a certain output current. Resistor RSEN can be selected using the formula:

(57)

8.2.2.2.5 SEPIC Capacitor Selection

The selection of SEPIC capacitor, CS, depends on the rms current. The rms current of the SEPIC capacitor is

given by:

(58)

The SEPIC capacitor must be rated for a large ACrms current relative to the output power. This property makes

the SEPIC much better suited to lower power applications where the rms current through the capacitor is small

(relative to capacitor technology). The voltage rating of the SEPIC capacitor must be greater than the maximum

input voltage. Tantalum capacitors are the best choice for SMT, having high rms current ratings relative to size.

Ceramic capacitors could be used, but the low C values will tend to cause larger changes in voltage across the

capacitor due to the large currents, and high C value ceramics are expensive. Electrolytics work well for through

hole applications where the size required to meet the rms current rating can be accommodated. There is an

energy balance between CSand L1, which can be used to determine the value of the capacitor. The basic

energy balance equation is:

(59)

Where

(60)

is the ripple voltage across the SEPIC capacitor, and

(61)

is the ripple current through the inductor L1. The energy balance equation can be solved to provide a minimum

value for CS:

(62)

8.2.2.2.6 Input Capacitor Selection

Similar to a boost converter, the SEPIC has an inductor at the input. Hence, the input current waveform is

continuous and triangular. The inductor ensures that the input capacitor sees fairly low ripple currents. However,

as the input capacitor gets smaller, the input ripple goes up. The rms current in the input capacitor is given by:

(63)

The input capacitor should be capable of handling the rms current. Although the input capacitor is not as critical

in a SEPIC application, low values can cause impedance interactions. Therefore a good quality capacitor should

be chosen in the range of 100 µF to 200 µF. If a value lower than 100 µF is used, then problems with impedance

interactions or switching noise can affect the LM3481. To improve performance, especially with VIN below 8 V, it

is recommended to use a 20Ωresistor at the input to provide a RC filter. This resistor is placed in series with the

VIN pin with only a bypass capacitor attached to the VIN pin directly (see Figure 34). A 0.1 µF or 1 µF ceramic

capacitor is necessary in this configuration. The bulk input capacitor and inductor will connect on the other side

of the resistor with the input power supply.

IRMS = ISWPEAK2 - ISWPEAK ('IL1 + 'IL2) +('IL1 + 'IL2)2

3(1-D) - IOUT2

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SNVS346F –NOVEMBER 2007–REVISED NOVEMBER 2014

Product Folder Links: LM3481 LM3481-Q1

Typical Applications (continued)

8.2.2.2.7 Output Capacitor Selection

The output capacitor of the SEPIC sees very large ripple currents similar to the output capacitor of a boost

converter. The rms current through the output capacitor is given by:

(64)

The ESR and ESL of the output capacitor directly control the output ripple. Use capacitors with low ESR and ESL

at the output for high efficiency and low ripple voltage. Surface mount tantalums, surface mount polymer

electrolytic and polymer tantalum, Sanyo- OSCON, or multi-layer ceramic capacitors are recommended at the

output for low ripple.

8.2.2.3 Application Curve

Figure 37. Start-Up Pattern for a 5-Vin, 12-Vout SEPIC Converter on LM3481 SEPIC Evaluation Module

(C2: Vin, C3:Vout)

LM3481

LM3481-Q1

SNVS346F –NOVEMBER 2007–REVISED NOVEMBER 2014

www.ti.com

Product Folder Links: LM3481 LM3481-Q1

9 Power Supply Recommendations

The LM3481 is designed to operate from various DC power supply including a car battery. If so, VIN input should

be protected from reversal voltage and voltage dump over 48 Volts. The impedance of the input supply rail

should be low enough that the input current transient does not cause drop below VIN UVLO level. If the input

supply is connected by using long wires, additional bulk capacitance may be required in addition to normal input

capacitor.

10 Layout

10.1 Layout Guidelines

Good board layout is critical for switching controllers such as the LM3481. First the ground plane area must be

sufficient for thermal dissipation purposes and second, appropriate guidelines must be followed to reduce the

effects of switching noise. Switch mode converters are very fast switching devices. In such devices, the rapid

increase of input current combined with the parasitic trace inductance generates unwanted Ldi/dt noise spikes.

The magnitude of this noise tends to increase as the output current increases. This parasitic spike noise may

turn into electromagnetic interference (EMI), and can also cause problems in device performance. Therefore,

care must be taken in layout to minimize the effect of this switching noise. The current sensing circuit in current

mode devices can be easily effected by switching noise. This noise can cause duty cycle jitter which leads to

increased spectral noise. Although the LM3481 has 250 ns blanking time at the beginning of every cycle to

ignore this noise, some noise may remain after the blanking time.

The most important layout rule is to keep the AC current loops as small as possible. Figure 38 shows the current

flow of a boost converter. The top schematic shows a dotted line which represents the current flow during on-

state and the middle schematic shows the current flow during off-state. The bottom schematic shows the currents

we refer to as AC currents. These currents are the most critical currents because current is changing in very

short time periods. The dotted lined traces of the bottom schematic are the once to make as short as possible.

Figure 38. Current Flow in a Boost Application

The PGND and AGND pins have to be connected to the same ground very close to the IC. To avoid ground loop

currents attach all the grounds of the system only at one point.

A ceramic input capacitor should be connected as close as possible to the Vin pin and grounded close to the

GND pin.

For a layout example please see AN-2094 LM3481 SEPIC Evaluation Board (SNVA461). For more information

about layout in switch mode power supplies refer to AN-1229 SIMPLE SWITCHER® PCB Layout Guidelines

(SNVA054).

Rsense

GND IN+OUT+

COMP

UVLO

Isense

FA LM3481

LM3481

LM3481-Q1

www.ti.com

SNVS346F –NOVEMBER 2007–REVISED NOVEMBER 2014

Product Folder Links: LM3481 LM3481-Q1

10.2 Layout Example

Figure 39. Typical Layout for a Boost Converter

LM3481

LM3481-Q1

SNVS346F –NOVEMBER 2007–REVISED NOVEMBER 2014

www.ti.com

Product Folder Links: LM3481 LM3481-Q1

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Custom Design with WEBENCH Tools

Click here to create a custom design using the LM3481 device with the WEBENCH®Power Designer.

1. Start by entering your VIN, VOUT and IOUT requirements.

2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and

compare this design with other possible solutions from Texas Instruments.

3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real

time pricing and component availability.

4. In most cases, you will also be able to:

– Run electrical simulations to see important waveforms and circuit performance,

– Run thermal simulations to understand the thermal performance of your board,

– Export your customized schematic and layout into popular CAD formats,

– Print PDF reports for the design, and share your design with colleagues.

5. Get more information about WEBENCH tools at www.ti.com/webench.

11.1.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.1.3 Related Documentation

•AN-1286 Compensation for the LM3478 Boost Controller (SNVA067)

•AN-2094 LM3481 SEPIC Evaluation Board (SNVA461)

•AN-1229 SIMPLE SWITCHER® PCB Layout Guidelines (SNVA054)

• SNVU111 330mW AC or DC Tiny Flyback Converter Power Supply (SNVU111)

11.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 1. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

LM3481 Click here Click here Click here Click here Click here

LM3481-Q1 Click here Click here Click here Click here Click here

11.3 Trademarks

WEBENCH is a registered trademark of Texas Instruments.

11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

LM3481

LM3481-Q1

www.ti.com

SNVS346F –NOVEMBER 2007–REVISED NOVEMBER 2014

Product Folder Links: LM3481 LM3481-Q1

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 21-Sep-2016

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM3481MM/NOPB ACTIVE VSSOP DGS 10 1000 Green (RoHS

& no Sb/Br) CU NIPDAUAG | CU SN Level-1-260C-UNLIM -40 to 125 SJPB

LM3481MMX/NOPB ACTIVE VSSOP DGS 10 3500 Green (RoHS

& no Sb/Br) CU NIPDAUAG | CU SN Level-1-260C-UNLIM -40 to 125 SJPB

LM3481QMM/NOPB ACTIVE VSSOP DGS 10 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SUAB

LM3481QMMX/NOPB ACTIVE VSSOP DGS 10 3500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SUAB

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

PACKAGE OPTION ADDENDUM

www.ti.com 21-Sep-2016

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LM3481, LM3481-Q1 :

•Catalog: LM3481

•Automotive: LM3481-Q1

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM3481MM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LM3481MMX/NOPB VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LM3481QMM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LM3481QMMX/NOPB VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 8-Aug-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM3481MM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0

LM3481MMX/NOPB VSSOP DGS 10 3500 367.0 367.0 35.0

LM3481QMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0

LM3481QMMX/NOPB VSSOP DGS 10 3500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 8-Aug-2017

Pack Materials-Page 2

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