DAC904
DAC904
14-Bit, 165MSPS
DIGITAL-TO-ANALOG CONVERTER
FEATURES
●SINGLE +5V OR +3V OPERATION
●
HIGH SFDR: 20MHz Output at 100MSPS: 64dBc
●LOW GLITCH: 3pV-s
●LOW POWER: 170mW at +5V
●INTERNAL REFERENCE:
Optional Ext. Reference
Adjustable Full-Scale Range
Multiplying Option
APPLICATIONS
●COMMUNICATION TRANSMIT CHANNELS
WLL, Cellular Base Station
Digital Microwave Links
Cable Modems
●WAVEFORM GENERATION
Direct Digital Synthesis (DDS)
Arbitrary Waveform Generation (ARB)
●MEDICAL/ULTRASOUND
●HIGH-SPEED INSTRUMENTATION AND
CONTROL
●VIDEO, DIGITAL TV
DESCRIPTION
The DAC904 is a high-speed, Digital-to-Analog Converter (DAC)
offering a 14-bit resolution option within the family of high-
performance converters. Featuring pin compatibility among fam-
ily members, the DAC908, DAC900, and DAC902 provide a
component selection option to an 8-, 10-, and 12-bit resolution,
respectively. All models within this family of DACs support
update rates in excess of 165MSPS with excellent dynamic
performance, and are especially suited to fulfill the demands of
a variety of applications.
The advanced segmentation architecture of the DAC904 is
optimized to provide a high Spurious-Free Dynamic Range
(SFDR) for single-tone, as well as for multi-tone signals—
essential when used for the transmit signal path of communica-
tion systems.
The DAC904 has a high impedance (200kΩ) current output with
a nominal range of 20mA and an output compliance of up to
1.25V. The differential outputs allow for both a differential or
single-ended analog signal interface. The close matching of the
current outputs ensures superior dynamic performance in the
differential configuration, which can be implemented with a
transformer.
Utilizing a small geometry CMOS process, the monolithic DAC904
can be operated on a wide, single-supply range of +2.7V to
+5.5V. Its low power consumption allows for use in portable and
battery-operated systems. Further optimization can be realized
by lowering the output current with the adjustable full-scale
option.
For noncontinuous operation of the DAC904, a power-down
mode results in only 45mW of standby power.
The DAC904 comes with an integrated 1.24V bandgap refer-
ence and edge-triggered input latches, offering a complete
converter solution. Both +3V and +5V CMOS logic families can
be interfaced to the DAC904.
The reference structure of the DAC904 allows for additional
flexibility by utilizing the on-chip reference, or applying an
external reference. The full-scale output current can be adjusted
over a span of 2-20mA, with one external resistor, while main-
taining the specified dynamic performance.
The DAC904 is available in SO-28 and TSSOP-28 packages.
Current
Sources
LSB
Switches
Segmented
Switches
+1.24V Ref. Latches
14-Bit Data Input
D13...D0
DAC904
FSA
BW +V
D
+V
A
AGND CLK DGND
REF
IN
INT/EXT
I
OUT
I
OUT
BYP
PD
DAC904
SBAS095C – MAY 2002
www.ti.com
Copyright © 2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
DAC904
2SBAS095C
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ELECTRICAL CHARACTERISTICS
At TA = full specified temperature range, +VA = +5V, +VD = +5V, differential transformer coupled output, 50Ω doubly terminated, unless otherwise specified.
DAC904U, E
PARAMETER CONDITIONS MIN TYP MAX UNITS
RESOLUTION 14 Bits
OUTPUT UPDATE RATE 2.7V to 3.3V 125 165 MSPS
Output Update Rate (fCLOCK) 4.5V to 5.5V 165 200 MSPS
Full Specified Temperature Range, Operating Ambient, TA–40 +85 °C
STATIC ACCURACY(1) TA = +25°C
Differential Nonlinearity (DNL) fCLOCK = 25MSPS, fOUT = 1.0MHz ±2.5 LSB
Integral Nonlinearity (INL) ±3.0 LSB
DYNAMIC PERFORMANCE TA = +25°C
Spurious-Free Dynamic Range (SFDR) To Nyquist
fOUT = 1.0MHz, fCLOCK = 25MSPS 72 79 dBc
fOUT = 2.1MHz, fCLOCK = 50MSPS 76 dBc
fOUT = 5.04MHz, fCLOCK = 50MSPS 68 dBc
fOUT = 5.04MHz, fCLOCK = 100MSPS 68 dBc
fOUT = 20.2MHz, fCLOCK = 100MSPS 64 dBc
fOUT = 25.3MHz, fCLOCK = 125MSPS 60 dBc
fOUT = 41.5MHz, fCLOCK = 125MSPS 55 dBc
fOUT = 27.4MHz, fCLOCK = 165MSPS 60 dBc
fOUT = 54.8MHz, fCLOCK = 165MSPS 55 dBc
Spurious-Free Dynamic Range within a Window
fOUT = 5.04MHz, fCLOCK = 50MSPS 2MHz Span 82 dBc
fOUT = 5.04MHz, fCLOCK = 100MSPS 4MHz Span 82 dBc
Total Harmonic Distortion (THD)
fOUT = 2.1MHz, fCLOCK = 50MSPS –75 dBc
fOUT = 2.1MHz, fCLOCK = 125MSPS –74 dBc
Two Tone
f
OUT1
= 13.5MHz, f
OUT2
= 14.5MHz, f
CLOCK
= 100MSPS
63 dBc
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
DEMO BOARD
PRODUCT ORDERING NUMBER COMMENT
DAC904U DEM-DAC90xU Populated evaluation board without DAC. Order sample of desired DAC90x model separately.
DAC904E DEM-DAC904E Populated evaluation board including the DAC904E.
DEMO BOARD ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
+VA to AGND......................................................................... –0.3V to +6V
+VD to DGND ........................................................................ –0.3V to +6V
AGND to DGND ................................................................. –0.3V to +0.3V
+VA to +VD............................................................................... –6V to +6V
CLK, PD to DGND ....................................................... –0.3V to VD + 0.3V
D0-D13 to DGND ......................................................... –0.3V to VD + 0.3V
IOUT, IOUT to AGND.......................................................... –1V to VA + 0.3V
BW, BYP to AGND....................................................... –0.3V to VA + 0.3V
REFIN, FSA to AGND................................................... –0.3V to VA + 0.3V
INT/EXT to AGND........................................................ –0.3V to VA + 0.3V
Junction Temperature .................................................................... +150°C
Case Temperature ......................................................................... +100°C
Storage Temperature..................................................................... +125°C
SPECIFIED
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD DESIGNATOR(1) RANGE MARKING NUMBER MEDIA, QUANTITY
DAC904U SO-28 DW –40°C to +85°C DAC904U DAC904U Rails, 28
" """"DAC904U/1K Tape and Reel, 1000
DAC904E TSSOP-28 PW –40°C to +85°C DAC904E DAC904E Rails, 52
" """"DAC904E/2K5 Tape and Reel, 2500
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PACKAGE/ORDERING INFORMATION
DAC904 3
SBAS095C www.ti.com
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = +25°C, +VA = +5V, +VD = +5V, differential transformer coupled output, 50Ω doubly terminated, unless otherwise specified.
DAC904U, E
PARAMETER CONDITIONS MIN TYP MAX UNITS
DYNAMIC PERFORMANCE (Cont.)
Output Settling Time(2) to 0.1% 30 ns
Output Rise Time(2) 10% to 90% 2 ns
Output Fall Time(2) 10% to 90% 2 ns
Glitch Impulse 3pV-s
DC-ACCURACY
Full-Scale Output Range(3)(FSR) All Bits HIGH, IOUT 2.0 20.0 mA
Output Compliance Range –1.0 +1.25 V
Gain Error With Internal Reference –10 ±1 +10 %FSR
Gain Error With External Reference –10 ±2 +10 %FSR
Gain Drift With Internal Reference ±120 ppmFSR/°C
Offset Error With Internal Reference –0.025 +0.025 %FSR
Offset Drift With Internal Reference ±0.1 ppmFSR/°C
Power-Supply Rejection, +VA–0.2 +0.2 %FSR/V
Power-Supply Rejection, +VD–0.025 +0.025 %FSR/V
Output Noise IOUT = 20mA, RLOAD = 50Ω50 pA/√Hz
Output Resistance 200 kΩ
Output Capacitance IOUT, IOUT to Ground 12 pF
REFERENCE
Reference Voltage +1.24 V
Reference Tolerance ±10 %
Reference Voltage Drift ±50 ppmFSR/°C
Reference Output Current 10 µA
Reference Input Resistance 1MΩ
Reference Input Compliance Range 0.1 1.25 V
Reference Small-Signal Bandwidth(4) 1.3 MHz
DIGITAL INPUTS
Logic Coding Straight Binary
Latch Command Rising Edge of Clock
Logic HIGH Voltage, VIH +VD = +5V 3.5 5 V
Logic LOW Voltage, VIL +VD = +5V 0 1.2 V
Logic HIGH Voltage, VIH +VD = +3V 2 3 V
Logic LOW Voltage, VIL +VD = +3V 0 0.8 V
Logic HIGH Current, IIH(5) +VD = +5V ±20 µA
Logic LOW Current, IIL +VD = +5V ±20 µA
Input Capacitance 5pF
POWER SUPPLY
Supply Voltages
+VA+2.7 +5 +5.5 V
+VD+2.7 +5 +5.5 V
Supply Current(6)
IVA 24 30 mA
IVA, Power-Down Mode 1.1 2 mA
IVD 815mA
Power Dissipation +5V, IOUT = 20mA 170 230 mW
+3V, IOUT = 2mA 50 mW
Power Dissipation, Power-Down Mode 45 mW
Thermal Resistance,
θ
JA
SO-28 75 °C/W
TSSOP-28 50 °C/W
NOTES: (1) At output IOUT, while driving a virtual ground. (2) Measured single-ended into 50Ω Load. (3) Nominal full-scale output current is 32x IREF; see Application
Section for details. (4) Reference bandwidth depends on size of external capacitor at the BW pin and signal level. (5) Typically 45µA for the PD pin, which has an
internal pull-down resistor. (6) Measured at fCLOCK = 50MSPS and fOUT = 1.0MHz.
DAC904
4SBAS095C
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Current
Sources
LSB
Switches
Segmented
MSB
Switches
+1.24V Ref. Latches
14-Bit Data Input
D13.......D0
DAC904
FSA
BW +V
D
+V
A
R
SET
AGND
NOTE: (1) Optional components.
CLK DGND
REF
IN
0.1µF
INT/EXT
I
OUT
I
OUT
BYP
PD
20pF
(1)
50Ω50Ω20pF
(1)
1:1 V
OUT
0.1µF
0.1µF
(1)
+5V +5V
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
CLK
+V
D
DGND
NC
+V
A
BYP
I
OUT
I
OUT
AGND
BW
FSA
REF
IN
INT/EXT
PD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DAC904
PIN DESIGNATOR DESCRIPTION
1 Bit 1 Data Bit 1 (D13), MSB
2 Bit 2 Data Bit 2 (D12)
3 Bit 3 Data Bit 3 (D11)
4 Bit 4 Data Bit 4 (D10)
5 Bit 5 Data Bit 5 (D9)
6 Bit 6 Data Bit 6 (D8)
7 Bit 7 Data Bit 7 (D7)
8 Bit 8 Data Bit 8 (D6)
9 Bit 9 Data Bit 9 (D5)
10 Bit 10 Data Bit 10 (D4)
11 Bit 11 Data Bit 11 (D3)
12 Bit 12 Data Bit 12 (D2)
13 Bit 13 Data Bit 13 (D1)
14 Bit 14 Data Bit 14 (D0), LSB
15 PD Power Down, Control Input; Active
HIGH.
Contains internal pull-down circuit;
may be left unconnected if not used.
16 INT/EXT Reference Select Pin; Internal ( = 0) or
External ( = 1) Reference Operation
17 REFIN Reference Input/Ouput. See Applications
section for further details.
18 FSA Full-Scale Output Adjust
19 BW Bandwidth/Noise Reduction Pin:
Bypass with 0.1µF to +VA for Optimum
Performance. (Optional)
20 AGND Analog Ground
21 IOUT Complementary DAC Current Output
22 IOUT DAC Current Output
23 BYP Bypass Node: Use 0.1µF to AGND
24 +VAAnalog Supply Voltage, 2.7V to 5.5V
25 NC No Internal Connection
26 DGND Digital Ground
27 +VDDigital Supply Voltage, 2.7V to 5.5V
28 CLK Clock Input
PIN DESCRIPTIONSPIN CONFIGURATION
Top View SO, TSSOP
TYPICAL CONNECTION CIRCUIT
DAC904 5
SBAS095C www.ti.com
TIMING DIAGRAM
t2 t1
tStH
tSET
tPD
CLOCK
D13 D0
Iout or
Iout
Data Changes Stable V alid Data Data Changes
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t1Clock Pulse HIGH Time 3 ns
t2Clock Pulse LOW Time 3 ns
tSData Setup Time 1.0 ns
tHData Hold Time 1.5 ns
tPD Propagation Delay Time 1 ns
tSET Output Settling Time to 0.1% 30 ns
DAC904
6SBAS095C
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TYPICAL CHARACTERISTICS: VD = VA = +5V
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
DAC Code
TYPICAL DNL
Error (LSBs)
10
8
6
4
2
0
–2
–4
–6
–8
–10
0
2k
4k
6k
8k
10k
12k
14k
16k
16384
TYPICAL INL
Error (LSBs)
10
8
6
4
2
0
–2
–4
–6
–8
–10
DAC Code
0
2k
4k
6k
8k
10k
12k
14k
16k
16384
SFDR vs f
OUT
AT 25MSPS
Frequency (MHz)
SFDR (dBc)
90
85
80
75
70
65
60 2.0 4.0 6.0 8.0 10.0 12.00
0dBFS
–6dBFS
SFDR vs f
OUT
AT 50MSPS
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55 5.0 10.0 15.0 20.0 25.00
–6dBFS
0dBFS
SFDR vs fOUT AT 100MSPS
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
50
45 10.0 20.0 30.0 40.0 50.00
0dBFS
–6dBFS
SFDR vs fOUT AT 125MSPS
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
50
45 10.0 20.0 30.0 50.040.0 60.00
0dBFS
–6dBFS
DAC904 7
SBAS095C www.ti.com
TYPICAL CHARACTERISTICS: VD = VA = +5V (Cont.)
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
SFDR vs f
OUT
AT 165MSPS
Frequency (MHz)
SFDR (dBc)
80
75
70
65
60
55
50
45
40 20.010.0 30.0 40.0 50.0 70.060.0 80.00
–6dBFS
0dBFS
SFDR vs f
OUT
AT 200MSPS
Frequency (MHz)
SFDR (dBc)
80
75
70
65
60
55
50
45
40 20.010.0 30.0 40.0 50.0 70.060.0 90.080.00
–6dBFS
0dBFS
DIFFERENTIAL vs SINGLE-ENDED SFDR vs f
OUT
AT 100MSPS
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
50
45 10.0 20.0 30.0 40.0 50.00
Diff (0dBFS)
I
OUT
(–6dBFS)
I
OUT
(0dBFS)
Diff (–6dBFS)
X
X
X
X
XX
X
SFDR vs I
OUTFS
and f
OUT
AT 100MSPS, 0dBFS
I
OUTFS
(mA)
SFDR (dBc)
80
75
70
65
60
55
50
45
40 510202
XXX
X
2.1MHz
20.2MHz
10.1MHz 5.04MHz
40.4MHz
*
*
**
THD vs fCLOCK AT fOUT = 2.1MHz
fCLOCK (MSPS)
THD (dBc)
–70
–75
–80
–85
–90
–95
–100 25 50 100 125 1500
2HD
4HD
3HD
XXXX
SFDR vs TEMPERATURE AT 100MSPS, 0dBFS
Temperature (°C)
SFDR (dBc)
85
80
75
70
65
60
55
50
45 –20 0 25 7050 85–40
2.1MHz
10.1MHz
40.4MHz
X
X
X
X
X
X
X
DAC904
8SBAS095C
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TYPICAL CHARACTERISTICS: VD = VA = +5V (Cont.)
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
DUAL-TONE OUTPUT SPECTRUM
Frequency (MHz)
Magnitude (dBm)
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100 5 101520253035404550
fCLOCK = 100MSPS
fOUT1 = 13.5MHz
fOUT2 = 14.5MHz
SFDR = 63dBc
Amplitude = 0dBFS
FOUR-TONE OUTPUT SPECTRUM
Frequency (MHz)
Magnitude (dBm)
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100 510152025
fCLOCK = 50MSPS
fOUT1 = 6.25MHz
fOUT2 = 6.75MHz
fOUT3 = 7.25MHz
fOUT4 = 7.75MHz
SFDR = 66dBc
Amplitude = 0dBFS
SFDR vs f
OUT
AT 25MSPS
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55 2.0 4.0 6.0 8.0 10.0 12.00
0dBFS
–6dBFS
SFDR vs f
OUT
AT 50MSPS
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55 5.0 10.0 15.0 20.0 25.00
–6dBFS
0dBFS
SFDR vs f
OUT
AT 100MSPS
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
50
45 10.0 20.0 30.0 40.0 50.00
–6dBFS
0dBFS
SFDR vs f
OUT
AT 125MSPS
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
50
45 10.0 20.0 30.0 50.040.0 60.00
0dBFS
–6dBFS
TYPICAL CHARACTERISTICS: VD = VA = +3V
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
DAC904 9
SBAS095C www.ti.com
SFDR vs fOUT AT 165MSPS
Frequency (MHz)
SFDR (dBc)
80
75
70
65
60
55
50
45
40 20.010.0 30.0 40.0 50.0 70.060.0 80.00
–6dBFS
0dBFS
DIFFERENTIAL vs SINGLE-ENDED SFDR vs f
OUT
AT 100MSPS
Frequency (MHz)
SFDR (dBc)
85
80
75
70
65
60
55
50
45 10.0 20.0 30.0 40.0 50.00
Diff (0dBFS)
I
OUT
(–6dBFS)
I
OUT
(0dBFS)
Diff (–6dBFS)
TYPICAL CHARACTERISTICS: VD = VA = +3V (Cont.)
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
I
OUTFS
(mA)
SFDR (dBc)
80
75
70
65
60
55
50
45
40 510202
XX
*
*
**
X
X
SFDR vs I
OUTFS
and f
OUT
AT 100MSPS
2.1MHz
5.04MHz
20.2MHz
10.1MHz
40.4MHz
THD vs fCLOCK AT fOUT = 2.1MHz
fCLOCK (MSPS)
THD (dBc)
–70
–75
–80
–85
–90
–95
–100 25 50 100 125 1500
2HD
4HD
3HD
SFDR vs TEMPERATURE AT 100MSPS, 0dBFS
Temperature (°C)
SFDR (dBc)
80
75
70
65
60
55
50
45
40 –20 0 25 7050 85–40
2.1MHz
10.1MHz
40.4MHz X
X
X
X
X
X
X
DUAL-TONE OUTPUT SPECTRUM
Frequency (MHz)
Magnitude (dBm)
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100 5 101520253035404550
f
CLOCK
= 100MSPS
f
OUT1
= 13.5MHz
f
OUT2
= 14.5MHz
SFDR = 64dBc
Amplitude = 0dBFS
DAC904
10 SBAS095C
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APPLICATION INFORMATION
THEORY OF OPERATION
The architecture of the DAC904 uses the current steering
technique to enable fast switching and a high update rate. The
core element within the monolithic DAC is an array of seg-
mented current sources that are designed to deliver a full-scale
output current of up to 20mA, as shown in Figure 1. An internal
decoder addresses the differential current switches each time
the DAC is updated and a corresponding output current is
formed by steering all currents to either output summing node,
IOUT or IOUT. The complementary outputs deliver a differential
output signal that improves the dynamic performance through
reduction of even-order harmonics, common-mode signals
(noise), and double the peak-to-peak output signal swing by a
factor of two, compared to single-ended operation.
FIGURE 1. Functional Block Diagram of the DAC904.
PMOS
Current
Source
Array
LSB
Switches
Segmented
MSB
Switches
+1.24V Ref
Latches and Switch
Decoder Logic
14-Bit Data Input
D13...D0
DAC904
Full-Scale
Adjust
Resistor
Ref
Control
Amp
Ref
Buffer
BW +V
D
+V
A
R
SET
2kΩ
CLK DGND
Ref
Input
0.1µFINT/EXT
I
OUT
I
OUT
BYP
PD
20pF
(1)
50Ω50Ω20pF
(1)
1:1 V
OUT
0.1µF
400pF
0.1µF
(1)
+3V to +5V
Analog
Bandwidth
Control
+3V to +5V
Digital
FSA
REF
IN
AGND
Analog
Ground Digital
Ground
Power Down
(internal pull-down)
Clock
Input
NOTE: Supply bypassing not shown. NOTE: (1) Optional.
TYPICAL CHARACTERISTICS: VD = VA = +3V (Cont.)
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
FOUR-TONE OUTPUT SPECTRUM
Frequency (MHz)
Magnitude (dBm)
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100 510152025
fCLOCK = 50MSPS
fOUT1 = 6.25MHz
fOUT2 = 6.75MHz
fOUT3 = 7.25MHz
fOUT4 = 7.75MHz
SFDR = 67dBc
Amplitude = 0dBFS
The segmented architecture results in a significant reduction
of the glitch energy, and improves the dynamic performance
(SFDR) and DNL. The current outputs maintain a very high
output impedance of greater than 200kΩ.
The full-scale output current is determined by the ratio of the
internal reference voltage (1.24V) and an external resistor,
RSET. The resulting IREF is internally multiplied by a factor of
32 to produce an effective DAC output current that can range
from 2mA to 20mA, depending on the value of RSET.
The DAC904 is split into a digital and an analog portion, each
of which is powered through its own supply pin. The digital
section includes edge-triggered input latches and the de-
coder logic, while the analog section comprises the current
source array with its associated switches and the reference
circuitry.
DAC904 11
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DAC TRANSFER FUNCTION
The total output current, IOUTFS, of the DAC904 is the sum-
mation of the two complementary output currents:
IOUTFS = IOUT + IOUT (1)
The individual output currents depend on the DAC code and
can be expressed as:
IOUT = IOUTFS • (Code/16384) (2)
IOUT = IOUTFS • (16383 – Code/16384) (3)
where ‘Code’ is the decimal representation of the DAC data
input word. Additionally, IOUTFS is a function of the reference
current IREF, which is determined by the reference voltage
and the external setting resistor, RSET.
IOUTFS = 32 • IREF = 32 • VREF/RSET (4)
In most cases the complementary outputs will drive resistive
loads or a terminated transformer. A signal voltage will
develop at each output according to:
VOUT = IOUT • RLOAD (5)
VOUT = IOUT • RLOAD (6)
The value of the load resistance is limited by the output
compliance specification of the DAC904. To maintain speci-
fied linearity performance, the voltage for IOUT and IOUT
should not exceed the maximum allowable compliance range.
The two single-ended output voltages can be combined to
find the total differential output swing:
(7)
VVVCode IR
OUTDIFF OUT OUT OUTFS LOAD
==
•••–(–)2 16383
16384
ANALOG OUTPUTS
The DAC904 provides two complementary current outputs,
IOUT and IOUT. The simplified circuit of the analog output
stage representing the differential topology is shown in
Figure 2. The output impedance of 200kΩ 12pF for IOUT
and IOUT results from the parallel combination of the differen-
tial switches, along with the current sources and associated
parasitic capacitances.
The signal voltage swing that may develop at the two
outputs, IOUT and IOUT, is limited by a negative and positive
compliance. The negative limit of –1V is given by the break-
down voltage of the CMOS process, and exceeding it will
compromise the reliability of the DAC904, or even cause
permanent damage. With the full-scale output set to 20mA,
the positive compliance equals 1.25V, operating with
FIGURE 2. Equivalent Analog Output.
IOUT IOUT
DAC904
RLRL
+VA
+VD = 5V. Note that the compliance range decreases to
about 1V for a selected output current of IOUTFS = 2mA.
Care should be taken that the configuration of the DAC904
does not exceed the compliance range to avoid degradation
of the distortion performance and integral linearity.
Best distortion performance is typically achieved with the
maximum full-scale output signal limited to approximately
0.5V. This is the case for a 50Ω doubly-terminated load and
a 20mA full-scale output current. A variety of loads can be
adapted to the output of the DAC904 by selecting a suitable
transformer while maintaining optimum voltage levels at
IOUT and IOUT. Furthermore, using the differential output
configuration in combination with a transformer will be instru-
mental for achieving excellent distortion performance. Com-
mon-mode errors, such as even-order harmonics or noise,
can be substantially reduced. This is particularly the case
with high output frequencies and/or output amplitudes below
full-scale.
For those applications requiring the optimum distortion and
noise performance, it is recommended to select a full-scale
output of 20mA. A lower full-scale range down to 2mA may
be considered for applications that require a low power
consumption, but can tolerate a reduced performance level.
INPUT CODE (D13 - D0) IOUT IOUT
11 1111 1111 1111 20mA 0mA
10 0000 0000 0000 10mA 10mA
00 0000 0000 0000 0mA 20mA
TABLE I. Input Coding versus Analog Output Current.
OUTPUT CONFIGURATIONS
The current output of the DAC904 allows for a variety of
configurations, some of which are illustrated below. As men-
tioned previously, utilizing the converter’s differential outputs
will yield the best dynamic performance. Such a differential
output circuit may consist of an RF transformer (see Figure 3)
or a differential amplifier configuration (see Figure 4). The
DAC904
12 SBAS095C
www.ti.com
FIGURE 4. Difference Amplifier Provides Differential to Single-
Ended Conversion and AC-Coupling.
The OPA680 is configured for a gain of 2. Therefore, oper-
ating the DAC904 with a 20mA full-scale output will produce
a voltage output of ±1V. This requires the amplifier to operate
off of a dual power supply (±5V). The tolerance of the
resistors typically sets the limit for the achievable common-
mode rejection. An improvement can be obtained by fine
tuning resistor R4.
This configuration typically delivers a lower level of ac perfor-
mance than the previously discussed transformer solution
because the amplifier introduces another source of distor-
tion. Suitable amplifiers should be selected based on their
slew-rate, harmonic distortion, and output swing capabilities.
High-speed amplifiers like the OPA680 or OPA687 may be
considered. The ac performance of this circuit may be
improved by adding a small capacitor, CDIFF, between the
outputs IOUT and IOUT,
as shown in Figure 4
. This will introduce
a real pole to create a low-pass filter in order to slew-limit the
DAC’s fast output signal steps that otherwise could drive the
amplifier into slew-limitations or into an overload condition;
both would cause excessive distortion. The difference ampli-
fier can easily be modified to add a level shift for applications
requiring the single-ended output voltage to be unipolar, i.e.,
swing between 0V and +2V.
IOUT
IOUT
DAC904
RL
26.1ΩRL
28.7ΩR4
402Ω
R3
200Ω
R2
402Ω
R1
200Ω
OPA680
CDIFF +5V
VOUT
–5V
transformer configuration is ideal for most applications with ac
coupling, while op amps will be suitable for a DC-coupled
configuration.
The single-ended configuration (see Figure 6) may be consid-
ered for applications requiring a unipolar output voltage. Con-
necting a resistor from either one of the outputs to ground will
convert the output current into a ground-referenced voltage
signal. To improve on the DC linearity, an I-to-V converter can
be used instead. This will result in a negative signal excursion
and, therefore, requires a dual supply amplifier.
DIFFERENTIAL WITH TRANSFORMER
Using an RF transformer provides a convenient way of
converting the differential output signal into a single-ended
signal while achieving excellent dynamic performance, as
shown in Figure 3. The appropriate transformer should be
carefully selected based on the output frequency spectrum
and impedance requirements. The differential transformer
configuration has the benefit of significantly reducing com-
mon-mode signals, thus improving the dynamic performance
over a wide range of frequencies. Furthermore, by selecting
a suitable impedance ratio (winding ratio), the transformer
can be used to provide optimum impedance matching while
controlling the compliance voltage for the converter outputs.
The model shown in Figure 3 has a 1:1 ratio and may be
used to interface the DAC904 to a 50Ω load. This results in
a 25Ω load for each of the outputs, IOUT and IOUT. The output
signals are ac coupled and inherently isolated because of the
transformer's magnetic coupling.
As shown in Figure 3, the transformer’s center tap is con-
nected to ground. This forces the voltage swing on IOUT and
IOUT to be centered at 0V. In this case the two resistors, RS,
may be replaced with one, RDIFF, or omitted altogether. This
approach should only be used if all components are close to
each other, and if the VSWR is not important. A complete
power transfer from the DAC output to the load can be
realized, but the output compliance range should be ob-
served. Alternatively, if the center tap is not connected, the
signal swing will be centered at RS • IOUTFS/2. However, in
this case, the two resistors (RS) must be used to enable the
necessary DC-current flow for both outputs.
DIFFERENTIAL CONFIGURATION USING AN OP AMP
If the application requires a DC-coupled output, a difference
amplifier may be considered, as shown in Figure 4. Four
external resistors are needed to configure the voltage-feed-
back op amp OPA680 as a difference amplifier performing
the differential to single-ended conversion. Under the shown
configuration, the DAC904 generates a differential output
signal of 0.5Vp-p at the load resistors, RL. The resistor values
shown were selected to result in a symmetric 25Ω loading for
each of the current outputs since the input impedance of the
difference amplifier is in parallel to resistors RL, and should
be considered.
FIGURE 3. Differential Output Configuration Using an RF
Transformer.
I
OUT
I
OUT
DAC904
1:1
ADT1-1WT
(Mini-Circuits)
R
S
50Ω
R
S
50Ω
R
L
Optional
R
DIFF
DAC904 13
SBAS095C www.ti.com
FIGURE 5. Dual, Voltage-Feedback Amplifier OPA2680 Forms
Differential Transimpedance Amplifier.
DUAL TRANSIMPEDANCE OUTPUT CONFIGURATION
The circuit example of Figure 5 shows the signal output
currents connected into the summing junction of the OPA2680,
which is set up as a transimpedance stage, or I-to-V con-
verter. With this circuit, the DAC’s output will be kept at a
virtual ground, minimizing the effects of output impedance
variations, and resulting in the best DC linearity (INL). How-
ever, as mentioned previously, the amplifier may be driven
into slew-rate limitations, and produce unwanted distortion.
This may occur especially at high DAC update rates.
The DC gain for this circuit is equal to feedback resistor RF.
At high frequencies, the DAC output impedance (CD1, CD2)
will produce a zero in the noise gain for the OPA2680 that
may cause peaking in the closed-loop frequency response.
CF is added across RF to compensate for this noise-gain
peaking. To achieve a flat transimpedance frequency re-
sponse, the pole in each feedback network should be set to:
1
24ππRC GBP
RC
FF FD
=(8)
with GBP = Gain Bandwidth Product of OPA,
which will give a corner frequency f-3dB of approximately:
fGBP
RC
dB FD
−
=
3
2π
(9)
1/2
OPA2680
1/2
OPA2680
DAC904
–V
OUT
= I
OUT
• R
F
–V
OUT
= I
OUT
• R
F
R
F1
R
F2
C
F1
C
F2
C
D1
C
D2
I
OUT
I
OUT
50Ω
50Ω–5V
+5V
The full-scale output voltage is defined by the product of
IOUTFS • R
F, and has a negative unipolar excursion. To
improve on the ac performance of this circuit, adjustment of
RF and/or IOUTFS should be considered. Further extensions of
this application example may include adding a differential
filter at the OPA2680’s output followed by a transformer, in
order to convert to a single-ended signal.
SINGLE-ENDED CONFIGURATION
Using a single load resistor connected to the one of the DAC
outputs, a simple current-to-voltage conversion can be ac-
complished. The circuit in Figure 6 shows a 50Ω resistor
connected to IOUT, providing the termination of the further
connected 50Ω cable. Therefore, with a nominal output
current of 20mA, the DAC produces a total signal swing of
0V to 0.5V into the 25Ω load.
Different load resistor values may be selected as long as the
output compliance range is not exceeded. Additionally, the
output current, IOUTFS, and the load resistor may be mutually
adjusted to provide the desired output signal swing and
performance.
FIGURE 6. Driving a Doubly-Terminated 50Ω Cable Directly.
I
OUT
I
OUT
DAC904
25Ω
50Ω50Ω
I
OUTFS
= 20mA V
OUT
= 0V to +0.5V
INTERNAL REFERENCE OPERATION
The DAC904 has an on-chip reference circuit that comprises
a 1.24V bandgap reference and a control amplifier. Ground-
ing pin 16, INT/EXT, enables the internal reference opera-
tion. The full-scale output current, IOUTFS, of the DAC904 is
determined by the reference voltage, VREF, and the value of
resistor RSET. IOUTFS can be calculated by:
IOUTFS = 32 • IREF = 32 • VREF / RSET (10)
The external resistor R
SET
connects to the FSA pin (Full-
Scale Adjust), see Figure 7. The reference control amplifier
operates as a V-to-I converter producing a reference current,
I
REF
, which is determined by the ratio of V
REF
and R
SET
, as
shown in Equation 10. The full-scale output current, I
OUTFS
,
results from multiplying I
REF
by a fixed factor of 32.
DAC904
14 SBAS095C
www.ti.com
FIGURE 8. External Reference Configuration.
FIGURE 7. Internal Reference Configuration.
DIGITAL INPUTS
The digital inputs, D0 (LSB) through D13 (MSB) of the
DAC904 accepts standard-positive binary coding. The digital
input word is latched into a master-slave latch with the rising
edge of the clock. The DAC output becomes updated with
the following falling clock edge (refer to the electrical charac-
teristic table and timing diagram for details). The best perfor-
mance will be achieved with a 50% clock duty cycle, how-
ever, the duty cycle may vary as long as the timing specifi-
cations are met. Additionally, the setup and hold times may
be chosen within their specified limits.
All digital inputs are CMOS compatible. The logic thresholds
depend on the applied digital supply voltage such that they
are set to approximately half the supply voltage;
Vth = +VD/2 (±20% tolerance). The DAC904 is designed to
operate over a supply range of 2.7V to 5.5V.
POWER-DOWN MODE
The DAC904 features a power-down function that can be
used to reduce the supply current to less than 9mA over the
specified supply range of 2.7V to 5.5V. Applying a logic HIGH
to the PD pin will initiate the power-down mode, while a logic
LOW enables normal operation. When left unconnected, an
internal active pull-down circuit will enable the normal opera-
tion of the converter.
GROUNDING, DECOUPLING, AND
LAYOUT INFORMATION
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high
frequency designs. Multilayer pc-boards are recommended
for best performance since they offer distinct advantages
such as minimization of ground impedance, separation of
signal layers by ground layers, etc.
Using the internal reference, a 2kΩ resistor value results in a
20mA full-scale output. Resistors with a tolerance of 1% or
better should be considered. Selecting higher values, the con-
verter output can be adjusted from 20mA down to 2mA.
Operating the DAC904 at lower than 20mA output currents may
be desirable for reasons of reducing the total power consump-
tion, improving the distortion performance, or observing the
output compliance voltage limitations for a given load condition.
It is recommended to bypass the REF
IN
pin with a ceramic chip
capacitor of 0.1µF or more. The control amplifier is internally
compensated, and its small signal bandwidth is approximately
1.3MHz. For optional ac performance, an additional capacitor
(C
COMPEXT
) should be applied between the BW pin and the
analog supply, +V
A
, as shown in Figure 7. Using a 0.1µF
capacitor, the small-signal bandwidth and output impedance of
the control amplifier is further diminished, reducing the noise
that is fed into the current source array. This also helps shunting
feedthrough signals more effectively, and improving the noise
performance of the DAC904.
EXTERNAL REFERENCE OPERATION
The internal reference can be disabled by applying a logic
HIGH (+VA) to pin INT/EXT. An external reference voltage
can then be driven into the REFIN pin, which in this case
functions as an input, as shown in Figure 8. The use of an
external reference may be considered for applications that
require higher accuracy and drift performance, or to add the
ability of dynamic gain control.
While a 0.1µF capacitor is recommended to be used with the
internal reference, it is optional for the external reference
operation. The reference input, REFIN, has a high input
impedance (1MΩ) and can easily be driven by various
sources. Note that the voltage range of the external refer-
ence should stay within the compliance range of the refer-
ence input (0.1V to 1.25V).
DAC904
CCOMPEXT
0.1µF
Optional
Bandlimiting
Capacitor
CCOMP
400pF
+1.24V Ref.
RSET
2kΩ0.1µFINT/EXT
FSA
BW
+5V
+VA
REFIN
Current
Sources
IREF = VREF
RSET
Ref
Control
Amp
R
SET
+5V
External
Reference
I
REF
= V
REF
R
SET
DAC904
C
COMPEXT
0.1µF
C
COMP
400pF
+1.24V Ref.
INT/EXT
FSA
BW
+5V
+V
A
REF
IN
Current
Sources
Ref
Control
Amp
DAC904 15
SBAS095C www.ti.com
The DAC904 uses separate pins for its analog and digital
supply and ground connections. The placement of the decou-
pling capacitor should be such that the analog supply (+VA)
is bypassed to the analog ground (AGND), and the digital
supply bypassed to the digital ground (DGND). In most cases
0.1µF ceramic chip capacitors at each supply pin are ad-
equate to provide a low impedance decoupling path. Keep in
mind that their effectiveness largely depends on the proximity
to the individual supply and ground pins. Therefore, they
should be located as close as physically possible to those
device leads. Whenever possible, the capacitors should be
located immediately under each pair of supply/ground pins
on the reverse side of the pc-board. This layout approach will
minimize the parasitic inductance of component leads and
pcb runs.
Further supply decoupling with surface mount tantalum ca-
pacitors (1µF to 4.7µF) may be added as needed in proximity
of the converter.
Low noise is required for all supply and ground connections
to the DAC904. It is recommended to use a multilayer pc-
board utilizing separate power and ground planes. Mixed
signal designs require particular attention to the routing of the
different supply currents and signal traces. Generally, analog
supply and ground planes should only extend into analog
signal areas, such as the DAC output signal and the refer-
ence signal. Digital supply and ground planes must be
confined to areas covering digital circuitry, including the
digital input lines connecting to the converter, as well as the
clock signal. The analog and digital ground planes should be
joined together at one point underneath the DAC. This can be
realized with a short track of approximately 1/8 inch (3mm).
The power to the DAC904 should be provided through the
use of wide pcb runs or planes. Wide runs will present a
lower trace impedance, further optimizing the supply decou-
pling. The analog and digital supplies for the converter
should only be connected together at the supply connector of
the pc-board. In the case of only one supply voltage being
available to power the DAC, ferrite beads along with bypass
capacitors may be used to create an LC filter. This will
generate a low-noise analog supply voltage that can then be
connected to the +VA supply pin of the DAC904.
While designing the layout, it is important to keep the analog
signal traces separate from any digital line, in order to
prevent noise coupling onto the analog signal path.
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC904E ACTIVE TSSOP PW 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC904E/2K5 ACTIVE TSSOP PW 28 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC904E/2K5G4 ACTIVE TSSOP PW 28 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC904EG4 ACTIVE TSSOP PW 28 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC904U ACTIVE SOIC DW 28 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC904U/1K ACTIVE SOIC DW 28 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC904U/1KG4 ACTIVE SOIC DW 28 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC904UG4 ACTIVE SOIC DW 28 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC904E/2K5 TSSOP PW 28 2500 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
DAC904U/1K SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Jul-2010
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC904E/2K5 TSSOP PW 28 2500 346.0 346.0 33.0
DAC904U/1K SOIC DW 28 1000 346.0 346.0 49.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Jul-2010
Pack Materials-Page 2
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