Document Number: MC33903_4_5
Rev. 14.0, 2/2018
NXP Semiconductors
Data Sheet: Advance Information
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© NXP B.V. 2018.
SBC Gen2 with CAN high speed and
LIN interface
The 33903/4/5 is the second generation family of the System Basis Chip (SBC).
It combines several features and enhances present module designs. The device
works as an advanced power management unit for the MCU with additional
integrated circuits such as sensors and CAN transceivers. It has a built-in
enhanced high-speed CAN interface (ISO11898-2 and -5) with local and bus
failure diagnostics, protection, and fail-safe operation modes. The SBC may
include zero, one or two LIN 2.1 interfaces with LIN output pin switches. It
includes up to four wake-up input pins that can also be configured as output
drivers for flexibility. This device is powered by SMARTMOS technology.
This device implements multiple Low-power (LP) modes, with very low-current
consumption. In addition, the device is part of a family concept where pin
compatibility adds versatility to module design.
The 33903/4/5 also implements an innovative and advanced fail-safe state
machine and concept solution.
Features
• Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with
possibility of usage external PNP to extend current capability and share power
dissipation
• Voltage, current, and temperature protection
• Extremely low quiescent current in LP modes
• Fully-protected embedded 5.0 V regulator for the CAN driver
• Multiple undervoltage detections to address various MCU specifications and
system operation modes (i.e. cranking)
• Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs, with
overcurrent detection and undervoltage protection
• MUX output pin for device internal analog signal monitoring and power supply
monitoring
• Advanced SPI, MCU, ECU power supply, and critical pins diagnostics and
monitoring.
• Multiple wake-up sources in LP modes: CAN or LIN bus, I/O transition,
automatic timer, SPI message, and VDD overcurrent detection.
• ISO11898-5 high-speed CAN interface compatibility for baud rates of 40 kb/s
to 1.0 Mb/s
• Scalable product family of devices ranging from 0 to 2 LINs which are
compatible to J2602-2 and LIN 2.1
33903/
33903/4/5
EK Suffix (Pb-free)
98ASA10556D
32-PIN SOIC
EK Suffix (Pb-free)
98ASA10506D
54-PIN SOIC
Applications
•Aircraft and marine systems
• Automotive and robotic systems
• Farm equipment
• Industrial actuator controls
• Lamp and inductive load controls
• DC motor control applications requiring diagnostics
• Applications where high-side switch control is
required
SYSTEM BASIS CHIP
2NXP Semiconductors
33903/4/5
Table of Contents
1. Simplified application diagrams ..................................................................................................................................................... 3
2. Orderable part ................................................................................................................................................................................ 7
3. Internal block diagrams .................................................................................................................................................................. 9
4. Pin Connections ........................................................................................................................................................................... 11
4.1. Pinout diagram ....................................................................................................................................................................... 11
5. Electrical characteristics .............................................................................................................................................................. 16
5.1. Maximum ratings .................................................................................................................................................................... 16
5.2. Static electrical characteristics ............................................................................................................................................... 18
5.3. Dynamic electrical characteristics .......................................................................................................................................... 26
5.4. Timing diagrams .................................................................................................................................................................... 29
6. Functional description .................................................................................................................................................................. 32
6.1. Introduction ............................................................................................................................................................................ 32
6.2. Functional pin description ...................................................................................................................................................... 32
7. Functional device operation ......................................................................................................................................................... 36
7.1. Mode and state description .................................................................................................................................................... 36
7.2. LP modes ............................................................................................................................................................................... 37
7.3. State diagram ......................................................................................................................................................................... 39
7.4. Mode change ......................................................................................................................................................................... 40
7.5. Watchdog operation ............................................................................................................................................................... 40
7.6. Functional block operation versus mode ............................................................................................................................... 43
7.7. Illustration of device mode transitions .................................................................................................................................... 44
7.8. Cyclic sense operation during LP modes ............................................................................................................................... 45
7.9. Cyclic INT operation during LP VDD on mode ....................................................................................................................... 47
7.10. Behavior at power up and power down ................................................................................................................................ 48
7.11. Fail-safe operation ............................................................................................................................................................... 51
8. CAN interface .............................................................................................................................................................................. 55
8.1. CAN interface description ...................................................................................................................................................... 55
8.2. CAN bus fault diagnostic ........................................................................................................................................................ 58
9. LIN block ...................................................................................................................................................................................... 62
9.1. LIN interface description ........................................................................................................................................................ 62
9.2. LIN operational modes ........................................................................................................................................................... 63
10. Serial peripheral interface .......................................................................................................................................................... 64
10.1. High level overview .............................................................................................................................................................. 64
10.2. Detail operation .................................................................................................................................................................... 64
10.3. Detail of control bits and register mapping ........................................................................................................................... 68
10.4. Flags and device status ....................................................................................................................................................... 84
11. Typical applications ................................................................................................................................................................... 92
12. Packaging ................................................................................................................................................................................ 100
12.1. SOIC 32 package dimensions ........................................................................................................................................... 100
12.2. SOIC 54 package dimensions ........................................................................................................................................... 103
13. Revision history ....................................................................................................................................................................... 106
NXP Semiconductors 3
33903/4/5
SIMPLIFIED APPLICATION DIAGRAMS
1 Simplified application diagrams
Figure 1. 33905D simplified application diagram
Figure 2. 33905S simplified application diagram
CS
SCLK
MOSI
INT
5V-CAN
V
SUP1
I/O-0
I/O-1
MISO
RXD
TXD
CANL
CANH
GND
RST
DBG
V
DD
SPLIT
V
BAT
V
B
Q1*
D1
V
BAUX
SAFE
RXD-L1
TXD-L1
LIN-TERM 1
LIN-1
V
E
Q2
(5.0 V/3.3 V)
V
DD
V
SUP2
V
AUX
V
CAUX
LIN-TERM 2
LIN-2
RXD-L2
TXD-L2
MUX-OUT
33905D
MCU
SPI
A/D
CAN Bus
LIN Bus
LIN Bus
VSENSE
* = Optional
CS
SCLK
MOSI
INT
5V-CAN
V
SUP1
I/O-0
I/O-1
MISO
RXD
TXD
CANL
CANH
GND
RST
DBG
V
DD
SPLIT
V
BAT
V
B
Q1*
D1
V
BAUX
SAFE
RXD-L
TXD-L
LIN-T
LIN
V
E
Q2
(5.0 V/3.3 V)
V
DD
V
SUP2
V
AUX
V
CAUX
I/O-3
MUX-OUT
33905S
MCU
SPI
A/D
CAN Bus
LIN Bus
VSENSE
V
BAT
* = Optional
4NXP Semiconductors
33903/4/5
SIMPLIFIED APPLICATION DIAGRAMS
Figure 3. 33904 simplified application diagram
Figure 4. 33903 simplified application diagram
33904
CS
SCLK
MOSI
INT
5V-CAN
V
SUP1
I/O-0
I/O-1
MISO
RXD
TXD
CANL
CANH
GND
RST
DBG
V
DD
SPLIT
V
BAT
V
B
Q1*
D1
V
BAUX
SAFE
I/O-3
V
E
Q2
(5.0 V/3.3 V)
V
DD
V
SUP2
V
AUX
V
CAUX
I/O-2
MUX-OUT
MCU
SPI
A/D
CAN Bus
VSENSE
V
BAT
* = Optional
CS
SCLK
MOSI
INT
5V-CAN
VSUP2
I/O-0
MISO
RXD
TXD
CANL
CANH
GND
RST
DBG
VDD
SPLIT
V
BAT
D1
V
DD
33903
MCU
SPI
CAN Bus
SAFE
VSUP1
NXP Semiconductors 5
33903/4/5
SIMPLIFIED APPLICATION DIAGRAMS
Figure 5. 33903D simplified application diagram
Figure 6. 33903S simplified application diagram
CS
SCLK
MOSI
INT
5V-CAN
V
SUP
IO-0
MISO
RXD
TXD
CANL
CANH
GND
RST
DBG
V
DD
SPLIT
V
BAT
V
B
Q1*
D1
SAFE
RXD-L1
TXD-L1
LIN-T1/I/O-2
LIN-1
V
E
V
DD
LIN-T2/IO-3
LIN-2 RXD-L2
TXD-L2
MUX-OUT
33903D
MCU
SPI
A/D
CAN Bus
LIN Bus
LIN Bus
VSENSE
* = Optional
CS
SCLK
MOSI
INT
5V-CAN
V
SUP
IO-0
MISO
RXD
TXD
CANL
CANH
GND
RST
DBG
V
DD
SPLIT
V
BAT
V
B
Q1*
D1
SAFE
RXD-L1
TXD-L1
LIN-T1/I/O-2
LIN-1
V
E
V
DD
MUX-OUT
33903S
MCU
SPI
A/D
CAN Bus
LIN Bus
VSENSE
* = Optional
I/O-3
V
BAT
6NXP Semiconductors
33903/4/5
SIMPLIFIED APPLICATION DIAGRAMS
Figure 7. 33903P simplified application diagram
CS
SCLK
MOSI
INT
5V-CAN
V
SUP
IO-0
MISO
RXD
TXD
CANL
CANH
GND
RST
DBG
V
DD
SPLIT
V
BAT
V
B
Q1*
D1
SAFE
V
E
V
DD
MUX-OUT
33903P
MCU
SPI
A/D
CAN Bus
VSENSE
* = Optional
I/O-3
V
BAT
V
BAT
I/O-2
NXP Semiconductors 7
33903/4/5
ORDERABLE PART
2 Orderable part
Table 1. MC33905 orderable part variations - (all devices rated at TA = -40 °C TO 125 °C)
NXP part number Version
(1), (2), (3)
VDD output
voltage
LIN
interface(s)
Wake-up input / LIN master
termination Package VAUX VSENSE MUX
MC33905D (Dual LIN)
MCZ33905BD3EK/R2 B
3.3 V
2
2 Wake-up + 2 LIN terms
or
3 Wake-up + 1 LIN terms
or
4 Wake-up + no LIN terms
SOIC 54-pin
exposed pad Yes Yes Yes
MCZ33905CD3EK/R2 C
MCZ33905DD3EK/R2 D
MCZ33905D5EK/R2
5.0 V
MCZ33905BD5EK/R2 B
MCZ33905CD5EK/R2 C
MCZ33905DD5EK/R2 D
MC33905S (Single LIN)
MCZ33905BS3EK/R2 B
3.3 V
1
3 Wake-up + 1 LIN terms
or
4 Wake-up + no LIN terms
SOIC 32-pin
exposed pad Yes Yes Yes
MCZ33905CS3EK/R2 C
MCZ33905DS3EK/R2 D
MCZ33905S5EK/R2
5.0 V
MCZ33905BS5EK/R2 B
MCZ33905CS5EK/R2 C
MCZ33905DS5EK/R2 D
Notes
1. Design changes in the ‘B’ version resolved VSUP slow ramp up issues, enhanced device current consumption and improved oscillator stability. ‘B’
version has an errata linked to the SPI operation.
2. Design changes in the ‘C’ version resolve the SPI deviation of all prior versions, and does not have the RxD short to ground detection feature.
3. ’C’ versions are no longer recommended for new design.
’D’ versions are recommended for new design, and include quality improvement, and has no electrical parameters specification changes.
Table 2. MC33904 orderable part variations - (all devices rated at TA = -40 °C TO 125 °C)
NXP part number Version
(4), (5), (6)
VDD output
voltage
LIN
interface(s)
Wake-up input / LIN master
termination Package VAUX VSENSE MUX
MC33904
MCZ33904B3EK/R2 B
3.3 V
04 Wake-up SOIC 32 pin
exposed pad Yes Yes Yes
MCZ33904C3EK/R2 C
MCZ33904D3EK/R2 D
MCZ33904A5EK/R2 A
5.0 V
MCZ33904B5EK/R2 B
MCZ33904C5EK/R2 C
MCZ33904D5EK/R2 D
Notes
4. Design changes in the “B” version resolved VSUP slow ramp up issues, enhanced device current consumption and improved oscillator stability.
‘B’ version has an errata linked to the SPI operation.
5. Design changes in the “C” version resolve the SPI deviation of all prior versions, and does not have the RxD short to ground detection feature.
6. ’C’ versions are no longer recommended for new design.
’D’ versions are recommended for new design, and include quality improvement, and has no electrical parameters specification changes.
8NXP Semiconductors
33903/4/5
ORDERABLE PART
Table 3. MC33903 orderable part variations - (all devices rated at TA = -40 °C TO 125 °C)
NXP part number Version
(8), (9), (10)
VDD output
voltage
LIN
interface(s)
Wake-up input / LIN master
termination Package VAUX VSENSE MUX
MC33903
MCZ33903B3EK/R2 B
3.3 V(7)
01 Wake-up SOIC 32 pin
exposed pad No No No
MCZ33903C3EK/R2 C
MCZ33903D3EK/R2 D
MCZ33903B5EK/R2 B
5.0 V(7)
MCZ33903C5EK/R2 C
MCZ33903D5EK/R2 D
MC33903D (Dual LIN)
MCZ33903BD3EK/R2 B
3.3 V
2
1 Wake-up + 2 LIN terms
or
2 Wake-up + 1 LIN terms
or
3 Wake-up + no LIN terms
SOIC 32 pin
exposed pad No Yes Yes
MCZ33903CD3EK/R2 C
MCZ33903DD3EK/R2 D
MCZ33903BD5EK/R2 B
5.0 VMCZ33903CD5EK/R2 C
MCZ33903DD5EK/R2 D
MC33903S (Single LIN)
MCZ33903BS3EK/R2 B
3.3 V
1
2 Wake-up + 1 LIN terms
or
3 Wake-up + no LIN terms
SOIC 32 pin
exposed pad No Yes Yes
MCZ33903CS3EK/R2 C
MCZ33903DS3EK/R2 D
MCZ33903BS5EK/R2 B
5.0 VMCZ33903CS5EK/R2 C
MCZ33903DS5EK/R2 D
MC33903P
MCZ33903CP5EK/R2 C5.0 V
03 Wake-up SOIC 32 pin
exposed pad No Yes Yes
MCZ33903DP5EK/R2 D
MCZ33903CP3EK/R2 C3.3 V
MCZ33903DP3EK/R2 D
Notes
7. VDD does not allow usage of an external PNP on the 33903.
8. Design changes in the ‘B’ version resolved VSUP slow ramp up issues, enhanced device current consumption and improved oscillator stability. ‘B’
version has an errata linked to the SPI operation.
9. Design changes in the “C” version resolve the SPI deviation of all prior versions, and does not have the RxD short to ground detection feature.
10. ’C’ versions are no longer recommended for new design.
’D’ versions are recommended for new design, and include quality improvement, and has no electrical parameters specification changes.
NXP Semiconductors 9
33903/4/5
INTERNAL BLOCK DIAGRAMS
3 Internal block diagrams
Figure 8. 33905 internal block diagram
Figure 9. 33904 internal block diagram
CS
SCLK
MOSI
INT
5 V-CAN
VSUP1
I/O-1
MISO
GND
SPI
RST
V
DD
Regulator
DBG
5V-CAN
Configurable
VDD
VB
Analog Monitoring
VBAUX
5 V Auxiliary
SAFE
Signals Condition & Analog MUX
Input-Output
VSENSE
VE
Regulator
V
S2-INT
Oscillator
Regulator
State Machine
Fail-safe
Power Management
VSUP2
V
S2-INT
VAUX
VCAUX
MUX-OUT
I/O-0
RXD
TXD
Enhanced High Speed CAN
Physical Interface
CANL
CANH
SPLIT
LIN Term #1
LIN-T1
LIN1 RXD-L1
TXD-L1
LIN 2.1 Interface - #1
V
S2-INT
LIN Term #2
LIN-T2
LIN2 RXD-L2
TXD-L2
LIN 2.1 Interface - #2
V
S2-INT
I/O-3
LIN Term #1
CS
SCLK
MOSI
INT
5 V-CAN
VSUP1
I/O-1
MISO
GND
SPI
RST
V
DD
Regulator
DBG
5V-CAN
Configurable
VDD
VB
Analog Monitoring
VBAUX
5V Auxiliary
SAFE
Signals Condition & Analog MUX
Input-Output
VSENSE
VE
Regulator
V
S2-INT
Oscillator
Regulator
State Machine
Fail-safe
Power Management
VSUP2
V
S2-INT
VAUX
VCAUX
MUX-OUT
I/O-0
LIN-T
LIN RXD-L
TXD-L
LIN 2.1 Interface - #1
RXD
TXD
Enhanced High Speed CAN
Physical Interface
CANL
CANH
SPLIT
V
S2-INT
33905D
33905S
CS
SCLK
MOSI
INT
5V-CAN
VSUP1
MISO
GND
SPI
RST
V
DD
Regulator
DBG
5V-CAN
Configurable
VDD
VB
Analog Monitoring
VBAUX
5V Auxiliary
SAFE
Signals Condition & Analog MUX
Input-Output
VSENSE
VE
Regulator
V
S2-INT
Oscillator
Regulator
State Machine
Fail-safe
Power Management
VSUP2
V
S2-INT
VAUX
VCAUX
MUX-OUT
RXD
TXD
Enhanced High Speed CAN
Physical Interface
CANL
CANH
SPLIT
I/O-1
I/O-2
I/O-3
I/O-0
10 NXP Semiconductors
33903/4/5
INTERNAL BLOCK DIAGRAMS
Figure 10. 33903 internal block diagram
CS
SCLK
MOSI
INT
5 V-CAN
VSUP2
MISO
GND
SPI
RST
V
DD
Regulator
DBG
5V-CAN
Configurable
VDD
Input-Output Regulator
V
S2-INT
Oscillator
State Machine
Power Management
V
S2-INT
I/O-0
RXD
TXD
Enhanced High Speed CAN
Physical Interface
CANL
CANH
SPLIT
SAFE
VSUP1
CS
SCLK
MOSI
INT
5 V-CAN
VSUP
MISO
GND
SPI
RST
V
DD
Regulator
DBG
5V-CAN
Configurable
VDD
VB
Analog Monitoring
SAFE
Signals Condition & Analog MUX
Input-Output
VSENSE
VE
Regulator
V
S-INT
Oscillator
State Machine
Fail-safe
Power Management
V
S-INT
MUX-OUT
IO-0
RXD
TXD
Enhanced High-speed CAN
Physical Interface
CANL
CANH
SPLIT
LIN Term #1
LIN-T1
LIN1 RXD-L1
TXD-L1
LIN 2.1 Interface - #1
V
S-INT
LIN Term #2
LIN-T2
LIN2 RXD-L2
TXD-L2
LIN 2.1 Interface - #2
V
S-INT
33903
33903D
I/O-3
LIN Term #1
CS
SCLK
MOSI
INT
5 V-CAN
VSUP
MISO
GND
SPI
RST
V
DD
Regulator
DBG
5V-CAN
Configurable
VDD
VB
Analog Monitoring
SAFE
Signals Condition & Analog MUX
Input-Output
VSENSE
VE
Regulator
V
S-INT
Oscillator
State Machine
Fail-safe
Power Management
MUX-OUT
I/O-0
LIN-T
LIN RXD-L
TXD-L
LIN 2.1 Interface - #1
RXD
TXD
Enhanced High Speed CAN
Physical Interface
CANL
CANH
SPLIT
V
S-INT
V
S-INT
I/O-3
CS
SCLK
MOSI
INT
5 V-CAN
VSUP
MISO
GND
SPI
RST
V
DD
Regulator
DBG
5V-CAN
Configurable
VDD
VB
Analog Monitoring
SAFE
Signals Condition & Analog MUX
Input-Output
VSENSE
VE
Regulator
V
S-INT
Oscillator
State Machine
Fail-safe
Power Management
MUX-OUT
I/O-0
RXD
TXD
Enhanced High Speed CAN
Physical Interface
CANL
CANH
SPLIT
V
S-INT
I/O-2
33903S
33903P
NXP Semiconductors 11
33903/4/5
PIN CONNECTIONS
4 Pin Connections
4.1 Pinout diagram
Figure 11. 33905D, MC33905S, MC33904 and MC33903 pin connections
4
5
6
7
8
9
10
11
12
2
3
54
51
50
49
48
47
46
45
44
43
53
52
1
13
14
15
16
42
41
40
39
MC33905D
17
18
19
20
21
22
23
24
25
26
27
38
37
36
35
34
33
32
31
30
29
28
TXD-L2
GND
RXD-L2
LIN-2
MISO
SCLK
MOSI
VSENSE
CS
VDD
TXD
VE
VB
I/O-1
RXD-L1
TXD-L1
LIN-1
INT
RST
RXD
SAFE
5V-CAN
CANL
SPLIT
DBG
CANH
VSUP2
MUX-OUT
V-AUX
V-CAUX
V-BAUX
VSUP1
LIN-T1/I/O-2
GND CAN
LIN-T2/I/O-3
I/O-0
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
4
5
6
7
8
9
10
11
12
2
3
32
29
28
27
26
25
24
23
22
21
31
30
1
13
14
15
16
20
19
18
17
MC33904
MISO
SCLK
MOSI
VSENSE
CS
VDD
TXD
SAFE
5V-CAN
CANL
SPLIT
DBG
CANH
VSUP2 VE
VB
I/O-1
NC
NC
NC
MUX-OUT
V-AUX
V-CAUX
V-BAUX
VSUP1
I/O-2
GND CAN
INT
RST
I/O-3 RXD
I/O-0
4
5
6
7
8
9
10
11
12
2
3
32
29
28
27
26
25
24
23
22
21
31
30
1
13
14
15
16
20
19
18
17
MC33905S
MISO
SCLK
MOSI
VSENSE
CS
VDD
TXD
SAFE
5V-CAN
CANL
SPLIT
DBG
CANH
VSUP2 VE
VB
I/O-1
RXD-L
TXD-L
LIN
MUX-OUT
V-AUX
V-CAUX
V-BAUX
VSUP1
LIN-T/I/O-2
GND CAN
INT
RST
I/O-3 RXD
I/O-0
GROUND
GROUND
4
5
6
7
8
9
10
11
12
2
3
32
29
28
27
26
25
24
23
22
21
31
30
1
13
14
15
16
20
19
18
17
MC33903
MISO
SCLK
MOSI
CS
VDD
TXD
SAFE
5V-CAN
CANL
SPLIT
DBG
CANH
NC
NC
NC
NC
VSUP1
GND CAN
INT
RST
RXD
I/O-0
GROUND
NC
NC
NC
NC
VSUP2
NC
NC
NC
NC
NC
Note: MC33905D, MC33905S, MC33904 and MC33903 are footprint compatible,
GROUND
32 pin exposed package
GND - LEAD FRAME
32 pin exposed package
GND - LEAD FRAME
32 pin exposed package
GND - LEAD FRAME
54 pin exposed package
GND - LEAD FRAME
12 NXP Semiconductors
33903/4/5
PIN CONNECTIONS
Figure 12. 33905D, MC33905S, MC33904 and MC33903 pin connections
4
5
6
7
8
9
10
11
12
2
3
32
29
28
27
26
25
24
23
22
21
31
30
1
13
14
15
16
20
19
18
17
MC33903D
MISO
SCLK
MOSI
VSENSE
CS
VDD
TXD
SAFE
5V-CAN
CANL
SPLIT
DBG
CANH
VE
LIN1
GND
LIN2
MUX-OUT
VSUP
GND CAN INT
RST
RXD
IO-0
32 pin exposed package
GROUND
RXD-L1
TXD-L1
VB
LIN-T2 / I/O-3
LIN-T1 / I/O-2
TXD-L2
GND
RXD-L2
4
5
6
7
8
9
10
11
12
2
3
32
29
28
27
26
25
24
23
22
21
31
30
1
13
14
15
16
20
19
18
17
MC33903S
MISO
SCLK
MOSI
VSENSE
CS
VDD
TXD
SAFE
5V-CAN
CANL
SPLIT
DBG
CANH
VE
LIN
GND
NC
MUX-OUT
VSUP
GND CAN INT
RST
RXD
I/O-0
32 pin exposed package
GROUND
RXD-L
TXD-L
VB
I/O-3
LIN-T / I/O-2
NC
GND
NC
Note: MC33903D, MC33903S, and MC33903P are footprint compatible.
GND - LEAD FRAMEGND - LEAD FRAME
4
5
6
7
8
9
10
11
12
2
3
32
29
28
27
26
25
24
23
22
21
31
30
1
13
14
15
16
20
19
18
17
MC33903P
MISO
SCLK
MOSI
VSENSE
CS
VDD
TXD
SAFE
5V-CAN
CANL
SPLIT
DBG
CANH
VE
N/C
GND
NC
MUX-OUT
VSUP
GND CAN INT
RST
RXD
I/O-0
32 pin exposed package
GROUND
N/C
N/C
VB
I/O-3
I/O-2
NC
GND
NC
GND - LEAD FRAME
NXP Semiconductors 13
33903/4/5
PIN CONNECTIONS
4.2 Pin definitions
A functional description of each pin can be found in the Functional pin description section beginning on page 32.
Table 4. 33903/4/5 pin definitions
54 Pin
33905D
32 Pin
33905S
32 Pin
33904
32 Pin
33903
32 Pin
33903D
32 Pin
33903S
32 Pin
33903P Pin Name Pin
Function
Formal
Name Definition
1-3, 20-
22, 27-
30, 32-
35, 52-
54
N/A 17, 18,
19
3-4,11-
14, 17-
21, 31,
32
N/A N/A N/A N/C No
Connect -Connect to GND.
N/A N/A N/A N/A N/A 14, 16,
17
14, 16,
17, 19-
21
N/C No
Connect
Do NOT connect the N/C pins to GND. Leave
these pins Open.
4111222VSUP/1 Power
Battery
Voltage
Supply 1
Supply input for the device internal supplies,
power on reset circuitry and the VDD regulator.
VSUP and VSUP1 supplies are internally
connected on part number MC33903BDEK and
MC33903BSEK
5 2 2 2 N/A N/A N/A VSUP2 Power
Battery
Voltage
Supply 2
Supply input for 5 V-CAN regulator, VAUX
regulator, I/O and LIN pins. VSUP1 and VSUP2
supplies are internally connected on part
number MC33903BDEK and MC33903BSEK
6 3 3 N/A 3 3 3
LIN-T2
or
I/O-3
Output
or
Input/
Output
LIN
Termination 2
or
Input/Output
3
33903D and 33905D - Output pin for the LIN2
master node termination resistor.
or
33903P, 33903S, 33903D, 33904, 33905S and
33905D - Configurable pin as an input or HS
output, for connection to external circuitry
(switched or small load). The input can be used
as a programmable Wake-up input in (LP)
mode. When used as a HS, no
overtemperature protection is implemented. A
basic short to GND protection function, based
on switch drain-source overvoltage detection, is
available.
7 4 4 N/A 4 4 4
LIN-T1
or
LIN-T
or
I/O-2
Output
or
Input/
Output
LIN
Termination
1
or
Input/Output
2
33905D - Output pin for the LIN1 master node
termination resistor.
or
33903P, 33903S, 33903D, 33904, 33905S and
33905D - Configurable pin as an input or HS
output, for connection to external circuitry
(switched or small load). The input can be used
as a programmable Wake-up input in (LP)
mode. When used as a HS, no
overtemperature protection is implemented. A
basic short to GND protection function, based
on switch drain-source overvoltage detection, is
available.
8555555SAFE Output Safe Output
(Active LOW)
Output of the safe circuitry. The pin is asserted
LOW if a fault event occurs (e.g.: software
watchdog is not triggered, VDD low, issue on the
RST pin, etc.). Open drain structure.
96666665 V-CAN Output 5V-CAN
Output voltage for the embedded CAN
interface. A capacitor must be connected to this
pin.
10 777777CANH Output CAN High CAN high output.
11 888888CANL Output CAN Low CAN low output.
12 999999GND-CAN Ground GND-CAN Power GND of the embedded CAN interface
13 10 10 10 10 10 10 SPLIT Output SPLIT Output Output pin for connection to the middle point of
the split CAN termination
14 NXP Semiconductors
33903/4/5
PIN CONNECTIONS
14 11 11 N/A N/A N/A N/A VBAUX Output VB Auxiliary Output pin for external path PNP transistor
base
15 12 12 N/A N/A N/A N/A VCAUX Output VCOLLECT
OR Auxiliary
Output pin for external path PNP transistor
collector
16 13 13 N/A N/A N/A N/A VAUX Output VOUT
Auxiliary Output pin for the auxiliary voltage.
17 14 14 N/A 11 11 11 MUX-OUT Output Multiplex
Output
Multiplexed output to be connected to an MCU
A/D input. Selection of the analog parameter
available at MUX-OUT is done via the SPI. A
switchable internal pull-down resistor is
integrated for VDD current sense
measurements.
18 15 15 15 12 12 12 I/O-0 Input/
Output
Input/Output
0
Configurable pin as an input or output, for
connection to external circuitry (switched or
small load). The voltage level can be read by
the SPI and via the MUX output pin. The input
can be used as a programmable Wake-up input
in LP mode. In LP, when used as an output, the
High-side (HS) or Low-side (LS) can be
activated for a cyclic sense function.
19 16 16 16 13 13 13 DBG Input Debug
Input to activate the Debug mode. In Debug
mode, no watchdog refresh is necessary.
Outside of Debug mode, connection of a
resistor between DBG and GND allows the
selection of Safe mode functionality.
23 N/A N/A N/A 14 N/A N/A TXD-L2 Input LIN Transmit
Data 2
LIN bus transmit data input. Includes an internal
pull-up resistor to VDD.
24,31 N/A N/A N/A 15, 18 15, 18 15, 18 GND Ground Ground Ground of the IC.
25 N/A N/A N/A 16 N/A N/A RXD-L2 Output LIN Receive
Data LIN bus receive data output.
26 N/A N/A N/A 17 N/A N/A LIN2 Input/
Output LIN bus LIN bus input output connected to the LIN bus.
36 17 N/A N/A 19 19 N/A
33903D/5D
LIN-1
33903S/5S
LIN
Input/
Output LIN bus LIN bus input output connected to the LIN bus.
37 18 N/A N/A 20 20 N/A
33903D/5D
TXD-L11
33903S/5S
TXD-L
Input LIN Transmit
Data
LIN bus transmit data input. Includes an internal
pull-up resistor to VDD.
38 19 N/A N/A 21 21 N/A
33903D/5D
RXD-L1
33903S/5S
RXD-L
Output LIN Receive
Data LIN bus receive data output.
39 20 20 N/A 22 22 22 VSENSE Input Sense input
Direct battery voltage input sense. A serial
resistor is required to limit the input current
during high voltage transients.
40 21 21 N/A N/A N/A N/A I/O-1 Input/
Output
Input Output
1
Configurable pin as an input or output, for
connection to external circuitry (switched or
small load). The voltage level can be read by
the SPI and the MUX output pin. The input can
be used as a programmable Wake-up input in
(LP) mode. It can be used in association with
I/O-0 for a cyclic sense function in (LP) mode.
Table 4. 33903/4/5 pin definitions (continued)
54 Pin
33905D
32 Pin
33905S
32 Pin
33904
32 Pin
33903
32 Pin
33903D
32 Pin
33903S
32 Pin
33903P Pin Name Pin
Function
Formal
Name Definition
NXP Semiconductors 15
33903/4/5
PIN CONNECTIONS
41 22 22 22 23 23 23 RST Output Reset Output
(Active LOW)
This is the device reset output whose main
function is to reset the MCU. This pin has an
internal pull-up to VDD. The reset input voltage
is also monitored in order to detect external
reset and safe conditions.
42 23 23 23 24 24 24 INT Output
Interrupt
Output
(Active LOW)
This output is asserted low when an enabled
interrupt condition occurs. This pin is an open
drain structure with an internal pull up resistor
to VDD.
43 24 24 24 25 25 25 CS Input Chip Select
(Active LOW)
Chip select pin for the SPI. When the CS is low,
the device is selected. In (LP) mode with VDD
ON, a transition on CS is a Wake-up condition
44 25 25 25 26 26 26 SCLK Input Serial Data
Clock
Clock input for the Serial Peripheral Interface
(SPI) of the device
45 26 26 26 27 27 27 MOSI Input Master Out /
Slave In SPI data received by the device
46 27 27 27 28 28 28 MISO Output Master In /
Slave Out
SPI data sent to the MCU. When the CS is high,
MISO is high-impedance
47 28 28 28 29 29 29 VDD Output Voltage
Digital Drain
5.0 or 3.3 V output pin of the main regulator for
the Microcontroller supply.
48 29 29 29 30 30 30 TXD Input Transmit
Data
CAN bus transmit data input. Internal pull-up to
VDD
49 30 30 30 31 31 31 RXD Output Receive Data CAN bus receive data output
50 31 31 N/A 32 32 32 VE Voltage
Emitter
Connection to the external PNP path transistor.
This is an intermediate current supply source
for the VDD regulator
51 32 32 N/A 1 1 1 VB Output Voltage Base Base output pin for connection to the external
PNP pass transistor
EX PAD EX PAD EX PAD EX PAD EX PAD EX PAD EX PAD GND Ground Ground Ground
Table 4. 33903/4/5 pin definitions (continued)
54 Pin
33905D
32 Pin
33905S
32 Pin
33904
32 Pin
33903
32 Pin
33903D
32 Pin
33903S
32 Pin
33903P Pin Name Pin
Function
Formal
Name Definition
16 NXP Semiconductors
33903/4/5
ELECTRICAL CHARACTERISTICS
5 Electrical characteristics
5.1 Maximum ratings
Table 5. Maximum ratings
All voltages are referenced to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol Ratings Value Unit Notes
Electrical ratings(11)
VSUP1/2
VSUP1/2TR
Supply Voltage at VSUP/1 and VSUP2
Normal Operation (DC)
Transient Conditions (Load Dump)
-0.3 to 28
-0.3 to 40
V
VBUSLIN
VBUSLINTR
DC voltage on LIN/1 and LIN2
Normal Operation (DC)
Transient Conditions (Load Dump)
-28 to 28
-28 to 40
V
VBUS
VBUSTR
DC voltage on CANL, CANH, SPLIT
Normal Operation (DC)
Transient Conditions (Load Dump)
-28 to 28
-32 to 40
V
VSAFE
VSAFETR
DC Voltage at SAFE
Normal Operation (DC)
Transient Conditions (Load Dump)
-0.3 to 28
-0.3 to 40
V
VI/O
VI/OTR
DC Voltage at I/O-0, I/O-1, I/O-2, I/O-3 (LIN-T Pins)
Normal Operation (DC)
Transient Conditions (Load Dump)
-0.3 to 28
-0.3 to 40
V
VDIGLIN DC voltage on TXD-L, TXD-L1 TXD-L2, RXD-L, RXD-L1, RXD-L2 -0.3 to VDD +0.3 V
VDIG DC voltage on TXD, RXD -0.3 to VDD +0.3 V(13)
VINT DC Voltage at INT -0.3 to 10 V
VRST DC Voltage at RST -0.3 to VDD +0.3 V
VRST DC Voltage at MOSI, MSIO, SCLK and CS -0.3 to VDD +0.3 V
VMUX DC Voltage at MUX-OUT -0.3 to VDD +0.3 V
VDBG DC Voltage at DBG -0.3 to 10 V
ILH Continuous current on CANH and CANL 200 mA
VREG DC voltage at VDD, 5V-CAN, VAUX, VCAUX -0.3 to 5.5 V
VREG DC voltage at VBASE and VBAUX -0.3 to 40 V(12)
VE DC voltage at VE -0.3 to 40 V(13)
VSENSE DC voltage at VSENSE -28 to 40 V
Notes
11. The voltage on non-VSUP pins should never exceed the VSUP voltage at any time or permanent damage to the device may occur.
12. If the voltage delta between VSUP/1/2 and VBASE is greater than 6.0 V, the external VDD ballast current sharing functionality may be damaged.
13. Potential Electrical Over Stress (EOS) damage may occur if RXD is in contact with VE while the device is ON.
NXP Semiconductors 17
33903/4/5
ELECTRICAL CHARACTERISTICS
Figure 13. PCB with top and bottom layer dissipation area (dual layer)
VESD1-1
VESD1-2
VESD2-1
VESD2-2
VESD3-1
VESD3-2
VESD3-3
VESD4-1
VESD4-2
VESD4-3
ESD Capability
AECQ100(14)
Human Body Model - JESD22/A114 (CZAP = 100 pF, RZAP = 1500 Ω)
CANH and CANL. LIN1 and LIN2, Pins versus all GND pins
all other Pins including CANH and CANL
Charge Device Model - JESD22/C101 (CZAP = 4.0 pF)
Corner Pins (Pins 1, 16, 17, and 32)
All other Pins (Pins 2-15, 18-31)
Tested per IEC 61000-4-2 (CZAP = 150 pF, RZAP = 330 Ω)
Device unpowered, CANH and CANL pin without capacitor, versus GND
Device unpowered, LIN, LIN1 and LIN2 pin, versus GND
Device unpowered, VS1/VS2 (100 nF to GND), versus GND
Tested per specific OEM EMC requirements for CAN and LIN with
additional capacitor on VSUP/1/2 pins (See Typical applications on page
92)
CANH, CANL without bus filter
LIN, LIN1 and LIN2 with and without bus filter
I/O with external components (22 k - 10 nF)
±8000
±2000
±750
±500
±15000
±15000
±15000
±9000
±12000
±7000
V
Thermal ratings
TJJunction temperature 150 °C
TAAmbient temperature -40 to 125 °C
TST Storage temperature -50 to 150 °C
Thermal resistance
RθJA Thermal resistance junction to ambient 50 °C/W (17)
TPPRT Peak package reflow temperature during reflow Note 16 °C (15), (16)
Notes
14. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), the Charge Device Model (CDM),
and Robotic (CZAP = 4.0 pF).
15. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
16. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and
Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all
orderable parts, and review parametrics.
17. This parameter was measured according to Figure 13:
Table 5. Maximum ratings (continued)
All voltages are referenced to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage
to the device.
Symbol Ratings Value Unit Notes
PCB 100mm x 100mm
Bottom side
20mm x 40mm
Top side, 300 sq. mm
(20mmx15mm)
Bottom view
18 NXP Semiconductors
33903/4/5
ELECTRICAL CHARACTERISTICS
5.2 Static electrical characteristics
Table 6. Static electrical characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Unit Notes
Power input
VSUP1/VSUP2 Nominal DC Voltage Range 5.5 -28 V(18)
VSUP1/VSUP2 Extended DC Low Voltage Range 4.0 -5.5 V(19)
VS1_LOW
Undervoltage Detector Thresholds, at the VSUP/1 pin,
Low threshold (VSUP/1 ramp down)
High threshold (VSUP/1 ramp up)
Hysteresis
Note: function not active in LP mode
5.5
-
0.22
6.0
-
0.35
6.5
6.6
0.5
V
VS2_LOW
Undervoltage Detector Thresholds, at the VSUP2 pin:
Low threshold (VSUP2 ramp down)
High threshold (VSUP2 ramp up)
Hysteresis
Note: function not active in LP modes
5.5
-
0.22
6.0
-
0.35
6.5
6.6
0.5
V
VS_HIGH
VSUP Overvoltage Detector Thresholds, at the VSUP/1 pin:
Not active in LP modes 16.5 17 18.5 V
BATFAIL Battery loss detection threshold, at the VSUP/1 pin. 2.0 2.8 4.0 V
VSUP-TH1 VSUP/1 to turn VDD ON, VSUP/1 rising -4.1 4.5 V
VSUP-TH1HYST VSUP/1 to turn VDD ON, hysteresis (Guaranteed by design) 150 180 mV
ISUP1
Supply current
- from VSUP/1
- from VSUP2, (5V-CAN VAUX, I/O OFF)
-
-
2.0
0.05
4.0
0.85
mA (20), (21)
ISUP1+2
Supply current, ISUP1 + ISUP2, Normal mode, VDD ON
- 5 V-CAN OFF, VAUX OFF
- 5 V-CAN ON, CAN interface in Sleep mode, VAUX OFF
- 5 V-CAN OFF, Vaux ON
- 5 V-CAN ON, CAN interface in TXD/RXD mode, VAUX OFF, I/O-x
disabled
-
-
-
-
2.8
-
-
-
4.5
5.0
5.5
8.0
mA
ILPM_OFF
LP mode VDD OFF. Wake-up from CAN, I/O-x inputs
VSUP ≤ 18 V, -40 to 25 °C
VSUP ≤ 18 V, 125 °C
-
-
15
-
35
50
μA
ILPM_ON
LP mode VDD ON (5.0 V) with VDD undervoltage and VDD
overcurrent monitoring, Wake-up from CAN, I/O-x inputs
VSUP ≤ 18 V, -40 to 25 °C, IDD = 1.0 μA
VSUP ≤ 18 V, -40 to 25 °C, IDD = 100 μA
VSUP ≤ 18 V, 125 °C, IDD = 100 μA
-
-20
40
-
-
65
85
μA
IOSC
LP mode, additional current for oscillator (used for: cyclic sense,
forced Wake-up, and in LP VDD ON mode cyclic interruption and
watchdog)
VSUP ≤ 18 V, -40 to 125 °C -5.0 9.0
μA
VDBG Debug mode DBG voltage range 8.0 -10 V
Notes
18. All parameters in spec (ex: VDD regulator tolerance).
19. Device functional, some parameters could be out of spec. VDD is active, device is not in Reset mode if the lowest VDD undervoltage reset threshold
is selected (approx. 3.4 V). CAN and I/Os are not operational.
20. In Run mode, CAN interface in Sleep mode, 5 V-CAN and VAUX turned OFF. IOUT at VDD < 50 mA. Ballast: turned OFF or not connected.
21. VSUP1 and VSUP2 supplies are internally connected on part number MC33903BDEK and MC33903BSEK. Therefore, ISUP1 and ISUP2 cannot
be measured individually.
NXP Semiconductors 19
33903/4/5
ELECTRICAL CHARACTERISTICS
VDD Voltage regulator, VDD pin
VOUT-5.0
VOUT-5.0-EMC
VOUT-3.3
Output Voltage
VDD = 5.0 V, VSUP 5.5 to 28 V, IOUT 0 to 150 mA
VDD = 5.0 V, under EMC immunity test condition
VDD = 3.3 V, VSUP 5.5 to 28 V, IOUT 0 to 150 mA
4.9
4.9
3.234
5.0
5.0
3.3
5.1
5.15
3.4
V(22)
VDROP
Drop voltage without external PNP pass transistor
VDD = 5.0 V, IOUT = 100 mA
VDD = 5.0 V, IOUT = 150 mA
-
-
330
-
450
500
mV (23)
VDROP-B
Drop voltage with external transistor
IOUT = 200 mA (I_BALLAST + I_INTERNAL)-350 500 mV (23)
VSUP1-3.3
VSUP/1 to maintain VDD within VOUT-3.3 specified voltage range
VDD = 3.3 V, IOUT = 150 mA
VDD = 3.3 V, IOUT = 200 mA, external transistor implemented
4.0
4.0
-
-
-
-
V
KExternal ballast versus internal current ratio (I_BALLAST = K x Internal
current) 1.5 2.0 2.5
ILIM Output Current limitation, without external transistor 150 350 550 mA
TPW Temperature pre-warning (Guaranteed by design) -140 -°C
TSD Thermal shutdown (Guaranteed by design) 160 - - °C
CEXT Range of decoupling capacitor (Guaranteed by design) 4.7 -100 μF(24)
VDDLP
LP mode VDD ON, IOUT ≤ 50 mA (time limited)
VDD = 5.0 V, 5.6 V ≤ VSUP ≤ 28 V
VDD = 3.3 V, 5.6 V ≤ VSUP ≤ 28 V
4.75
3.135
5.0
3.3
5.25
3.465
V
LP-IOUTDC
LP mode VDD ON, dynamic output current capability (Limited duration.
Ref. to device description). - - 50 mA
LP-ITH
LP VDD ON mode:
Overcurrent Wake-up threshold.
Hysteresis
1.0
0.1
3.0
1.0
-
-
mA
LP-VDROP
LP mode VDD ON, drop voltage, at IOUT = 30 mA (Limited duration.
Ref. to device description) -200 400 mV (23)
LP-MINVS
LP mode VDD ON, min VSUP operation (Below this value, a VDD,
undervoltage reset may occur) 5.5 - - V
VDD_OFF VDD when VSUP < VSUP-TH1, at I_VDD ≤ 10 μA (Guaranteed by design) - - 0.3 V
VDD_START UP
VDD when VSUP ≥ VSUP-TH1, at I_VDD ≤ 40 mA (Guaranteed with
parameter VSUP-TH1
3.0 - - V
Notes
22. Guaranteed by design. During immunity tests, according to IEC62132-4, with RF injection applied to CAN or LIN pins. No filter components on
CAN or LIN pins. When immunity tests are performed with a CAN filter component (common mode choke) or LIN filter component (capacitor), the
VDD specification is 5.0 V ±2%.
23. For 3.3 V VDD devices, the drop-out voltage test condition leads to a VSUP below the min VSUP threshold (4.0 V). As a result, the dropout voltage
parameter cannot be specified.
24. The regulator is stable without an external capacitor. Usage of an external capacitor is recommended for AC performance.
Table 6. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Unit Notes
20 NXP Semiconductors
33903/4/5
ELECTRICAL CHARACTERISTICS
Voltage regulator for CAN interface supply, 5.0 V-CAN pin
5V-C OUT
Output voltage, VSUP/2 = 5.5 to 40 V
IOUT 0 to 160 mA 4.75 5.0 5.25 V
5V-C ILIM Output Current limitation 160 280 -mA (25)
5V-C UV Undervoltage threshold 4.1 4.5 4.7 V
5V-CTS Thermal shutdown (Guaranteed by design) 160 - - °C
CEXT-CAN External capacitance (Guaranteed by design) 1.0 -100 μF
V auxiliary output, 5.0 and 3.3 V selectable pin VB-Aux, VC-Aux, Vaux
VAUX
VAUX output voltage
VAUX = 5.0 V, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA
VAUX = 3.3 V, VSUP = VSUP2 5.5 to 40 V, IOUT 0 to 150 mA
4.75
3.135
5.0
3.3
5.25
3.465
V
VAUX-UVTH
VAUX undervoltage detector (VAUX configured to 5.0 V)
Low Threshold
Hysteresis
VAUX undervoltage detector (VAUX configured to 3.3 V, default
value)
4.2
0.06
2.75
4.5
-
3.0
4.70
0.12
3.135
V
VAUX-ILIM
VAUX overcurrent threshold detector
VAUX set to 3.3 V
VAUX set to 5.0 V
250
230
360
330
450
430
mA
VAUX CAP External capacitance (Guaranteed by design) 2.2 -100 μF
Undervoltage reset and reset function, RST pin
VRST-TH1
VDD undervoltage threshold down - 90% VDD (VDD 5.0 V)
VDD undervoltage threshold up - 90% VDD (VDD 5.0 V)
VDD undervoltage threshold down - 90% VDD (VDD 3.3 V)
VDD undervoltage threshold up - 90% VDD (VDD 3.3 V)
4.5
-
2.75
-
4.65
-
3.0
-
4.85
4.90
3.135
3.135
V
(26), (28)
(26), (28)
VRST-TH2-5 VDD undervoltage reset threshold down - 70% VDD (VDD 5.0 V) 2.95 3.2 3.45 V(27), (28)
VRST-HYST
Hysteresis
for threshold 90% VDD, 5.0 V device
for threshold 70% VDD, 5.0 V device
Hysteresis 3.3 V VDD
for threshold 90% VDD, 3.3 V device
20
10
10
-
-
-
150
150
150
mV
VRST-LP
VDD undervoltage reset threshold down - LP VDD ON mode
(Note: device change to Normal Request mode). VDD 5.0 V
(Note: device change to Normal Request mode). VDD 3.3 V
4.0
2.75
4.5
3.0
4.85
3.135
V
VOL Reset VOL @ 1.5 mA, VSUP 5.5 to 28 V - 300 500 mV
IRESET LOW Current limitation, Reset activated, VRESET = 0.9 x VDD 2.5 7.0 10 mA
RPULL-UP Pull-up resistor (to VDD pin) 8.0 11 15 kΩ
Notes
25. Current limitation will be reported by setting a flag.
26. Generate a Reset or an INT. SPI programmable
27. Generate a Reset
28. In Non-LP modes
Table 6. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Unit Notes
NXP Semiconductors 21
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ELECTRICAL CHARACTERISTICS
Undervoltage reset and reset function, RST PIN (continued)
VSUP-RSTL VSUP to guaranteed reset low level 2.5 - - V (29)
VRST-VTH
Reset input threshold
Low threshold, VDD = 5.0 V
High threshold, VDD = 5.0 V
Low threshold, VDD = 3.3 V
High threshold, VDD = 3.3 V
1.5
-
0.99
-
-
-
-
-
-
3.5
-
2.31
V
VHYST Reset input hysteresis 0.5 1.0 1.5 V
I/O pins when function selected is output
VI/O-0 HSDRP I/O-0 HS switch drop @ I = -12 mA, VSUP = 10.5 V - 0.5 1.4 V
VI/O-2-3 HSDRP I/O-2 and I/O-3 HS switch drop @ I = -20 mA, VSUP = 10.5 V - 0.5 1.4 V
VI/O-1 HSDRP I/O-1, HS switch drop @ I = -400 μA, VSUP = 10.5 V - 0.4 1.4 V
VI/O-01 LSDRP I/O-0, I/O-1 LS switch drop @ I = 400 μA, VSUP = 10.5 V - 0.4 1.4 V
II/O_LEAK Leakage current, I/O-x ≤ VSUP -0.1 3.0 μA
I/O pins when function selected is input
VI/O_NTH Negative threshold 1.4 2.0 2.9 V
VI/O_PTH Positive threshold 2.1 3.0 3.8 V
VI/O_HYST Hysteresis 0.2 1.0 1.4 V
II/O_IN Input current, I/O ≤ VSUP/2 -5.0 1.0 5.0 μA
RI/O-X
I/O-0 and I/O-1 input resistor. I/O-0 (or I/O-1) selected in
register, 2.0 V < VI/O-X <16 V (Guaranteed by design). -100 - kΩ
VSENSE input
VSENSE_TH
VSENSE undervoltage threshold (Not active in LP modes)
Low Threshold
High threshold
Hysteresis
8.1
-
0.1
8.6
-
0.25
9.0
9.1
0.5
V
RVSENSE
Input resistor to GND. In all modes except in LP modes. (Guaranteed
by design). -125 - kΩ
Notes
29. Reset must be kept low
Table 6. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Unit Notes
22 NXP Semiconductors
33903/4/5
ELECTRICAL CHARACTERISTICS
Analog MUX output
VOUT_MAX Output Voltage Range, with external resistor to GND >2.0 kΩ0.0 - VDD - 0.5 V
RMI Internal pull-down resistor for regulator output current sense 0.8 1.9 2.8 kΩ
CMUX External capacitor at MUX OUTPUT (Guaranteed by design) - - 1.0 nF (30)
TEMP-COEFF
Chip temperature sensor coefficient (Guaranteed by design and
device characterization)
VDD = 5.0 V
VDD = 3.3 V
20
13.2
21
13.9
22
14.6
mv/°C
VTEMP
Chip temperature: MUX-OUT voltage
VDD = 5.0 V, TA = 125 °C
VDD = 3.3 V, TA = 125 °C
3.6
2.45
3.75
2.58
3.9
2.65
V
VTEMP(GD)
Chip temperature: MUX-OUT voltage (guaranteed by design and
characterization)
TA = -40 °C, VDD = 5.0 V
TA = 25 °C, VDD = 5.0 V
TA = -40 °C, VDD = 3.3 V
TA = 25 °C, VDD = 3.3 V
0.12
1.5
0.07
1.08
0.30
1.65
0.19
1.14
0.48
1.8
0.3
1.2
V
VSENSE GAIN
Gain for VSENSE, with external 1.0 k 1% resistor
VDD = 5.0 V
VDD = 3.3 V
5.42
8.1
5.48
8.2
5.54
8.3
VSENSE OFFSET Offset for VSENSE, with external 1.0 k 1% resistor -20 -20 mV
VSUP/1 RATIO
Divider ratio for VSUP/1
VDD = 5.0 V
VDD = 3.3 V
5.335
7.95
5.5
8.18
5.665
8.45
VI/O RATIO
Attenuation/Gain ratio for I/O-0 and I/O-1 actual voltage:
VDD = 5.0 V, I/O = 16 V (Attenuation, MUX-OUT register bit 3 set to
1)
VDD = 5.0 V, (Gain, MUX-OUT register bit 3 set to 0)
VDD = 3.3 V, I/O = 16 V (Attenuation, MUX-OUT register bit 3 set to
1)
VDD = 3.3 V, (Gain, MUX-OUT register bit 3 set to 0)
3.8
-
5.6
-
4.0
2.0
5.8
1.3
4.2
-
6.2
-
VREF
Internal reference voltage
VDD = 5.0 V
VDD = 3.3 V
2.45
1.64
2.5
1.67
2.55
1.7
V
IDD_RATIO
Current ratio between VDD output & IOUT at MUX-OUT
(IOUT at MUX-OUT = IDD out / IDD_RATIO)
At IOUT = 50 mA
I_OUT from 25 to 150 mA
80
62.5
97
97
115
117
SAFE output
VOL SAFE low level, at I = 500 μA0.0 0.2 1.0 V
ISAFE-IN
Safe leakage current (VDD low, or device unpowered). VSAFE 0 to
28 V. -0.0 1.0 μA
Notes
30. When C is higher than CMUX, a serial resistor must be inserted
Table 6. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Unit Notes
NXP Semiconductors 23
33903/4/5
ELECTRICAL CHARACTERISTICS
Interrupt
VOL Output low voltage, IOUT = 1.5 mA -0.2 1.0 V
RPU Pull-up resistor 6.5 10 14 kΩ
VOH-LPVDDON Output high level in LP VDD ON mode (Guaranteed by design) 3.9 4.3 V
VMAX
Leakage current INT voltage = 10 V (to allow high-voltage on MCU
INT pin) -35 100 μA
I SINK Sink current, VINT > 5.0 V, INT low state 2.5 6.0 10 mA
MISO, MOSI, SCLK, CS pins
VOL Output low voltage, IOUT = 1.5 mA (MISO) - - 1.0 V
VOH Output high voltage, IOUT = -0.25 mA (MISO) VDD -0.9 - V
VIL Input low voltage (MOSI, SCLK,CS) - - 0.3 x VDD V
VIH Input high voltage (MOSI, SCLK,CS)0.7 x VDD - - V
IHZ Tri-state leakage current (MISO) -2.0 -2.0 μA
IPU Pull-up current (CS)200 370 500 μA
CAN logic input pins (TXD)
VIH High Level Input Voltage 0.7 x VDD - VDD + 0.3 V
VIL Low Level Input Voltage -0.3 -0.3 x VDD V
IPDWN
Pull-up Current, TXD, VIN = 0 V
VDD = 5.0 V
VDD = 3.3 V
-850
-500
-650
-250
-200
-175
µA
CAN data output pins (RXD)
VOUTLOW
Low Level Output Voltage
IRXD = 5.0 mA 0.0 -0.3 x VDD
V
VOUTHIGH
High Level Output Voltage
IRX = -3.0 mA 0.7 x VDD - VDD
V
IOUTHIGH
High Level Output Current
VRXD = VDD - 0.4 V 2.5 5.0 9.0 mA
IOUTLOW
Low Level Input Current
VRXD = 0.4 V 2.5 5.0 9.0 mA
Table 6. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Unit Notes
24 NXP Semiconductors
33903/4/5
ELECTRICAL CHARACTERISTICS
CAN output pins (CANH, CANL)
VCOM Bus pins common mode voltage for full functionality -12 -12 V
VCANH-VCANL Differential input voltage threshold 500 -900 mV
VDIFF-HYST Differential input hysteresis 50 - - mV
RIN Input resistance 5.0 -50 kΩ
RIN-DIFF Differential input resistance 10 -100 kΩ
RIN-MATCH Input resistance matching -3.0 0.0 3.0 %
VCANH
CANH output voltage (45 Ω < RBUS < 65 Ω)
TXD dominant state
TXD recessive state
2.75
2.0
3.5
2.5
4.5
3.0
V
VCANL
CANL output voltage (45 Ω < RBUS < 65 Ω)
TXD dominant state
TXD recessive state
0.5
2.0
1.5
2.5
2.25
3.0
V
VOH-VOL
Differential output voltage (45 Ω < RBUS < 65 Ω)
TXD dominant state
TXD recessive state
1.5
-0.5
2.0
0.0
3.0
0.05
V
ICANH CAN H output current capability - Dominant state - - -30 mA
ICANL CAN L output current capability - Dominant state 30 - - mA
ICANL-OC CANL overcurrent detection - Error reported in register 75 120 195 mA
ICANH-OC CANH overcurrent detection - Error reported in register -195 -120 -75 mA
RINSLEEP
CANH, CANL input resistance to GND, device supplied, CAN in Sleep
mode, V_CANH, V_CANL from 0 to 5.0 V 5.0 -50 kΩ
VCANLP CANL, CANH output voltage in LP VDD OFF and LP VDD ON modes -0.1 0.0 0.1 V
ICAN-UN_SUP1
CANH, CANL input current, VCANH, VCANL = 0 to 5.0 V, device
unpowered (VSUP, VDD, 5V-CAN: open). -3.0 10 µA (31)
ICAN-UN_SUP2
CANH, CANL input current, VCANH, VCANL = -2.0 to 7.0 V, device
unpowered (VSUP, VDD, 5V-CAN: open). - - 250 µA (31)
VDIFF-R-LP Differential voltage for recessive bit detection in LP mode - - 0.4 V(32)
VDIFF-D-LP Differential voltage for dominant bit detection in LP mode 1.15 - - V (32)
CANH and CANL diagnostic information
VLG CANL to GND detection threshold 1.6 1.75 2.0 V
VHG CANH to GND detection threshold 1.6 1.75 2.0 V
VLVB CANL to VBAT detection threshold, VSUP/1 and VSUP2 > 8.0 V - VSUP -2.0 - V
VHVB CANH to VBAT detection threshold, VSUP/1 and VSUP2 > 8.0 V - VSUP -2.0 - V
VL5 CANL to VDD detection threshold 4.0 VDD -0.43 - V
VH5 CANH to VDD detection threshold 4.0 VDD -0.43 - V
Notes
31. VSUP, VDD, 5V-CAN: shorted to GND, or connected to GND via a 47 k resistor instances are guaranteed by design and device characterization.
32. Guaranteed by design and device characterization.
Table 6. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Unit Notes
NXP Semiconductors 25
33903/4/5
ELECTRICAL CHARACTERISTICS
SPLIT
VSPLIT
Output voltage
Loaded condition ISPLIT = ±500 µA
Unloaded condition Rmeasure > 1.0 MΩ
0.3 x VDD
0.45 x VDD
0.5 x VDD
0.5 x VDD
0.7 x VDD
0.55 x VDD
V
ILSPLIT
Leakage current
-12 V < VSPLIT < +12 V
-22 to -12 V < VSPLIT < +12 to +35 V
-
-
0.0
-
5.0
200
µA
LIN terminals (LIN-T/1, LIN-T2)
VLT_HSDRP LIN-T1, LIN-T2, HS switch drop @ I = -20 mA, VSUP > 10.5 V - 1.0 1.4 V
LIN1 & LIN2 33903D/5D pin - LIN 33903S/5S pin (parameters guaranteed for VSUP/1, VSUP2 7.0 V ≤ VSUP ≤ 18 V)
VBAT Operating Voltage Range 8.0 -18 V
VSUP Supply Voltage Range 7.0 -18 V
IBUS_LIM
Current Limitation for Driver Dominant State
Driver ON, VBUS = 18 V 40 90 200 mA
IBUS_PAS_DOM
Input Leakage Current at the receiver
Driver off; VBUS = 0 V; VBAT = 12 V -1.0 - - mA
IBUS_PAS_REC
Leakage Output Current to GND
Driver Off; 8.0 V < VBAT < 18 V; 8.0 V < VBUS < 18 V; VBUS ≥ VBAT - - 20 µA
IBUS_NO_GND
Control unit disconnected from ground (Loss of local ground must not
affect communication in the residual network)
GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V (Guaranteed by
design)
-1.0 -1.0 mA
IBUSNO_BAT
VBAT Disconnected; VSUP_DEVICE = GND; 0 < VBUS < 18 V (Node has
to sustain the current that can flow under this condition. Bus must
remain operational under this condition). (Guaranteed by design)
- - 100 µA
VBUSDOM Receiver Dominant State - - 0.4 VSUP
VBUSREC Receiver Recessive State 0.6 - - VSUP
VBUS_CNT
Receiver Threshold Center
(VTH_DOM + VTH_REC)/2 0.475 0.5 0.525 VSUP
VHYS
Receiver Threshold Hysteresis
(VTH_REC - VTH_DOM) - - 0.175 VSUP
VBUSWU LIN Wake-up threshold from LP VDD ON or LP VDD OFF mode -5.3 5.8 V
RSLAVE LIN Pull-up Resistor to VSUP 20 30 60 kΩ
TLINSD Overtemperature Shutdown (Guaranteed by design) 140 160 180 °C
TLINSD_HYS Overtemperature Shutdown Hysteresis (Guaranteed by design) -10 -°C
Table 6. Static electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect
the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Unit Notes
26 NXP Semiconductors
33903/4/5
ELECTRICAL CHARACTERISTICS
5.3 Dynamic electrical characteristics
Table 7. Dynamic electrical characteristics
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Unit Notes
SPI timing
FREQ SPI Operation Frequency (MISO cap = 50 pF) 0.25 -4.0 MHz
tPCLK SCLK Clock Period 250 - N/A ns
tWSCLKH SCLK Clock High Time 125 - N/A ns
tWSCLKL SCLK Clock Low Time 125 - N/A ns
tLEAD
Falling Edge of CS to Rising Edge of SCLK
‘C’ and ‘D’ versions
All others
30
550
-
-
N/A
N/A
ns
tLEAD
Falling Edge of CS to Rising Edge of SCLK when CS_low flag is set to
‘1’
‘C’ and ‘D’ versions
All others
0.030
0.55
-
-
2.5
2.5
μs
tLAG Falling Edge of SCLK to Rising Edge of CS 30 - N/A ns
tSISU MOSI to Falling Edge of SCLK 30 - N/A ns
tSIH Falling Edge of SCLK to MOSI 30 - N/A ns
tRSO MISO Rise Time (CL = 50 pF) - - 30 ns
tFSO MISO Fall Time (CL = 50 pF) - - 30 ns
tSOEN
tSODIS
Time from Falling to MISO Low-impedance
Time from Rising to MISO High-impedance
-
-
-
-
30
30 ns
tVALID Time from Rising Edge of SCLK to MISO Data Valid - - 30 ns
tCSLOW
Delay between falling and rising edge on CS
‘C’ and ‘D’ versions
All others
1.0
5.5
-
-
N/A
N/A
μs
tCS-TO CS Chip Select Low Timeout Detection 2.0 - - ms
Supply, voltage regulator, reset
tVS_LOW1/2_DGLT VSUP undervoltage detector threshold deglitcher 30 50 100 μs
tRISE-ON Rise time at turn ON. VDD from 1.0 to 4.5 V. 2.2 μF at the VDD pin. 50 250 800 μs
tRST-DGLT Deglitcher time to set RST pin low 20 30 40 μs
Reset pulse duration
tRST-PULSE
VDD undervoltage (SPI selectable)
short, default at power on when BATFAIL bit set
medium
medium long
long
0.9
4.0
8.5
17
1.0
5.0
10
20
1.4
6.0
12
24
ms
tRST-WD Watchdog reset 0.9 1.0 1.4 ms
I/O input
tIODT Deglitcher time (Guaranteed by design) 19 30 41 μs
VSENSE input
tBFT Undervoltage deglitcher time 30 -100 μs
NXP Semiconductors 27
33903/4/5
ELECTRICAL CHARACTERISTICS
Interrupt
tINT-PULSE
INT pulse duration (refer to SPI for selection. Guaranteed by design)
short (25 to 125 °C)
short (-40 °C)
long (25 to 125 °C)
long (-40 °C)
20
20
90
90
25
25
100
100
35
40
130
140
μs
State diagram timings
tD_NM
Delay for SPI Timer A, Timer B or Timer C write command after
entering Normal mode
(No command should occur within tD_NM.
tD_NM delay definition: from CS rising edge of “Go to Normal mode (i.e.
0x5A00)” command to CS falling edge of “Timer write” command)
60 - - μs
tTIMING-ACC
Tolerance for: watchdog period in all modes, FWU delay, Cyclic sense
period and active time, Cyclic Interrupt period, LP mode overcurrent
(unless otherwise noted)
-10 -10 %(36)
CAN dynamic characteristics
tDOUT TXD Dominant State Timeout 300 600 1000 µs
tDOM Bus dominant clamping detection 300 600 1000 µs
tLRD
Propagation loop delay TXD to RXD, recessive to dominant (Fast slew
rate) 60 120 210 ns
tTRD Propagation delay TXD to CAN, recessive to dominant -70 110 ns
tRRD Propagation delay CAN to RXD, recessive to dominant -45 140 ns
tLDR
Propagation loop delay TXD to RXD, dominant to recessive (Fast slew
rate) 100 120 200 ns
tTDR Propagation delay TXD to CAN, dominant to recessive -75 150 ns
tRDR Propagation delay CAN to RXD, dominant to recessive -50 140 ns
tLOOP-MSL
Loop time TXD to RXD, Medium Slew Rate (Selected by SPI)
Recessive to Dominant
Dominant to Recessive
-
-
200
200
-
-
ns
tLOOP-SSL
Loop time TXD to RXD, Slow Slew Rate (Selected by SPI)
Recessive to Dominant
Dominant to Recessive
-
-
300
300
-
-
ns
tCAN-WU1-F
CAN Wake-up filter time, single dominant pulse detection (See
Figure 35)0.5 2.0 5.0 μs(33)
tCAN-WU3-F CAN Wake-up filter time, 3 dominant pulses detection 300 - - ns (34)
tCAN-WU3-TO
CAN Wake-up filter time, 3 dominant pulses detection timeout (See
Figure 36)- - 120 μs(35)
Notes
33. No Wake-up for single pulse shorter than tCAN-WU1 min. Wake-up for single pulse longer than tCAN-WU1 max.
34. Each pulse should be greater than tCAN-WU3-F min. Guaranteed by design, and device characterization.
35. The 3 pulses should occur within tCAN-WU3-TO. Guaranteed by design, and device characterization.
36. Guaranteed by design.
Table 7. Dynamic electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Unit Notes
28 NXP Semiconductors
33903/4/5
ELECTRICAL CHARACTERISTICS
LIN physical layer: driver characteristics for normal slew rate - 20.0 kBit/sec according to lin physical layer specification
Bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. See Figure 18, page 30.
D1
Duty Cycle 1:
THREC(MAX) = 0.744 * VSUP
THDOM(MAX) = 0.581 * VSUP
D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V ≤ VSUP ≤ 18 V 0.396 - -
D2
Duty Cycle 2:
THREC(MIN) = 0.422 * VSUP
THDOM(MIN) = 0.284 * VSUP
D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V ≤ VSUP ≤ 18 V - - 0.581
LIN physical layer: driver characteristics for slow slew rate - 10.4 kBit/sec according to lin physical layer specification
Bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω, 10 nF / 500 Ω. Measurement thresholds. See Figure 19, page 31.
D3
Duty Cycle 3:
THREC(MAX) = 0.778 * VSUP
THDOM(MAX) = 0.616 * VSUP
D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V ≤ VSUP ≤ 18 V 0.417 - -
D4
Duty Cycle 4:
THREC(MIN) = 0.389 * VSUP
THDOM(MIN) = 0.251 * VSUP
D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V ≤ VSUP ≤ 18 V - - 0.590
LIN physical layer: driver characteristics for fast slew rate
SRFAST LIN Fast Slew Rate (Programming Mode) -20 - V / μs
LIN physical layer: characteristics and wake-up timings. VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 kΩ, 6.8 nF / 660 Ω,
10 nF / 500 Ω. See Figure 18, page 30.
t
REC_PD
t
REC_SYM
Propagation Delay and Symmetry (See Figure 18, page 30 and
Figure 19, page 31)
Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR,
tREC_PDF)
Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR
-
- 2.0
4.2
-
6.0
2.0
μs
t PROPWL
Bus Wake-up Deglitcher (LP VDD OFF and LP VDD ON modes) (See
Figure 20, page 30 for LP VDD OFF mode and Figure 21, page 31 for
LP mode)
42 70 95 μs
t
WAKE_LPVDDOFF
t
WAKE_LPVDDON
Bus Wake-up Event Reported
From LP VDD OFF mode
From LP VDD ON mode
-
1.0
-
-
1500
12
μs
t TXDDOM TXD Permanent Dominant State Delay (Guaranteed by design) 0.65 1.0 1.35 s
Table 7. Dynamic electrical characteristics (continued)
Characteristics noted under conditions 5.5 V ≤ VSUP ≤ 28 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Symbol Characteristic Min. Typ. Max. Unit Notes
NXP Semiconductors 29
33903/4/5
ELECTRICAL CHARACTERISTICS
5.4 Timing diagrams
Figure 14. SPI timing
Figure 15. CAN signal propagation loop delay TXD to RXD
Figure 16. CAN signal propagation delays TXD to CAN and CAN to RXD
Di 0
Do 0
Undefined Don’t Care Di n Don’t Care
tLEAD
tSIH
tSISU
tLAG
tPCLK
tWCLKH
tWCLKL
tVALID
Do n
tSODIS
CS
SCLK
MOSI
MISO
tSOEN
tCSLOW
TXD
RXD
0.3 x V
DD
t
LRD
0.7 x V
DD
t
LDR
0.3 x V
DD
0.7 x V
DD
TXD
VDIFF
0.9 V
t
TRD
0.5 V
t
TDR
RXD
t
RRD
t
RDR
0.3 x VDD
0.7 x V
DD
0.3 x V
DD
0.7 x V
DD
30 NXP Semiconductors
33903/4/5
ELECTRICAL CHARACTERISTICS
.
Figure 17. Test circuit for CAN timing characteristics
Figure 18. LIN timing measurements for normal slew rate
VSUP
12 V
CANL
22 μF
10 μF
SPLIT
GND
TXD
RXD
Signal generator
All pins are not shown
RBUS
15 pF
CBus
100 pF
60 Ω
100 nF
5 V_CAN
CANH
TXD
LIN
RXD
tBIT tBIT
tBUS_DOM(MAX) tBUS_REC(MIN)
tREC_PDF(1)
74.4% V
SUP
42.2% VSUP
58.1% VSUP
28.4% VSUP
tBUS_REC(MAX)
VLIN_REC
tBUS_DOM(MIN)
RXD
Output of receiving Node 1
Output of receiving Node 2
THREC(MAX)
THDOM(MAX)
THREC(MIN)
THDOM(MIN)
Thresholds of
receiving node 1
Thresholds of
receiving node 2
tREC_PDR(1)
tREC_PDF(2)
tREC_PDR(2)
NXP Semiconductors 31
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ELECTRICAL CHARACTERISTICS
Figure 19. LIN timing measurements for slow slew rate
Figure 20. LIN wake-up LP VDD off mode timing
Figure 21. LIN Wake-up LP VDD ON Mode Timing
TXD
LIN
RXD
tBIT tBIT
tBUS_DOM(MAX) tBUS_REC(MIN)
tREC_PDF(1)
77.8% V
SUP
38.9% VSUP
61.6% VSUP
25.1% VSUP
tBUS_REC(MAX)
VLIN_REC
tBUS_DOM(MIN)
RXD
Output of receiving Node 1
Output of receiving Node 2
THREC(MAX)
THDOM(MAX)
THREC(MIN)
THDOM(MIN)
Thresholds of
receiving node 1
Thresholds of
receiving node 2
tREC_PDR(1)
tREC_PDF(2)
tREC_PDR(2)
VDD
LIN
V
TT
Dominant level
0.4 V
V
3V
SUP
PROPWL WAKE
BUSWU
REC
IRQ
LIN
V
LIN_REC
TT
Dominant level
0.4 V V
IRQ stays low until SPI reading command
PROPWL
WAKE
BUSWU
SUP
32 NXP Semiconductors
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FUNCTIONAL DESCRIPTION
6 Functional description
6.1 Introduction
The MC33903_4_5 is the second generation of System Basis Chip, combining:
- Advanced power management unit for the MCU, the integrated CAN interface and for the additional ICs such as sensors, CAN
transceiver.
- Built in enhanced high speed CAN interface (ISO11898-2 and -5), with local and bus failure diagnostic, protection, and fail-safe operation
mode.
- Built in LIN interface, compliant to LIN 2.1 and J2602-2 specification, with local and bus failure diagnostic and protection.
- Innovative hardware configurable fail-safe state machine solution.
- Multiple LP modes, with low current consumption.
- Family concept with pin compatibility; with and without LIN interface devices.
6.2 Functional pin description
6.2.1 Power supply (VSUP/1 and VSUP2)
Note: VSUP1 and VSUP2 supplies are externally available on all devices except the 33903D, 33903S, and 33903P, where these are
connected internally.
VSUP1 is the input pin for the internal supply and the VDD regulator. VSUP2 is the input pin for the 5 V-CAN regulator, LIN’s interfaces
and I/O functions. The VSUP block includes over and undervoltage detections which can generate interrupt. The device includes a loss
of battery detector connected to VSUP/1.
Loss of battery is reported through a bit (called BATFAIL). This generates a POR (Power On Reset).
6.2.2 VDD voltage regulator (VDD)
The regulator has two main modes of operation (Normal mode and LP mode). It can operate with or without an external PNP transistor.
In Normal mode, without external PNP, the max DC capability is 150 mA. Current limitation, temperature pre-warning flag and
overtemperature shutdown features are included. When VDD is turned ON, rise time from 0 to 5.0 V is controlled. Output voltage is 5.0 V.
A 3.3 V option is available via dedicated part number.
If current higher than 150 mA is required, an external PNP transistor must be connected to VE (PNP emitter) and VB (PNP base) pins, in
order to increase total current capability and share the power dissipation between internal VDD transistor and the external transistor. See
External transistor Q1 (VE and VB). The PNP can be used even if current is less than 150 mA, depending upon ambient temperature,
maximum supply and thermal resistance. Typically, above 100-200 mA, an external ballast transistor is recommended.
6.2.3 VDD regulator in LP mode
When the device is set in LP VDD ON mode, the VDD regulator is able to supply the MCU with a DC current below typically 1.5 mA (LP-
ITH). Transient current can also be supplied up to a tenth of a mA. Current in excess of 1.5 mA is detected, and this event is managed by
the device logic (Wake-up detection, timer start for overcurrent duration monitoring or watchdog refresh).
6.2.4 External transistor Q1 (VE and VB)
The device has a dedicated circuit to allow usage of an external “P” type transistor, with the objective to share the power dissipation
between the internal transistor of the VDD regulator and the external transistor. The recommended bipolar PNP transistor is MJD42C or
BCP52-16.
When the external PNP is connected, the current is shared between the internal path transistor and the external PNP, with the following
typical ratio: 1/3 in the internal transistor and 2/3 in the external PNP. The PNP activation and control is done by SPI.
The device is able to operate without an external transistor. In this case, the VE and VB pins must remain open.
NXP Semiconductors 33
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FUNCTIONAL DESCRIPTION
6.2.5 5 V-CAN voltage regulator for CAN and analog MUX
This regulator is supplied from the VSUP/2 pin. A capacitor is required at 5 V-CAN pin. Analog MUX and part of the LIN interfaces are
supplied from 5 V-CAN. Consequently, the 5 V-CAN must be ON in order to have Analog MUX operating and to have the LIN interface
operating in TXD/RXD mode.
The 5 V-CAN regulator is OFF by default and must be turned ON by SPI. In Debug mode, the 5 V-CAN is ON by default.
6.2.6 V auxiliary output, 5.0 and 3.3 V selectable
(VB-Aux, VC-Aux, and VCaux) - Q2
The VAUX block is used to provide an auxiliary voltage output, 5.0 or 3.3 V, selectable by the SPI. It uses an external PNP pass transistor
for flexibility and power dissipation constraints. The external recommended bipolar transistors are MJD42C or BCP52-16.
An overcurrent and undervoltage detectors are provided.
VAUX is controlled via the SPI, and can be turned ON or OFF. VAUX low threshold detection and overcurrent information will disable VAUX,
and are reported in the SPI and can generate INT. VAUX is OFF by default and must be turned ON by the SPI.
6.2.7 Undervoltage reset and reset function (RST)
The RST pin is an open drain structure with an internal pull-up resistor. The LS driver has limited current capability when asserted low, in
order to tolerate a short to 5.0 V. The RST pin voltage is monitored in order to detect failure (e.g. RST pin shorted to 5.0 V or GND).
The RST pin reports an undervoltage condition to the MCU at the VDD pin, as a RST failure in the watchdog refresh operation. VDD
undervoltage reset also operates in LP VDD ON mode.
Two VDD undervoltage thresholds are included. The upper (typically 4.65 V, RST-TH1-5) can lead to a Reset or an Interrupt. This is selected
by the SPI. When “RST-TH2-5“is selected, in Normal mode, an INT is asserted when VDD falls below “RST-TH1-5“, then, when VDD falls
below “RST-TH2-5” a Reset will occur. This will allow the MCU to operate in a degraded mode (i.e., with 4.0 V VDD).
6.2.8 I/O pins (I/O-0: I/O-3)
I/Os are configurable input/output pins. They can be used for small loads or to drive external transistors. When used as output drivers, the
I/Os are either a HS or LS type. They can also be set to high-impedance. I/Os are controlled by the SPI and at power on, the I/Os are set
as inputs. They include overload protection by temperature or excess of a voltage drop.
When I/O-0/-1/-2/-3 voltage is greater than VSUP/2 voltage, the leakage current (II/O_LEAK) parameter is not applicable
• I/O-0 and I/O-1 will have current flowing into the device through three diodes limited by an 80 kOhm resistor (in series).
• I/O-2 and I/O-3 will have unlimited current flowing into the device through one diode.
In LP mode, the state of the I/O can be turned ON or OFF, with extremely low power consumption (except when there is a load). Protection
is disabled in LP mode. When cyclic sense is used, I/O-0 is the HS/LS switch, I/O-1, -2 and -3 are the wake inputs. I/O-2 and I/O-3 pins
share the LIN Master pin function.
6.2.9 VSENSE input (VSENSE)
This pin can be connected to the battery line (before the reverse battery protection diode), via a serial resistor and a capacitor to GND. It
incorporates a threshold detector to sense the battery voltage and provide a battery early warning. It also includes a resistor divider to
measure the VSENSE voltage via the MUX-OUT pin.
6.2.10 MUX-output (MUXOUT)
The MUX-OUT pin (Figure 22) delivers an analog voltage to the MCU A/D input. The voltage to be delivered to MUX-OUT is selected via
the SPI, from one of the following functions: VSUP/1, VSENSE, I/O-0, I/O-1, Internal 2.5 V reference, die temperature sensor, VDD current
copy.
Voltage divider or amplifier is inserted in the chain, as shown in Figure 22.
For the VDD current copy, a resistor must be added to the MUX-OUT pin, to convert current into voltage. Device includes an internal 2.0 k
resistor selectable by the SPI.
Voltage range at MUX-OUT is from GND to VDD. It is automatically limited to VDD (max 3.3 V for 3.3 V part numbers).
The MUX-OUT buffer is supplied from 5 V-CAN regulator, so the 5 V-CAN regulator must be ON in order to have:
34 NXP Semiconductors
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FUNCTIONAL DESCRIPTION
1) MUX-OUT functionality and
2) SPI selection of the analog function.
If the 5 V-CAN is OFF, the MUX-OUT voltage is near GND and the SPI command that selects one of the analog inputs is ignored.
Delay must be respected between SPI commands for 5 V-CAN turned ON and SPI to select MUX-OUT function. The delay depends
mainly upon the 5 V-CAN capacitor and load on 5 V-CAN.
The delay can be estimated using the following formula: delay = C(5 V-CAN) x U (5.0 V) / I_lim 5 V-CAN.
C = cap at 5 V-CAN regulator, U = 5.0 V,
I_LIM 5 V-CAN = min current limit of 5 V-CAN regulator (parameter 5 V-C ILIM).
Note:
As there is no link between 5VCAN and VDD, the 5VCAN can starts after both the VDD and RSTB are released. To ensure the MCU can
use MUXOUT output information, it must verify the presence of the 5VCAN. This can be done for instance by checking the 5VCAN
undervoltage flag (bit4 of the 0xDF00 SPI command).
Figure 22. Analog multiplexer block diagram
6.2.11 DGB (DGB) and debug mode
6.2.11.1 Primary function
It is an input used to set the device in Debug mode. This is achieved by applying a voltage between 8.0 and 10 V at the DEBUG pin and
then, powering up the device (See State diagram). When the device leaves the INIT Reset mode and enters into INIT mode, it detects the
voltage at the DEBUG pin to be between a range of 8.0 to 10 V, and activates the Debug mode.
When Debug mode is detected, no Watchdog SPI refresh commands are necessary. This allows an easy debug of the hardware and
software routines (i.e. SPI commands).
When the device is in Debug mode it is reported by the SPI flag. While in Debug mode, and the voltage at DBG pin falls below the 8.0 to
10 V range, the Debug mode is left, and the device starts the watchdog operation, and expects the proper watchdog refresh. The Debug
mode can be left by SPI. This is recommended to avoid staying in Debug mode when an unwanted Debug mode selection (FMEA pin) is
present. The SPI command has a higher priority than providing 8.0 to 10 V at the DEBUG pin.
D1
V
BAT
VSUP/1
S_in
I/O-1
I/O-0
M
ultiplexer
V
DD-I_COPY
R
M(*)
(*)Optional
A/D in
MCU
S_iddc
MUX-OUT
S_g3.3
Tem p
VSENSE
S_g5
R
SENSE
1.0 k
R
MI
S_ir
S_in
S_in
S_in
V
REF
: 2.5 V
5V-CAN
S_I/O_att
S_I/O_att
All swicthes and resistor are configured and controlled via the SPI
RM: internal resistor connected when VREG current monitor is used
S_g3.3 and S_g5 for 5.0 V or 3.3 V VDD versions
S_iddc to select VDD regulator current copy
S_in1 for LP mode resistor bridge disconnection
S_ir to switch on/off of the internal RMI resistor
S_I/O_att for I/O-0 and I/O-1 attenuation selection
buffer
5V-CAN
NXP Semiconductors 35
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FUNCTIONAL DESCRIPTION
6.2.11.2 Secondary function
The resistor connected between the DBG pin and the GND selects the Fail-Safe mode operation. DBG pin can also be connected directly
to GND (this prevents the usage of Debug mode).
Flexibility is provided to select SAFE output operation via a resistor at the DBG pin or via a SPI command. The SPI command has higher
priority than the hardware selection via Debug resistor. When the Debug mode is selected, the SAFE modes cannot be configured via the
resistor connected at DBG pin.
6.2.12 SAFE
6.2.12.1 Safe output pin
This pin is an output and is asserted low when a fault event occurs. The objective is to drive electrical safe circuitry and set the ECU in a
known state, independent of the MCU and SBC, once a failure has been detected. The SAFE output structure is an open drain, without
a pull-up.
6.2.13 Interrupt (INT)
The INT output pin is asserted low or generates a low pulse when an interrupt condition occurs. The INT condition is enabled in the INT
register. The selection of low level or pulse and pulse duration are selected by SPI.
No current will flow inside the INT structure when VDD is low, and the device is in LP VDD OFF mode. This allows the connection of an
external pull-up resistor and connection of an INT pin from other ICs without extra consumption in unpowered mode.
INT has an internal pull-up structure to VDD. In LP VDD ON mode, a diode is inserted in series with the pull-up, so the high level is slightly
lower than in other modes.
6.2.14 CANH, CANL, SPLIT, RXD, TXD
These are the pins of the high speed CAN physical interface, between the CAN bus and the micro controller. A detail description is
provided in the document.
6.2.15 LIN, LIN-T, TXDL and RXDL
These are the pins of the LIN physical interface. Device contains zero, one or two LIN interfaces.
The MC33903, MC33903P, and MC33904 do not have a LIN interface. However, the MC33903S/5S (S = Single) and MC33903D/5D
(D=Dual) contain 1 and 2 LIN interfaces, respectively.
LIN, LIN1 and LIN2 pins are the connection to the LIN sub buses. LIN interfaces are connected to the MCU via the TXD, TXD-L1 and
TXD-L2 and RXD, RXD-L1 and RXD-L2 pins.
The device also includes one or two HS switches to VSUP/2 pin which can be used as a LIN master termination switch. Pins LINT, LINT-
1 and LINT-2 pins are the same as I/O-2 and I/O-3.
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FUNCTIONAL DEVICE OPERATION
7 Functional device operation
7.1 Mode and state description
The device has several operation modes. The transitions and conditions to enter or leave each mode are illustrated in the state diagram.
7.1.1 INIT reset
This mode is automatically entered after the device is “powered on”. In this mode, the RST pin is asserted low, for a duration of typically
1.0 ms. Control bits and flags are ‘set’ to their default reset condition. The BATFAIL is set to indicate the device is coming from an
unpowered condition, and all previous device configurations are lost and “reset” the default value. The duration of the INIT reset is typically
1.0 ms.
INIT reset mode is also entered from INIT mode if the expected SPI command does not occur in due time (Ref. INIT mode), and if the
device is not in the debug mode.
7.1.2 INIT
This mode is automatically entered from the INIT Reset mode. In this mode, the device must be configured via SPI within a time of 256 ms
max. Four registers called INIT Wdog, INIT REG, INIT LIN I/O and INIT MISC must be, and can only be configured during INIT mode.
Other registers can be written in this and other modes.
Once the INIT register configuration is done, a SPI Watchdog Refresh command must be sent in order to set the device into Normal mode.
If the SPI watchdog refresh does not occur within the 256 ms period, the device will return into INIT Reset mode for typically 1.0 ms, and
then re enter into INIT mode.
Register read operation is allowed in INIT mode to collect device status or to read back the INIT register configuration.
When INIT mode is left by a SPI watchdog refresh command, it is only possible to re-enter the INIT mode using a secured SPI command.
In INIT mode, the CAN, LIN1, LIN2, VAUX, I/O_x and Analog MUX functions are not operating. The 5 V-CAN is also not operating, except
if the Debug mode is detected.
7.1.3 Reset
In this mode, the RST pin is asserted low. Reset mode is entered from Normal mode, Normal Request mode, LP VDD on mode and from
the Flash mode when the watchdog is not triggered, or if a VDD low condition is detected.
The duration of reset is typically 1.0 ms by default. You can define a longer Reset pulse activation only when the Reset mode is entered
following a VDD low condition. Reset pulse is always 1.0 ms, when reset mode is entered due to wrong watchdog refresh command.
Reset mode can be entered via the secured SPI command.
7.1.4 Normal request
This mode is automatically entered after RESET mode, or after a Wake-up from LP VDD ON mode.
A watchdog refresh SPI command is necessary to transition to NORMAL mode. The duration of the Normal request mode is 256 ms when
Normal Request mode is entered after RESET mode. Different durations can be selected by SPI when normal request is entered from LP
VDD ON mode.
If the watchdog refresh SPI command does not occur within the 256 ms (or the shorter user defined time out), then the device will enter
into RESET mode for a duration of typically 1.0 ms.
Note: in init reset, init, reset and normal request modes as well as in LP modes, the VDD external PNP is disabled.
7.1.5 Normal
In this mode, all device functions are available. This mode is entered by a SPI watchdog refresh command from Normal Request mode,
or from INIT mode.
During Normal mode, the device watchdog function is operating, and a periodic watchdog refresh must occur. When an incorrect or
missing watchdog refresh command is initiated, the device will enter into Reset mode.
While in Normal mode, the device can be set to LP modes (LP VDD ON or LP VDD OFF) using the SPI command. Dedicated, secured SPI
commands must be used to enter from Normal mode to Reset mode, INIT mode or Flash mode.
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FUNCTIONAL DEVICE OPERATION
7.1.6 Flash
In this mode, the software watchdog period is extended up to typically 32 seconds. This allow programming of the MCU flash memory
while minimizing the software over head to refresh the watchdog. The flash mode is entered by Secured SPI command and is left by SPI
command. Device will enter into Reset mode. When an incorrect or missing watchdog refresh command device will enter into Reset mode.
An interrupt can be generated at 50% of the watchdog period.
CAN interface operates in Flash mode to allow flash via CAN bus, inside the vehicle.
7.1.7 Debug
Debug is a special operation mode of the device which allows for easy software and hardware debugging. The debug operation is detected
after power up if the DBG pin is set to 8.0 to 10 V range.
When debug is detected, all the software watchdog operations are disabled: 256 ms of INIT mode, watchdog refresh of Normal mode and
Flash mode, Normal Request time out (256 ms or user defined value) are not operating and will not lead to transition into INIT reset or
Reset mode.
When the device is in Debug mode, the SPI command can be sent without any time constraints with respect to the watchdog operation
and the MCU program can be “halted” or “paused” to verify proper operation.
Debug can be left by removing 8 to 10 V from the DEBUG pin, or by the SPI command (Ref. to MODE register).
The 5 V-CAN regulator is ON by default in Debug mode.
7.2 LP modes
The device has two main LP modes: LP mode with VDD OFF, and LP mode with VDD ON.
Prior to entering into LP mode, I/O and CAN Wake-up flags must be cleared (Ref. to mode register). If the Wake-up flags are not cleared,
the device will not enter into LP mode. In addition, the CAN failure flags (i.e. CAN_F and CAN_UF) must be cleared, in order to meet the
LP current consumption specification.
7.2.1 LP - VDD off
In this mode, VDD is turned OFF and the MCU connected to VDD is unsupplied. This mode is entered using SPI. It can also be entered
by an automatic transition due to fail-safe management. 5 V-CAN and VAUX regulators are also turned OFF.
When the device is in LP VDD OFF mode, it monitors external events to Wake-up and leave the LP mode. The Wake-up events can occur
from:
•CAN
• LIN interface, depending upon device part number
• Expiration of an internal timer
• I/O-0, and I/O-1 inputs, and depending upon device part number and configuration, I/O-2 and/or -3 input
• Cyclic sense of I/O-1 input, associated by I/O-0 activation, and depending upon device part number and configuration, cyclic sense
of I/O-2 and -3 input, associated by I/O-0 activation
When a Wake-up event is detected, the device enters into Reset mode and then into Normal Request mode. The Wake-up sources are
reported to the device SPI registers. In summary, a Wake-up event from LP VDD OFF leads to the VDD regulator turned ON, and the MCU
operation restart.
7.2.2 LP - VDD ON
In this mode, the voltage at the VDD pin remains at 5.0 V (or 3.3 V, depending upon device part number). The objective is to maintain the
MCU powered, with reduced consumption. In such mode, the DC output current is expected to be limited to 100 μA or a few mA, as the
ECU is in reduced power operation mode.
During this mode, the 5 V-CAN and VAUX regulators are OFF. The optional external PNP at VDD will also be automatically disabled when
entering this mode.
The same Wake-up events as in LP VDD OFF mode (CAN, LIN, I/O, timer, cyclic sense) are available in LP VDD on mode. In addition, two
additional Wake-up conditions are available.
• Dedicated SPI command. When device is in LP VDD ON mode, the Wake-up by SPI command uses a write to “Normal Request
mode”, 0x5C10.
• Output current from VDD exceeding LP-ITH threshold.
38 NXP Semiconductors
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FUNCTIONAL DEVICE OPERATION
In LP VDD ON mode, the device is able to source several tenths of mA DC. The current source capability can be time limited, by a
selectable internal timer. Timer duration is up to 32 ms, and is triggered when the output current exceed the output current threshold
typically 1.5 mA.
This allows for instance, a periodic activation of the MCU, while the device remains in LP VDD on mode. If the duration exceed the selected
time (ex 32 ms), the device will detect a Wake-up.
Wake-up events are reported to the MCU via a low level pulse at INT pulse. The MCU will detect the INT pulse and resume operation.
7.2.2.1 Watchdog function in LP VDD on mode
It is possible to enable the watchdog function in LP VDD ON mode. In this case, the principle is timeout.
Refresh of the watchdog is done either by:
• a dedicated SPI command (different from any other SPI command or simple CS activation which would Wake-up - Ref. to the
previous paragraph)
• or by a temporary (less than 32 ms max) VDD over current Wake-up (IDD > 1.5 mA typically).
As long as the watchdog refresh occurs, the device remains in LP VDD on mode.
7.2.2.2 Mode transitions
Mode transitions are either done automatically (i.e. after a timeout expired or voltage conditions), or via a SPI command, or by an external
event such as a Wake-up. Some mode changes are performed using the Secured SPI commands.
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FUNCTIONAL DEVICE OPERATION
7.3 State diagram
Figure 23. State diagram
INIT Reset
start T_IR
INIT
start T_INIT
T_IR expired
T_INIT expired
or VDD<VDD_UVTH
NORMAL (4)
start T_WDN
SPI write (0x5A00)
SPI secured (3)
watchdog refresh
FLASH
start T_WDF
SPI secured (3)
watchdog refresh
RESET
(config)
start T_R
(1.0 ms or config) VDD<VDD_UVTH or T_WD expired
POWER DOWN
SPI secured
VSUP fall
VSUP/1 rise > VSUP-TH1
NORMAL
start T_NR
REQUEST
(256 ms or config)
(1) watchdog refresh in closed window or enhanced watchdog refresh failure
T_R expired
SPI write (0x5A00)
T_NR expired
LP
start T_WDL (2)
VDD ON
LP
VDD OFF
Wake-up
if enable
Wake-up (5)
(2) If enable by SPI, prior to enter LP VDD ON mode
LP VDDON
start T_OC time
IDD > 1.5 mA
I-DD>IOC
I-DD<IOC
T_OC expired
SPI
& VDD>VDD_UVTH
watchdog refresh
SPI
or T_WDF expired
or VDD<VDD_UVTH
VSUP fall
Debug
FAIL-SAFE DETECTED
detection
(watchdog refresh)
(1.5 mA)
(1.5 mA)
by SPI
by SPI
mode
(T_IR =1.0ms)
(T_INIT =256ms)
(T_WDN = config)
T_WDL expired or VDD<VDD_UVTHLP
or Wake-up
or watchdog failure (1) or SPI secured
(watchdog refresh)
VDD<VDD_UVTHLP
by SPI
& VDD > VDD_UVTH
Ext reset
(3) Ref. to “SPI secure” description
(4) VDD external PNP is disable in all mode except Normal and Flash modes.
(5) Wake-up from LP VDD ON mode by SPI command is done by a SPI mode change: 0X5C10
or VDD TSD
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FUNCTIONAL DEVICE OPERATION
7.4 Mode change
7.4.1 ‘Secured SPI’ description
A request is done by a SPI command, the device provide on MISO an unpredictable ‘random code’. Software must perform a logical
change on the code and return it to the device with the new SPI command to perform the desired action.
The ‘random code’ is different at every exercise of the secured procedure and can be read back at any time.
The secured SPI uses the Special MODE register for the following transitions:
- from Normal mode to INT mode
- from Normal mode to Flash mode
- from Normal mode to Reset mode (reset request).
“Random code” is also used when the ‘advance watchdog’ is selected.
7.4.2 Changing of device critical parameters
Some critical parameters are configured one time at device power on only, while the batfail flag is set in the INIT mode. If a change is
required while device is no longer in INIT mode, device must be set back in INIT mode using the “SPI secure” procedure.
7.5 Watchdog operation
7.5.1 In normal request mode
In Normal Request mode, the device expects to receive a watchdog configuration before the end of the normal request time out period.
This period is reset to a long (256 ms) after power on and when BATFAIL is set.
The device can be configured to a different (shorter) time out period which can be used after Wake-up from LP VDD on mode.
After a software watchdog reset, the value is restored to 256 ms, in order to allow for a complete software initialization, similar to a device
power up. In Normal Request mode the watchdog operation is “timeout” only and can be triggered/observed any time within the period.
7.5.2 Watchdog type selection
Three types of watchdog operation can be used:
- Window watchdog (default)
- Timeout operation
- Advanced
The selection of watchdog is performed in INIT mode. This is done after device power up and when the BATFAIL flag is set. The Watchdog
configuration is done via the SPI, then the Watchdog mode selection content is locked and can be changed only via a secured SPI
procedure.
7.5.2.1 Window watchdog operation
The window watchdog is available in Normal mode only. The watchdog period selection can be kept (SPI is selectable in INIT mode),
while the device enters into LP VDD ON mode. The watchdog period is reset to the default long period after BATFAIL.
The period and the refresh of watchdog are done by the SPI. A refresh must be done in the open window of the period, which starts at
50% of the selected period and ends at the end of the period.
If the watchdog is triggered before 50%, or not triggered before end of period, a reset has occurred. The device enters into Reset mode.
7.5.2.2 Watchdog in debug mode
When the device is in Debug mode (entered via the DBG pin), the watchdog continues to operate but does not affect the device operation
by asserting a reset. For the user, operation appears without the watchdog.
When Debug mode is left by software (SPI mode reg), the watchdog period starts at the end of the SPI command.
When Debug mode is left by hardware (DBG pin below 8-10 V), the device enters into Reset mode.
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FUNCTIONAL DEVICE OPERATION
7.5.2.3 Watchdog in flash mode
During Flash mode, watchdog can be set to a long timeout period. Watchdog is timeout only and an INT pulse can be generated at 50%
of the time window.
7.5.2.4 Advance watchdog operation
When the Advance watchdog is selected (at INIT mode), the refresh of the watchdog must be done using a random number and with 1,
2, or 4 SPI commands. The number for the SPI command is selected in INIT mode.
The software must read a random byte from the device, and then must return the random byte inverted to clear the watchdog. The random
byte write can be performed in 1, 2, or 4 different SPI commands.
If one command is selected, all eight bits are written at once.
If two commands are selected, the first write command must include four of the eight bits of the inverted random byte. The second
command must include the next four bits. This completes the watchdog refresh.
If four commands are selected, the first write command must include two of the eight bits of the inverted random byte. The second
command must include the next two bits, the 3rd command must include the next two, and the last command, must include the last two.
This completes the watchdog refresh. When multiple writes are used, the most significant bits are sent first. The latest SPI command
needs to be done inside the open window time frame, if window watchdog is selected.
7.5.3 Detail SPI operation and SPI commands for all watchdog types.
All SPI commands and examples do not use parity functions.
In INIT mode, the watchdog type (window, timeout, advance and number of SPI commands) is selected using the register Init watchdog,
bits 1, 2 and 3. The watchdog period is selected using the TIM_A register. The watchdog period selection can also be done in Normal
mode or in Normal Request mode.
Transition from INIT mode to Normal mode or from Normal Request mode to Normal mode is done using a single watchdog refresh
command (SPI 0x 5A00).
While in Normal mode, the Watchdog Refresh Command depends upon the watchdog type selected in INIT mode. They are detailed in
the paragraph below:
7.5.3.1 Simple watchdog
The Refresh command is 0x5A00. It can be send any time within the watchdog period, if the timeout watchdog operation is selected (INIT-
watchdog register, bit 1 WD N/Win = 0). It must be send in the open window (second half of the period) if the Window Watchdog operation
was selected (INIT-watchdog register, bit 1 WD N/Win = 1).
7.5.3.2 Advance watchdog
The first time the device enters into Normal mode (entry on Normal mode using the 0x5A00 command), Random (RNDM) code must be
read using the SPI command, 0x1B00. The device returns on MISO second byte the RNDM code. The full 16 bits MISO is called 0x XXRD.
RD is the complement of the RD byte.
7.5.3.3 Advance watchdog, refresh by 1 SPI command
The refresh command is 0x5ARD. During each refresh command, the device will return on MISO, a new Random Code. This new Random
Code must be inverted and send along with the next refresh command. It must be done in an open window, if the Window operation was
selected.
7.5.3.4 Advance watchdog, refresh by two SPI commands
The refresh command is split in two SPI commands.
The first partial refresh command is 0x5Aw1, and the second is 0x5Aw2. Byte w1 contains the first four inverted bits of the RD byte plus
the last four bits equal to zero. Byte w2 contains four bits equal to zero plus the last four inverted bits of the RD byte.
During this second refresh command the device returns on MISO a new Random Code. This new random code must be inverted and send
along with the next two refresh commands and so on. The second command must be done in an open window if the Window operation
was selected.
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FUNCTIONAL DEVICE OPERATION
7.5.3.5 Advance watchdog, refresh by four SPI commands
The refresh command is split into four SPI commands.
The first partial refresh command is 0x5Aw1, the second is 0x5Aw2, the third is 0x5Aw3, and the last is 0x5Aw4.
Byte w1 contains the first two inverted bits of the RD byte, plus the last six bits equal to zero.
Byte w2 contains two bits equal to zero, plus the next two inverted bits of the RD byte, plus four bits equal to zero.
Byte w3 contains four bits equal to zero, plus the next two inverted bits of the RD byte, plus two bits equal to zero.
Byte w4 contains six bits equal to zero, plus the next two inverted bits of the RD byte.
During this fourth refresh command, the device will return, on MISO, a new Random Code. This new Random Code must be inverted and
send along with the next four refresh commands.
The fourth command must be done in an open window if the Window operation was selected.
7.5.4 Proper response to INT
During a device detect upon an INT, the software handles the INT in a timely manner: Access of the INT register is done within two
watchdog periods. This feature must be enabled by SPI using the INIT watchdog register bit 7.
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FUNCTIONAL DEVICE OPERATION
7.6 Functional block operation versus mode
The 5 V-CAN default is ON when the device is powered-up and set in Debug mode. It is fully controllable via the SPI command.
Table 8. Device block operation for each state
State VDD 5 V-CAN I/O-X VAUX CAN LIN1/2
Power down OFF OFF OFF OFF High-impedance High-impedance
Init Reset ON OFF HS/LS off
Wake-up disable OFF
OFF:
CAN termination 25 k to GND
Transmitter / receiver /Wake-up
OFF
OFF:
internal 30 k pull-up
active. Transmitter:
receiver / Wake-up OFF.
LIN term OFF
INIT ON OFF (38) WU disable
(39)(40)(41)
OFF OFF OFF
Reset ON Keep SPI
config WU disable
(39)(40)(41)
OFF OFF OFF
Normal Request ON Keep SPI
config WU disable
(39)(40)(41)
OFF OFF OFF
Normal ON SPI config SPI config
WU SPI config SPI config SPI config SPI config
LP VDD OFF OFF OFF user defined
WU SPI config OFF OFF + Wake-up en/dis OFF + Wake-up en/dis
LP VDD ON ON(37) OFF user defined
WU SPI config OFF OFF + Wake-up en/dis OFF + Wake-up en/dis
SAFE output low:
Safe case A
safe case
A:ON
safe case B:
OFF
A: Keep SPI
config, B: OFF
HS/LS off
Wake-up by
change state
OFF OFF + Wake-up enable OFF + Wake-up enable
FLASH ON SPI config SPI config OFF SPI config OFF
Notes
37. With limited current capability
38. 5 V-CAN is ON in Debug mode.
39. I/O-0 and I/O-1, configured as an output high-side switch and ON in Normal mode will remain ON in RESET, INIT or Normal Request.
40. I/O-0, configured as an output low-side switch and ON in Normal mode will turn OFF when entering Reset mode, resume operation in Normal
mode.
41. I/O-1, configured as an output low-side switch and ON in Normal mode will remain ON in RESET, INIT or Normal Request.
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FUNCTIONAL DEVICE OPERATION
7.7 Illustration of device mode transitions
Figure 24. Power up normal and LP modes
V
SUP
V
DD
RST
INT
SPI
MODE
V
DD-UV
(4.5 V typically)
RESET INIT
Series of SPI
Single SPI
NORMAL
BATFAIL
5V-CAN
>4.0 V
VAUX
APower up to Normal Mode
B
s_11
s_1
s_11: write INT registers
s_1: go to Normal mode
s_12
s_2
V
DD-UV
NORMAL LP V
DD
OFF
C
s_2: go to
LP VDD OFF mode
s_12: LP Mode configuration
B
Normal to LP
V
SUP
V
DD
RST
INT
SPI
5V-CAN
VAUX
legend:
s_13
s_3
NORMAL LP V
DD
On
D
B
Normal to LP
V
SUP
V
DD
RST
INT
SPI
5V-CAN
VAUX
s_13: LP Mode configuration
s_3: go to LP mode
V
DD
OFF Mode V
DD
ON Mode
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FUNCTIONAL DEVICE OPERATION
Figure 25. Wake-up from LP modes
7.8 Cyclic sense operation during LP modes
This function can be used in both LP modes: VDD OFF and VDD ON.
Cyclic sense is the periodic activation of I/O-0 to allow biasing of external contact switches. The contact switch state can be detected via
I/O-1, -2, and -3, and the device can Wake-up from either LP mode. Cyclic sense is optimized and designed primarily for closed contact
switch in order to minimize consumption via the contact pull-up resistor.
CWake-up from LP V
DD
OFF Mode
V
DD
-UV
(4.5 V typically)
RESET
NORMAL
s_14
s_4
REQUEST NORMAL
CAN bus
Based on reg configuration
Based on reg configuration
CAN Wake-up
I/O-x toggle
pattern
Available Wake-up events (exclusive)
Wake-up detected
Start
FWU timer
duration (50-8192 ms)
.
SPI selectable
FWU timer
LP V
DD
_OFF
V
SUP
V
DD
RST
INT
SPI
MODE
5V-CAN
VAUX
D
s_14
s_4
NORMAL
REQUEST NORMAL
LP V
DD
ON
Based on reg configuration
Based on reg configuration
CAN bus
CAN Wake-up
I/O-x toggle
pattern
I
DD
current I
DD-OC
(3.0 mA typically)
I
DD OC
deglitcher or timer (100 us typically, 3 -32 ms)
Wake-up detected
Start
FWU timer
duration (50-8192 ms)
Stop
SPI selectable
FWU timer
SPI
Wake-up from LP V
DD
ON Mode
V
SUP
V
DD
RST
INT
SPI
MODE
5V-CAN
VAUX
LIN Bus
LIN Wake-up filter
LIN Bus
LIN Wake-up filter
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FUNCTIONAL DEVICE OPERATION
7.8.1 Principle
A dedicated timer provides an opportunity to select a cyclic sense period from 3.0 to 512 ms (selection in timer B).
At the end of the period, the I/O-0 will be activated for a duration of T_CSON (SPI selectable in INIT register, to 200 μs, 400 μs, 800 μs, or
1.6 ms). The I/O-0 HS transistor or LS transistor can be activated. The selection is done by the state of I/O-0 prior to entering in LP mode.
During the T-CSON duration, the I/O-x’s are monitored. If one of them is high, the device will detect a Wake-up. (Figure 26).
Cyclic sense period is selected by the SPI configuration prior to entering LP mode. Upon entering LP mode, the I/O-0 should be activated.
The level of I/O-1 is sense during the I/O-0 active time, and is deglitched for a duration of typically 30 μs. This means that I/O-1 should be
in the expected state for a duration longer than the deglitch time. The diagram below (Figure 26) illustrates the cyclic sense operation,
with I/O-0 HS active and I/O-1 Wake-up at high level.
Figure 26. Cyclic sense operation - switch to GND, wake-up by open switch
I/O-0
I/O-1
NORMAL MODE LP MODE
I/O-0 HS active in Normal mode I/O-0 HS active during cyclic sense active time
Cyclic sense period
Cyclic sense active time
RESET or NORMAL REQUEST MODE
Wake-up detected.
state of I/O-1 low => no Wake-up
Cyclic sense active
I/O-1 deglitcher time
I/O-1 high => Wake-up
I/O-0
I/O-1
Zoom
time (ex 200 us)
Wake-up event detected
I/O-0
I/O-1
S1 closed S1 openS1
(typically 30 us)
S1
R
I/O-2
R
S2
R
S3
I/O-3
I/O-0
I/O-1
S1
R
I/O-2
R
S2
R
S3
I/O-3
Upon entering in LP mode, all 3
contact switches are closed.
In LP mode, 1 contact switch is open.
High level is detected on I/O-x, and device wakes up.
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FUNCTIONAL DEVICE OPERATION
7.9 Cyclic INT operation during LP VDD on mode
7.9.1 Principle
This function can be used only in LP VDD ON mode (LP VDD ON). When Cyclic INT is selected and device is in LP VDD ON mode, the
device will generate a periodic INT pulse.
Upon reception of the INT pulse, the MCU must acknowledge the INT by sending SPI commands before the end of the next INT period
in order to keep the process going.
When Cyclic INT is selected and operating, the device remains in LP VDD ON mode, assuming the SPI commands are issued properly.
When no/improper SPI commands are sent, the device will cease Cyclic INT operation and leave LP VDD ON mode by issuing a reset.
The device will then enter into Normal Request mode. VDD current capability and VDD regulator behavior is similar as in LP VDD ON
mode.
7.9.1.1 Operation
Cyclic INT period selection: register timer B
SPI command in hex 0x56xx [example; 0x560E for 512ms cyclic Interrupt period (SPI command without parity bit)].
This command must be send while the device is in Normal mode.
SPI commands to acknowledge INT: (2 commands)
- read the Random code via the watchdog register address using the following command: MOSI 0x1B00 device report on MISO second
byte the RNDM code (MISO bit 0-7).
- write watchdog refresh command using the random code inverted: 0x5A RNDb.
These commands can occur at any time within the period.
Initial entry in LP mode with Cyclic INT: after the device is set in LP VDD ON mode, with cyclic INT enable, no SPI command is necessary
until the first INT pulse occurs. The acknowledge process must start only after the 1st INT pulse.
Leave LP mode with Cyclic INT:
This is done by a SPI Wake-up command, similar to SPI Wake-up from LP VDD ON mode: 0x5C10. The device will enter into Normal
Request mode.
Improper SPI command while Cyclic INT operates:
When no/improper SPI commands are sent, while the device is in LP VDD ON mode with Cyclic INT enable, the device will cease Cyclic
INT operation and leave LP VDD ON mode by issuing a reset. The device will then enter into Normal Request mode.
Figure 27 describes the complete Cyclic Interrupt operation.
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FUNCTIONAL DEVICE OPERATION
Figure 27. Cyclic interrupt operation
7.10 Behavior at power up and power down
7.10.1 Device power up
This section describe the device behavior during ramp up, and ramp down of VSUP/1, and the flexibility offered mainly by the Crank bit and
the two VDD undervoltage reset thresholds.
The figures below illustrate the device behavior during VSUP/1 ramp up. As the Crank bit is by default set to 0, VDD is enabled when
VSUP/1 is above VSUP TH 1 parameters.
NORMAL MODE
INT
SPI
Timer B
LP V
DD
Cyclic INT period Cyclic INT period
LP V
DD
ON MODE
ON mode
Read RNDM code
Write RNDM code inv.
1st period 2nd period
NORMAL
MODE
Cyclic INT period
Cyclic INT period
3rd period
SPI Wake-up: 0x5C10
Write Timer B, select Cyclic INT period (ex: 512 ms, 0x560E)
Write Device mode: LP V
DD
ON with Cyclic INT enable (example: 0x5C90)
Cyclic INT period
Legend for SPI commands
INT
SPI
RST
RESET and
REQUEST
Prepare LP V
DD
ON In LP V
DD
ON with Cyclic INT Leave LP
Improper or no
with Cyclic INT V
DD
ON Mode
LP V
DD
ON MODE
Leave LP V
DD
ON and Cyclic INT due to improper operation
REQUEST
acknowledge SPI command
NORMAL
MODE
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FUNCTIONAL DEVICE OPERATION
Figure 28. VDD start-up versus VSUP/1 tramp
7.10.2 Device power down
The figures below illustrate the device behavior during VSUP/1 ramp down, based on Crank bit configuration, and VDD undervoltage reset
selection.
7.10.2.1 Crank bit reset (INIT watchdog register, Bit 0 =0)
Bit 0 = 0 is the default state for this bit.
During VSUP/1 ramp down, VDD remain ON until device enters in Reset mode due to a VDD undervoltage condition (VDD < 4.6 V or VDD <
3.2 V typically, threshold selected by the SPI). When device is in Reset, if VSUP/1 is below “VSUP_TH1”, VDD is turned OFF.
7.10.2.2 Crank bit set (INIT watchdog register, Bit 0 =1)
The bit 0 is set by SPI write. During VSUP/1 ramp down, VDD remains ON until device detects a POR and set BATFAIL. This occurs for a
VSUP/1 approx 3.0 V.
D1
V
BAT
VSUP/1
V
SUP_TH1
V
SUP_NOMINAL
(ex 12 V)
V
DD NOMINAL
(ex 5.0 V)
VDD
Gnd
V
DD_START UP
V
DD_OFF
90% V
DD_START UP
10% V
DD_START UP
VDD
VSUP/1
I_VDD
V
SUP
slew rate
3390X
V
DD_UV TH
(typically 4.65 V)
RST
1.0 ms
V
SUP_NOMINAL
V
DD
(3.3 V)
VDD
VSUP1
RESET
(ex 12 V)
V
BAT
V
DD_UV TH
(typ 3.0 V)
V
SUP_TH1
(4.1V)
Case 1: VDD 3.3V, “V
DD UV TH
3.0 V”,
with bit Crank =0 (default value)
Case 2: VDD 3.3V, “V
DD UV TH
3.0 V”, with bit Crank =1
V
SUP_NOMINAL
V
DD
(3.3 V)
VDD
VSUP1
RESET
(ex 12 V)
V
BAT
V
DD_UV TH
(typ 3.0 V)
V
SUP_TH1
(4.1V)
minV
SUP
(2.8 V)
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FUNCTIONAL DEVICE OPERATION
Figure 29. VDD behavior during VSUP/1 ramp down
V
SUP_NOMINAL
V
DD
(5.0 V)
VDD
VSUP/1
RST
(ex 12 V)
V
BAT
V
DD_UV TH
(typically 4.65 V)
V
SUP_TH1
(4.1 V)
V
SUP_NOMINAL
V
DD
(5.0 V)
VDD
VSUP/1
RST
(ex 12 V)
V
BAT
V
DD_UV TH
(typically 4.65 V)
V
SUP_TH1
(4.1 V)
INT
V
DD_UV TH2
(typically 3.2 V)
V
SUP_NOMINAL
V
DD
(5.0 V)
VDD
VSUP/1
RST
(ex 12 V)
V
BAT
V
DD_UV TH
(typically 4.65 V)
INT
V
DD_UV TH2
(typically 3.2 V)
BATFAIL (3.0 V)
(1)
(2)
(1) reset then (2) V
DD
turn OFF
V
SUP_NOMINAL
V
DD
(5.0 V)
VDD
VSUP/1
RST
(ex 12 V)
V
BAT
V
DD_UV TH
(typically 4.65 V)
BATFAIL (3.0 V)
Case 4: “VDD UV 4.6V”, with bit Crank = 1
Case 5: “VDD UV TH 3.2V”, with bit Crank = 0 (default value) Case 6: “VDD UV 3.2V”, with bit Crank = 1
Case 3: “VDD UV TH 4.6V”, with bit Crank = 0 (default value)
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FUNCTIONAL DEVICE OPERATION
7.11 Fail-safe operation
7.11.1 Overview
Fail-safe mode is entered when specific fail conditions occur. The ‘Safe state’ condition is defined by the resistor connected at the DGB
pin. Safe mode is entered after additional event or conditions are met: time out for CAN communication and state at I/O-1 pin.
Exiting the safe state is always possible by a Wake-up event: in the safe state, the device can automatically be awakened by CAN and
I/O (if configured as inputs). Upon Wake-up, the device operation is resumed: enter in Reset mode.
7.11.2 Fail-safe functionality
Upon dedicated event or issue detected at a device pin (i.e. RST short to VDD), the Safe mode can be entered. In this mode, the SAFE
pin is active low.
7.11.2.1 Description
Upon activation of the SAFE pin, and if the failure condition that make the SAFE pin activated have not recovered, the device can help
to reduce ECU consumption, assuming that the MCU is not able to set the whole ECU in LP mode. Two main cases are available:
7.11.2.2 Mode A
Upon SAFE activation, the MCU remains powered (VDD stays ON), until the failure condition recovers (i.e. S/W is able to properly
control the device and properly refresh the watchdog).
7.11.2.3 Modes B1, B2 and B3
Upon SAFE activation, the system continues to monitor external event, and disable the MCU supply (turn VDD OFF). The external
events monitored are: CAN traffic, I/O-1 low level or both of them. 3 sub cases exist, B1, B2 and B3.
Note: no CAN traffic indicates that the ECU of the vehicle are no longer active, thus that the car is being parked and stopped. The I/O low
level detection can also indicate that the vehicle is being shutdown, if the I/O-1 pin is connected for instance to a switched battery signal
(ignition key on/off signal).
The selection of the monitored events is done by hardware, via the resistor connected at DBG pin, but can be over written by software,
via a specific SPI command.
By default, after power up the device detect the resistor value at DBG pin (upon transition from INIT to Normal mode), and, if no specific
SPI command related to Debug resistor change is send, operates according to the detected resistor.
The INIT MISC register allow you to verify and change the device behavior, to either confirm or change the hardware selected behavior.
Device will then operate according to the SAFE mode configured by the SPI.
Table 9 illustrates the complete options available:
Table 9. Fail-safe options
Resistor at
DBG pin SPI coding - register INIT MISC bits [2,1,0]
(higher priority that Resistor coding)
Safe mode
code VDD status
<6.0 k bits [2,1,0) = [111]: verification enable: resistor at DBG pin is
typically 0 kohm (RA) - Selection of SAFE mode A Aremains ON
typically 15 k bits [2,1,0) = [110]: verification enable: resistor at DBG pin is
typically 15 kohm (RB1) - Selection of SAFE mode B1 B1 Turn OFF 8.0 s after CAN traffic bus idle
detection.
typically 33 k bits [2,1,0) = [101]: verification enable: resistor at DBG pin is
typically 33 kohm (RB2 - Selection of SAFE mode B2 B2 Turn OFF when I/O-1 low level detected.
typically 68 k bits [2,1,0) = [100]: verification enable: resistor at DBG pin is
typically 68 kohm (RB3) - Selection of SAFE mode B3 B3 Turn OFF 8.0 s after CAN traffic bus idle
detection AND when I/O-1 low level detected.
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FUNCTIONAL DEVICE OPERATION
7.11.2.4 Exit of safe mode
Exit of the safe state with VDD OFF is always possible by a Wake-up event: in this safe state the device can automatically awakened by
CAN and I/O (if I/O Wake-up was enable by the SPI prior to enter into SAFE mode). Upon Wake-up, the device operation is resumed, and
device enters in Reset mode. The SAFE pin remains active, until there is a proper read and clear of the SPI flags reporting the SAFE
conditions.
.
Figure 30. Safe operation flow chart
7.11.2.5 Conditions to set SAFE pin active low
Watchdog refresh issue: SAFE activated at 1st reset pulse or at the second consecutive reset pulse (selected by bit 4, INIT watchdog
register).
VDD low: VDD < RST-TH. SAFE pin is set low at the same time as the RST pin is set low. The RST pin is monitored to verify that reset is not
clamped to a low level preventing the MCU to operate. If this is the case, the Safe mode is entered.
watchdog failure
VDD low:
Rst s/c GND:
- SAFE low
8 consecutive watchdog failure (5)
State A: RDBG <6.0 k AND
- SAFE low
- Reset: 1.0 ms
- VDD ON
- Reset low
INIT, b) ECU external signal
State B1: RDBG =15k AND
State B3:
State B2: - SAFE low
- Reset low
- VDD OFF
a) Evaluation of
Bus idle timeout expired
Normal, FLASH
VDD <VDD_UVTH
Rst <2.5 V, t >100 ms
Device state:
RESET NR
bit 4, INIT watchdog = 1 (1) detection of 2nd
consecutive watchdog failure
SAFE low
SAFE high
SAFE low
Reset: 1.0 ms pulse
bit 4, INIT watchdog = 0 (1) Reset: 1.0 ms pulse
Normal Request
power up, or SPI
at DBG pin during
RESET
SAFE pin release
failure recovery, SAFE pin remains low
SPI (3)
AND Bus idle time out expired
RESET Wake-up (2), VDD ON, SAFE pin remains low
register content
(SAFE high)
Failure events
1) bit 4 of INIT Watchdog register
2) Wake-up event: CAN, LIN or I/O-1 high level (if I/O-1 Wake-up previously enabled)
3) SPI commands: 0x1D80 or 0xDD80 to release SAFE pin
4) Recovery: reset low condition released, VDD low condition released, correct SPI watchdog refresh
5) detection of 8 consecutive watchdog failures: no correct SPI watchdog refresh command occurred for duration of 8 x 256 ms.
6) Dynamic behavior: 1.0 ms reset pulse every 256 ms, due to no watchdog refresh SPI command, and device state transition
Legend:
RDBG = 33 k AND I/O-1 low
RDBG =47 k AND I/O-1 low
- VDD ON
(6)
- SAFE low
- VDD ON
- Reset low
periodic pulse
State A: RDBG <6.0 k AND
watchdog failure
(VDD low or RST s/c GND) failure
safe state A
safe state B
Resistor detected
between RESET and NORMAL REQUEST mode, or INIT RESET and INIT modes.
- bus idle time out
- I/O-1 monitoring
monitoring (7):
7) 8 second timer for bus idle timeout. I/O-1 high to low transition.
SAFE Operation Flow Chart
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FUNCTIONAL DEVICE OPERATION
7.11.2.6 SAFE mode A illustration
Figure 31 illustrates the event and consequences when SAFE mode A is selected via the appropriate debug resistor or SPI configuration.
Figure 31. SAFE mode A behavior illustration
RST
V
DD
failure event, i.e. watchdog
SAFE OFF state ON state
8 x 256 ms delay time to enter in SAFE mode
V
DD
RST
SAFE
to evaluate resistor at DBG pin
and monitor ECU external events
1st 8th
2nd
Behavior Illustration for Safe State A (RDG < 6.0 kohm), or Selection by the SPI
step 1: Failure illustration
RST
V
DD
failure event, V
DD
low
SAFE OFF state ON state
100 ms delay time to enter in SAFE mode
to evaluate resistor at DBG pin
and monitor ECU external events
V
DD_UV TH
100ms
V
DD
RST
SAFE
V
DD
< V
DD_UV TH
GND GND
RST
V
DD
failure event, Reset s/c GND
SAFE OFF state ON state
100 ms deglitcher time to activate SAFE and
enter in SAFE mode to evaluate resistor at the DBG pin
and monitor ECU external events
2.5 V
100ms
V
DD
RST
SAFE
step 2: Consequence on
VDD, RST and SAFE
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FUNCTIONAL DEVICE OPERATION
7.11.2.7 SAFE mode B1, B2 and B3 illustration
Figure 32 illustrates the event, and consequences when SAFE mode B1, B2, or B3 is selected via the appropriate debug resistor or SPI
configuration.
Figure 32. SAFE modes B1, B2, or B3 behavior illustration
DBG resistor => safe state B1
V
DD
RST
SAFE
CAN bus
CAN bus idle time
I/O-1
I/O-1 high to low transition
DBG resistor => safe state B2
DBG resistor => safe state B3
CAN bus
CAN bus idle time
I/O-1
I/O-1 high to low transition
step 2:
RST
V
DD
failure event, i.e. watchdog
SAFE OFF state ON state
8 x 256 ms delay time to enter in SAFE mode
to evaluate resistor at the DBG pin
and monitor ECU external events
1st 8th
2nd
step 1: Failure illustration
RST
V
DD
failure event, V
DD
low
SAFE OFF state ON state
100 ms delay time to enter in SAFE mode
to evaluate resistor at DBG pin
and monitor ECU external events
V
DD_UV TH
100 ms
GND
RST
V
DD
failure event, Reset s/c GND
SAFE OFF state ON state
100 ms deglitcher time to activate SAFE and
enter in SAFE mode to evaluate resistor at DBG pin
and monitor ECU external events
2.5 V
100 ms
V
DD
RST
SAFE
V
DD
OFF
RST
SAFE
V
DD
If V
DD
failure recovered
V
DD
< V
DD_UV TH
V
DD
OFF
GND
step 3: Consequences for VDD
If Reset s/c GND recovered
Behavior illustration for the safe state B (RDG > 10 kohm)
Wake-up
ECU external condition
met => VDD disable
ECU external event to
RDBG resistor or
disable VDD based on
SPI configuration
Exclusive detection of
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CAN INTERFACE
8CAN interface
8.1 CAN interface description
The figure below is a high level schematic of the CAN interface. It exist in a LS driver between CANL and GND, and a HS driver from
CANH to 5 V-CAN. Two differential receivers are connected between CANH and CANL to detect a bus state and to Wake-up from CAN
Sleep mode. An internal 2.5 V reference provides the 2.5 V recessive levels via the matched RIN resistors. The resistors can be switched
to GND in CAN Sleep mode. A dedicated split buffer provides a low-impedance 2.5 V to the SPLIT pin, for recessive level stabilization.
Figure 33. CAN interface block diagram
8.1.1 Can interface supply
The supply voltage for the CAN driver is the 5 V-CAN pin. The CAN interface also has a supply pass from the battery line through the
VSUP/2 pin. This pass is used in CAN Sleep mode to allow Wake-up detection.
During CAN communication (transmission and reception), the CAN interface current is sourced from the 5 V-CAN pin. During CAN LP
mode, the current is sourced from the VSUP/2 pin.
8.1.2 TXD/RXD mode
In TXD/RXD mode, both the CAN driver and the receiver are ON. In this mode, the CAN lines are controlled by the TXD pin level and the
CAN bus state is reported on the RXD pin.
The 5 V-CAN regulator must be ON. It supplies the CAN driver and receiver.The SPLIT pin is active and a 2.5 V biasing is provided on
the SPLIT output pin.
Differential
Receiver
Driver
Driver
2.5 V
Receiver
Pattern
Detection
CANH
CANL
QH
QL
R
IN
R
IN
VSUP/2
5V-CAN
Failure Detection Buffer
5V-CAN
SPLIT
Wake-up
& Management
TXD
RXD
5V-CAN
Thermal
SPI & State machine
SPI & State machine
SPI & State machine
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CAN INTERFACE
8.1.2.1 Receive only mode
This mode is used to disable the CAN driver, but leave the CAN receiver active. In this mode, the device is only able to report the CAN
state on the RXD pin. The TXD pin has no effect on CAN bus lines. The 5 V-CAN regulator must be ON. The SPLIT pin is active and a
2.5 V biasing is provided on the SPLIT output pin.
8.1.2.2 Operation in TXD/RXD mode
The CAN driver will be enabled as soon as the device is in Normal mode and the TXD pin is recessive.
When the CAN interface is in Normal mode, the driver has two states: recessive or dominant. The driver state is controlled by the TXD
pin. The bus state is reported through the RXD pin.
When TXD is high, the driver is set in the recessive state, and CANH and CANL lines are biased to the voltage set with 5 V-CAN divided
by 2, or approx. 2.5 V.
When TXD is low, the bus is set into the dominant state, and CANL and CANH drivers are active. CANL is pulled low and CANH is pulled
high.
The RXD pin reports the bus state: CANH minus the CANL voltage is compared versus an internal threshold (a few hundred mV).
If “CANH minus CANL” is below the threshold, the bus is recessive and RXD is set high.
If “CANH minus CANL” is above the threshold, the bus is dominant and RXD is set low.
The SPLIT pin is active and provides a 2.5 V biasing to the SPLIT output.
8.1.2.3 TXD/RXD mode and slew rate selection
The CAN signal slew rate selection is done via the SPI. By default and if no SPI is used, the device is in the fastest slew rate. Three slew
rates are available. The slew rate controls the recessive to dominant, and dominant to recessive transitions. This also affects the delay
time from the TXD pin to the bus and from the bus to the RXD. The loop time is thus affected by the slew rate selection.
8.1.2.4 Minimum baud rate
The minimum baud rate is determined by the shortest TXD permanent dominant timing detection. The maximum number of consecutive
dominant bits in a frame is 12 (6 bits of active error flag and its echo error flag).
The shortest TXD dominant detection time of 300 μs lead to a single bit time of: 300 μs / 12 = 25 μs.
So the minimum Baud rate is 1 / 25 μs = 40 kBaud.
8.1.2.5 Sleep mode
Sleep mode is a reduced current consumption mode. CANH and CANL drivers are disabled and CANH and CANL lines are terminated
to GND via the RIN resistor, the SPLIT pin is high-impedance. In order to monitor bus activities, the CAN Wake-up receiver can be enabled.
It is supplied internally from VSUP/2.
Wake-up events occurring on the CAN bus pin are reporting by dedicated flags in SPI and by INT pulse, and results in a device Wake-up
if the device was in LP mode. When the device is set back into Normal mode, CANH and CANL are set back into the recessive level. This
is illustrated in Figure 34.
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Figure 34. Bus signal in TXD/RXD and LP mode
8.1.2.6 Wake-up
When the CAN interface is in Sleep mode with Wake-up enabled, the CAN bus traffic is detected. The CAN bus Wake-up is a pattern
Wake-up. The Wake-up by the CAN is enabled or disabled via the SPI.
Figure 35. Single dominant pulse wake-up
8.1.2.7 Pattern wake-up
In order to Wake-up the CAN interface, the Wake-up receiver must receive a series of three consecutive valid dominant pulses, by
default when the CANWU bit is low. CANWU bit can be set high by SPI and the Wake-up will occur after a single pulse duration of 2.0 μs
(typically). A valid dominant pulse should be longer than 500 ns. The three pulses should occur in a time frame of 120 μs, to be considered
valid. When three pulses meet these conditions, the wake signal is detected. This is illustrated by the following figure.
CANL
CANH
TXD
RXD
2.5 V
CANL-DOM
CANH-DOM
CANL/CANH-REC
2.5 V
High ohmic termination (50 kohm) to GND
SPLIT
Dominant state Recessive state
Bus Driver Receiver
(bus dominant set by other IC)
High-impedance
Normal or Listen Only mode Normal or Listen Only mode
Go to sleep,
CANH-CANL
Sleep or Stand-by mode
CANL
CANH
Internal Wake-up signal
Dominant
CAN
Pulse # 1
Dominant
Pulse # 2
t
CAN WU1-F
Can Wake-up detected
bus
Internal differential Wake-up receiver signal
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.
Figure 36. Pattern wake-up - multiple dominant detection
8.1.3 BUS termination
The device supports the two main types of bus terminations:
• Differential termination resistors between CANH and CANL lines.
• SPLIT termination concept, with the mid point of the differential termination connected to GND through a capacitor and to the SPLIT pin.
• In application, the device can also be used without termination.
•Figure 37 illustrates some of the most common terminations.
Figure 37. Bus termination options
8.2 CAN bus fault diagnostic
The device includes diagnostic of bus short-circuit to GND, VBAT, and internal ECU 5.0 V. Several comparators are implemented on
CANH and CANL lines. These comparators monitor the bus level in the recessive and dominant states. The information is then managed
by a logic circuitry to properly determine the failure and report it.
CANL
CANH
Internal Wake-up signal
Dominant
Internal differential Wake-up receiver signal
CAN
Pulse # 1
Dominant
Pulse # 2
Dominant
Pulse # 3
Dominant
Pulse # 4
tCAN WU3-F tCAN WU3-F tCAN WU3-F
tCAN WU3-TO
Dominant Pulse # n: duration 1 or multiple dominant bits
Can Wake-up detected
bus
CANH
CANL
SPLIT CAN bus
60
60
Standard termination
CANH
CANL
SPLIT CAN bus
120
No
connect
CANH
CANL
SPLIT
No termination
No
connect
ECU connector
ECU connector
CAN bus
ECU connector
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Figure 38. CAN bus simplified structure truth table for failure detection
The following table indicates the state of the comparators when there is a bus failure, and depending upon the driver state.
8.2.1 Detection principle
In the recessive state, if one of the two bus lines are shorted to GND, VDD (5.0 V), or VBAT, the voltage at the other line follows the shorted
line, due to the bus termination resistance. For example: if CANL is shorted to GND, the CANL voltage is zero, the CANH voltage
measured by the Hg comparator is also close to zero.
In the recessive state, the failure detection to GND or VBAT is possible. However, it is not possible with the above implementation to
distinguish which of the CANL or CANH lines are shorted to GND or VBAT. A complete diagnostic is possible once the driver is turned
on, and in the dominant state.
8.2.1.1 Number of samples for proper failure detection
The failure detector requires at least one cycle of the recessive and dominant states to properly recognize the bus failure. The error will
be fully detected after five cycles of the recessive-dominant states. As long as the failure detection circuitry has not detected the same
error for five recessive-dominant cycles, the error is not reported.
8.2.2 Bus clamping detection
If the bus is detected to be in dominant for a time longer than (TDOM), the bus failure flag is set and the error is reported in the SPI.
This condition could occur when the CANH line is shorted to a high-voltage. In this case, current will flow from the high-voltage short-
circuit, through the bus termination resistors (60 Ω), into the SPLIT pin (if used), and into the device CANH and CANL input resistors,
which are terminated to internal 2.5 V biasing or to GND (Sleep mode).
Table 10. Failure detection truth table
Failure description Driver recessive state Driver dominant state
Lg (threshold 1.75 V) Hg (threshold 1.75 V) Lg (threshold 1.75 V) Hg (threshold 1.75 V)
No failure 1 1 0 1
CANL to GND 0 0 0 1
CANH to GND 0 0 0 0
Lb (threshold VSUP -2.0 V) Hb (threshold VSUP -2.0 V) Lb (threshold VSUP -2.0 V) Hb (threshold VSUP -2.0 V)
No failure 0 0 0 0
CANL to VBAT 1 1 1 1
CANH to VBAT 1 1 0 1
L5 (threshold VDD -0.43 V) H5 (threshold VDD -0.43 V) L5 (threshold VDD -0.43 V) H5 (threshold VDD -0.43 V)
No failure 0 0 0 0
CANL to 5.0 V 1 1 1 1
CANH to 5.0 V 1 1 0 1
Hg CANH
CANLLg
VDD
Vrg
Vrg
Hb Vrvb
Lb Vrvb
Logic
TXD
Diag
VDD (5.0 V)
GND (0.0 V)
Recessive level (2.5 V)
VBAT (12-14 V)
VRVB (VSUP-2.0 V)
VRG (1.75 V)
CANL dominant level (1.4 V)
CANH dominant level (3.6 V)
L5 Vr5
H5 Vr5
VR5 (VDD-.43 V)
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Depending upon the high-voltage short-circuit, the number of nodes, usage of the SPLIT pin, RIN actual resistor and mode state (Sleep
or Active) the voltage across the bus termination can be sufficient to create a positive dominant voltage between CANH and CANL, and
the RXD pin will be low. This would prevent start of any CAN communication and thus, proper failure identification requires five pulses on
TXD. The bus dominant clamp circuit will help to determine such failure situation.
8.2.3 RXD permanent recessive failure (does not apply to ‘C’ and ‘D’ versions)
The aim of this detection is to diagnose an external hardware failure at the RXD output pin and ensure that a permanent failure at RXD
does not disturb the network communication. If RXD is shorted to a logic high signal, the CAN protocol module within the MCU will not
recognize any incoming message. In addition, it will not be able to easily distinguish the bus idle state and can start communication at any
time. In order to prevent this, RXD failure detection is necessary. When a failure is detected, the RXD high flag is set and CAN switches
to receive only mode.
Figure 39. RXD path simplified schematic, RXD short to VDD detection
8.2.3.1 Implementation for detection
The implementation senses the RXD output voltage at each low to high transition of the differential receiver. Excluding the internal
propagation delay, the RXD output should be low when the differential receiver is low. When an external short to VDD at the RXD output,
RXD will be tied to a high level and can be detected at the next low to high transition of the differential receiver.
As soon as the RXD permanent recessive is detected, the RXD driver is deactivated.
Once the error is detected the driver is disabled and the error is reported via SPI in CAN register.
8.2.3.2 Recovery condition
The internal recovery is done by sampling a correct low level at TXD as shown in the following illustration.
Figure 40. RXD path simplified schematic, RXD short to VDD detection
CANH
CANL
Diff
VDD
Rxsense
RXD driver
RXD
TXD
TXD driver
60
VDD
Logic
Diag
CANL&H
Diff output
RXD output
RXD short to VDD
Prop delay
RXD flag
RXD flag latched
VDD/2 Sampling Sampling
The RXD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register.
CANL&H
Diff output
RXD output RXD short to VDD
RXD flag
RXD flag latched
Sampling
Sampling
The RXD flag is not the RXPR bit in the LPC register, and neither is the CANF in the INTR register.
RXD no longer shorted to VDD
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8.2.4 TXD permanent dominant
8.2.4.1 Principle
If the TXD is set to a permanent low level, the CAN bus is set into dominant level, and no communication is possible. The device has a
TXD permanent timeout detector. After the timeout (TDOUT), the bus driver is disabled and the bus is released into a recessive state. The
TXD permanent flag is set.
8.2.4.2 Recovery
The TXD permanent dominant is used and activated when there is a TXD short to RXD. The recovery condition for a TXD permanent
dominant (recovery means the re-activation of the CAN drivers) is done by entering into a Normal mode controlled by the MCU or when
TXD is recessive while RXD change from recessive to dominant.
8.2.5 TXD to RXD short-circuit
8.2.5.1 Principle
When TXD is shorted to RXD during incoming dominant information, RXD is set to low. Consequently, the TXD pin is low and drives CANH
and CANL into a dominant state. Thus the bus is stuck in dominant. No further communication is possible.
8.2.5.2 Detection and recovery
The TXD permanent dominant timeout will be activated and release the CANL and CANH drivers. However, at the next incoming dominant
bit, the bus will then be stuck in dominant again. The recovery condition is same as the TXD dominant failure
8.2.6 Important information for bus driver reactivation
The driver stays disabled until the failure is/are removed (TXD and/or RXD is no longer permanent dominant or recessive state or shorted)
and the failure flags cleared (read). The CAN driver must be set by SPI in TXD/RXD mode in order to re enable the CAN bus driver.
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LIN BLOCK
9 LIN block
9.1 LIN interface description
The physical interface is dedicated to automotive LIN sub-bus applications.
The interface has 20 kbps and 10 kbps baud rates, and includes as well as a fast baud rate for test and programming modes. It has
excellent ESD robustness and immunity against disturbance, and radiated emission performance. It has safe behavior when a LIN bus
short-to-ground, or a LIN bus leakage during LP mode. Digital inputs are related to the device VDD pin.
9.1.1 Power supply pin (VSUP/2)
The VSUP/2 pin is the supply pin for the LIN interface. To avoid a false bus message, an undervoltage on VSUP/2 disables the
transmission path (from TXD to LIN) when
VSUP/2 falls below 6.1 V.
9.1.2 Ground pin (GND)
When there is a ground disconnection at the module level, the LIN interface do not have significant current consumption on the LIN bus
pin when in the recessive state.
9.1.3 LIN bus pin (LIN, lin1, lin2)
The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems, and is compliant to the LIN
bus specification 2.1 and SAEJ2602-2. The LIN interface is only active during Normal mode.
9.1.3.1 Driver characteristics
The LIN driver is a LS MOSFET with internal overcurrent thermal shutdown. An internal pull-up resistor with a serial diode structure is
integrated so no external pull-up components are required for the application in a slave node. An additional pull-up resistor of 1.0 kΩ must
be added when the device is used in the master node. The 1.0 kΩ pull-up resistor can be connected to the LIN pin or to the ECU battery
supply.
The LIN pin exhibits no reverse current from the LIN bus line to VSUP/2, even in the event of a GND shift or VSUP/2 disconnection. The
transmitter has a 20 kbps, 10 kbps and fast baud rate, which are selected by SPI.
9.1.3.2 Receiver characteristics
The receiver thresholds are ratiometric with the device VSUP/2 voltage.
If the VSUP/2 voltage goes below typically 6.1 V, the LIN bus enters into a recessive state even if communication is sent on TXD.
If LIN driver temperature reaches the overtemperature threshold, the transceiver and receiver are disabled. When the temperature falls
below the overtemperature threshold, LIN driver and receiver will be automatically enabled.
9.1.4 Data input pin (TXD-L, TXD-L1, TXD-L2)
The TXD-L,TXD-L1 and TXD-L2 input pin is the MCU interface to control the state of the LIN output. When TXD-L is LOW (dominant),
LIN output is LOW. When TXD-L is HIGH (recessive), the LIN output transistor is turned OFF.
This pin has an internal pull-up current source to VDD to force the recessive state if the input pin is left floating.
If the pin stays low (dominant sate) more than t TXDDOM, the LIN transmitter goes automatically in recessive state. This is reported by flag
in LIN register.
9.1.5 Data output pin (RXD-L, RXD-L1, RXD-L2)
This output pin is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive) is reported by a high voltage
on RXD, LIN LOW (dominant) is reported by a low voltage on RXD.
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9.2 LIN operational modes
The LIN interface have two operational modes, Transmit receiver and LIN disable modes.
9.2.1 Transmit receive
In the TXD/RXD mode, the LIN bus can transmit and receive information.
When the 20 kbps baud rate is selected, the slew rate and timing are compatible with LIN protocol specification 2.1.
When the 10 kbps baud rate is selected, the slew rate and timing are compatible with J2602-2.
When the fast baud rate is selected, the slew rate and timing are much faster than the above specification and allow fast data transition.
The LIN interface can be set by the SPI command in TXD/RXD mode, only when TXD-L is at a high level. When the SPI command is send
while TXD-L is low, the command is ignored.
9.2.2 Sleep mode
This mode is selected by SPI, and the transmission path is disabled. Supply current for LIN block from VSUP/2 is very low (typically 3.0 μA).
LIN bus is monitor to detect Wake-up event. In the Sleep mode, the internal 725 kOhm pull-up resistor is connected and the 30 kOhm
disconnected. The LIN block can be awakened from Sleep mode by detection of LIN bus activity.
9.2.2.1 LIN bus activity detection
The LIN bus Wake-up is recognized by a recessive to dominant transition, followed by a dominant level with a duration greater than 70 μs,
followed by a dominant to recessive transition. This is illustrated in Figures 20 and 21. Once the Wake-up is detected, the event is reported
to the device state machine. An INT is generated if the device is in LP VDD ON mode, or VDD will restart if the device was in LP VDDOFF
mode. The Wake-up can be enable or disable by the SPI.
Fail-safe Features
Table 11 describes the LIN block behavior when there is a failure.
Table 11. LIN block failure
Fault Functionnal
mode Condition Consequence Recovery
LIN supply Undervoltage
TXD RXD
LIN supply voltage < 6.0 V (typically) LIN transmitter in recessive State Condition gone
TXD Pin Permanent
Dominant TXD pin low for more than t TXDDOM LIN transmitter in recessive State Condition gone
LIN Thermal Shutdown TXD RXD LIN driver temperature > 160 °C
(typically)
LIN transmitter and receiver
disabled
HS turned off
Condition gone
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10 Serial peripheral interface
10.1 High level overview
The device uses a 16 bits SPI, with the following arrangements:
MOSI, Master Out Slave In bits:
• bits 15 and 14 (called C1 and C0) are control bits to select the SPI operation mode (write control bit to device register, read back of
the control bits, read of device flag).
• bit 13 to 9 (A4 to A0) to select the register address.
• bit 8 (P/N) has two functions: parity bit in write mode (optional, = 0 if not used), Next bit ( = 1) in read mode.
• bit 7 to 0 (D7 to D0): control bits
MISO, Master In Slave Out bits:
• bits 15 to 8 (S15 to S8) are device status bits
• bits 7 to 0 (Do7 to Do0) are either extended device status bits, device internal control register content or device flags.
The SPI implementation does not support daisy chain capability.
Figure 41 is an overview of the SPI implementation.
Figure 41. SPI overview
10.2 Detail operation
The SPI operation deviation (does not apply to ‘C’ and ‘D’ versions).
In some cases, the SPI write command is not properly interpreted by the device. This results in either a ‘non received SPI command’ or
a ‘corrupted SPI command’. Important: Due to this, the tLEAD and tCSLOW parameters must be carefully acknowledged.
Only SPI write commands (starting with bits 15,14 = 01) are affected. The SPI read commands (starting with bits 15,14 = 00 or 11) are
not affected.
The occurrence of this issue is extremely low and is caused by the synchronization between internal and external signals. In order to
guarantee proper operation, the following steps must be taken.
1. Ensure the duration of the Chip Select Low (tCSLOW) state is >5.5 μs.
Note: In data sheet revisions prior to 7.0, this parameter is not specified and is indirectly defined by the sum of 3 parameters, tLEAD + 16
x tPCLK + tLAG (sum = 4.06 μs).
Bit 15 Bit 13 Bit 11Bit 12 Bit 10Bit 14 Bit 9 Bit 8
C1 A4 A2C0
Bit 7 Bit 5 Bit 3Bit 4 Bit 2Bit 6 Bit 1 Bit 0
D7 D5 D3D4 D2D6 D1 D0
control bits
A3
register address Parity (optional) or
A0
A1 P/N
data
MOSI
S15 S13 S11S14 Do7 Do5 Do3Do4 Do2Do6 Do1 Do0
S12 S9
S10 S8
MISO
Device Status Extended Device Status, Register Control bits or Device Flags
Next bit = 1
CS
SCLK
MOSI
MISO Tri-state Tri-state
SPI Wave Form, and Signals Polarity
S15 S14 Do0
C1 C0 D0
SCLK signal is low outside of CS active
CS active low. Must rise at end of 16 clocks,
MOSI and MISO data changed at SCLK rising edge
and sampled at falling edge. Msb first.
MISO tri-state outside of CS active
Don’t CareDon’t Care
for write commands, MOSI bits [15, 14] = [0, 1]
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2. Ensure SPI timing parameter tLEAD is a min. of 550 ns.
Note: In data sheet revisions prior to 7.0, the tLEAD parameter is a min of 30 ns.
3. Make sure to include a SPI read command after a SPI write command.
In case a series of SPI write commands is used, only one additional SPI read is necessary. The recommended SPI read command is
“device ID read: 0x2580” so device operation is not affected (ex: clear flag). Other SPI read commands may also be used.
When the previous steps are implemented, the device will operate as follows:
For a given SPI write command (named SPI write ‘n’):
• In case the SPI write command ‘n’ is not accepted, the following SPI command (named SPI ‘n+1’) will finish the write process of the
SPI write ‘n’, thanks to step 2 (tLAG > 550 ns) and step 3 (which is the additional SPI command ‘n+1’).
• By applying steps 1, 2, and 3, no SPI command is ignored. Worst case, the SPI write ‘n’ is executed at the time the SPI ‘n+1’ is sent.
This will lead to a delay in device operation (delay between SPI command ‘n’ and ‘n+1’).
Note: Occurrence of an incorrect command is reduced, thanks to step 1 (extension of tCSLOW duration to >5.5 μs).
Sequence examples:
Example 1:
• 0x60C0 (CAN interface control) – in case this command is missed, next write command will complete it
• 0x66C0 (LIN interface control) – in case this command is missed, next read command will complete it
• 0x2580 (read device ID) – Additional command to complete previous LIN command, in case it was missed
Example 2:
• 0x60C0 (CAN interface control) - in case this command is missed, next write command will complete it
• 0x66C0 (LIN interface control) - in case this command is missed, next read command will complete it
• 0x2100 (read CAN register content) – this command will complete previous one, in case it was missed
• 0x2700 (read LIN register content)
SPI Operation if the CSB low flag is set to '1' (All product versions)
When the ‘CSB low’ flag is set (Bit 4 = '1' using the 0xE300 SPI command), the next SPI write commands are executed by the device only
if the SPI tLEAD time is between 30 ns and 2.5 µs maximum for the ‘C’ and ‘D’ versions, and 550 ns and 2.5 µs maximum for others
versions.
The occurrence of the CSB flag set to ‘1’ is extremely low and is directly linked to an intermittent short to ground on the board trace or a
CSB driven low by the MCU. In both cases, the CSB pin must be asserted low for more than 2.0 ms to set the flag.
The tLEAD time is represented in the SPI timing diagram (Figure 14) and corresponds to the time between CSB high to low transition and
first SCLK signal.
Note:
If the flag is cleared by a read command and the fault is no longer present, the 2.5 µs maximum of tLEAD time does not apply, but can also
be respected. This means if all the SPI write commands use a maximum tLEAD time of 2.5 µs, they are all interpreted by the device,
whatever the indication of the ‘CSB low’ flag.
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10.2.1 Bits 15, 14, and 8 functions
Table 12 summarizes the various SPI operation, depending upon bit 15, 14, and 8.
10.2.2 Bits 13-9 functions
The device contains several registers coded on five bits (bits 13 to 9).
Each register controls or reports part of the device’s function. Data can be written to the register to control the device operation or to set
the default value or behavior. Every register can also be read back in order to ensure that it’s content (default setting or value previously
written) is correct. In addition, some of the registers are used to report device flags.
10.2.2.1 Device status on MISO
When a write operation is performed to store data or control bits into the device, the MISO pin reports a 16 bit fixed device status composed
of 2 bytes: Device Fixed Status (bits 15 to 8) + extended Device Status (bits 7 to 0). In a read operation, MISO will report the Fixed device
status (bits 15 to 8) and the next eight bits will be the content of the selected register.
10.2.3 Register adress table
Table 13 is a list of device registers and addresses, coded with bits 13 to 9.
Table 12. SPI operations (bits 8, 14, & 15)
Control Bits MOSI[15-14], C1-C0 Type of Command Parity/Next
MOSI[8] P/N Note for Bit 8 P/N
00
Read back of register
content and block (CAN,
I/O, INT, LINs) real time
state. See Table 39.
1Bit 8 must be set to 1, independently of the parity function
selected or not selected.
01
Write to register
address, to control the
device operation
0If bit 8 is set to “0”: means parity not selected OR
parity is selected AND parity = 0
1if bit 8 is set to “1”: means parity is selected AND parity = 1
10 Reserved
11 Read of device flags
form a register address 1Bit 8 must be set to 1, independently of the parity function
selected or not selected.
Table 13. Device registers with corresponding address
Address
MOSI[13-9]
A4...A0
Description Quick Ref.
Name Functionality
0_0000 Analog Multiplexer MUX 1) Write ‘device control bits’ to register address.
2) Read back register ‘control bits’
0_0001 Memory byte A RAM_A
1) Write ‘data byte’ to register address.
2) Read back ‘data byte’ from register address
0_0010 Memory byte B RAM_B
0_0011 Memory byte C RAM_C
0_0100 Memory byte D RAM_D
0_0101 Initialization Regulators Init REG
1) Write ‘device initialization control bits’ to register address.
2) Read back ‘initialization control bits’ from register address
0_0110 Initialization Watchdog Init
watchdog
0_0111 Initialization LIN and I/O Init LIN I/O
0_1000 Initialization Miscellaneous functions Init MISC
0_1001 Specific modes SPE_MOD
E
1) Write to register to select device Specific mode, using
‘Inverted Random Code’
2) Read ‘Random Code’
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10.2.4 Complete SPI operation
Table 14 is a compiled view of all the SPI capabilities and options. Both MOSI and MISO information are described.
Note: P = 0 if parity bit is not selected or parity = 0. P = 1 if parity is selected and parity = 1.
10.2.5 Parity bit 8
10.2.5.1 Calculation
The parity is used for the write-to-register command (bit 15,14 = 01). It is calculated based on the number of logic one contained in bits
15-9,7-0 sequence (this is the entire 16 bits of the write command except bit 8).
Bit 8 must be set to 0 if the number of 1 is odd. Bit 8 must be set to 1if the number of 1 is even.
0_1010 Timer_A: watchdog & LP MCU consumption TIM_A
1) Write ‘timing values’ to register address
2) Read back register ‘timing values’
0_1011 Timer_B: Cyclic Sense & Cyclic Interrupt TIM_B
0_1100 Timer_C: watchdog LP & Forced Wake-up TIM_C
0_1101 Watchdog Refresh watchdog Watchdog Refresh Commands
0_1110 Mode register MODE
1) Write to register to select LP mode, with optional “Inverted
Random code” and select Wake-up functionality
2) Read operations:
Read back device ‘Current mode’
Read ‘Random Code’,
Leave ‘Debug mode’
0_1111 Regulator Control REG
1) Write ‘device control bits’ to register address, to select device
operation.
2) Read back register ‘control bits’.
3) Read device flags from each of the register addresses.
1_0000 CAN interface control CAN
1_0001 Input Output control I/O
1_0010 Interrupt Control Interrupt
1_0011 LIN1 interface control LIN1
1_0100 LIN2 interface control LIN2
Table 14. SPI capabilities with options
Type of Command MOSI/
MISO
Control bits
[15-14]
Address
[13-9]
Parity/Next
bits [8] Bit 7 Bits [6-0]
Read back of “device control bits” (MOSI bit
7 = 0)
OR
Read specific device information (MOSI bit
7 = 1)
MOSI 00 address 1 0 000 0000
MISO Device Fixed Status (8 bits) Register control bits content
MOSI 00 address 1 1 000 0000
MISO Device Fixed Status (8 bits) Device ID and I/Os state
Write device control bit to address selected
by bits (13-9).
MISO return 16 bits device status
MOSI 01 address (note) Control bits
MISO Device Fixed Status (8 bits) Device Extended Status (8 bits)
Reserved MOSI 10 Reserved
MISO Reserved
Read device flags and Wake-up flags, from
register address (bit 13-9), and sub address
(bit 7).
MISO return fixed device status (bit 15-8) +
flags from the selected address and sub-
address.
MISO 11 address Reserved 0Read of device flags form a register
address, and sub address LOW (bit 7)
MOSI Device Fixed Status (8 bits) Flags
MISO 11 address 1 1 Read of device flags form a register
address, and sub address HIGH (bit 7)
MOSI Device Fixed Status (8 bits) Flags
Table 13. Device registers with corresponding address (continued)
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10.2.5.2 Examples 1:
MOSI [bit 15-0] = 01 00 011 P 01101001, P should be 0, because the command contains 7 bits with logic 1. Thus the Exact command will
then be: MOSI [bit 15-0] = 01 00 011 0 01101001
10.2.5.3 Examples 2:
MOSI [bit 15-0] = 01 00 011 P 0100 0000, P should be 1, because the command contains 4 bits with logic 1. Thus the Exact command
will then be: MOSI [bit 15-0] = 01 00 011 1 0100 0000
10.2.5.4 Parity function selection
All SPI commands and examples do not use parity functions. The parity function is optional. It is selected by bit 6 in INIT MISC register.
If parity function is not selected (bit 6 of INIT MISC = 0), then Parity bits in all SPI commands (bit 8) must be ‘0’.
10.3 Detail of control bits and register mapping
The following tables contain register bit meaning arranged by register address, from address 0_000 to address 1_0100
10.3.1 MUX and RAM registers
Table 15. MUX Register(42)
MOSI First Byte [15-8]
[b_15 b_14] 0_0000 [P/N]
MOSI Second Byte, bits 7-0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01 00 _ 000 P MUX_2 MUX_1 MUX_0 Int 2K I/O-att 0 0 0
Default state 0 0 0 0 0 0 0 0
Condition for default POR, 5 V-CAN off, any mode different from Normal
Bits Description
b7 b6 b5 MUX_2, MUX_1, MUX_0 - Selection of external input signal or internal signal to be measured at MUX-OUT pin
000 All functions disable. No output voltage at MUX-OUT pin
001 VDD regulator current recopy. Ratio is approx 1/97. Requires an external resistor or selection of Internal 2.0 K (bit 3)
010 Device internal voltage reference (approx 2.5 V)
011 Device internal temperature sensor voltage
100 Voltage at I/O-0. Attenuation or gain is selected by bit 3.
101 Voltage at I/O-1. Attenuation or gain is selected by bit 3.
110 Voltage at VSUP/1 pin. Refer to electrical table for attenuation ratio (approx 5)
111 Voltage at VSENSE pin. Refer to electrical table for attenuation ratio (approx 5)
b4 INT 2k - Select device internal 2.0 kohm resistor between AMUX and GND. This resistor allows the measurement of a voltage proportional
to the VDD output current.
0Internal 2.0 kohm resistor disable. An external resistor must be connected between AMUX and GND.
1Internal 2.0 kohm resistor enable.
b3 I/O-att - When I/O-0 (or I/O-1) is selected with b7,b6,b5 = 100 (or 101), b3 selects attenuation or gain
between I/O-0 (or I/O-1) and MUX-OUT pin
0Gain is approx 2 for device with VDD = 5.0 V (Ref. to electrical table for exact gain value)
Gain is approx 1.3 for device with VDD = 3.3 V (Ref. to electrical table for exact gain value)
1Attenuation is approx 4 for device with VDD = 5.0 V (Ref. to electrical table for exact attenuation value)
Attenuation is approx 6 for device with VDD = 3.3 V (Ref. to electrical table for exact attenuation value)
Notes
42. The MUX register can be written and read only when the 5V-CAN regulator is ON. If the MUX register is written or read while 5V-CAN is OFF, the
command is ignored, and the MXU register content is reset to default state (all control bits = 0).
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10.3.2 INIT registers
Note: these registers can be written only in INIT mode
Table 16. Internal memory registers A, B, C, and D, RAM_A, RAM_B, RAM_C, and RAM_D
MOSI First Byte [15-8]
[b_15 b_14] 0_0xxx [P/N]
MOSI Second Byte, bits 7-0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
01 00 _ 001 P Ram a7 Ram a6 Ram a5 Ram a4 Ram a3 Ram a2 Ram a1 Ram a0
Default state 0 0 0 0 0 0 0 0
Condition for default POR
01 00 _ 010 P Ram b7 Ram b6 Ram b5 Ram b4 Ram b3 Ram b2 Ram b1 Ram b0
Default state 0 0 0 0 0 0 0 0
Condition for default POR
01 00 _ 011 P Ram c7 Ram c6 Ram c5 Ram c4 Ram c3 Ram c2 Ram c1 Ram c0
Default state 0 0 0 0 0 0 0 0
Condition for default POR
01 00 _ 100 P Ram d7 Ram d6 Ram d5 Ram d4 Ram d3 Ram d2 Ram d1 Ram d0
Default state 0 0 0 0 0 0 0 0
Condition for default POR
Table 17. Initialization regulator registers, INIT REG (note: register can be written only in INIT mode)
MOSI First Byte [15-8]
[b_15 b_14] 0_0101 [P/N]
MOSI Second Byte, bits 7-0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01 00 _ 101 P I/O-x sync VDDL rst[1] VDDL rst[0] VDD rstD[1] VDD rstD[0] VAUX5/3 Cyclic on[1] Cyclic on[0]
Default state 1 0 0 0 0 0 0 0
Condition for default POR
Bit Description
b7 I/O-x sync - Determine if I/O-1 is sensed during I/O-0 activation, when cyclic sense function is selected
0I/O-1 sense anytime
1I/O-1 sense during I/O-0 activation
b6, b5 VDDL RST[1] VDDL RST[0] - Select the VDD undervoltage threshold, to activate RST pin and/or INT
00 Reset at approx 0.9 VDD.
01 INT at approx 0.9 VDD, Reset at approx 0.7 VDD
10 Reset at approx 0.7 VDD
11 Reset at approx 0.9 VDD.
b4, b3 VDD RSTD[1] VDD RSTD[0] - Select the RST pin low lev duration, after VDD rises above the VDD undervoltage threshold
00 1.0 ms
01 5.0 ms
10 10 ms
11 20 ms
b2 [VAUX 5/3] - Select Vauxilary output voltage
0 VAUX = 3.3 V
1 VAUX = 5.0 V
b1, b0 Cyclic on[1] Cyclic on[0] - Determine I/O-0 activation time, when cyclic sense function is selected
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00 200 μs (typical value. Ref. to dynamic parameters for exact value)
01 400 μs (typical value. Ref. to dynamic parameters for exact value)
10 800 μs (typical value. Ref. to dynamic parameters for exact value)
11 1600 μs (typical value. Ref. to dynamic parameters for exact value)
Table 18. Initialization watchdog registers, INIT watchdog (note: register can be written only in INIT mode)
MOSI First Byte [15-8]
[b_15 b_14] 0_0110 [P/N]
MOSI Second Byte, bits 7-0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01 00 _ 110 P WD2INT MCU_OC OC-TIM WD Safe WD_spi[1] WD_spi[0] WD N/Win Crank
Default state 0 1 0 0 0 1 0
Condition for default POR
Bit Description
b7 WD2INT - Select the maximum time delay between INT occurrence and INT source read SPI command
0Function disable. No constraint between INT occurrence and INT source read.
1INT source read must occur before the remaining of the current watchdog period plus 2 complete watchdog periods.
b6, b5 MCU_OC, OC-TIM - In LP VDD ON, select watchdog refresh and VDD current monitoring functionality. VDD_OC_LP threshold
is defined in device electrical parameters (approx 1.5 mA)
In LP mode, when watchdog is not selected
no
watchdog +
00
In LP VDD ON mode, VDD overcurrent has no effect
no
watchdog +
01
In LP VDD ON mode, VDD overcurrent has no effect
no
watchdog +
10
In LP VDD ON mode, VDD current > VDD_OC_LP threshold for a time > 100 μs (typically) is a wake-up event
no
watchdog +
11
In LP VDD ON mode, VDD current > VDD_OC_LP threshold for a time > I_mcu_OC is a wake-up event. I_mcu_OC time is
selected in Timer register (selection range from 3.0 to 32 ms)
In LP mode when watchdog is selected
watchdog +
00 In LP VDD ON mode, VDD current > VDD_OC_LP threshold has no effect. watchdog refresh must occur by SPI command.
watchdog +
01 In LP VDD ON mode, VDD current > VDD_OC_LP threshold has no effect. watchdog refresh must occur by SPI command.
watchdog +
10 In LP VDD ON mode, VDD overcurrent for a time > 100 μs (typically) is a wake-up event.
watchdog +
11
In LP VDD ON mode, VDD current > VDD_OC_LP threshold for a time < I_mcu_OC is a watchdog refresh condition. VDD current
> VDD_OC_LP threshold for a time > I_mcu_OC is a wake-up event. I_mcu_OC time is selected in Timer register (selection
range from 3.0 to 32 ms)
b4 WD Safe - Select the activation of the SAFE pin low, at first or second consecutive RESET pulse
0SAFE pin is set low at the time of the RST pin low activation
1SAFE pin is set low at the second consecutive time RST pulse
b3, b2 WD_spi[1] WD_spi[0] - Select the Watchdog (watchdog) Operation
00 Simple Watchdog selection: watchdog refresh done by a 8 bits or 16 bits SPI
01 Enhanced 1: Refresh is done using the Random Code, and by a single 16 bits.
10 Enhanced 2: Refresh is done using the Random Code, and by two 16 bits command.
Bit Description
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11 Enhanced 4: Refresh is done using the Random Code, and by four 16 bits command.
b1 WD N/Win - Select the Watchdog (watchdog) Window or Timeout operation
0Watchdog operation is TIMEOUT, watchdog refresh can occur anytime in the period
1Watchdog operation is WINDOW, watchdog refresh must occur in the open window (second half of period)
b0 Crank - Select the VSUP/1 threshold to disable VDD, while VSUP1 is falling toward GND
0 VDD disable when VSUP/1 is below typically 4.0 V (parameter VSUP-TH1), and device in Reset mode
1 VDD kept ON when VSUP/1 is below typically 4.0 V (parameter VSUP_TH1)
Table 19. Initialization LIN and I/O registers, INIT LIN I/O (note: register can be written only in INIT mode)
MOSI First Byte [15-8]
[b_15 b_14] 0_0111 [P/N]
MOSI Second Byte, bits 7-0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01 00 _ 111 P I/O-1 ovoff LIN_T2[1] LIN_T2[0] LIN_T/1[1] LIN_T/1[0] I/O-1 out-en I/O-0 out-en Cyc_Inv
Default state 0 0 0 0 0 0 0
Condition for default POR
Bit Description
b7 I/O-1 ovoff - Select the deactivation of I/O-1 when VDD or VAUX overvoltage condition is detected
0Disable I/O-1 turn off.
1Enable I/O-1 turn off, when VDD or VAUX overvoltage condition is detected.
b6, b5 LIN_T2[1], LIN_T2[0] - Select pin operation as LIN Master pin switch or I/O
00 pin is OFF
01 pin operation as LIN Master pin switch
10 pin operation as I/O: HS switch and Wake-up input
11 N/A
b4, b3 LIN_T/1[1], LIN_T/1[0] - Select pin operation as LIN Master pin switch or I/O
00 pin is OFF
01 pin operation as LIN Master pin switch
10 pin operation as I/O: HS switch and Wake-up input
11 N/A
b2 I/O-1 out-en- Select the operation of the I/O-1 as output driver (HS, LS)
0Disable HS and LS drivers of pin I/O-1. I/O-1 can only be used as input.
1Enable HS and LS drivers of pin I/O-1. Pin can be used as input and output driver.
b1 I/O-0 out-en - Select the operation of the I/O-0 as output driver (HS, LS)
0Disable HS and LS drivers of I/O-0 can only be used as input.
1Enable HS and LS drivers of the I/O-0 pin. Pin can be used as input and output drivers.
b0 Cyc_Inv - Select I/O-0 operation in device LP mode, when cyclic sense is selected
Bit Description
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0During cyclic sense active time, I/O is set to the same state prior to entering in to LP mode. During cyclic sense off time, I/O-0
is disable (HS and LS drivers OFF).
1
During cyclic sense active time, I/O is set to the same state prior to entering in to LP mode. During cyclic sense off time, the
opposite driver of I/O_0 is actively set. Example: If I/0_0 HS is ON during active time, then I/O_O LS is turned ON at expiration
of the active time, for the duration of the cyclic sense period.
Table 20. Initialization Miscellaneous Functions, INIT MISC (Note: Register can be written only in INIT mode)
MOSI First Byte [15-8]
[b_15 b_14] 0_1000 [P/N]
MOSI Second Byte, bits 7-0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01 01_ 000 P LPM w
RNDM SPI parity INT pulse INT width INT flash Dbg Res[2] Dbg Res[1] Dbg Res[0]
Default state 0 0 0 0 0 0 0
Condition for default POR
Bit Description
b7 LPM w RNDM - This enables the usage of random bits 2, 1 and 0 of the MODE register to enter into LP VDD OFF or LP VDD
ON.
0Function disable: the LP mode can be entered without usage of Random Code
1Function enabled: the LP mode is entered using the Random Code
b6 SPI parity - Select usage of the parity bit in SPI write operation
0Function disable: the parity is not used. The parity bit must always set to logic 0.
1Function enable: the parity is used, and parity must be calculated.
b5 INT pulse -Select INT pin operation: low level pulse or low level
0INT pin will assert a low level pulse, duration selected by bit [b4]
1INT pin assert a permanent low level (no pulse)
b4 INT width - Select the INT pulse duration
0INT pulse duration is typically 100 μs. Ref. to dynamic parameter table for exact value.
1INT pulse duration is typically 25 μs. Ref. to dynamic parameter table for exact value.
b3 INT flash - Select INT pulse generation at 50% of the Watchdog Period in Flash mode
Function disable
Function enable: an INT pulse will occur at 50% of the Watchdog Period when device in Flash mode.
b2, b1, b0 Dbg Res[2], Dbg Res[1], Dbg Res[0] - Allow verification of the external resistor connected at DBG pin. Ref. to parametric
table for resistor range value.(43)
0xx Function disable
100 100 verification enable: resistor at DBG pin is typically 68 kohm (RB3) - Selection of SAFE mode B3
101 101 verification enable: resistor at DBG pin is typically 33 kohm (RB2 - Selection of SAFE mode B2
110 110 verification enable: resistor at DBG pin is typically 15 kohm (RB1) - Selection of SAFE mode B1
111 111 verification enable: resistor at DBG pin is typically 0 kohm (RA) - Selection of SAFE mode A
Notes
43. Bits b2,1 and 0 allow the following operation:
First, check the resistor device has detected at the DEBUG pin. If the resistor is different, bit 5 (Debug resistor) is set in INTerrupt
register (Ref. to device flag table).
Second, over write the resistor decoded by device, to set the SAFE mode operation by SPI. Once this function is selected by bit 2 = 1,
this selection has higher priority than ‘hardware’, and device will behave according to b2,b1 and b0 setting
Bit Description
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10.3.3 Specific mode register
10.3.3.1 The SPE mode register is used for the following operation
- Set the device in RESET mode, to exercise or test the RESET functions.
- Go to INIT mode, using the Secure SPi command.
- Go to FLASH mode (in this mode the watchdog timer can be extended up to 32 s).
- Activate the SAFE pin by S/W.
This mode (called Special mode) is accessible from the secured SPI command, which consist of 2 commands:
1) reading a random code and
2) then write the inverted random code plus mode selection or SAFE pin activation:
Return to INIT mode is done as follow (this is done from Normal mode only):
1) Read random code:
MOSI : 0001 0011 0000 0000 [Hex:0x 13 00]
MISO report 16 bits, random code are bits (5-0)
miso = xxxx xxxx xxR5 R4 R3 R2 R1 R0 (RXD = 6 bits random code)
2) Write INIT mode + random code inverted
MOSI : 0101 0010 01 Ri5 Ri4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 52 HH] (RIX = random code inverted)
MISO : xxxx xxxx xxxx xxxx (don’t care)
SAFE pin activation: SAFE pin can be set low, only in INIT mode, with following commands:
1) Read random code:
MOSI : 0001 0011 0000 0000 [Hex:0x 13 00]
MISO report 16 bits, random code are bits (5-0)
miso = xxxx xxxx xxR5 R4 R3 R2 R1 R0 (RXD = 6 bits random code)
2) Write INIT mode + random code bits 5:4 not inverted and random code bits 3:0 inverted
MOSI : 0101 0010 01 R5 R4 Ri3 Ri2 Ri1 Ri0 [Hex 0x 52 HH] (RIX = random code inverted)
MISO : xxxx xxxx xxxx xxxx (don’t care)
Return to Reset or Flash mode is done similarly to the go to INIT mode, except that the b7 and b6 are set according to the table above
(b7, b6 = 00 - go to reset, b7, b6 = 10 - go to Flash).
Table 21. Specific mode register, SPE_MODE
MOSI First Byte [15-8]
[b_15 b_14] 01_001 [P/N]
MOSI Second Byte, bits 7-0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01 01_ 001 P Sel_Mod[1] Sel_Mod[0] Rnd_C5b Rnd_C4b Rnd_C3b Rnd_C2b Rnd_C1b Rnd_C0b
Default state 0 0 0 0 0 0 0
Condition for default POR
Bit Description
b7, b6 Sel_Mod[1], Sel_Mod[0] - Mode selection: these 2 bits are used to select which mode the device will enter upon a SPI
command.
00 RESET mode
01 INIT mode
10 FLASH mode
11 N/A
b5....b0 [Rnd_C4b... Rnd_C0b] - Random Code inverted, these six bits are the inverted bits obtained from the SPE MODE Register
read command.
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10.3.4 Timer registers
Table 22. Timer register A, LP VDD overcurrent & watchdog period normal mode, TIM_A
MOSI First Byte [15-8]
[b_15 b_14] 01_010 [P/N]
MOSI Second Byte, bits 7-0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01 01_ 010 P I_mcu[2] I_mcu[1] I_mcu[1] watchdog
Nor[4] W/D_N[4] W/D_Nor[3] W/D_N[2] W/D_Nor[0]
Default state 0 0 0 1 1 1 1 0
Condition for default POR
LP VDD overcurrent (ms)
b7
b6, b5
00 01 10 11
03 (def) 612 24
1 4 8 16 32
Watchdog period in device normal mode (ms)
b4, b3
b2, b1, b0
000 001 010 011 100 101 110 111
00 2.5 510 20 40 80 160 320
01 3 6 12 24 48 96 192 384
10 3.5 714 28 56 112 224 448
11 4 8 16 32 64 128 256 (def) 512
Table 23. Timer register B, cyclic sense and cyclic INT, in device LP mode, TIM_B
MOSI First Byte [15-8]
[b_15 b_14] 01_011 [P/N]
MOSI Second Byte, bits 7-0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01 01_ 011 P Cyc-sen[3] Cyc-sen[2] Cyc-sen[1] Cyc-sen[0] Cyc-int[3] Cyc-int[2] Cyc-int[1] Cyc-int[0]
Default state 0 0 0 0 0 0 0 0
Condition for default POR
Cyclic sense (ms)
b7
b6, b5, b4
000 001 010 011 100 101 110 111
0 3 6 12 24 48 96 192 384
1 4 8 16 32 64 128 256 512
Cyclic interrupt (ms)
b3
b2, b1, b0
000 001 010 011 100 101 110 111
06 (def) 12 24 48 96 192 384 768
1 8 16 32 64 128 258 512 1024
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10.3.5 Watchdog and mode registers
Table 24. Timer register C, watchdog LP mode or flash mode and forced wake-up timer, TIM_C
MOSI First Byte [15-8]
[b_15 b_14] 01_100 [P/N]
MOSI Second Byte, bits 7-0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01 01_ 100 P WD-LP-F[3] WD-LP-F[2] WD-LP-F[1] WD-LP-F[0] FWU[3] FWU[2] FWU[1] FWU[0]
Default state 0 0 0 0 0 0 0 0
Condition for default POR
Table 25. Typical timing values
Watchdog in LP VDD ON mode (ms)
b7
b6, b5, b4
000 001 010 011 100 101 110 111
012 24 48 96 192 384 768 1536
116 32 64 128 256 512 1024 2048
Watchdog in flash mode (ms)
b7
b6, b5, b4
000 001 010 011 100 101 110 111
048 (def) 96 192 384 768 1536 3072 6144
1256 512 1024 2048 4096 8192 16384 32768
Forced wake-up (ms)
b3
b2, b1, b0
000 001 010 011 100 101 110 111
048 (def) 96 192 384 768 1536 3072 6144
164 128 258 512 1024 2048 4096 8192
Table 26. Watchdog refresh register, watchdog(44)
MOSI First Byte [15-8]
[b_15 b_14] 01_101 [P/N]
MOSI Second Byte, bits 7-0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01 01_ 101 P 0 0 0 0 0 0 0 0
Default state 0 0 0 0 0 0 0 0
Condition for default POR
Notes
44. The Simple Watchdog Refresh command is in hexadecimal: 5A00. This command is used to refresh the watchdog and also to
transition from INIT mode to Normal mode, and from Normal Request mode to Normal mode (after a wake-up of a reset)
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.
Prior to enter in LP VDD ON or LP VDD OFF, the Wake-up flags must be cleared or read.
This is done by the following SPI commands (See Table 39, Device flag, I/O real time and device identification):
0xE100 for CAN Wake-up clear
0xE380 for I/O Wake-up clear
0xE700 for LIN1 Wake-up clear
0xE900 for LIN2 Wake-up clear
If Wake-up flags are not cleared, the device will enter into the selected LP mode and immediately Wake-up. In addition, the CAN failure
flags (i.e. CAN_F and CAN_UF) must be cleared in order to meet the low power current consumption specification. This is done by the
following SPI command:
0xE180 (read CAN failure flags)
When the device is in LP VDD ON mode, the Wake-up by a SPI command uses a write to ‘Normal Request mode’, 0x5C10.
Table 27. MODE register, mode
MOSI First Byte [15-8]
[b_15 b_14] 01_110 [P/N]
MOSI Second Byte, bits 7-0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01 01_ 110 P mode[4] mode[3] mode[2] mode[1] mode[0] Rnd_b[2] Rnd_b[1] Rnd_b[0]
Default state N/A N/A N/A N/A N/A N/A N/A N/A
Table 28. LP VDD off selection and FWU / cyclic sense selection
b7, b6, b5, b4, b3 FWU Cyclic Sense
0 1100 OFF OFF
0 1101 OFF ON
0 1110 ON OFF
0 1111 ON ON
Table 29. LP VDD on selection and operation mode
b7, b6, b5, b4, b3 FWU Cyclic Sense Cyclic INT Watchdog
1 0000 OFF OFF OFF OFF
1 0001 OFF OFF OFF ON
1 0010 OFF OFF ON OFF
1 0011 OFF OFF ON ON
1 0100 OFF ON OFF OFF
1 0101 OFF ON OFF ON
1 0110 OFF ON ON OFF
1 0111 OFF ON ON ON
1 1000 ON OFF OFF OFF
1 1001 ON OFF OFF ON
1 1010 ON OFF ON OFF
1 1011 ON OFF ON ON
1 1100 ON ON OFF OFF
1 1101 ON ON OFF ON
1 1110 ON ON ON OFF
1 1111 ON ON ON ON
b2, b1, b0
Random Code inverted, these 3bits are the inverted bits obtained from the previous SPI command.
The usage of these bits are optional and must be previously selected in the INIT MISC register [See
bit 7 (LPM w RNDM) in Table 20]
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10.3.5.1 Mode register features
The mode register includes specific functions and a ‘global SPI command’ that allow the following:
- read device current mode
- read device Debug status
- read state of SAFE pin
- leave Debug state
- release or turn off SAFE pin
- read a 3 bit Random Code to enter in LP mode
These global commands are built using the MODE register address bit [13-9], along with several combinations of bit [15-14] and bit [7].
Note, bit [8] is always set to 1.
10.3.5.2 Entering into LP mode using random code
- LP mode using Random Code must be selected in INIT mode via bit 7 of the INIT MISC register.
- In Normal mode, read the Random Code using 0x1D00 or 0x1D80 command. The 3 Random Code bits are available on MISO bits 2,1 and 0.
- Write LP mode by inverting the 3 random bits.
Example - Select LP VDD OFF without cyclic sense and FWU:
1. in hex: 0x5C60 to enter in LP VDD OFF mode without using the 3 random code bits.
2. if Random Code is selected, the commands are:
- Read Random Code: 0x1D00 or 0x1D80,
MISO report in binary: bits 15-8, bits 7-3, Rnd_[2], Rnd_[1], Rnd_[0].
- Write LP VDD OFF mode, using Random Code inverted:
in binary: 0101 1100 0110 0 Rnd_b[2], Rnd_b[1], Rnd_b[0].
Table 30 summarizes these commands
Table 31 describes MISO bits 7-0, used to decode the device’s current mode.
Table 30. Device modes
Global commands and effects
Read device current mode, Leave debug mode.
Keep SAFE pin as is.
MOSI in hexadecimal: 1D 00
MOSI bits 15-14 bits 13-9 bit 8 bit 7 bits 6-0
00 01 110 1 0 000 0000
MISO bit 15-8 bit 7-3 bit 2-0
Fix Status device current mode Random code
Read device current mode
Release SAFE pin (turn OFF).
MOSI in hexadecimal: 1D 80
MOSI bits 15-14 bits 13-9 bit 8 bit 7 bits 6-0
00 01 110 1 1 000 0000
MISO bit 15-8 bit 7-3 bit 2-0
Fix Status device current mode Random code
Read device current mode, Leave debug mode.
Keep SAFE pin as is.
MOSI in hexadecimal: DD 00
MISO reports Debug and SAFE state (bits 1,0)
MOSI bits 15-14 bits 13-9 bit 8 bit 7 bits 6-0
11 01 110 1 0 000 0000
MISO bit 15-8 bit 7-3 bit 2 bit 1 bit 0
Fix Status device current mode XSAFE DEBUG
Read device current mode, Keep DEBUG mode
Release SAFE pin (turn OFF).
MOSI in hexadecimal: DD 80
MISO reports Debug and SAFE state (bits 1,0)
MOSI bits 15-14 bits 13-9 bit 8 bit 7 bits 6-0
11 01 110 1 1 000 0000
MISO bit 15-8 bit 7-3 bit 2 bit 1 bit 0
Fix Status device current mode XSAFE DEBUG
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Table 32 describes the SAFE and DEBUG bit decoding.
Table 31. MISO bits 7-3
Device current mode, any of the above commands
b7, b6, b5, b4, b3 MODE
0 0000 INIT
0 0001 FLASH
0 0010 Normal Request
0 0011 Normal mode
1 XXXX Low Power mode (Table 29)
Table 32. SAFE and DEBUG status
SAFE and DEBUG bits
b1 description
0SAFE pin ON, driver activated
1SAFE pin OFF, not activated
b0 description
0Debug mode OFF
1Debug mode Active
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10.3.6 Regulator, CAN, I/O, INT and lin registers
Table 33. Regulator register
MOSI First Byte [15-8]
[b_15 b_14] 01_111 [P/N]
MOSI Second Byte, bits 7-0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01 01_ 111 P VAUX[1] VAUX[0] -5V-can[1] 5V-can[0] VDD bal en VDD bal auto VDD OFF en
Default state 0 0 N/A 0 0 N/A N/A N/A
Condition for default POR POR
Bits Description
b7 b6 VAUX[1], VAUX[0] - Vauxilary regulator control
00 Regulator OFF
01 Regulator ON. undervoltage (UV) and Overcurrent (OC) monitoring flags not reported. VAUX is disabled when UV or OC
detected after 1.0 ms blanking time.
10 Regulator ON. undervoltage (UV) and overcurrent (OC) monitoring flags active. VAUX is disabled when UV or OC detected after
1.0 ms blanking time.
11 Regulator ON. undervoltage (UV) and overcurrent (OC) monitoring flags active. VAUX is disabled when UV or OC detected after
25 μs blanking time.
b4 b3 5 V-can[1], 5 V-can[0] - 5V-CAN regulator control
00 Regulator OFF
01 Regulator ON. Thermal protection active. undervoltage (UV) and overcurrent (OC) monitoring flags not reported. 1.0 ms
blanking time for UV and OC detection. Note: by default when in Debug mode
10 Regulator ON. Thermal protection active. undervoltage (UV) and overcurrent (OC) monitoring flags active. 1.0 ms blanking time
for UV and OC detection.
11 Regulator ON. Thermal protection active. undervoltage (UV) and overcurrent (OC) monitoring flags active after 25 μs blanking
time.
b2 VDD bal en - Control bit to Enable the VDD external ballast transistor
0External VDD ballast disable
1External VDD ballast Enable
b1 VDD bal auto - Control bit to automatically Enable the VDD external ballast transistor, if VDD is > typically 60 mA
0Disable the automatic activation of the external ballast
1Enable the automatic activation of the external ballast, if VDD > typically 60 mA
b0 VDD OFF en - Control bit to allow transition into LP VDD OFF mode (to prevent VDD turn OFF)
0Disable Usage of LP VDD OFF mode
1Enable Usage of LP VDD OFF mode
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Table 34. CAN register(45)
MOSI First byte [15-8]
[b_15 b_14] 10_000 [P/N]
MOSI Second Byte, bits 7-0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01 10_ 000P CAN mod[1] CAN mod[0] Slew[1] Slew[0] Wake-up 1/3 - - CAN int
Default state 1 0 0 0 0 - - 0
Condition for default note POR POR POR
Bits Description
b7 b6 CAN mod[1], CAN mod[0] - CAN interface mode control, Wake-up enable / disable
00 CAN interface in Sleep mode, CAN Wake-up disable.
01 CAN interface in receive only mode, CAN driver disable.
10 CAN interface is in Sleep mode, CAN Wake-up enable. In device LP mode,
CAN Wake-up is reported by device Wake-up. In device Normal mode, CAN Wake-up reported by INT.
11 CAN interface in transmit and receive mode.
b5 b4 Slew[1] Slew[0] - CAN driver slew rate selection
00/11 FAST
01 MEDIUM
10 SLOW
b3 Wake-up 1/3 - Selection of CAN Wake-up mechanism
03 dominant pulses Wake-up mechanism
1Single dominant pulse Wake-up mechanism
b0 CAN INT - Select the CAN failure detection reporting
0Select INT generation when a bus failure is fully identified and decoded (i.e. after 5 dominant pulses on TxCAN)
1Select INT generation as soon as a bus failure is detected, event if not fully identified
Notes
45. The first time the device is set to Normal mode, the CAN is in Sleep Wake-up enabled (bit7 = 1, bit 6 =0). The next time the device is
set in Normal mode, the CAN state is controlled by bits 7 and 6.
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Table 35. I/O register
MOSI First byte [15-8]
[b_15 b_14] 10_001 [P/N]
MOSI Second Byte, bits 7-0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01 10_ 001P I/O-3 [1] I/O-3 [0] I/O-2 [1] I/O-2 [0] I/O-1 [1] I/O-1 [0] I/O-0 [1] I/O-0 [0]
Default state 0 0 0 0 0 0 0 0
Condition for default POR
Bits Description
b7 b6 I/O-3 [1], I/O-3 [0] - I/O-3 pin operation
00 I/O-3 driver disable, Wake-up capability disable
01 I/O-3 driver disable, Wake-up capability enable.
10 I/O-3 HS driver enable.
11 I/O-3 HS driver enable.
b5 b4 I/O-2 [1], I/O-2 [0] - I/O-2 pin operation
00 I/O-2 driver disable, Wake-up capability disable
01 I/O-2 driver disable, Wake-up capability enable.
10 I/O-2 HS driver enable.
11 I/O-2 HS driver enable.
b3 b2 I/O-1 [1], I/O-1 [0] - I/O-1 pin operation
00 I/O-1 driver disable, Wake-up capability disable
01 I/O-1 driver disable, Wake-up capability enable.
10 I/O-1 LS driver enable.
11 I/O-1 HS driver enable.
b1 b0 I/O-0 [1], I/O-0 [0] - I/O-0 pin operation
00 I/O-0 driver disable, Wake-up capability disable
01 I/O-0 driver disable, Wake-up capability enable.
10 I/O-0 LS driver enable.
11 I/O-0 HS driver enable.
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Table 36. INT register
MOSI First byte [15-8]
[b_15 b_14] 10_010 [P/N]
MOSI Second Byte, bits 7-0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01 10_ 010P CAN failure MCU req LIN2 fail LIN1fail I/O SAFE -Vmon
Default state 0 0 0 0 0 0 0 0
Condition for default POR
Bits Description
b7 CAN failure - control bit for CAN failure INT (CANH/L to GND, VDD or VSUP, CAN overcurrent, Driver Overtemp, TXD-PD,
RXD-PR, RX2HIGH, and CANBUS Dominate clamp)
0INT disable
1INT enable.
b6 MCU req - Control bit to request an INT. INT will occur once when the bit is enable
0INT disable
1INT enable.
b5 LIN2 fail - Control bit to enable INT when of failure on LIN2 interface
0INT disable
1INT enable.
b4 LIN/1 fail - Control bit to enable INT when of failure on LIN1 interface
0INT disable
1INT enable.
b3 I/O - Bit to control I/O interruption: I/O failure
0INT disable
1INT enable.
b2 SAFE - Bit to enable INT when of: Vaux overvoltage, VDD overvoltage, VDD Temp pre-warning, VDD undervoltage(46), SAFE
resistor mismatch, RST terminal short to VDD, MCU request INT.(47)
0INT disable
1INT enable.
b0 VMON - enable interruption by voltage monitoring of one of the voltage regulator: VAUX, 5 V-CAN, VDD (IDD Overcurrent, VSUV,
VSOV, VSENSELOW, 5V-CAN low or thermal shutdown, VAUX low or VAUX overcurrent
0INT disable
1INT enable.
Notes
46. If VDD undervoltage is set to 70% of VDD, see bits b6 and b5 in Table 15 on page 69.
47. Bit 2 is used in conjunction with bit 6. Both bit 6 and bit 2 must be set to 1 to activate the MCU INT request.
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Table 37. LIN/1 Register(49)
MOSI First byte [15-8]
[b_15 b_14] 10_010 [P/N]
MOSI Second Byte, bits 7-0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01 10_ 011P LIN mode[1] LIN mode[0] Slew rate[1] Slew rate[0] -LIN T/1 on - VSUP ext
Default state 0 0 0 0 0 0 0 0
Condition for default POR
Bits Description
b7 b6 LIN mode [1], LIN mode [0] - LIN/1 interface mode control, Wake-up enable / disable
00 LIN/1 disable, Wake-up capability disable
01 not used
10 LIN/1 disable, Wake-up capability enable
11 LIN/1 Transmit Receive mode(48)
b5 b4 Slew rate[1], Slew rate[0] LIN/1 slew rate selection
00 Slew rate for 20 kbit/s baud rate
01 Slew rate for 10 kbit/s baud rate
10 Slew rate for fast baud rate
11 Slew rate for fast baud rate
b2 LIN T/1 on
0LIN/1 termination OFF
1LIN/1 termination ON
b0 VSUP ext
0LIN goes recessive when device VSUP/2 is below typically 6.0 V. This is to meet J2602 specification
1LIN continues operation below VSUP/2 6.0 V, until 5 V-CAN is disabled.
Notes
48. The LIN interface can be set in TXD/RXD mode only when the TXD-L input signal is in recessive state. An attempt to set TXD/RXD
mode, while TXD-L is low, will be ignored and the LIN interface remains disabled.
49. In order to use the LIN interface, the 5V-CAN regulator must be set to ON.
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10.4 Flags and device status
10.4.1 Description
The table below is a summary of the device flags, I/O real time level, device Identification, and includes examples of SPI commands (SPI
commands do not use parity functions). They are obtained using the following commands.
This command is composed of the following:
bits 15 and 14:
• [1 1] for failure flags
• - [0 0] for I/O real time status, device identification and CAN LIN driver receiver real time state.
• bit 13 to 9 are the register address from which the flags is to be read.
•bit 8 = 1 (this is not parity bit function, as this is a read command).
When a failure event occurs, the respective flag is set and remains latched until it is cleared by a read command (provided the failure
event has recovered).
Table 38. LIN2 register(51)
MOSI First byte [15-8]
[b_15 b_14] 10_010 [P/N]
MOSI Second Byte, bits 7-0
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
01 10_ 100P LIN mode[1] LIN mode[0] Slew rate[1] Slew rate[0] -LIN T2 on - VSUP ext
Default state 0 0 0 0 0 0 0 0
Condition for default POR
Bits Description
b7 b6 LIN mode [1], LIN mode [0] - LIN 2 interface mode control, Wake-up enable / disable
00 LIN2 disable, Wake-up capability disable
01 not used
10 LIN2 disable, Wake-up capability enable
11 LIN2 Transmit Receive mode(50)
b5 b4 Slew rate[1], Slew rate[0] LIN 2slew rate selection
00 Slew rate for 20 kbit/s baud rate
01 Slew rate for 10 kbit/s baud rate
10 Slew rate for fast baud rate
11 Slew rate for fast baud rate
b2 LIN T2 on
0LIN 2 termination OFF
1LIN 2 termination ON
b0 VSUP ext
0LIN goes recessive when device VSUP/2 is below typically 6.0 V. This is to meet J2602 specification
1LIN continues operation below VSUP/2 6.0 V, until 5 V-CAN is disabled.
Notes
50. The LIN interface can be set in TXD/RXD mode only when the TXD-L input signal is in a recessive state. An attempt to set TXD/RXD
mode while TXD-L is low, will be ignored and the LIN interface will remain disabled.
51. In order to use the LIN interface, the 5V-CAN regulator must be set to ON.
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Table 39. Device flag, I/O real time and device identification
Bits 15-14 13-9 8 7 6 5 4 3 2 1 0
MOSI
MOSI bits 15-7
Next 7 MOSI bits (bits 6.0) should be “000_0000”
bits [15,
14]
Address
[13-9] bit 8 bit
7
MISO 8 Bits Device Fixed Status
(bits 15...8)
MISO bits [7-0], device response on MISO pin
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
REG
11 0_1111
REG 1 0 VAUX_LOW
VAUX_overCU
RRENT
5V-CAN_
THERMAL
SHUTDO
WN
5V-CAN_
UV
5V-CAN_
overCURR
ENT
VSENSE_
LOW
VSUP_
underVOLT
AGE
IDD-OC-
NORMAL
MODE
11 1 - - -
VDD_
THERMAL
SHUTDOW
N
RST_LOW
(<100 ms)
VSUP_
BATFAIL
IDD-OC-LP
VDDON
MODE
Hexa SPI commands to get Vreg Flags: MOSI 0x DF 00, and MOSI Ox DF 80
CAN
11 1_0000
CAN 1
0CAN
Wake-up -CAN
Overtemp RXD low(52) Rxd high TXD dom Bus Dom
clamp
CAN
Overcurren
t
1CAN_UF CAN_F CANL
to VBAT
CANL to
VDD
CANL to
GND
CANH to
VBAT
CANH to
VDD
CANH to
GND
Hexa SPI commands to get CAN Flags: MOSI 0x E1 00, and MOSI 0x E1 80
00 1_0000
CAN 1 1 CAN Driver
State
CAN
Receiver
State
CAN WU
en/dis - - - - -
Hexa SPI commands to get CAN real time status: MOSI 0x 21 80
I/O
11 1_0001
I/O 1
0HS3 short
to GND
HS2 short to
GND
SPI parity
error
CSB low
>2.0 ms VSUP/2-UV VSUP/1-OV I/O_O
thermal
watchdog
flash mode
50%
1I/O_1-3
Wake-up
I/O_0-2
Wake-up
SPI Wake-
up FWU INT service
Timeout
LP VDD
OFF
Reset
request
Hardware
Leave
Debug
Hexa SPI commands to get I/O Flags and I/O Wake-up: MOSI 0x E3 00, and MOSI 0x E3 80
00 1_0001
I/O 1 1 I/O_3
state
I/O_2
state I/O_1 state I/O_0 state
Hexa SPI commands to get I/O real time level: MOSI 0x 23 80
SAFE
11 1_0010
SAFE 1
0INT
request RST high DBG
resistor
VDD temp
Pre-warning VDD UV
VDD
Overvoltag
e
VAUX_overVO
LTAGE
-
1 - - - VDD low
>100 ms
VDD low
RST
RST low
>100 ms
multiple
Resets
watchdog
refresh
failure
Hexa SPI commands to get INT and RST Flags: MOSI 0x E5 00, and MOSI 0x E5 80
00 1_0010
SAFE 1 1 VDD (5.0 V
or 3.3 V)
device
p/n 1
device
p/n 0 id4 id3 id2 id1 id0
Hexa SPI commands to get device Identification: MOSI 0x 2580
example: MISO bit [7-0] = 1011 0100: MC33904, 5.0 V version, silicon Rev. C and D
LIN/1 11 1_0011
LIN 1 1 0 - LIN1
Wake-up
LIN1 Term
short to
GND
LIN 1
Overtemp RXD1 low RXD1 high TXD1 dom LIN1 bus
dom clamp
Hexa SPI commands to get LIN 2 Flags: MOSI 0x E7 00
00
1_0011
LIN 1 1 1 LIN1 State LIN1 WU
en/dis - - - - - -
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Hexa SPI commands to get LIN1 real time status: MOSI 0x 27 80
LIN2 11 1_0100
LIN 2 1 0 - LIN2
Wake-up
LIN2 Term
short to
GND
LIN 2
Overtemp RXD2 low RXD2 high TXD2 dom LIN2 bus
dom clamp
Hexa SPI commands to get LIN 2 Flags: MOSI 0x E9 00
00 1_0100
LIN 2 1 1 LIN2 State LIN2 WU
en/dis - - - - - -
Hexa SPI commands to get LIN2 real time status: MOSI 0x 29 80
Notes
52. Not available on ‘C’ and ‘D’ versions
Table 40. Flag descriptions
Flag Description
REG
VAUX_LOW
Description Reports that VAUX regulator output voltage is lower than the VAUX_UV threshold.
Set / Reset condition Set: VAUX below threshold for t >100 μs typically. Reset: VAUX above threshold and flag read (SPI)
VAUX_overCUR
RENT
Description Report that current out of VAUX regulator is above VAUX_OC threshold.
Set / Reset condition Set: Current above threshold for t >100 μs. Reset: Current below threshold and flag read by SPI.
5 V-CAN_
THERMAL
SHUTDOWN
Description Report that the 5 V-CAN regulator has reached overtemperature threshold.
Set / Reset condition Set: 5 V-CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read
(SPI)
5V-CAN_UV
Description Reports that 5 V-CAN regulator output voltage is lower than the 5 V-CAN UV threshold.
Set / Reset condition Set: 5V-CAN below 5V-CAN UV for t >100 μs typically. Reset: 5V-CAN > threshold and flag read (SPI)
5V-can_
overcurrent
Description Report that the CAN driver output current is above threshold.
Set / Reset condition Set: 5V-CAN current above threshold for t>100 μs. Reset: 5V-CAN current below threshold and flag
read (SPI)
VSENSE_
LOW
Description Reports that VSENSE pin is lower than the VSENSE LOW threshold.
Set / Reset condition Set: VSENSE below threshold for t >100 μs typically. Reset: VSENSE above threshold and flag read
(SPI)
VSUP_
UNDERVOLTAG
E
Description Reports that VSUP/1 pin is lower than the VS1_LOW threshold.
Set / Reset condition Set: VSUP/1 below threshold for t >100 μs typically. Reset: VSUP/1 above threshold and flag read (SPI)
IDD-OC-
NORMAL MODE
Description Report that current out of VDD pin is higher that IDD-OC threshold, while device is in Normal mode.
Set / Reset condition Set: current above threshold for t>100 μs typically. Reset; current below threshold and flag read (SPI)
VDD_
THERMAL
SHUTDOWN
Description Report that the VDD has reached overtemperature threshold, and was turned off.
Set / Reset condition Set: VDD OFF due to thermal condition. Reset: VDD recover and flag read (SPI)
RST_LOW
(<100 ms)
Description Report that the RST pin has detected a low level, shorter than 100 ms
Set / Reset condition Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI)
VSUP_
BATFAIL
Description Report that the device voltage at VSUP/1 pin was below BATFAIL threshold.
Set / Reset condition Set: VSUP/1 below BATFAIL. Reset: VSUP/1 above threshold, and flag read (SPI)
IDD-OC-LP
VDDON mode
Description Report that current out of VDD pin is higher that IDD-OC threshold LP, while device is in LP VDD ON
mode.
Set / Reset condition Set: current above threshold for t>100 μs typically. Reset; current below threshold and flag read (SPI)
Table 39. Device flag, I/O real time and device identification
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CAN
CAN driver
state
Description Report real time CAN bus driver state: 1 if Driver is enable, 0 if driver disable
Set / Reset condition
Set: CAN driver is enable. Reset: CAN driver is disable. Driver can be disable by SPI command (ex
CAN set in RXD only mode) or following a failure event (ex: TXD Dominant). Flag read SPI command
(0x2180) do not clear the flag, as it is “real time” information.
CAN receiver
state
Description Report real time CAN bus receiver state: 1 if Enable, 0 if disable
Set / Reset condition
Set: CAN bus receiver is enable. Reset: CAN bus receiver is disable. Receiver disable by SPI
command (ex: CAN set in sleep mode). Flag read SPI command (0x2180) do not clear the flag, as it
is “real time” information.
CAN WU
enable
Description Report real time CAN bus Wake-up receiver state: 1 if WU receiver is enable, 0 if disable
Set / Reset condition
Set: CAN Wake-up receiver is enable. Reset: CAN Wake-up receiver is disable. Wake-up receiver is
controlled by SPI, and is active by default after device Power ON. SPI command (0x2180) do not
change flag state.
CAN
Wake-up
Description Report that Wake-up source is CAN
Set / Reset condition Set: after CAN wake detected. Reset: Flag read (SPI)
CAN
Overtemp
Description Report that the CAN interface has reach overtemperature threshold.
Set / Reset condition Set: CAN thermal sensor above threshold. Reset: thermal sensor below threshold and flag read (SPI)
RXD low(53) Description Report that RXD pin is shorted to GND.
Set / Reset condition Set: RXD low failure detected. Reset: failure recovered and flag read (SPI)
Rxd high Description Report that RXD pin is shorted to recessive voltage.
Set / Reset condition Set: RXD high failure detected. Reset: failure recovered and flag read (SPI)
TXD dom Description Report that TXD pin is shorted to GND.
Set / Reset condition Set: TXD low failure detected. Reset: failure recovered and flag read (SPI)
Bus Dom
clamp
Description Report that the CAN bus is dominant for a time longer than tDOM
Set / Reset condition Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI)
CAN
Overcurrent
Description Report that the CAN current is above CAN overcurrent threshold.
Set / Reset condition Set: CAN current above threshold. Reset: current below threshold and flag read (SPI)
CAN_UF Description Report that the CAN failure detection has not yet identified the bus failure
Set / Reset condition Set: bus failure pre detection. Reset: CAN bus failure recovered and flag read
CAN_F Description Report that the CAN failure detection has identified the bus failure
Set / Reset condition Set: bus failure complete detetction.Reset: CAN bus failure recovered and flag read
CANL
to VBAT
Description Report CAN L short to VBAT failure
Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI)
CANL to VDD Description Report CANL short to VDD
Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI)
CANL to GND Description Report CAN L short to GND failure
Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI)
CANH
to VBAT
Description Report CAN H short to VBAT failure
Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI)
CANH to VDD Description Report CANH short to VDD
Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI)
CANH to
GND
Description Report CAN H short to GND failure
Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI)
Notes
53. Not available on ‘C’ and ‘D’ versions
Table 40. Flag descriptions
Flag Description
88 NXP Semiconductors
33903/4/5
SERIAL PERIPHERAL INTERFACE
I/O
HS3 short to
GND
Description Report I/O-3 HS switch short to GND failure
Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI)
HS2 short to
GND
Description Report I/O-2 HS switch short to GND failure
Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI)
SPI parity
error
Description Report SPI parity error was detected.
Set / Reset condition Set: failure detected. Reset: flag read (SPI)
CSB low
>2.0 ms
Description Report SPI CSB was low for a time longer than typically 2.0 ms
Set / Reset condition Set: failure detected. Reset: flag read (SPI)
VSUP/2-UV
Description Report that VSUP/2 is below VS2_LOW threshold.
Set / Reset condition Set VSUP/2 below VS2_LOW thresh. Reset VSUP/2 > VS2_LOW thresh and flag read (SPI)
VSUP/1-OV
Description Report that VSUP/1 is above VS_HIGH threshold.
Set / Reset condition Set VSUP/1 above VS_HIGH threshold. Reset VSUP/1 < VS_HIGH thresh and flag read (SPI)
I/O-0 thermal
Description Report that the I/O-0 HS switch has reach overtemperature threshold.
Set / Reset condition Set: I/O-0 HS switch thermal sensor above threshold. Reset: thermal sensor below threshold and flag
read (SPI)
watchdog
flash mode
50%
Description Report that the watchdog period has reach 50% of its value, while device is in Flash mode.
Set / Reset condition Set: watchdog period > 50%. Reset: flag read
I/O-1-3 Wake-
up
Description Report that Wake-up source is I/O-1 or I/O-3
Set / Reset condition Set: after I/O-1 or I/O-3 wake detected. Reset: Flag read (SPI)
I/O-0-2 Wake-
up
Description Report that Wake-up source is I/O-0 or I/O-2
Set / Reset condition Set: after I/O-0 or I/O-2 wake detected. Reset: Flag read (SPI)
SPI Wake-up Description Report that Wake-up source is SPI command, in LP VDD ON mode.
Set / Reset condition Set: after SPI Wake-up detected. Reset: Flag read (SPI)
FWU Description Report that Wake-up source is forced Wake-up
Set / Reset condition Set: after Forced Wake-up detected. Reset: Flag read (SPI)
INT service
Timeout
Description Report that INT timeout error detected.
Set / Reset condition Set: INT service timeout expired. Reset: flag read.
LP VDD OFF Description Report that LP VDD OFF mode was selected, prior Wake-up occurred.
Set / Reset condition Set: LP VDD OFF selected. Reset: Flag read (SPI)
Reset request Description Report that RST source is an request from a SPI command (go to RST mode).
Set / Reset condition Set: After reset occurred due to SPI request. Reset: flag read (SPI)
Hardware
Leave Debug
Description Report that the device left the Debug mode due to hardware cause (voltage at DBG pin lower than
typically 8.0 V).
Set / Reset condition Set: device leave debug mode due to hardware cause. Reset: flag read.
Table 40. Flag descriptions
Flag Description
NXP Semiconductors 89
33903/4/5
SERIAL PERIPHERAL INTERFACE
INT
INT request Description Report that INT source is an INT request from a SPI command.
Set / Reset condition Set: INT occurred. Reset: flag read (SPI)
RST high Description Report that RST pin is shorted to high voltage.
Set / Reset condition Set: RST failure detection. Reset: flag read.
DBG resistor Description Report that the resistor at DBG pin is different from expected (different from SPI register content).
Set / Reset condition Set: failure detected. Reset: correct resistor and flag read (SPI).
VDD TEMP PRE-
WARNING
Description Report that the VDD has reached overtemperature pre-warning threshold.
Set / Reset condition Set: VDD thermal sensor above threshold. Reset: VDD thermal sensor below threshold and flag read
(SPI)
VDD UV
Description Reports that VDD pin is lower than the VDDUV threshold.
Set / Reset condition Set: VDD below threshold for t >100 μs typically. Reset: VDD above threshold and flag read (SPI)
VDD
overVOLTAGE
Description Reports that VDD pin is higher than the typically VDD + 0.6 V threshold. I/O-1 can be turned OFF if
this function is selected in INIT register.
Set / Reset condition Set: VDD above threshold for t >100 μs typically. Reset: VDD below threshold and flag read (SPI)
VAUX_overVOL
TAGE
Description Reports that VAUX pin is higher than the typically VAUX + 0.6 V threshold. I/O-1 can be turned OFF if
this function is selected in INIT register.
Set / Reset condition Set: VAUX above threshold for t >100 μs typically. Reset: VAUX below threshold and flag read (SPI)
VDD LOW
>100 ms
Description Reports that VDD pin is lower than the VDDUV threshold for a time longer than 100 ms
Set / Reset condition Set: VDD below threshold for t >100 ms typically. Reset: VDD above threshold and flag read (SPI)
VDD LOW
Description Report that VDD is below VDD undervoltage threshold.
Set / Reset condition Set: VDD below threshold. Reset: fag read (SPI)
VDD (5.0 V or
3.3 V)
Description 0: mean 3.3 V VDD version
1: mean 5.0 V VDD version
Set / Reset condition N/A
Device P/N1
and 0
Description
Describe the device part number:
00: MC33903
01: MC33904
10: MC33905S
11: MC333905D
Set / Reset condition N/A
Device id 4 to
0
Description
Describe the silicon revision number
10010: silicon revision A (Pass 3.1)
10011: silicon revision B (Pass 3.2)
10100: silicon revision C and D
Set / Reset condition N/A
RST low
>100 ms
Description Report that the RST pin has detected a low level, longer than 100 ms (Reset permanent low)
Set / Reset condition Set: after detection of reset low pulse. Reset: Reset pulse terminated and flag read (SPI)
Multiple
Resets
Description Report that the more than 8 consecutive reset pulses occurred, due to missing or wrong watchdog
refresh.
Set / Reset condition Set: after detection of multiple reset pulses. Reset: flag read (SPI)
watchdog
refresh failure
Description Report that a wrong or missing watchdog failure occurred.
Set / Reset condition Set: failure detected. reset: flag read (SPI)
Table 40. Flag descriptions
Flag Description
90 NXP Semiconductors
33903/4/5
SERIAL PERIPHERAL INTERFACE
10.4.2 Fix and extended device status
For every SPI command, the device response on MISO is fixed status information. This information is either:
Two Bytes
Fix Status + Extended Status: when a device write command is used (MOSI bits 15-14, bits C1 C0 = 01)
One Byte
Fix Status: when a device read operation is performed (MOSI bits 15-14, bits C1 C0 = 00 or 11).
LIN/1/2
LIN/1/2 bus
dom clamp
Description Report that the LIN/1/2 bus is dominant for a time longer than tDOM
Set / Reset condition Set: Bus dominant clamp failure detected. Reset: failure recovered and flag read (SPI)
LIN/1/2 State
Description Report real time LIN interface TXD/RXD mode. 1 if LIN is in TXD/RXD mode. 0 is LIN is not in TXD/
RXD mode.
Set / Reset condition
Set: LIN in TXD RXD mode. Reset: LIN not in TXD/RXD mode. LIN not in TXD/RXD mode by SPI
command (ex LIN set in Sleep mode) or following a failure event (ex: TxL Dominant). Flag read SPI
command (0x2780 or 0x2980) do not clear it, as it is ‘real time’ flag.
LIN/1/2 WU
Description Report real time LIN Wake-up receiver state. 1 if LIN Wake-up is enable, 0 if LIN Wake-up is disable
(means LIN signal will not be detected and will not Wake-up the device).
Set / Reset condition
Set: LIN WU enable (LIN interface set in Sleep mode Wake-up enable). Reset: LIN Wake-up disable
(LIN interface set in Sleep mode Wake-up disable). Flag read SPI command (0x2780 or 0x2980) do
not clear the flag, as it is ‘real time’ information.
LIN/1/2
Wake-up
Description Report that Wake-up source is LIN/1/2
Set / Reset condition Set: after LIN/1/2 wake detected. Reset: Flag read (SPI)
LIN/1/2 Term
short to GND
Description Report LIN/1/2 short to GND failure
Set / Reset condition Set: failure detected. Reset failure recovered and flag read (SPI)
LIN/1/2
overtemp
Description Report that the LIN/1/2 interface has reach overtemperature threshold.
Set / Reset condition Set: LIN/1/2 thermal sensor above threshold. Reset: sensor below threshold and flag read (SPI)
RXD-L/1/2
low
Description Report that RXD/1/2 pin is shorted to GND.
Set / Reset condition Set: RXD low failure detected. Reset: failure recovered and flag read (SPI)
RXD-L/1/2
high
Description Report that RXD/1/2pin is shorted to recessive voltage.
Set / Reset condition Set: RXD high failure detected. Reset: failure recovered and flag read (SPI)
TXD-L/1/2
dom
Description Report that TXD/1/2 pin is shorted to GND.
Set / Reset condition Set: TXD low failure detected. Reset: failure recovered and flag read (SPI)
Table 41. Status bits description
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MISO INT WU RST CAN-
GLIN-G I/O-G SAFE-
G
VREG-
G
CAN-
BUS
CAN-
LOC LIN2 LIN1 I/O-1 I/O-0 VREG-
1VREG-0
Bits Description
INT Indicates that an INT has occurred and that INT flags are pending to be read.
WU Indicates that a Wake-up has occurred and that Wake-up flags are pending to be read.
RST Indicates that a reset has occurred and that the flags that report the reset source are pending to be read.
CAN-G The INT, WU, or RST source is CAN interface. CAN local or CAN bus source.
LIN-G The INT, WU, or RST source is LIN2 or LIN1 interface
I/O-G The INT, WU, or RST source is I/O interfaces.
SAFE-G The INT, WU, or RST source is from a SAFE condition
VREG-G The INT, WU, or RST source is from a Regulator event, or voltage monitoring event
CAN-LOC The INT, WU, or RST source is CAN interface. CAN local source.
CAN-BUS The INT, WU, or RST source is CAN interface. CAN bus source.
Table 40. Flag descriptions
Flag Description
NXP Semiconductors 91
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SERIAL PERIPHERAL INTERFACE
LIN2 The INT, WU, or RST source is LIN2 interface
LIN/LIN1 The INT, WU, or RST source is LIN1 interface
I/O-0 The INT, WU, or RST source is I/O interface, flag from I/O sub adress Low (bit 7 = 0)
I/O-1 The INT, WU, or RST source is I/O interface, flag from I/O sub adress High (bit 7 = 1)
VREG-1 The INT, WU, or RST source is from a Regulator event, flag from REG register sub adress high (bit 7 = 1)
VREG-0 The INT, WU, or RST source is from a Regulator event, flag from REG register sub adress low (bit 7 = 0)
Bits Description
92 NXP Semiconductors
33903/4/5
TYPICAL APPLICATIONS
11 Typical applications
Figure 42. 33905D typical application schematic
CS
SCLK
MOSI
INT
5V-CAN
MISO
RXD
TXD
GND
RST
V
DD
V
SUP2
I/O-1
CANL
CANH
SPLIT
I/O-0
VE
MCU
V
BAT
Q1
D1
Safe Circuitry
V
BAT
CAN BUS
V
BAUX
V
AUX
SAFE
MUX A/D
SPI
CAN
V
SENSE
V
SUP1
Q2
V
CAUX
V
SUP
V
SUP
V
SUP
V
SUP
V
DD
INT
RST
RF module
Switch Detection Interface
CAN xcvr
Safing Micro Controller
5.0 V (3.3 V)
DBG
V
B
eSwitch
RXD-L1
TXD-L1
LIN1
RXD-L2
TXD-L2
LIN2
1.0 k
22 k
100 nF
100 nF
100 nF
22
μ
F
>4.7
μ
F
>2.2
μ
F
4.7 nF
<10 k
4.7 k *
60
60
* Optional
*
Notes
54.
Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10
μF
on VSUP1/VSUP2 pins
(54)
LIN1
LIN TERM1
LIN BUS 1
1.0 k
1.0 k
VSUP1/2
option 1 option 2
LIN2
LIN TERM2
LIN BUS 1
1.0 k
1.0 k
VSUP1/2
option 1 option 2
>1.0
μ
F
N/C
NXP Semiconductors 93
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TYPICAL APPLICATIONS
Figure 43. 33905S typical application schematic
CS
SCLK
MOSI
INT
5V-CAN
MISO
RXD
TXD
GND
RST
VDD
VSUP2
I/O-1
CANL
CANH
SPLIT
I/O-0
VE
MCU
V
BAT
Q1*
D1
Safe Circuitry
V
BAT
CAN BUS
VBAUX VAUX
SAFE
MUX A/D
SPI
CAN
VSENSE
VSUP1
Q2
VCAUX
V
SUP
V
SUP
V
SUP
V
SUP
VDD
INT
RST
RF module
Switch Detection Interface
CAN xcvr
Safing Micro Controller
5.0 V (3.3 V)
DBG
VB
eSwitch
RXD-L1
TXD-L1
LIN1
I/O-3
V
SUP
1.0 k
22 k
100 nF
100 nF
100 nF
22 μF
>1.0 μF
>4.7 μF
>2.2 μF
4.7 nF
<10 k
4.7 k *
60
60
(55)
Notes
55.
Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10
μF
on VSUP1/VSUP2 pins
LIN1
LIN TERM1
LIN BUS 1
1.0 k
1.0 k
VSUP1/2
option 1 option 2
94 NXP Semiconductors
33903/4/5
TYPICAL APPLICATIONS
Figure 44. 33904 typical application schematic
CS
SCLK
MOSI
INT
5V-CAN
MISO
RXD
TXD
GND
RST
VDD
VSUP2
I/O-1
CANL
CANH
DBG
SPLIT
I/O-0
VE
VB
MCU
V
BAT
Q1*
D1
Safe Circuitry
V
BAT
CAN BUS
VBAUX VAUX
SAFE
MUX A/D
SPI
CAN
VSENSE
VSUP1
Q2
VCAUX
V
SUP
V
SUP
OR
V
SUP
V
SUP
VDD
INT
RST
RF module
Switch Detection Interface
CAN xcvr
function
eSwitch
Safing Micro Controller
5V (3.3 V)
I/O-3
I/O-2
V
SUP
V
BAT
1.0 k
22 k
100 nF
100nF
100 nF
22 μF
>4.7 μF
>2.2 μF
4.7 nF
<10 k
4.7 k *
60
60
100 nF
* Optional
22 k
(56)
Notes
56.
Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10
μF
on VSUP1/VSUP2 pins
>1.0 μF
N/C
NXP Semiconductors 95
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TYPICAL APPLICATIONS
Figure 45. 33903 typical application schematic
CS
SCLK
MOSI
INT
5V-CAN
MISO
RXD
TXD
GND
RST
VDD
CANL
CANH
DBG
SPLIT
I/O-0
MCU
Safe Circuitry
V
BAT
CAN BUS
SAFE
SPI
CAN
OR
V
SUP
V
SUP
VDD
INT
RST
function
22 k 100 nF
>1.0 μF
>4.7 μF
4.7 nF
60
60
(57)
Notes
57.
Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10
μF
on VSUP1/VSUP2 pins
VSUP1
V
BAT
D1
V
SUP
100 nF
22 μFVSUP2
N/C
96 NXP Semiconductors
33903/4/5
TYPICAL APPLICATIONS
Figure 46. 33903D typical application schematic
CS
SCLK
MOSI
INT
5V-CAN
MISO
RXD
TXD
GND
RST
VDD
VSUP
CANL
CANH
SPLIT
IO-0
VE
MCU
V
BAT
Q1
D1
Safe Circuitry
V
BAT
CAN BUS
SAFE
MUX A/D
SPI
CAN
VSENSE
V
SUP
V
SUP
V
SUP
VDD
INT
RST
DBG
VB
RXD-L1
TXD-L1
LIN1
RXD-L2
TXD-L2
LIN2
LIN BUS 1 LIN1
LIN-T1
1.0 k
1.0 k
22 k
100 nF
100 nF
100 nF
22 μF
>1.0 μF>4.7 μF
4.7 nF
4.7 k (optional)
60
60
* = Optional
*
1.0 k
option1 option2
LIN BUS 2 LIN2
LIN-T2
1.0 k
1.0 k
option1 option2
VSUP
VSUP
Notes
58.
Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10
μF
on VSUP pin
NXP Semiconductors 97
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TYPICAL APPLICATIONS
Figure 47. 33903S typical application schematic
CS
SCLK
MOSI
INT
5V-CAN
MISO
RXD
TXD
GND
RST
VDD
VSUP
CANL
CANH
SPLIT
VE
MCU
V
BAT
Q1
D1
Safe Circuitry
V
BAT
CAN BUS
SAFE
MUX A/D
SPI
CAN
VSENSE
V
SUP
V
SUP
V
SUP
VDD
INT
RST
DBG
VB
RXD-L
TXD-L
LIN
LIN BUS LIN
LIN-T
1.0 k
1.0 k
22 k
100 nF
100 nF
100 nF
22 μF
>1.0 μF>4.7 μF
4.7 nF
4.7 k (optional)
60
60
* = Optional
*
1.0 k
option1 option2
VSUP
Notes
59.
Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10
μF
on VSUP pin
60. Leave N/C pins open.
IO-3
V
SUP
IO-0
N/C
98 NXP Semiconductors
33903/4/5
TYPICAL APPLICATIONS
Figure 48. 33903P typical application schematic
CS
SCLK
MOSI
INT
5V-CAN
MISO
RXD
TXD
GND
RST
VDD
VSUP
CANL
CANH
SPLIT
VE
MCU
V
BAT
Q1
D1
Safe Circuitry
V
BAT
CAN BUS
SAFE
MUX A/D
SPI
CAN
VSENSE
V
SUP
V
SUP
V
SUP
VDD
INT
RST
DBG
VB
1.0 k
22 k
100 nF
100 nF
100 nF
22 μF
>1.0 μF>4.7 μF
4.7 nF
4.7 k (optional)
60
60
* = Optional
*
Notes
61.
Tested per specific OEM EMC requirements for CAN and LIN with additional
capacitor > 10
μF
on VSUP pin
62. Leave N/C pins open.
IO-3
V
SUP
IO-0
N/C
I/O-2
V
BAT
100 nF
22 k
NXP Semiconductors 99
33903/4/5
TYPICAL APPLICATIONS
The following figure illustrates the application case where two reverse battery diodes can be used for optimization of the filtering and
buffering capacitor at the VDD pin. This allows using a minimum value capacitor at the VDD pin to guarantee reset-free operation of the
MCU during the cranking pulse and temporary (50 ms) loss of the VBAT supply.
Applications without an external ballast on VDD and without using the VAUX regulator are illustrated as well.
Figure 49. Application options
ex2: Split V
SUP
Supply
ex 4: No External Transistor - No VAUX
ex 3: No External Transistor, V
DD
~100 mA Capability
ex1: Single V
SUP
Supply
Optimized solution for cranking pulses.
C1 is sized for MCU power supply buffer only.
VDD
VSUP2 VE
VB
V
BAT
Q1
D1
VBAUX VAUX
5.0 V/3.3 V
VSUP1
Q2
Partial View
VDD
VE
VB
V
BAT
D1
VBAUX
VDD
VE
VB
V
BAT
D1
VDD
VE
VB
V
BAT
Q1
D2
VSUP2
VSUP1
VSUP2
VSUP1
VSUP2
VSUP1
D1
C1
C2
VCAUX
Q2
VAUX
VCAUX
Q2
VBAUX VAUXVCAUX
VBAUX VAUXVCAUX
Partial View
Partial View
Partial View
5.0 V/3.3 V
5.0 V/3.3 V
delivered by internal path transistor.
NXP Semiconductors 101
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PACKAGING
102 NXP Semiconductors
33903/4/5
PACKAGING
NXP Semiconductors 103
33903/4/5
PACKAGING
12.2 SOIC 54 package dimensions
104 NXP Semiconductors
33903/4/5
PACKAGING
NXP Semiconductors 105
33903/4/5
PACKAGING
106 NXP Semiconductors
33903/4/5
REVISION HISTORY
13 Revision history
Revision Date Description of changes
4.0 9/2010
• Initial Release - This document supersedes document MC33904_5.
• Initial release of document includes the MC33903 part number, the VDD 3.3 V version description, and the silicon revision
rev. 3.2. Change details available upon request.
5.0 12/2010
• Added 7.9. Cyclic INT operation during LP VDD on mode 47
• Changed VSUP pin to VSUP1 and pin 2 (NC) to VSUP2 for the 33903 device
• Removed . Drop voltage without external PNP pass transistor 19 for VDD=3.3 V devices
• Added VSUP1-3.3 to . VDD Voltage regulator, VDD pin 19.
• Added . Pull-up Current, TXD, VIN = 0 V 23 for VDD=3.3 V devices
• Revised 10.3.1. MUX and RAM registers 68
• Revised 41. Status bits description 90
• Added 10.3.5.2. Entering into LP mode using random code 77.
6.0 4/2011
• Removed part numbers MCZ33905S3EK/R2, MCZ33904A3EK/R2 and MCZ33905D3EK/R2, and added part numbers
MCZ33903BD3EK/R2, MCZ33903BD5EK/R2, MCZ33903BS3EK/R2 and MCZ33903BS5EK/R2.
• Voltage Supply was improved from 27V to 28V.
• Changed Classification from Advance Information to Technical Data.
• Updated Notes in Tables 8.
• Revised Tables 8; Attenuation/Gain ratio for I/O-0 and I/O-1 actual voltage: to reflect a Typical value.
• Corrected typographical errors throughout.
• Added Chip temperature: MUX-OUT voltage (guaranteed by design and characterization) parameter to Tables 8.
• Updated I/O pins (I/O-0: I/O-3) on page 33.
7.0 9/2011
• Updated VOUT-5.0-EMC maximum
• Updated tLEAD parameter
• Added tCSLOW parameter
• Updated the Detail operation section to reflect the importance of acknowledging tLEAD and tCSLOW.
• Corrected typographical error in Tables 34 CAN REGISTER for Slew Rate bits b5,b4
8.0 1/2011
• Added 12 PCZ devices to the ordering information
• Bit label change on Table 39 from INT to SAFE
• Revised notes on Table 1 to include “C” version
•Split Falling Edge of CS to Rising Edge of SCLK to differentiate the “C” version
• Added “C” version note to Table 39 and Table 40
• Added device ID 10100 Rev C, Pass 3.3 to Device id 4 to 0
• Added Debug mode DBG voltage range parameter. Already detailed in text.
• Added the MC33903P device, making additions throughout the document, where applicable.
9.0
2/2012 • Changed all PC devices to MC devices.
4/2013 • No technical changes. Revised back page. Updated document properties. Added SMARTMOS sentence to first
paragraph.
10.0 2/2014
• Added package type in Table 1.
• Added new parameter to Output Voltage on page 19 for VDD
• Added (22)
• Updated section 7.5.2.2. Watchdog in debug mode 40. Replaced “set” by “left”.
11.0 8/2014
• Changed tCS-TO in the Dynamic electrical characteristics from 2.5 to 2.0
• Note added to MUX-output (MUXOUT) on page 33 of Functional pin description
• Added a paragraph in the SPI Detail operation section for the maximum tLEAD time in case the ‘CSB low’ flag is set
• Added maximum tLEAD time in case the ‘CSB low’ flag is set to 1 in the Dynamic electrical characteristics table
12.0 8/2016
• Updated as per CIN 201608012I
• Added ‘D’ version orderable part numbers to Table 1, Table 2, and Table 3
• Updated note (2), (5), (9)
• Added note (3), (6), (10) (‘C’ versions are no longer recommended for new design) to Table 1, Table 2, and Table 3
• Added reference to ‘D’ version in the document where applicable
• Updated flag description for device id 4 to 0 in Table 40
• Updated to NXP document format and style
13.0 5/2017
• Updated Figure 29 to include 3.3 V information
• Updated workflow step 3 in Figure 30 (SPI commands: changed 0xDD00 to 0x1D80)
• Updated bit 1 description in Table 32
14.0 2/2018
• Updated note (7) (deleted “Output current limited to 100 mA”)
• Updated values for VRST-VTH in Table 6 as per CIN 201712019I
• Removed typ. and max. values for VRST-VTH (Low threshold, VDD = 5.0 V)
• Removed min. and typ. values for VRST-VTH (High threshold, VDD = 5.0 V)
• Removed typ. and max. values for VRST-VTH (Low threshold, VDD = 3.3 V)
• Removed min. and typ. values for VRST-VTH (High threshold, VDD = 3.3 V)
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Document Number: MC33903_4_5
Rev. 14.0
2/2018
