SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258I – DECEMBER 1995 – REVISED JANUAR Y 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Operating Range 2-V to 5.5-V VCC
D
Designed Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems
D
Incorporate Three Enable Inputs to Simplify
Cascading and/or Data Reception
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-833, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) DIPs
description
The ’AHC138 decoders/demultiplexers are
designed for high-performance memory-decoding
and data-routing applications that require very
short propagation-delay times. In
high-performance memory systems, these
decoders can be used to minimize the effects of
system decoding. When employed with
high-speed memories utilizing a fast enable
circuit, the delay times of these decoders and the
enable time of the memory are usually less than
the typical access time of the memory. This means
that the effective system delay introduced by the
decoders is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.
The SN54AHC138 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AHC138 is characterized for operation from –40°C to 85°C.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
3212019
910111213
4
5
6
7
8
18
17
16
15
14
Y1
Y2
NC
Y3
Y4
C
G2A
NC
G2B
G1
B
A
NC
Y6
Y5 V
Y0
Y7
GND
NC
SN54AHC138 . . . FK PACKAGE
(TOP VIEW)
CC
NC – No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
B
C
G2A
G2B
G1
Y7
GND
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
SN54AHC138 ...J OR W PACKAGE
SN74AHC138 . . . D, DB, DGV, N, OR PW PACKAGE
(TOP VIEW)
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258I – DECEMBER 1995 – REVISED JANUAR Y 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
ENABLE INPUTS SELECT INPUTS OUTPUTS
G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H X X X X H H H H H H H H
XXHXXXHHHHHHHH
LXXXXXHHHHHHHH
HLLLLLLHHHHHHH
HLLLLHHLHHHHHH
HLLLHLHHLHHHHH
HLLLHHHHHLHHHH
HLLHLLHHHHLHHH
HLLHLHHHHHHLHH
HLLHHLHHHHHHLH
H L L H H H H H H H H H H L
logic symbols (alternatives)†
BIN/OCT
1
1
A
2
2
B
4
3
C
4
5
6
G1
Y0
15
0
&
EN
Y1
14
1
Y2
13
2
Y3
12
3
Y4
11
4
Y5
10
5
Y6
9
6
Y7
7
7
DMUX
0
1
A2
B
2
3
C
4
5
6
G1
Y0
15
0
&
Y1
14
1
Y2
13
2
Y3
12
3
Y4
11
4
Y5
10
5
Y6
9
6
Y7
7
7
G7
0
G2A
G2B
G2A
G2B
†These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258I – DECEMBER 1995 – REVISED JANUAR Y 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
G1
G2B
G2A
C
B
A
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Data
Outputs
Select
Inputs
Enable
Inputs
1
2
3
4
5
6
15
14
13
12
11
10
9
7
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258I – DECEMBER 1995 – REVISED JANUAR Y 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54AHC138 SN74AHC138
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 2 5.5 2 5.5 V
VCC = 2 V 1.5 1.5
VIH High-level input voltage VCC = 3 V 2.1 2.1 V
VCC = 5.5 V 3.85 3.85
VCC = 2 V 0.5 0.5
VIL Low-level input voltage VCC = 3 V 0.9 0.9 V
VCC = 5.5 V 1.65 1.65
VIInput voltage 0 5.5 0 5.5 V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V –50 –50
m
A
IOH High-level output current VCC = 3.3 V ± 0.3 V –4 –4
mA
VCC = 5 V ±0.5 V –8 –8
mA
VCC = 2 V 50 50
m
A
IOL Low-level output current VCC = 3.3 V ±0.3 V 4 4
mA
VCC = 5 V ±0.5 V 8 8
mA
∆t/∆v
In
p
ut transition rise or fall rate
VCC = 3.3 V ± 0.3 V 100 100
ns/V
∆t/∆
v
Inp
u
t
transition
rise
or
fall
rate
VCC = 5 V ±0.5 V 20 20
ns/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54AHC138 SN74AHC138
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 2 1.9 1.9
IOH = –50
m
A3 V 2.9 3 2.9 2.9
VOH 4.5 V 4.4 4.5 4.4 4.4 V
OH
IOH = –4 mA 3 V 2.58 2.48 2.48
IOH = –8 mA 4.5 V 3.94 3.8 3.8
2 V 0.1 0.1 0.1
IOL = 50
m
A3 V 0.1 0.1 0.1
VOL 4.5 V 0.1 0.1 0.1 V
OL
IOL = 4 mA 3 V 0.36 0.5 0.44
IOL = 8 mA 4.5 V 0.36 0.5 0.44
IIVI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1
m
A
ICC VI = VCC or GND, IO = 0 5.5 V 4 40 40
m
A
CiVI = VCC or GND 5 V 2 10 10 pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258I – DECEMBER 1995 – REVISED JANUAR Y 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ±0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C SN54AHC138 SN74AHC138
UNIT
PARAMETER
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
UNIT
tPLH
ABC
Any Y
CL=15
p
F
8.2* 11.4* 1* 13* 1 13
ns
tPHL
A
,
B
,
C
An
y
Y
C
L =
15
pF
8.2* 11.4* 1* 13* 1 13
ns
tPLH
G1
Any Y
CL=15
p
F
8.1* 12.8* 1* 15* 1 15
ns
tPHL
G1
An
y
Y
C
L =
15
pF
8.1* 12.8* 1* 15* 1 15
ns
tPLH
G2A G2B
Any Y
CL=15
p
F
8.2* 11.4* 1* 13.5* 1 13.5
ns
tPHL
G2A
,
G2B
An
y
Y
C
L =
15
pF
8.2* 11.4* 1* 13.5* 1 13.5
ns
tPLH
ABC
Any Y
CL=50
p
F
10 15.8 1 18 1 18
ns
tPHL
A
,
B
,
C
An
y
Y
C
L =
50
pF
10 15.8 1 18 1 18
ns
tPLH
G1
Any Y
CL=50
p
F
10.6 16.3 1 18.5 1 18.5
ns
tPHL
G1
An
y
Y
C
L =
50
pF
10.6 16.3 1 18.5 1 18.5
ns
tPLH
G2A G2B
Any Y
CL=50
p
F
10.7 14.9 1 17 1 17
ns
tPHL
G2A
,
G2B
An
y
Y
C
L =
50
pF
10.7 14.9 1 17 1 17
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C SN54AHC138 SN74AHC138
UNIT
PARAMETER
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
UNIT
tPLH
ABC
Any Y
CL=15
p
F
5.7* 8.1* 1* 9.5* 1 9.5
ns
tPHL
A
,
B
,
C
An
y
Y
C
L =
15
pF
5.7* 8.1* 1* 9.5* 1 9.5
ns
tPLH
G1
Any Y
CL=15
p
F
5.6* 8.1* 1* 9.5* 1 9.5
ns
tPHL
G1
An
y
Y
C
L =
15
pF
5.6* 8.1* 1* 9.5* 1 9.5
ns
tPLH
G2A G2B
Any Y
CL=15
p
F
5.8* 8.1* 1* 9.5* 1 9.5
ns
tPHL
G2A
,
G2B
An
y
Y
C
L =
15
pF
5.8* 8.1* 1* 9.5* 1 9.5
ns
tPLH
ABC
Any Y
CL=50
p
F
7.2 10.1 1 11.5 1 11.5
ns
tPHL
A
,
B
,
C
An
y
Y
C
L =
50
pF
7.2 10.1 1 11.5 1 11.5
ns
tPLH
G1
Any Y
CL=50
p
F
7.1 10.1 1 11.5 1 11.5
ns
tPHL
G1
An
y
Y
C
L =
50
pF
7.1 10.1 1 11.5 1 11.5
ns
tPLH
G2A G2B
Any Y
CL=50
p
F
7.3 10.1 1 11.5 1 11.5
ns
tPHL
G2A
,
G2B
An
y
Y
C
L =
50
pF
7.3 10.1 1 11.5 1 11.5
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 13 pF
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258I – DECEMBER 1995 – REVISED JANUAR Y 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
W aveform 1
S1 at VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC VOL + 0.3 V
50% VCC ≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST S1
VCC
0 V
50% VCC
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
From Output
Under Test CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1 VCC
RL = 1 kΩGND
From Output
Under Test CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% VCC
50% VCC 50% VCC
50% VCC
50% VCC 50% VCC
50% VCC 50% VCC
VOH – 0.3 V
Figure 1. Load Circuit and Voltage Waveforms
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258I – DECEMBER 1995 – REVISED JANUAR Y 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
BIN/OCT
1
1
A0
2
2
A1
4
3
A3
4
5
6
0
15
0
&
EN
1
14
1
2
13
2
3
12
3
4
11
4
5
10
5
6
9
6
7
7
7
SN74AHC138
VCC
BIN/OCT
1
1
2
2
4
3
4
5
6
8
15
0
&
EN
9
14
1
10
13
2
11
12
3
12
11
4
13
10
5
14
9
6
15
7
7
SN74AHC138
BIN/OCT
1
1
2
2
4
3
4
5
6
16
15
0
&
EN
17
14
1
18
13
2
19
12
3
20
11
4
21
10
5
22
9
6
23
7
7
SN74AHC138
A2
A4
Figure 2. 24-Bit Decoding Scheme
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258I – DECEMBER 1995 – REVISED JANUAR Y 2000
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
VCC
BIN/OCT
1
1
A0
2
2
A1
4
3
A3 4
5
6
0
15
0
&
EN
1
14
1
2
13
2
3
12
3
4
11
4
5
10
5
6
9
6
7
7
7
SN74AHC138
A2
A4
BIN/OCT
1
1
2
2
4
3
4
5
6
8
15
0
&
EN
9
14
1
10
13
2
11
12
3
12
11
4
13
10
5
14
9
6
15
7
7
SN74AHC138
BIN/OCT
1
1
2
2
4
3
4
5
6
16
15
0
&
EN
17
14
1
18
13
2
19
12
3
20
11
4
21
10
5
22
9
6
23
7
7
SN74AHC138
BIN/OCT
1
1
2
2
4
3
4
5
6
24
15
0
&
EN
25
14
1
26
13
2
27
12
3
28
11
4
29
10
5
30
9
6
31
7
7
SN74AHC138
Figure 3. 32-Bit Decoding Scheme
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 2000, Texas Instruments Incorporated
