● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
HV300
Features
PWRGD = Active HIGH
-10V to -90V input voltage range
Few external components
0.33mA typical standby supply current
Programmable over/under voltage limits with
hysteresis
Programmable current limit
Active control during all phases of start-up
Programmable timing
8-Lead SOIC package
Applications
Central office switching
Servers
POTS line cards
ISDN line cards
xDSL line cards
PBX Systems
Powered Ethernet for VoIP
Distributed power systems
Negative power supply control
Antenna and fixed wireless systems
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General Description
The Supertex HV300, Hotswap Controller, Negative Supply controls the power
supply connection during insertion of cards or modules into live backplanes.
It may be used in traditional ‘negative 48V’ powered systems or for higher
voltage busses up to negative 90V.
Operation during the initial power up prevents turn-on glitches, and after
complete charging of load capacitors (typically found in filters at the input
of DC-DC converters) the HV300 issues a power good signal. This signal is
typically used to enable the DC-DC converter. Once a PWRGD signal has
been established, the device sleeps in a low power state, important for large
systems with many individual hotswap cards or modules.
An external power MOSFET is required as the pass element, plus a ramp
capacitor, and resistors to establish current limiting and over and under voltage
lockouts. There is no need for additional external snubber components.
Features are programmable over voltage and under voltage detection of the
input voltage which locks out the load connection if the bus (input) voltage
is out of range. An internal voltage regulator creates a stable reference,
and maintains accurate gate drive voltage. The unique control loop scheme
provides full current control and limiting during start up.
Theory of Operation
Initially the external N-channel MOSFET is held off by the gate signal,
preventing an input glitch. After a delay (while internal circuits are activated)
the inrush current to the load is limited by the gate control output. The current
may ramp up and limit at a maximum value programmed by an external
resistor. Initial time delay, to allow for contact bounce, and charging operation
is determined by the single external ramp capacitor connected to the RAMP
pin. When the load capacitor is fully charged, the controller emerges from
current limit mode, an additional time delay occurs before the external N-
channel MOSFET pass transistor is switched to full conduction, and the
PWRGD output signal is activated. The controller will then transition to a low
power standby mode.
Typical Application Circuit
Hotswap, Inrush Current Limiter Controllers
(Negative Supply Rail)
VDD
UV
OV
VEE SENSE GATE
-48V R4
50mΩ
R1
487kΩ
R2
6.81kΩ
R3
9.76kΩ
Q1
IRF530
CLOAD
+5V
HV300
8
3
2
47
COM
DC/DC
PWM
CONVERTER
1
GND
NOTES: 1. Undervoltage Shutdown (UV) set to 35V.
2. Overvoltage Shutdown (OV) set to 65V.
3. Remove jumper if short pin is used.
PWRGD
ENABLE
5
RAMP
6
C1
10nF
GND
Long Pin
Short Pin
Jumper
Long Pin
2
HV300
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Ordering Information
Device
Package Option
8-Lead SOIC
4.90x3.90mm body
1.75mm height (max)
1.27mm pitch
HV300 HV300LG-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter Value
VEE referenced to VDD pin +0.3 to -100V
VPWRGD referenced to VEE voltage -0.3 to +100V
Operating ambient temperature -40°C to +85°C
Operating junction temperature -40°C to +125°C
Storage temperature -65°C to +150°C
UV and OV referenced to VEE -0.3 to +12V
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
Pin Configuration
Sym Parameter Min Typ Max Units Conditions
Supply (Referenced to VDD pin)
VEE Supply voltage -90 - -10 V ---
IEE
Supply current - 550 650 µA VEE = -48V, mode = limiting
Standby mode supply current - 330 400 µA VEE = -48V, mode = standby
OV and UV Control (Referenced to VEE pin)
VUVH UV high threshold - 1.26 - V Low to high transition
VUVL UV low threshold - 1.16 - V High to low transition
VUVHY UV hysteresis - 100 - mV ---
VOVH OV high threshold - 1.26 - V Low to high transition
VOVL OV low threshold - 1.16 - V High to low transition
VOVHY OV hysteresis - 100 - mV ---
Electrical Characteristics (VIN = -10 to -90V, -40°C ≤ TA ≤ +85°C unless otherwise noted)
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
YWW
HV300
LLLL
8-Lead SOIC (LG)
(top view)
Product Marking
1
2
3
4
8
7
6
5
PWRGD
OV
UV
VEE
VDD
RAMP
GATE
SENSE
8-Lead SOIC (LG)
Package may or may not include the following marks: Si or
3
HV300
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Sym Parameter Min Typ Max Units Conditions
Current Limit (Referenced to VEE pin)
VSENSE Current limit threshold voltage 40 50 60 mV VUV = VEE + 1.9V, VOV = VEE + 0.5V
Gate Drive Output (Referenced to VEE pin)
VGATE Maximum GATE drive voltage 9.0 10 11 V VUV = VEE + 1.9V, VOV = VEE + 0.5V
IGATEUP GATE drive pull-up current 500 - - µA VUV = VEE + 1.9V, VOV = VEE + 0.5V
IGATEDOWN GATE drive pull-down current 40 - - mA VUV = VEE, VOV = VEE + 0.5V
Timing Control (Test Conditions: C =100µF, CRAMP = 10nF, VUV = VEE +1.9V, VOV = VEE +0.5V, External MOSFET is IRF5303)
IRAMP Ramp pin output current - 10 - µA VSENSE = 0V
tPOR Time from UV to GATE turn on12.0 - - ms ---
tRISE Time from GATE turn on to VSENSE limit 400 - - µs ---
tLIMIT Duration of current limit mode - - 5.0 ms ---
tPWRGD Time from current limit to PWRGD - 5.0 - ms ---
VRAMP Voltage on ramp pin in current limit mode2- 3.6 - V ---
Power Good Output (Referenced to VEE pin)
VPWRGD
Power good pin breakdown voltage 90 - - V ---
Power good pin output low voltage - 0.5 0.8 V IPWRGD = 1.0mA
Dynamic Characteristics
tGATEHLOV OV delay - - 500 ns ---
tGATEHLUV UV delay - - 500 ns ---
Electrical Characteristics (VIN = -10 to -90V, -40°C ≤ TA ≤ +85°C unless otherwise noted)
Notes
This timing depends on the threshold voltage of the external N-Channel MOSFET. The higher its threshold is, the longer this timing.
This voltage depends on the characteristics of the external N-Channel MOSFET. VGS(th) = 3.0V for an IRF530.
IRF530 is a registered trademark of International Rectifier.
1.
2.
3.
Waveforms
Drain
50V/div
VIN
50V/div
GATE
5.0V/div
IINRUSH
500mA/div
5.0ms/div
PWRGD Logic
Device Condition PWRGD
HV300 Not Ready 0 VEE
Ready 1 Hi Z
4
HV300
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Timing Diagram
GND
-48V
VIN
IIN
tSTART
contact
bounce
ILIM
PWRGD
VUVL
tRISE t
PWRGD
VGATE
Initialization Limiting Full On
VGATE
VOUT
tLIM
tTH
VRAMP
VRAMP
VGATE
inactive
active
VOUT
VIN
VGS(th)
VGS(lim)
VEE
tPOR
Functional Block Diagram
LOGIC
VINT
VDD
UV
OV
VEE
SENSE GATERAMP
VREF
UVLO
and
POR
Band Gap
Reference
Internal
Supply
Regulator
VINT
5kΩ
VINT - 1.2V
Switch
VREF
2VREF
Transconductor
Buffer
PWRGD
+
-
10mA
C
C
C
A
C
Automatic
Restart
Delay
Circuit
Breaker
100mV
Note:
VINT is the internally regulated supply voltage and can range from 9.0 to 11V.
VGS(th) is the gate threshold voltage of the external pass transistor and may be obtained from its datasheet.
VGS(lim) is the pass transistor gate-source voltage required to obtain the limit curent. It is dependent on the pass transistor’s characteristics and may
be obtained from the transfer characteristics curves on the transistor datasheet.
gfs is the transconductance of the pass transistor and may be obtained from its datasheet.
RFB is the internal feedback resistor and is 5.0kΩ nominal.
1.
2.
3.
4.
5.
ILIM = VSENSE
RSENSE
tSTART = 12V CRAMP
IRAMP
tTH = VGS(th)
CRAMP
IRAMP
tPOR = tSTART + tTH
tRISE ≈ CRAMP
gfs
IRAMP - RSENSE
0.9ILIM RFB
tLIM ≈ VIN CLOAD - 1 tRISE
ILIM 2
tPWRGD = (VINT - VGS(LIM) - 1.2V) CRAMP
IRAMP
5
HV300
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Functional Description
Insertion Into Hot Backplanes
Telecom, Data Network and some computer applications
require the ability to insert and remove circuit cards from
systems without powering down the entire system. All cir-
cuit cards have some filter capacitance on the power rails,
which is especially true in circuit cards or network terminal
equipment utilizing distributed power systems. The insertion
can result in high inrush currents that can cause damage to
connector and circuit cards and may result in unacceptable
disturbances on the system backplane power rails.
The HV300 was designed to allow the insertion of these
circuit cards or connection of terminal equipment by elimi-
nating these inrush currents and powering up these circuits
in a controlled manner after full connector insertion has been
achieved. The HV300 is intended to provide this function on
a negative supply rail in the range of -10 to -90V.
Operation
On initial power application an internal regulator seeks to
provide 10V for the internal IC circuitry. Until the proper
internal voltage is achieved all circuits are held reset, the
open drain PWRGD signal is inactive to inhibit the start of
any load circuitry and the gate to source voltage of the ex-
ternal N-channel MOSFET is held low. Once the internal un-
der voltage lock out (UVLO) has been satisfied, the circuit
checks the input supply voltage under voltage (UV) and over
voltage (OV) sense circuits to ensure that the input voltage
is within acceptable programmed limits. These limits are de-
termined by the selected values of resistors R1, R2 and R3,
which form a voltage divider.
Assuming the above conditions are satisfied and while con-
tinuing to hold the PWRGD output inactive and the external
MOSFET GATE voltage low, the current source feeding the
RAMP pin is turned on. The external capacitor connected to
it begins to charge, thus starting an initial time delay deter-
mined by the value of the capacitor. If an interruption of the
input power occurs during this time (i.e. caused by contact
bounce) or the OV or UV limits are exceeded, an immedi-
ate reset occurs and the external capacitor connected to the
RAMP pin is discharged.
When the voltage on the RAMP pin reaches an internally
set voltage limit, the gate drive circuitry begins to turn on the
external MOSFET; allowing the current to softly rise over a
period of a few hundred micro-seconds to the current limit
set point. While the circuit is limiting current, the voltage on
the RAMP pin will be fixed.
Depending on the value of the load capacitance and the
programmed current limit, charging may continue for some
time. The magnitude of the current limit is programmed by
comparing a voltage developed by a sense resistor connect-
ed between the VEE and SENSE pins to 50mV (Typical).
Once the load capacitor has been charged, the current will
drop which will cause the ramp voltage to continue rising;
providing yet another programmed delay.
When the ramp voltage is within 1.2V of the internally regu-
lated voltage, the controller will force the GATE full on and
will activate the PWRGD pin and the circuit will transition to a
low power standby mode. The PWRGD pin is often used as
an enable for downstream DC/DC converter loads.
At any time during the start up cycle or thereafter, crossing
the UV and OV limits (including hysteresis) will cause an im-
mediate reset of all internal circuitry. Thereafter the start up
process will begin again.
Application Information
Under Voltage and Over Voltage Detection
The UV and OV pins are connected to comparators with
nominal 1.21V thresholds and 100mV of hysteresis (1.21V
± 50mV). They are used to detect under voltage and over
voltage conditions at the input to the circuit. Whenever the
OV pin rises above its threshold or the UV pin falls below its
threshold the GATE voltage is immediately pulled low, the
PWRGD signal is deactivated and the external capacitor
connected to the RAMP pin is discharged.
The under voltage and over voltage trip points can be pro-
grammed by means of the three resistor divider formed by
R1, R2 and R3. Since the input currents on the UV and OV
pins are negligible the resistor values may be calculated as
follows:
UVOFF = VUVH = 1.16 = |VEEUV| • (R2+R3) / (R1+R2+R3)
OVOFF = VOVL = 1.26 = |VEEOV| • R3 / (R1+R2+R3)
Where |VEEUV| and |VEEOV| are Under & Over Voltage Set
points.
If we select a divider current of 100µA at a nominal operating
input voltage of 50V then:
(R1+R2+R3) = 50V / 100µA = 500kΩ
6
HV300
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
From the second equation for an over voltage set point of
65V, the value of R3 may be calculated.
OVOFF = 1.26 = 65 • R3 / 500kΩ
R3 = (1.26 • 500K) / 65 = 9.69 kΩ
The closest 1% value is 9.76kΩ.
From the first equation for an under voltage set point of 35V,
the value R2 can be calculated.
UVOFF = 1.16 = 35 • (R2 + R3) / 500K
R2 = (1.16 • 500K) / 35 – 9.76kΩ = 6.81kΩ.
The closest 1% value is 6.81kΩ.
Then R1 = 500K – (R2 + R3) = 483kΩ
The closest 1% value is 487kΩ.
Undervoltage/Overvoltage Operation
Current Limit
The current limit magnitude above which the current will
not be allowed to rise during startup is programmed using a
sense resistor connected from the SENSE pin to VEE pin.
For example to program a current limit of 1.0A, one would
choose a resistor as follows:
RSENSE = 50mV / ISENSE
RSENSE = 50mV / 1.0A
RSENSE = 50mΩ
GND
VIN
Pass
Transistor
OFF
ON
UVOFF
UVON
OVOFF
OVON
Pin # Function Description
1 PWRGD
This pin is held low during inrush current limiting and changes to high impedance state when the
external MOSFET is fully turned on. This pin may be used as an enable control when connected
directly to a PWM power module.
2 OV
This pin, when raised above its high threshold, will immediately cause the GATE pin to be pulled
low. The GATE pin will remain low until the voltage on this pin falls below the low threshold limit,
initiating a new start-up cycle.
3 UV
This Under Voltage sense pin, when below its low threshold limit will ensure that the GATE pin
is low. The GATE pin will remain low until the voltage on this pin rises above the high threshold,
initializing a new start-up cycle.
4 VEE This pin is the negative voltage power supply input to the circuit.
5 VDD This pin is the positive voltage power supply input to the circuit.
6 RAMP
This pin provides a current output so that a timing ramp voltage is generated when a capacitor is
connected. The initial portion of the ramp provides a time delay, which in conjunction with the Un-
der Voltage detection circuit eliminates circuit card insertion contact bounce. The RAMP pin also
controls the delay between the current limit mode disengaging and the PWRGD signal activating;
as well as the current rise profile after the initial turn on delay.
7 GATE This is the GATE driver output for the external N-Channel MOSFET.
8 SENSE The current sense resistor connected from this pin to VEE pin programs the current limit. Constant
current output mode is established when the voltage drop across this resistor reaches 50mV.
Pin Description
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com.
©2009 All rights reserved. Unauthorized use or reproduction is prohibited.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
7
HV300
(The package drawings in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV300
A030509
8-Lead SOIC (Narrow Body) Package Outline (LG)
4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
1
8
Seating
Plane
Gauge
Plane
L
L1
L2
E
E1
D
eb
AA2
A1
Seating
Plane
A
A
Top View
Side View
View B
View B
θ1
θ
Note 1
(Index Area
D/2 x E1/2)
View A-A
h
h
Note 1
Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1
Dimension
(mm)
MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80*
1.27
BSC
0.25 0.40
1.04
REF
0.25
BSC
0O5O
NOM - - - - 4.90 6.00 3.90 - - - -
MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8O15O
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not specified in the original JEDEC drawing. The value listed is for reference only.
Drawings are not to scale.
Supertex Doc. #: DSPD-8SOLGTG, Version H101708.
Note:
This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier;
an embedded metal marker; or a printed indicator.
1.
