DCP02
DCP02
1
FEATURES DESCRIPTION
APPLICATIONS
IBIAS
Power
Stage
VOUT
Divide-by-2
Reset
800kHz
Oscillator
Watchdog/
Startup
PSU
Thermal
Shutdown
SYNC/DISABLE
VS
0V
PowerControllerIC
0V
DCP02 Series
SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008www.ti.com
Miniature, 2W, IsolatedUNREGULATED DC/DC CONVERTERS
2
•Up To 89% Efficiency
The DCP02 series is a family of 2W, isolated,unregulated DC/DC converters. Requiring a minimum•Thermal Protection
of external components and including on-chip device•Device-to-Device Synchronization
protection, the DCP02 series provides extra features•SO-28 Power Density of 106W/in
3
(6.5W/cm
3
)
such as output disable and synchronization of•EN55022 Class B EMC Performance switching frequencies.•UL1950 Recognized Component
The use of a highly integrated package design resultsin highly reliable products with power densities of•JEDEC 14-Pin and SO-28 Packages
79W/in
3
(4.8W/cm
3
) for DIP-14, and 106W/in
3
(6.5W/cm
3
) for SO-28. This combination of featuresand small size makes the DCP02 suitable for a wide•Point-of-Use Power Conversion
range of applications.•Ground Loop Elimination•Data Acquisition
•Industrial Control and Instrumentation•Test Equipment
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
ORDERING INFORMATION
BasicModelNumber:2WProduct
VoltageInput:
5VIn
VoltageOutput:
5VOut
DualOutput:
PackageCode:
P=DIP-14
U=SO-28
DCP02 05 05 (D) ()
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
DCP02 Series
SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
For the most current package and ordering information, see the Package Option Addendum at the end of thisdata sheet, or see the TI website at www.ti.com.
Supplemental Ordering Information
Over operating free-air temperature range (unless otherwise noted)
(1)
PARAMETER DCP02 Series UNIT
5V input models 7 V12V input models 15 VInput Voltage
15V input models 18 V24V input models 29 VStorage temperature range – 60 to +125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
At T
A
= +25 °C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT
Power 100% full load 2 W
Ripple Output capacitor = 1 µF, 50% load 20 mV
PP
Room to cold 0.046 %/ °CVoltage vs. Temperature
Room to hot 0.016 %/ °C
INPUT
Voltage range on V
S
– 10 10 %
ISOLATION
1s Flash test 1 kVrmsVoltage
60s test, UL1950
(1)
1 kVrms
LINE REGULATION
V
S
(min) to V
S
(typ) 1 15 %Output Voltage I
O
= constant
(2)
V
S
(typ) to V
S
(max) 1 15 %
(1) During UL1950 recognition tests only.(2) I
OUT
≥10% load current
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ELECTRICAL CHARACTERISTICS PER DEVICE
DCP02 Series
SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008
ELECTRICAL CHARACTERISTICS (continued)At T
A
= +25 °C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWITCHING/SYNCHRONIZATION
Oscillator frequency (f
OSC
) Switching frequency = f
OSC
/2 800 kHz
Sync input low 0 0.4 V
Sync input current V
SYNC
= +2V 75 µA
Disable time 2 µs
Capacitance loading on SYNC pin External 3
(3)
pF
RELIABILITY
Demonstrated T
A
= +55 °C 75 FITS
THERMAL SHUTDOWN
IC temperature at shutdown +150 °C
Shutdown current 3 mA
TEMPERATURE RANGE
Operating – 40 +85 °C
(3) For more information, refer to application report SBAA035 , available for download at www.ti.com .
At T
A
= +25 °C, V
S
= nominal, C
IN
= 2.2 µF, C
OUT
= 1.0 µF, unless otherwise noted.
INPUT OUTPUT LOAD NO LOAD BARRIERVOLTAGE VOLTAGE REGULATION CURRENT EFFICIENCY CAPACITANCE(V) (V) (%) (mA) (%) (pF)
V
S
V
NOM
AT V
S
(TYP) I
Q
C
ISO
10% TO 100%75% LOAD
(1)
LOAD
(2)
0% LOAD 100% LOAD V
ISO
= 750Vrms
PRODUCT MIN TYP MAX MIN TYP MAX TYP MAX TYP TYP TYP
DCP020503P, U 4.5 5 5.5 3.13 3.3 3.46 19 30 18 74 26
DCP020505P, U 4.5 5 5.5 4.75 5 5.25 14 20 18 80 22
DCP020507P, U 4.5 5 5.5 6.65 7 7.35 14 25 20 81 30
DCP020509P, U 4.5 5 5.5 8.55 9 9.45 12 20 23 82 31
DCP020515DP, U 4.5 5 5.5 ± 14.25 ± 15 ± 15.75 11 20 27 85 24
DCP021205P, U 10.8 12 13.2 4.75 5 5.25 7 15 14 83 33
DCP021212P, U 10.8 12 13.2 11.4 12 12.6 7 20 15 87 47
DCP021212DP, U 10.8 12 13.2 ± 11.4 ± 12 ± 12.6 6 20 16 88 35
DCP021515P, U 13.5 15 16.5 14.25 15 15.75 6 20 15 88 42
DCP022405P 21.6 24 26.4 4.85 5 5.35 6 10 13 81 33
DCP022405U 21.6 24 26.4 4.75 5 5.25 10 15 13 81 33
DCP022405DP, U 21.6 24 26.4 ± 4.75 ± 5 +5.25 6 15 12 80 22
DCP022415DP, U 21.6 24 26.4 ± 14.25 ± 15 ± 15.75 6 25 16 79 44
(1) 100% load current = 2W/V
NOM
(typ)(2) Load regulation = (V
OUT
at 10% load - V
OUT
at 100%)/V
OUT
at 75% load
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DEVICE INFORMATION
DCP02
1
2
5
6
7
14
8
VS
0V
0V
+VOUT
NC
SYNC
NC
DCP02
1
2
5
6
7
14
8
VS
0V
0V
+VOUT
-VOUT
SYNC
NC
DCP02
1
2
3
12
13
14
28
27
26
17
16
15
VS
0V
0V
0V
+VOUT
NC
SYNC
NC
NC
NC
NC
NC
DCP02
1
2
3
12
13
14
28
27
26
17
16
15
VS
0V
0V
0V
+VOUT
-VOUT
SYNC
NC
NC
NC
NC
NC
DCP02 Series
SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008
NVA PACKAGE
NVA PACKAGEDIP-14 (Single-DIP)
DIP-14 (Dual-DIP)(Top View)
(Top View)
Table 1. Pin Description (Single-DIP)
Table 3. TERMINAL FUNCTIONS (Dual-DIP)TERMINAL
TERMINALNAME NO. DESCRIPTION
NAME NO. DESCRIPTIONV
S
1 Voltage input
V
S
1 Voltage input0V 2 Input side common
0V 2 Input side common0V 5 Output side common
0V 5 Output side common+V
OUT
6 +Voltage out
+V
OUT
6 +Voltage outNC 7, 8 Not connected
– V
OUT
7 – Voltage outSYNC 14 Synchronization pin
NC 8 Not connected
SYNC 14 Synchronization pinDVB PACKAGE
SO-28 (Single-SO)
DVB PACKAGE(Top View)
SO-28 (Dual-SO)
(Top View)
Table 2. TERMINAL FUNCTIONS (Single-SO)TERMINAL
Table 4. TERMINAL FUNCTIONS (Dual-SO)NAME NO. DESCRIPTION
TERMINALV
S
1 Voltage input
NAME NO. DESCRIPTION0V 2 Input side common
V
S
1 Voltage input0V 3 Input side common
0V 2 Input side common0V 12 Output side common
0V 3 Input side common+V
OUT
13 +Voltage out
0V 12 Output side common14, 15, 16,
+V
OUT
13 +Voltage outNC Not connected17, 26, 27
– V
OUT
14 – Voltage outSYNC 28 Synchronization pin
15, 16, 17,NC Not connected26, 27
SYNC 28 Synchronization pin
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TYPICAL CHARACTERISTICS
Temperature( C)°
V (V)
OUT
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
-20 20 40 60 80 1000-40
EmissionLevel,Peak(dBmA)
Frequency(MHz)
10.15 10 30
60
50
40
30
20
10
0
-10
-20
Temperature( C)°
P(W)
OUT
0 25 50 75 100-25-50
2.5
2.0
1.5
1.0
0.5
0
100
80
60
40
20
0
Load(%)
Efficiency(%)
0 25 50 75 100
DCP1212DP
DCP1205P
450
400
350
300
250
200
150
100
50
0
LoadCurrent(mA)
Ripple(mV )
PP
0 200
0.1 Fm
400
1 Fm
DCP02 Series
SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008
At T
A
= +25 °C, unless otherwise noted.
DCP020505P DCP020505PCONDUCTED EMISSIONS (500mA Load) V
OUT
vs TEMPERATURE (75% Load)
Figure 1. Figure 2.
DCP021205P DCP021205PV
OUT
vs LOAD POWER OUT vs TEMPERATURE (400mA Load)
Figure 3. Figure 4.
DCP0212 DCP020505PEFFICIENCY vs LOAD OUTPUT AC RIPPLE (20MHz Band)
Figure 5. Figure 6.
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FUNCTIONAL DESCRIPTIONOVERVIEW
POWER STAGE
OSCILLATOR AND WATCHDOG
THERMAL SHUTDOWN
CONSTRUCTION
SYNCHRONIZATION
DCP 02
VOUT1
VSUPPLY VS
0V
V +V
OUT1 OUT2
SYNC
0V
COM
DCP 02
VOUT2
VS
0V
SYNC
0V
C requiresalow-ESRceramiccapacitor:5Vto15Vversionis2.2 F;
24Vversionisminimum0.47 F.
m
IN
m
NOTE:(1)
CIN
(1) COUT
1.0 Fm
CIN
(1) COUT
1.0 Fm
DCP02 Series
SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008
This interference occurs because of the smallvariations in switching frequencies between theThe DCP02 offers up to 2W of unregulated output
DC/DC converters.power from a 5V, 12V, 15V, or 24V input source witha typical efficiency of up to 89%. This efficiency is The DCP02 overcomes this interference by allowingachieved through highly integrated packaging devices to be synchronized to one another. Up totechnology and the implementation of a custom eight devices can be synchronized by connecting thepower stage and control IC. The circuit design uses SYNC pins together, taking care to minimize thean advanced BiCMOS/DMOS process. capacitance of tracking. Stray capacitance (> 10pF)has the effect of reducing the switching frequency, oreven stopping the oscillator circuit. It is alsorecommended that power and ground lines beThe DCP02 uses a push-pull, center-tapped topology
star-connected.switching at 400kHz (divide-by-2 from an 800kHz
It should be noted that if synchronized devices areoscillator).
used at start up, all devices will draw maximumcurrent simultaneously. This configuration can causethe input voltage to dip; if it dips below the minimumThe onboard 800kHz oscillator generates the
input voltage (4.5V), the devices may not start up. Aswitching frequency via a divide-by-2 circuit. The
2.2 µF capacitor should be connected close to theoscillator can be synchronized to other DCP02
input pins.circuits or an external source, and is used to minimize
If more than eight devices are to be synchronized, itsystem noise.
is recommended that the SYNC pins be driven by anA watchdog circuit checks the operation of the
external device. Details are contained in Applicationoscillator circuit. The oscillator can be stopped by
Report SBAA035, External Synchronization of thepulling the SYNC pin low. The output pins will be
DCP01/02 Series of DC/DC Converters , available fortri-stated, which occurs in 2 µs.
download from www.ti.com .
The DCP02 is protected by a thermal-shutdown
The basic construction of the DCP02 is the same ascircuit. If the on-chip temperature exceeds +150 °C,
standard ICs; there is no substrate within the moldedthe device will shut down. Once the temperature falls
package. The DCP02 is constructed using an IC,below +150 °C, normal operation resumes.
rectifier diodes, and a wound magnetic toroid on aleadframe. Since there is no solder within thepackage, the DCP02 does not require any specialprinted circuit board (PCB) assembly processing. ThisIn the event that more than one DC/DC converter is
architecture results in an isolated DC/DC converterneeded onboard, beat frequencies and other
with inherently high reliability.electrical interference can be generated.
Figure 7. Connecting the DCP02 in Series
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ADDITIONAL FUNCTIONSDISABLE/ENABLE
DECOUPLING
Connecting the DCP02 in ParallelRipple Reduction
Connecting the DCP02 in Series
DCP 02
+VOUT
VSUPPLY +VOUT
-VOUT
-VOUT
0V
VS
0V
COM
C requiresalow-ESRceramiccapacitor:5Vto15Vversionis2.2 F;
24Vversionisminimum0.47 F.
m
IN
m
NOTE:(1)
CIN
(1)
C
1.0 F
OUT
m
C
1.0 F
OUT
m
VSUPPLY
2xPowerOut
COM
DCP 02
VOUT
VS
0V
SYNC
0V
DCP 02
VOUT
VS
0V
SYNC
0V
C requiresalow-ESRceramiccapacitor:5Vto15Vversionis2.2 F;
24Vversionisminimum0.47 F.
m
IN
m
NOTE:(1)
CIN
(1) C
1.0 F
OUT
m
CIN
(1) C
1.0 F
OUT
m
DCP02 Series
SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008
Connect the positive V
OUT
from one DCP02 to theThe DCP02 can be disabled or enabled by driving the negative V
OUT
(0V) of another (see Figure 7 ). If theSYNC pin using an open drain CMOS gate. If the SYNC pins are tied together, the self-synchronizationSYNC pin is pulled low, the DCP02 will be disabled. feature of the DCP02 prevents beat frequencies onThe disable time depends upon the external loading; the voltage rails. The SYNC feature of the DCP02the internal disable function is implemented in 2 µs. allows easy series connection without externalRemoval of the pull down causes the DCP02 to be filtering, thus minimizing cost.enabled.
The outputs on the dual-output DCP02 versions canCapacitive loading on the SYNC pin should be also be connected in series to provide two times theminimized in order to prevent a reduction in the magnitude of V
OUT
, as shown in Figure 8 . Foroscillator frequency. example, a dual 15V DCP022415D could beconnected to provide a 30V rail.
If the output power from one DCP02 is not sufficient,it is possible to parallel the outputs of multipleThe high switching frequency of 400kHz allows
DCP02s, as shown in Figure 9 . Again, the SYNCsimple filtering. To reduce ripple, it is recommended
feature allows easy synchronization to preventthat a 1 µF capacitor be used on V
OUT
. Dual outputs
power-rail beat frequencies at no additional filteringshould both be decoupled to pin 5. A 2.2 µF capacitor
cost.on the input is also recommended.
Multiple DCP02 isolated 2W DC/DC converters canbe connected in series to provide nonstandardvoltage rails. This configuration is possible by usingthe floating outputs provided by the galvanic isolationof the DCP02.
Figure 8. Connecting Dual Outputs in Series
Figure 9. Connecting Multiple DCP02s in Parallel
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APPLICATION INFORMATION
OPTIMIZING PERFORMANCE
TRANSFORMER DRIVE CIRCUIT
SELF-SYNCHRONIZATION
PCB Design
DCP02 Series
SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008
The DCP01B ,DCV01 , and DCP02 are three familiesof miniature DC/DC converters providing an isolatedunregulated voltage output. All are fabricated using a
Optimum performance can only be achieved if theCMOS/DMOS process with the DCP01B replacing
device is correctly supported. The very nature of athe familiar DCP01 family that was fabricated from a
switching converter requires power to be instantlybipolar process. The DCP02 is essentially an
available when it switches on. If the converter hasextension of the DCP01B family, providing a higher
DMOS switching transistors, the fast edges will createpower output with a significantly improved load
a high current demand on the input supply. Thisregulation. The DCV01 is tested to a higher isolation
transient load placed on the input is supplied by thevoltage.
external input decoupling capacitor, thus maintainingthe input voltage. Therefore, the input supply doesnot see this transient (this is an analogy tohigh-speed digital circuits). The positioning of theTransformer drive transistors have a characteristically
capacitor is critical and must be placed as close aslow value of transistor on resistance (R
DS
); thus, more
possible to the input pins and connected via apower is transferred to the transformer. The
low-impedance path.transformer drive circuit is limited by the base currentavailable to switch on the power transistors driving The optimum performance primarily depends on twothe transformer and the characteristic current gain factors:(beta), resulting in a slower turn-on time.
1. Connection of the input and output circuits forConsequently, more power is dissipated within the
minimal loss.transistor, resulting in a lower overall efficiency,
2. The ability of the decoupling capacitors toparticularly at higher output load currents.
maintain the input and output voltages at aconstant level.
The input synchronizations facility (SYNC
IN
) allowsfor easy synchronizing of multiple devices. If two to
The copper losses (resistance and inductance) caneight devices (maximum) have their respective
be minimized by the use of mutual ground and powerSYNC
IN
pins connected together, then all devices will
planes (tracks) where possible. If that is not possible,be synchronized.
use wide tracks to reduce the losses. If severaldevices are being powered from a common powerEach device has its own onboard oscillator. This
source, a star-connected system for the track mustoscillator is generated by charging a capacitor from a
be deployed; devices must not be connected inconstant current and producing a ramp. When this
series, as this will cascade the resistive losses. Theramp passes a threshold, an internal switch is
position of the decoupling capacitors is important.activated that discharges the capacitor to a second
They must be as close to the devices as possible inthreshold before the cycle is repeated.
order to reduce losses. See the PCB Layout sectionWhen several devices are connected together, all the
for more details.internal capacitors are charged simultaneously.
When one device passes its threshold during thecharge cycle, it starts the discharge cycle. All theother devices sense this falling voltage and, likewise,initiate a discharge cycle so that all devices dischargetogether. A subsequent charge cycle is only restartedwhen the last device has finished its discharge cycle.
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Decoupling Ceramic Capacitors Input Capacitor and the Effects of ESR
0fOFrequency
XL
Z
Where:
X isthereactanceduetothecapacitance.
C
X isthereactanceduetotheESL.
f istheresonantfrequency.
L
O
Z= (X X )Ö-
C L
2 2
+(ESR)
XC
DCP02 Series
SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008
All capacitors have losses because of internal If the input decoupling capacitor is not ceramic withequivalent series resistance (ESR), and to a lesser <20m ΩESR, then at the instant the power transistorsdegree, equivalent series inductance (ESL). Values switch on, the voltage at the input pins fallsfor ESL are not always easy to obtain. However, momentarily. Should the voltage fall belowsome manufacturers provide graphs of frequency approximately 4V, the DCP detects an under-voltageversus capacitor impedance. These graphs typically condition and switches the DCP drive circuits to theshow the capacitor impedance falling as frequency is off state. This detection is carried out as a precautionincreased (as shown in Figure 10 ). As the frequency against a genuine low input voltage condition thatincreases, the impedance stops decreasing and could slow down or even stop the internal circuitsbegins to rise. The point of minimum impedance from operating correctly. A slow-down or stoppageindicates the resonant frequency of the capacitor. would result in the drive transistors being turned onThis frequency is where the components of too long, causing saturation of the transformer andcapacitance and inductance reactance are of equal destruction of the device.magnitude. Beyond this point, the capacitor is not
Following detection of a low input voltage condition,effective as a capacitor.
the device switches off the internal drive circuits untilthe input voltage returns to a safe value. Then thedevice tries to restart. If the input capacitor is stillunable to maintain the input voltage, shutdownrecurs. This process is repeated until the capacitor ischarged sufficiently to start the device correctly.Otherwise, the device will be caught up in a loop.
Normal startup should occur in approximately 1msfrom power being applied to the device. If aconsiderably longer startup duration time isencountered, it is likely that either (or both) the inputsupply or the capacitors are not performingadequately.
For 5V to 15V input devices, a 2.2 µF low-ESRceramic capacitor ensures a good startupFigure 10. Capacitor Impedance vs Frequency
performance. For the remaining input voltage ranges,0.47 µF ceramic capacitors are recommended.Tantalum capacitors are not recommended, sinceAt f
O
, X
C
= X
L
; however, there is a 180 °phase
most do not have low-ESR values and will degradedifference resulting in cancellation of the imaginary
performance. If tantalum capacitors must be used,component. The resulting effect is that the impedance
close attention must be paid to both the ESR andat the resonant point is the real part of the complex
voltage as derated by the vendor.impedance; namely, the value of the ESR. Theresonant frequency must be well above the 800kHz
Output Ripple Calculation Exampleswitching frequency of the DCP and DCVs.
DCP020505: Output voltage 5V, Output current 0.4A.The effect of the ESR is to cause a voltage drop
At full output power, the load resistor is 12.5 Ω. Outputwithin the capacitor. The value of this voltage drop is
capacitor of 1 µF, ESR of 0.1 Ω. Capacitor dischargesimply the product of the ESR and the transient load
time 1% of 800kHz (ripple frequency):current, as shown:
t
DIS
= 0.0125 µsV
IN
= V
PK
– (ESR ×I
TR
) (1)
τ= C ×R
LOADWhere:
τ= 1 ×10
-6
×12.5 = 12.5 µsV
IN
is the voltage at the device input.
V
DIS
= V
O
(1 – EXP( – t
DIS
/τ))V
PK
is the maximum value of the voltage on the
V
DIS
= 5mVcapacitor during charge.
By contrast, the voltage dropped because of ESR:I
TR
is the transient load current.
V
ESR
= I
LOAD
×ESRThe other factor that affects the performance is the
V
ESR
= 40mVvalue of the capacitance. However, for the input and
Ripple voltage = 45mVthe full wave outputs (single-output voltage devices),ESR is the dominant factor.
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DUAL OUTPUT VOLTAGE DCP AND DCVs
Ripple and Noise
PCB LAYOUT
THERMAL MANAGEMENT
DCP02 Series
SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008
Clearly, increasing the capacitance has a much The SYNC
IN
pin, when not being used, is best left assmaller effect on the output ripple voltage than does a floating pad. A ground ring or annulus connectedreducing the value of the ESR for the filter capacitor. around the pin prevents noise being conducted ontothe pin. If the SYNC
IN
pin is to be connected to oneor more SYNC
IN
pins, then the linking trace should benarrow and must be kept short in length. In addition,The voltage output for the dual DCPs is half wave
no other trace should be in close proximity to thisrectified; therefore, the discharge time is 1.25 µs.
trace because that will increase the stray capacitanceRepeating the above calculations using the 100%
on this pin. In turn, the stray capacitance affects theload resistance of 25 Ω(0.2A per output), the results
performance of the oscillator.are:
τ= 25 µst
DIS
= 1.25 µs
Careful consideration should be given to the layout ofV
DIS
= 244mV
the PCB in order to obtain the best results.V
ESR
= 20mV
The DCP02 is a switching power supply, and as suchRipple Voltage = 266mV
can place high peak current demands on the inputsupply. In order to avoid the supply fallingThis time, it is the capacitor discharging that
momentarily during the fast switching pulses, groundcontributes to the largest component of ripple.
and power planes should be used to connect theChanging the output filter to 10 µF, and repeating the
power to the input of DCP02. If this connection is notcalculations, the result is:
possible, then the supplies must be connected in aRipple Voltage = 45mV.
star formation with the traces made as wide asThis value is composed of almost equal components.
possible.The previous calculations are given only as a guide.
If the SYNC
IN
pin is being used, then the traceCapacitor parameters usually have large tolerances
connection between device SYNC
IN
pins should beand can be susceptible to environmental conditions.
short to avoid stray capacitance. If the SYNC
IN
pin isnot being used, it is advisable to place a guard ring(connected to input ground) around this pin to avoidany noise pick up.Figure 11 and Figure 12 illustrate a printed circuit
The output should be taken from the device usingboard (PCB) layout for the two conventional
ground and power planes, thereby ensuring minimum(DCP01/02, DCV01), and two SO-28 surface-mount
losses.packages (DCP02U). Figure 13 shows the schematic.
A good quality, low-ESR ceramic capacitor placed asInput power and ground planes have been used,
close as practical across the input reduces reflectedproviding a low-impedance path for the input power.
ripple and ensures a smooth startup.For the output, the common or 0V has beenconnected via a ground plane, while the connections
A good quality. low-ESR capacitor (ceramicfor the positive and negative voltage outputs are
preferred) placed as close as practical across theconducted via wide traces in order to minimize
rectifier output terminal and output ground gives thelosses.
best ripple and noise performance. See ApplicationBulletin SBVA012, DC-to-DC Converter NoiseThe location of the decoupling capacitors in close
Reduction , for more information on noise rejection.proximity to their respective pins ensures low lossesdue to the effects of stray inductance, thus improvingthe ripple performance. This location is of particularimportance to the input decoupling capacitor,
Due to the high power density of this device, it isbecause this capacitor supplies the transient current
advisable to provide ground planes on the input andassociated with the fast switching waveforms of the
output.power drive circuits.
10 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): DCP02 Series
www.ti.com
DCP02 Series
SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008
Figure 11. Example of PCB Layout, Component-Side View
Figure 12. Example of PCB Layout, Non-Component-Side View
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): DCP02 Series
www.ti.com
1
2
3
13
12
14
DCP02xU
28
27
26
C16
R7C17 C18
R8C20 C19
VS4
0S4
+V4
COM4
-V4
NC
NC
1
2
3
13
12
14
C11
R5C13 C12
R6C14 C15
VS3
0S3
+V3
COM3
-V3
28
27
26
C1
R1C3C2-1 C2
R2C5C4-1 C4
VS1
0V1
+V1
COM1
-V1
C6
R3C8C7-1 C7
R4C10 C9-1 C9
VS2
0V2
+V2
COM2
-V2
1
2
6
5
7
1
2
6
5
7
14
14
DCP02xP
SYNC
DCP02xP
SYNC
DCP02xU
SYNC
SYNC
JP1
JP2
JP1
JP2
CON1
CON2
CON3
CON4
(1)CapacitorsC ,C ,C ,andC arethrough-holeplatedcomponentsconnectedinparallelwithC ,C ,C ,andC (1206SMD),respectively.
(2)Foroptimumlow-noiseperformance,uselow-ESRcapacitors.
(3)DonotconnecttheSYNCpinjumper(JP1−JP4)iftheSYNCfunctionisnotbeingused.
(4)Connectionstothepowerinputshouldbemadewithaminimumwireof16/0.2twistedpair,withthelengthkeptshort.
(5)VSxand0Vxareinputsupplyandgroundrespectively(xrepresentsthechannel).
(6)+Vxand −Vxarethepositiveandnegativeoutputs,referencedtoacommongroundCOMx.
(7)JPxarethelinksusedforself-synchronization;ifthisfacilityisnotbeingused,thelinksshouldbeunconnected.
(8)R1−R8arethepoweroutputloads;donotfittheseifanexternalloadisconnected.
(9)CON1andCON2areDIL-14;CON3andCON4areSO-28packages.
(10)NC=notconnected.
2−1 4−1 7−1 9−1 2 4 7 9
DCP02 Series
SBVS011K – MARCH 2000 – REVISED FEBRUARY 2008
Figure 13. Example of PCB Layout, Schematic Diagram
12 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): DCP02 Series
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DCP020503P ACTIVE PDIP NVA 7 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
DCP020503U ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DCP020505P ACTIVE PDIP NVA 7 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
DCP020505U ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DCP020505U/1K ACTIVE SOP DVB 12 1000 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DCP020505U/1KE4 ACTIVE SOP DVB 12 1000 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DCP020505UE4 ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DCP020507P ACTIVE PDIP NVA 7 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
DCP020507U ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DCP020507U/1K ACTIVE SOP DVB 12 1000 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DCP020509P ACTIVE PDIP NVA 7 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
DCP020509U ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DCP020509U/1K OBSOLETE SOP DVB 12 TBD Call TI Call TI Samples Not Available
DCP020515DP ACTIVE PDIP NVA 7 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
DCP020515DU ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DCP020515DU/1K ACTIVE SOP DVB 12 1000 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DCP021205P ACTIVE PDIP NVA 7 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
DCP021205PE4 ACTIVE PDIP NVA 7 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
DCP021205U ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DCP021205U/1K ACTIVE SOP DVB 12 1000 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DCP021212DP ACTIVE PDIP NVA 7 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
DCP021212DU ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DCP021212DU/1K ACTIVE SOP DVB 12 1000 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DCP021212P ACTIVE PDIP NVA 7 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
DCP021212U ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DCP021212U/1K ACTIVE SOP DVB 12 1000 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DCP021515P ACTIVE PDIP NVA 7 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
DCP021515PE4 ACTIVE PDIP NVA 7 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
DCP021515U ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DCP021515U/1K ACTIVE SOP DVB 12 1000 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Purchase Samples
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DCP022405DP ACTIVE PDIP NVA 7 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
DCP022405DU ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Purchase Samples
DCP022405P ACTIVE PDIP NVA 7 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
DCP022405U ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DCP022415DP ACTIVE PDIP NVA 7 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Request Free Samples
DCP022415DU ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Request Free Samples
DCP022415DU/1K ACTIVE SOP DVB 12 1000 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA
MPDS106A – AUGUST 2001 – REVISED NOVEMBER 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
DVB(R-PDSO-G12/28) PLASTIC SMALL-OUTLINE
4202104/B 11/01
Index
Area
114
1528
Seating
Plane
17,70
18,10
7,60
7,40
10,01
10,65
2,35
2,65
0,30
0,10
0,51
0,33 0,32
0,23
0,25
0,75 x 45°
1,27
0,40
0°–8°
C
F
G
1,27
D
0,25 M BAC SM 0,10
0,25 MBM
10,82
11,20
–A–
–B–
Base
Plane
–C–
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body length dimension does not include mold
flash, protrusions, or gate burrs. Mold flash, protrusions,
and gate burrs shall not exceed 0,15 mm per side.
D. Body width dimension does not include inter-lead flash
or portrusions. Inter-lead flash and protrusions
shall not exceed 0,25 mm per side.
E. The chamfer on the body is optional. If it is not present,
a visual index feature must be located within the
cross-hatched area.
F. Lead dimension is the length of terminal for soldering
to a substrate.
G. Lead width, as measured 0,36 mm or greater
above the seating plane, shall not exceed a
maximum value of 0,61 mm.
H. Lead-to-lead coplanarity shall be less than
0,10 mm from seating plane.
I. Falls within JEDEC MS-013-AE with the exception
of the number of leads.
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