19-1972; Rev 1; 10/92 CMOS, 12-Bit, Serial-Input Multiplying DAC General Description The MAX543 is a 12-bit, current-output, multiplying digi- tal-to-analog converter (DAC) that comes in space-sav- ing 8-pin DIP and 8- or 16-pin surface-mount SO packages. Its 3-wire serial interface saves additional board space and also results in low power dissipation. When used with microprocessors (Ps) with a serial port, the MAX543 minimizes the digital noise feedthrough from its input pins to its output. The serial port can be used as a dedicated analog bus and kept inactive while the MAX543 is in use. Serial interfacing aiso reduces the complexity of opto- or transformer-isolated applications. The MAX543 contains a 12-bit R-2R type DAC, a serial-in parallel-out shift register, a DAC register and control logic. On the rising edge of the clock (CLK) pulse, the serial input (SRI) data is shifted into the MAX543. When all the data is clocked in, it is transferred into the DAC register by taking the LOAD input low. The MAX543 is specified with a single power supply of either +5V or +15V. With a +5V supply, the digital inputs are TTL and +5V CMOS compatible. High-voltage CMOS compatibility is maintained with a +15V supply. Maxim's MAX543 uses low-tempco thin-film resistors laser trimmed to +1/4LSB linearity and better than +1LSB gain accuracy. The digital inputs are protected against electrostatic discharge (ESD) damage and can typically withstand over 5,000V of ESD voltages. Applications Automatic Calibration Motion-Control Systems MA MAIL/AM Features @ 12-Bit Accuracy in 8-Pin MiniDIP or SO @ Fast 3-Wire Serial Interface @ Low INL and DNL (+1/2LSB Max) @ Gain Accuracy to +1LSB Max @ Low Gain Tempco (S5ppm/"C Max) @ Operates with +5V or +15V Supplies @ TTL/CMOS Compatible @ ESD Protected Ordering Information PART TEMP. RANGE PIN-PACKAGE igen MAXS43ACPA 0Cto+70C 8 Plastic DIP 12 MAX543BCPA 0Cto+70C 8 Plastic DIP +H MAX543ACSA 0Cto+70C 8SO +12 MAX543BCSA O0Cto+70C 8SO +H MAX543ACWE 0C to +70C 16 Wide SO 41/2 MAX543BCWE O0Cto+70C 16 Wide SO +H MAX543BC/D OC to +70C Dice" + MAXS43AEPA -40C to +85C 8 Plastic DIP +1/2 MAX543BEPA -40C to +85C 8 Plastic DIP +H Ordering information continued on last page. * Contact factory far dice specifications. Pin Configurations TOP VIEW pP-Controlled Systems . 1 Programmable Amplifiers/Attenuators veer (| maaxian [2% Digitally Controlled Filters Fes[e] MAX543 [7] CLK Fi ti I Di tout [3] 6 | Sel unctiona jagram GND [a] 5] TOAD wer Les DIP maxim 12-BIT Ree | lout MAX543 DAG ~ e oT An aan a] Fre DAC REGISTER L vpo GND 4 MAX543 [7] VREF LOAD [3 6 | Voo Tt q [GND sat [4] e CLK SHIFT REGISTER : t so | T I Note: 8-DIP and 8-SOIC Pinouts differ. LOAD CLK SRI Wide SO on last page. MAXLAA Maxim Integrated Products 1 Call toll free 1-800-998-8800 for free samples or literature. EvVSxvMAX543 CMOS, 12-Bit, Serial-Input Multiplying DAC ABSOLUTE MAXIMUM RATINGS VDDtOGND 00... ccc ec eee eee +17V VREFtoGND 20... ce ee eee +25V VRFB to GND 00. ce eee +25V Digital Input Voltage toGND ............. -0.3V, Vop + 0.3V VIOUT toGND ... 0. eee eee eee -0.3V, Vop + 0.3V Continuous Power Dissipation (TA = +70C) 8-Pin Plastic DIP (derate 9.09mW/C above +70C) .. 727mW 8-Pin SO (derate 5.88mW/C above +70C) ........ 47imW 16-Pin Wide SO (derate 9.52mW/"C above +70C) .. 762mW 8-Pin CERDIP (derate 8.00mW/"C above +70C) .... 640mW Operating Temperature Ranges: MAX543AC/BC _ ww. eee 0C to +70C MAXS43AE/BE __ ww... eee eee -40C to +85C MAXS543AM/BMJA .....0.0.... 00 e eee -55C to +125C Storage Temperature Range .............. -65C to +150C Lead Temperature (soldering, 10sec) .............. +300C Stresses beyond those listed under Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Vop = +5V, +12V or +15V; VREF = +10V; ViouT = GND = OV; Ta = TMIN to Tmax, unless otherwise noted.) (Note 1) PARAMETER _| SYMBOL | CONDITIONS MIN TYP MAX | UNITS STATIC PERFORMANCE Resolution N 12 Bits Integral Nonlinearity INL MAXS43A V2 | icp MAX543B +1 : : + art Guaranteed monotonic to 12 bits MAX543A 11/2 Differential Nonlinearity DNL over temperature MAX543B i LSB MAX543A +1 : Usin Ta = +25C Gain Error FSE inter eal Are MAX543B +2 LSB Ta =TMIN to TMax | All grades +2 Gain Tempco a AGain/ATemp (Note 2) TCFS Using internal Rep +1 +5 = | ppm/C DC Supply Rejection PSR AVppD = +5% +0.001 | %/% DYNAMIC PERFORMANCE (Note 2) Ta = +25C, to 1/2LSB, lout load is 100Q1 I3pF, Current Settling Time ts DAC register alternately loaded with all 1s and 0.25 1 ys all Os VREF = OV, lout lead is 1000 | 13pF, Digital-to-Analog Glitch Q one. register alternately loaded with all 1s and 2 20 nv-s all Os AC Feedthrough at lout FTE vo OVp-p at 10kHz, DAC register loaded 0.4 1 mp-p Total Harmonic Distortion THD | VREF 6Vims at kHz, DAC register loaded 85 dB Output Noise-Voltage Density en our to 100kHz, measured between Rrg and 13 15 nVANHz REFERENCE INPUT Input Resistance RREF 7 11 15 kQ. Input Resistance Tempco TCR -200 ppm/C 2 MAXIAACMOS, 12-Bit, Serial-Input Multiplying DAC ELECTRICAL CHARACTERISTICS (continued) (VoD = +5V, +12V or +15V; VREF = +10V; ViouT = GND = OV; Ta = TMIN to TMaAx, unless otherwise noted.) (Note 1) EvrSxvN PARAMETER | sYMBot | CONDITIONS [ MIN TYP MAX | UNITS ANALOG OUTPUT = +25" All grad . LeakageC | DAC register masse MAXS4SACIBCI == = | eakage Current joaded with nA OUT 9 LKG all Os Aa MN to AE/BE +25 MAX543AM/BM +100 . DAC register loaded with all Os 55 80 | Capacitance (Note 2 Cout F ura ( ) ou DAC register loaded with all 1s 85 110 p DIGITAL INPUTS Input High Voltage VIH Vop = 5V 24 Vv Vpp = 15V 13.5 Input Low Voltage VIL Vop = 5V 0.8 Vv Vpp = 15V 1.5 Input Leakage Current lin Digital inputs at OV or Vop +1 pA Input Capacitance (Note 2) CIN Digital inputs at OV or Vpp 8 pF SWITCHING CHARACTERISTICS (Note 3) CLK Pulse Width High tCH 90 ns CLK Pulse Width Low tcL 120 ns SRI Data to CLK Setup tos 40 ns SRI Data to CLK Hold tDH 80 ns LOAD Pulse Width {LD 120 ns LSB CLK to LOAD tsL 0 ns LOAD High to CLK tic 0 ns POWER SUPPLY Vpp Range Vpp Vpp = 12V or 15V +11.40 +15.75 Vv Vpp = 5V +4.75 +5.25 Ipp Range Ipp All digital inputs at Vi_ or VIH 500 yA All digital inputs at OV or Vpp 5 100 Note 1: Tests are performed at Vpp = +5V and Vop = +15V. Operation at +12V is guaranteed by power-supply tejection (PSR) tests. Note 2: Guaranteed by design, not subject to test. Note 3: Sample tested to 0.1% AQL. MA AXAMAX543 CMOS, 12-Bit, Serial-Input Multiplying DAC GAIN (dB) THRESHOLD VOLTAGE (v) GAIN vs. FREQUENCY (OUTPUT AMPLIFIER: MAX400) 0 DIGITAL INPUT = "1 4 1441111711 -48 DIGITAL INPUT . 0000 0 ~y nn Voo = +6V VREF ; : oom 120 Jaze 1k 10k 400k 1M 10M FREQUENCY (Hz) LOGIC THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE 40 wpm wo o + 2 en oo o = wo an ~ o = as ao on THD (dB) LINEARITY ERROR (LSB) ONL (LSBs) TOTAL HARMONIC DISTORTION vs. FREQUENCY (MULTIPLYING MODE) Vo = +5V VIN = 6Vims OUTPUT AMPLIFIER: MAX400 Ta= 425C 10 100 1k 10k 100k FREQUENCY (Hz) LINEARITY ERROR vs. DIGITAL CODE 1.00 T om | ge 0.50 0.25 0 0.25 -0.50 0.75 -1.00 0 1024 2048 3072 4096 DIGITAL INPUT CODE (DECIMAL) DIFFERENTIAL NONLINEARITY ERROR vs. REFERENCE VOLTAGE 0.50 0.25 ~0.25 -0.50 -0.75 Ibo (mA) INL (LSB) Typical Operating Characteristics SUPPLY CURRENT vs. LOGIC INPUT VOLTAGE Vop = +5V 0 1 2 3 4 Vin (V) INTEGRAL NONLINEARITY ERROR vs. REFERENCE VOLTAGE 0.50 0.25 0.25 -0.50 0.75 2 4 6 8 10 VREF (V) MA AXLANCMOS, 12-Bit, Serial-Input Detailed Description D/A Gonverter The MAX543 DAC circuit consists of a laser-trimmed, thin-film R-2R resistor array with NMOS current switches, as shown in Figure 1. Binary weighted currents are switched to either louT or GND depending on the status of each input data bit. Although the current at louT and GND depends on the digital input code, the sum of the two output currents is always equal to the input current at VREF. The current output (louT) can be converted into a voltage by adding an external output amplifier (Figure 3). The VREF input accepts a wide range of signals, including fixed and time-varying voltage or current inputs. If a current source is used for the reference input, then a low-tempco external resistor should be used for RrB to minimize gain variation with temperature. The internal feedback resistor (RFB)is compensated with an NMOS switch that matches the NMOS switches used in the R-2R array. This results in excellent supply rejec- tion and gain-temperature coefficient. The IOUT pin output capacitance (COUT) is code depen- dent and is typically 55pF with all switches to GND and 85pF with all switches to IOUT. Digital Circuit Figure 2 shows the MAX543 timing diagram. The most significant bit (MSB) is always loaded first on the rising edge of the clock. When all data is shifted into the MAX543, the DAC register is loaded by taking the LOAD signal low. The DAC register is transparent when LOAD is low and latched when LOAD is high. If the LOAD signal is taken low before the LSB bit is fully shifted into the shift register, the DAC output can produce a glitch. If this is Multiplying DAC lout Figure 1. MAX543 Simplified Circuit undesirable, the LOAD signal can be delayed 30ns after the rising edge of the LSB clock edge to avoid this condition. The MAX543's input buffer inverters act as level shifters, converting TTL levels into CMOS logic levels. These input buffers are TTL and 5V-CMOS compatible (0.8V and 2.4V) at Vpp = 5V. For Vop = 15V the input buffers are CMOS compatible (1.5V and 13.5V). At this supply voltage, the input buffers are in their linear region when the input voltages are between 1V and 6V. Therefore, to minimize high supply currents, the digital input voltages should be kept as close to the supply and ground volt- ages (VoD and GND) as possible. Circuit Configurations Unipolar Operation Figure 3 shows the MAX543s basic application. This circuit is used for unipolar operation or 2-quadrant multi- plication. The code table for this mode is given in Table 1. Note that the polarity of the output is the inverse of the reference voltage, VREF. SRI X BIT 11 BIT 10 x MSB** ! os BITO XXX ae ] oH > ! | 1 | tcH tet 2 " CLK INPUT | }-}__1 LOAD SERIAL DATA INTO INPUT REGISTER LOAD $- | Figure 2. Write-Cycle Timing Diagram MAAXIAN EPSXVNMAX543 Multiplying DAC RA VREF +5V 20k Rt | R 1009, 20k VREF Vop Vop Rep Mm axXiAn \OUT Srl RB VREF _ Rt REF MAXSAS GND | MAXIM 1000 | CLK TOAD _ sal Vout MAX543 AADAAA CLK lout MAX400 MAX400 tOAD ] GND Figure 4. Bipolar Operation Figure 3. Unipolar Operation Table 2. Offset Binary-Code Table for Circuit of Figure 4 Table 1. Unipolar Binary-Code Table DIGITAL INPUT for Circult of Figure 3 ANALOG OUTPUT MSB LSB DIGITAL INPUT ANALOG OUTPUT ddq40049444111 +vrer (2042 2047 MSB LSB 2048 4095 41411 1111 #191171 -vrer (ee | 1000 0000 0001 +VREF x08 | 1000 0000 o000| -vrEF(2048)__ REF 1000 0000 0000 0 4096| 2 1 0000 oo000 0001 -VREF (555 O141 1111 #211171 VREF 7008 | 0000 0000 0000 a) 0000 0000 0000 _vrer (2048 2048 In many applications, gain adjustment will not be neces- Table 3. Twos-Complement Code Table sary since the parts gain accuracy is sufficient, or is trimmed at the reference source. In these cases, resis- DIGITAL INPUT ANALOG OUTPUT tors R1 and R2 in Figure 3 can be omitted. If the gain is MSB LSB trimmed and the DAC is operated over a wide tempera- 047 ture range, use low-tempco (<300ppm/"C) resistors for o144 4111 #1111 +VREF [358 | 2048 R1 and R2. Capacitor C1 provides phase compensation and re- 0000 0000 0001 +VREF (roe qd duces overshoot and ringing when fast amplifiers are used at the output of the DAC. 0000 oooo 0000 0 Bipolar Operation j Figure 4 shows the MAX543 operating in bipolar (or Vqad 444d 1444 -VREF (zo 4-quadrant multiplying) mode. A second amplifier and three matched resistors (R3 , R4 and R5) are required. 1000 0000 0000 -VREF (F5cs | These resistors must be of the same material (preferably 2048 MAXIMACMOS, 12-Bit, Serial-input metal film or wire-wound) for good temperature tracking characteristics (<15ppm/C), and should match to 0.01% for 12-bit performance. The output code is offset binary and is listed in Table 2. In multiplying applications, the MSB determines output polarity while the other 11 bits control the amplitude. The MSB can be inverted in software using an exclusive-OR instruction to make the MAX543 work with twos-complement coding. Table 3 shows the code relationships to output voltage for twos- complement operation. To adjust the circuit, load the DAC with a code of 1000 0000 0000 and trim R1 for a OV output. With R1 and R2 omitted, an alternative zero trim is needed to adjust the ratio of R38 and R4 for OV out. Trim full scale by loading the DAC with all Os or all 1s, and adjusting VREFs amplitude or varying R5 until the desired positive or negative output is obtained. In many applications, the gain adjustment will not be necessary, especially when using parts with a guaranteed maximum +1LSB gain error. In these cases the gain can be trimmed at the reference source and resistors R1 and R2 in Figure 4 omitted. However, if the trims are desired and the DAC is operated over a wide temperature range, then low- tempco (<300ppm/*C) resistors should be used for R1 and Re. Single-Supply Operation (Voltage Mode} The MAX543 can be conveniently used in single-supply (voltage mode) operation with louT biased at any voltage between GND and Vpp. louT must not be allowed to go 0.3V lower than the GND or 0.3V higher than Vpp. Oth- erwise, internal diodes wouid turn on, causing a high current flow from the supply that could damage the device. Figure 5 shows the MAX543 connected as a voltage-out- put DAC. lout is connected to the reference-voltage +15V Vop lou apace VREFF Vout MAX543 GND _ SRI REFERENCE VOLTAGE CLK_LOAD| 15V CMOS DIGITAL INPUTS qigure 5. Single-Supply Operation Using Voltage-Switching lode Multiplying DAC source and GND is grounded. The DAC output now appears at the VREF pin, which has a constant imped- ance equal to the reference input resistance (typically 11kQ). This output should be buffered with an op amp when a lower output impedance is required. RFs pin is not used in this mode. The input impedance of the reference input (!0UT) for this mode is code dependent, and the circuit's response time depends on the reference sources behavior with chang- ing load conditions. Two advantages of voltage-mode operation are single- supply operation and that a negative reference is not required for a positive output. Note that the reference input (\OUT) must always be positive and is limited to no more than 2.5V when Vpp is 15V. If the reference voltage is greater than 2.5V or VpD is reduced, resistance mis- matches in the DACs internal NMOS switches result in degraded integral (INL) and differential nonlinearity (DNL). The unipolar and bipolar circuits in Figures 3 and 4 can all be converted to voltage-output mode. MAX543 Opto-Isolated Application Figure 6a shows the MAX543 interface to optocouplers for isolated barrier applications. Three optocouplers (OC1, OC2 and OC3) carry the serial data and clocking signals across the isolation barrier. Isolated power sources, V+ and V-, supply the MAX543, the output amplifier and optocouplers. [f data word updates are infrequent and large analog output transitions can be tolerated while serial data is being clocked in, then parts count can be reduced by eliminating optocoupler OC3 and tying LOAD (pin 5) of the MAX543 low. When using type 6N136 optocouplers, this circuit ac- cepts serial data at a maximum clock rate of 100kHZ, or 130s per data word. The SERIAL DATA and LOAD signals should change coincident with the falling edge of CLOCK, as shown in the timing diagram (Figure 6b). A positive CLOCK cycle is masked during the time LOAD is low. The MAX543 will also work with 5V isolated supplies using the optocoupler circuit of Figure 6a. Change the values of R1 through R3 to 3kQ to maintain switching speed with the lower value of V+. Current drawn from V- for the MAX543 and optocoupler is 3.5mA at a 100kHz clock rate when all data bits are set to 0. V+ current drops to O (excluding reference and op-amp current) when no new data is being loaded and CLOCK, SERIAL DATA, and LOAD are static high. MAAXILIA ersxvMAX543 CMOS, 12-Bit, Serial-Input Multiplying DAC oct | one vy 8 +5V 2000 MA y sain + Vi y 8k 6 cik 3 en) 4 5 | pi OC2 _6N136 tour v 8} ff Vp vREF |-_ REFERENCE INPUT 2000, , MAXI Ww / TSR CLK MAX543 Rep t fn 8k +15V SERIAL : 3 6 para * four ANALOG OUTPUT mS Pe LOAD GND AXA - -15V C3 6N6 MAx400 4 8 we? 1? = RI" . ip > 8k __ q 6 LOAD ND 4 5 | P2 | NON-ISOLATED | ISOLATED *TTL- OR CMOS-LOGIC DEVICE **V4 = 15V. FOR V+ = 5V, USE 3k62 FOR RI, R2, R3 Figure 6a. MAX543 Opto-Coupled Application CLK DATA xX Xxx X Bi X 62 X Bs YX B4 X Bb Y 66 X BY YX BB X BO X BIO X Bi X BZ X xx X BI LOAD IDLE WORD N WORD N+1 Figure 6b. MAX543 Opto-lsolated Timing 8 MAXILAACMOS, 12-Bit, Serial-Input Multiplying DAC 8) ADDRESS BUS (16) A0-15 / ALE 8212 rye Ao we = 74LS138 8085 +5VE3 ADDRESS DECODER (8) AD0-7 DATA SoD ANALOG CIRCUITRY OMITTED FOR SIMPLICITY Figure 7, MAX543 8085 interface Microprocessor Interfacing Interfacing to the 8085 Figure 7 shows the MAX543 interfacing to the 8085 pP. The SOD line from the 8085 sends serial data to the DAC. This data is clocked into the MAX543 by executing mem- ory-write instructions. Generate the CLK input for the DAC by decoding address 8000 and WR signal. The data is transferred into the DAC register with a memeory- write instruction to address A000, which brings LOAD low. The data for the MAX543 is stored in right-justified format in registers H and L of the 8085. interfacing to the MC6800 Figure 8 shows the MAX543 interfacing to the MC6800 pP. Transfer the data into the MAX543 by executing successive memory-write instructions while changing the data between writes to construct the serial data to the DAC. The D7 data line is used for the SRI signal. The lower half of the memory location 0000 holds the four MSB data bits, and the 0001 location holds the eight LSB data bits. The memory address 2000, R/W, and 02 are decoded to genenrate the CLK signal for the DAC with each memory write. Similarly, amemory write to address 4000 transfers data into the DAC register by bringing the MAX543s LOAD input low. A0 16-BIT DATA BUS AIS fr RW Ei AQ A2 02 74L$138 MC6800 E3 ADDRESS coe DECODER 00 8-BIT DATA BUS 07 LOAD CLK MAAMXIAA MAX543 ANALOG CIRCUITRY OMITTED FOR SIMPLICITY Figure 8. MAX543 MC6800 Interface Applications Information Output Amplifier Offset For best linearity, terminate IouT and GND at exactly OV. In most applications, IoUT is connected to the summing junction of an inverting op amp. The amplifierss input offset voltage can degrade the DACs linearity by causing IOUT to be terminated to a non-zero voltage. The result- ing error is: Error Voltage = Vos (1 + RFB/Ro) where Vos is the op amps offset and Ro is the DACs output resistance. Ro is a function of the digital input code, and varies from approximately 11kQ to 33kQ. The error voltage range is then typically 4/3Vos to 2Vos - a change of 2/3Vos. Therefore, an amplifier with 3mV of offset will degrade the linearity by 2mV almost a full LSB with a 10V reference voltage. For best linearity, use a low-offset amplifier such as the MAX400, otherwise the amplifier offset must be trimmed to zero. A good guide rule is that Vos should be no more than 1/10LSB. The output-amplifer input bias current (lB) can also limit performance since IB X RFB generates an offset error. Therefore, IB should be much less than the DAC output current for 1LSB, typically 250nA with VREF = 10V. One tenth of this value, 25nA, is recommended. Offset and linearity can also be impaired if the output-amplifier non- MAAXIAN EvVSXVNMAX543 CMOS, 12-Bit, Serial-Input Multiplying DAC inverting input is grounded through a bias-current com- pensation resistor." This resistor adds to the offset at this pin and should not be used. Best performance is ob- tained when the noninverting input is directly connected to ground. Dynamic Considerations In static or DC applications, the output amplifiers AC characteristics are not critical. In higher-speed applica- tions where either the reference input is an AC signal or the DAC output must quickly settle to a new pro- grammmed value, the AC parameters of the output op amp must be considered. Another error source in dynamic applications is parasitic coupling of the signal from the VREF pin to louT. This is normally a function of board layout and lead-to-lead package capacitance. Noise signals can also be in- jected into the DAC outputs when the digital inputs are switched. This digital feedthrough is usually dependent on ciruit-board layout and on-chip capacitive coupling. Layout-induced feedthrough can be minimized with guard traces beween digital inputs, VREF, and IOUT pins. The DAC output follows the digital inputs when the LOAD pin is low. In this mode, invalid outputs and voltage glitches can appear at the DAC output. Keeping the LOAD input high until all the data is shifted into the MAX543 eliminates this problem. Compensation Acompenation capacitor, C1, may be required when the DAC is used with a high-speed output amplifier. The purpose of the capacitor is to cancel the pole formed by the DAC output capacitance, Cour, and the internal feedback resistor, RFB. Its value depends on the type of op amp used, but typically ranges from 10pF to 33pF. Too small a value causes output ringing, while excess capacitance overdamps the output. The size of C1 can be minimized and the output-voltage settling time im- proved by keeping the cirucit-boad trace and stray ca- pacitance at IOUT as low as possible. 10 Grounding and Bypassing Since ioUT and the noninverting input of the output amplifier are sensitive to offset voltages, nodes that are to be grounded should be connected directly to "single point" ground through a separate, low-resistance (less than 0.2Q) connection. The current at louT and GND varies with input code, creating a code-dependent error if these terminals are connected to ground (or a virtural ground") through a resistive path. Connect a 1pF bypass capacitor in parallel with a 0.01pF ceramic capacitor across VDD and GND, and as close to the pins as possible. The MAX543 has high-impedance digital inputs. To min- imize noise pick-up, tie them to either VDD or GND when not in use. It is good practice to connect active inputs to VDD or GND through high-value resistors (1MQ) to pre- vent static charge accumulation if the pins are left float- ing, such as when a circuit card is left unconnected. MAXIAACMOS, 12-Bit, Serial-Input Multiplying DAC Pin Configurations (continued) _ Ordering Information (continued) = PART TEMP. RANGE PIN-PACKAGE "iEERTY > TOP VIEW (LSBs) | Se ; MAX543AESA -40C to +85C 8 SO 1/2 ao ne. 11] ig] NC. MAX543BESA -40C to +85C 8 SO H A nc. [2| maxian H5] N.C. MAX543AEWE -40C to +85C 16 Wide SO +1/2 W veer [3] 14] voo MAX543BEWE -40C to +85C 16 Wide SO H Pre (4 3} CLK MAX543AEJA -40C10+85C 8 CERDIP 41/2 lor [5 12] sat MAX543BEJA -40C to +85C 8 CERDIP H ano [6 4] LOAD MAX543AMJA -55C to +125C 8 CERDIP 1/2 ono [7| ro} Nc. MAX543BMJA -55C to +125C 8 CERDIP +1 Nc. [| [9] N.C. WIDESO * PINS 6 AND 7 MUST BE CONNECTED TOGETHER AS CLOSE TO THE PACKAGE AS POSSIBLE Chip Topography Ree is Vpp 0.081" Br CLK __ il (2.06mm) 1) lout iii SRI LOAD ila es MAXLAAN "1MAX543 CMOS, 12-Bit, Serial-Input Multiplying DAC Package information NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2 aw MOLD FLASH DR PROTRUSIONS NOT 70 EXCEED ISmn (006 CONTROLLING DIMENSION. HILLIMETER MEETS JEDEC MS-012 AA. Ho 8 G4 i | Io fo) oo), q Ta os fpo - D i re 1 tt a3 Co aAAeg 4 Lu j , ia i 4 hi Lal f ~wifL a HT ; | u 3 Y c + L e al Bl le eA el B eB NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS L/vi MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 San eee 2. CONTROLLING DIMENSION: INCH BL PDIP OUTLINE 3.MEETS JEDEC MS-001 AB Ca rar av 21-324 [a [/ INCHES MILLIMETERS EH (2S aL SOIC GUTLINE MAXIM | [21-325 [a [7 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 Maxim integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 1994 Maxim Integrated Products Printed USA MAXIM is a registered trademark of Maxim Integrated Products.