FEDD514400D-01 Issue Date: Mar. 8, 2011 MSM514400D 1,048,576-Word x 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM514400D is a 1,048,576-word 4-bit dynamic RAM fabricated in LAPIS Semiconductor's silicon-gate CMOS technology. The MSM514400D achieves high integration, high-speed operation, and low-power consumption because LAPIS Semiconductor manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM514400D is available in a 26/20-pin plastic SOJ. FEATURES 1,048,576-word 4-bit configuration Single 5V power supply, 10% tolerance Input : TTL compatible, low input capacitance Output : TTL compatible, 3-state Refresh : 1024 cycles/16 ms, Fast page mode, read modify write capability CAS before RAS refresh, hidden refresh, RAS-only refresh capability Multi-bit test mode capability Package options: 26/20-pin 300mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM514400D -xxJS) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) Power Dissipation Cycle Time (Min.) Operating (Max.) Standby (Max.) tRAC tAA tCAC tOEA MSM514400D-60 60ns 30ns 15ns 15ns 110ns 495mW MSM514400D-70 70ns 35ns 20ns 20ns 130ns 440mW 5.5mW 1/15 FEDD514400D-01 MSM514400D PIN CONFIGRATION (TOP VIEW) DQ1 DQ2 WE RAS A9 1 2 3 4 5 26 25 24 23 22 VSS DQ4 DQ3 CAS OE A0 9 A1 10 A2 11 A3 12 VCC 13 18 17 16 15 14 A8 A7 A6 A5 A4 26/20-Pin Plastic SOJ Pin Name Function A0-A9 Address Input RAS Row Address Strobe CAS Column Address Strobe DQ1-DQ4 Data Input/Data Output OE Output Enable WE Write Enable VCC Power Supply (5 V) VSS Ground (0 V) Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/15 FEDD514400D-01 MSM514400D ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit Voltage on Any Pin Relative to VSS VT 1.0 to 7.0 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 C Storage Temperature Tstg 55 to 150 C *: Ta = 25C Recommended Operating Conditions (Ta = 0 C to 70 C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol Min. Typ. Max. Unit VCC VSS VIH VIL 4.5 5.0 5.5 V 0 0 0 V 2.4 6.5 V 1.0 0.8 V Capacitance (Vcc = 5V 10%, Ta = 25C, f=1MHz) Parameter Input Capacitance (A0 - A9) Input Capacitance (RAS, CAS, WE, OE) Output Capacitance (DQ1 - DQ4) Symbol Typ. Max. Unit CIN1 CIN2 CI/O 6 pF 7 pF 7 pF 3/15 FEDD514400D-01 MSM514400D DC Characteristics (Vcc = 5V 10%, Ta = 0C to 70C) Parameter Symbol MSM514400D -60 MSM514400D -70 Min. Max. Min. Max. 2.4 VCC 2.4 VCC V 0 0.4 0 0.4 V 10 10 10 10 A 10 10 10 10 A 90 80 mA 1, 2 RAS, CAS = VIH 2 2 RAS, CAS VCC 0.2V mA 1 1 1 90 80 mA 1, 2 5 5 mA 1 90 80 mA 1, 2 70 60 mA 1, 3 Condition Output High Voltage VOH IOH = 5.0mA Output Low Voltage VOL IOL = 4.2mA Unit Note 0V VI 6.5V; Input Leakage Current ILI Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) Power Supply Current (Standby) Average Power Supply Current ICC2 (Standby) 0V VO 5.5V RAS, CAS cycling, tRC = Min. ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable Average Power Supply Current ICC6 (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) Notes: 1. 2. 3. DQ disable RAS cycling, (RAS-only Refresh) Power Supply Current All other pins not under test = 0V RAS = cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tPC = Min. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. 4/15 FEDD514400D-01 MSM514400D AC Characteristic (1/2) (Vcc = 5V 10%, Ta = 0C to 70C) Note1,2,3,11,12 Parameter Symbol MSM514400D-60 MSM514400D-70 unit Note Min. Max. Min. Max. tRC 110 130 ns tRWC 150 180 ns tPC 40 45 ns tPRWC 85 95 ns Access Time from RAS tRAC 60 70 ns 4, 5, 6 Access Time from CAS tCAC 15 20 ns 4, 5 Access Time from Column Address tAA 30 35 ns 4, 6 Access Time from CAS Precharge tCPA 35 40 ns 4 Access Time from OE tOEA 15 20 ns 4 Output Low Impedance Time from CAS tCLZ 0 0 ns 4 CAS to Data Output Buffer Turn-off Delay Time tOFF 0 15 0 20 ns 7 OE to Data Output Buffer Turn-off Delay Time tOEZ 0 15 0 20 ns 7 Transition Time tT 3 50 3 50 ns 3 Refresh Period tREF 16 16 ns RAS Precharge Time tRP 40 50 ns RAS Pulse Width tRAS 60 10,000 70 10,000 ns RAS Pulse Width (Fast Page Mode) tRASP 60 100,000 70 100,000 ns RAS Hold Time tRSH 15 20 ns RAS Hold Time referenced to OE tROH 15 20 ns CAS Precharge Time (Fast Page Mode) tCP 10 10 ns CAS Pulse Width tCAS 15 10,000 20 10,000 ns CAS Hold Time tCSH 60 70 ns CAS to RAS Precharge Time tCRP 5 5 ns RAS Hold Time from CAS Precharge tRHCP 35 40 ns RAS to CAS Delay Time tRCD 20 45 20 50 ns 5 RAS to Column Address Delay Time tRAD 15 30 15 35 ns 6 Row Address Set-up Time tASR 0 0 ns Row Address Hold Time tRAH 10 10 ns Column Address Set-up Time tASC 0 0 ns Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time 5/15 FEDD514400D-01 MSM514400D AC Characteristic (2/2) (Vcc = 5V 10%, Ta = 0C to 70C) Note1,2,3,11,12 Parameter Symbol MSM514400D -60 MSM514400D -70 Min. Max. Min. Max. unit Note Column Address Hold Time tCAH 15 15 ns Column Address Hold Time from RAS tAR 50 55 ns Column Address to RAS Lead Time tRAL 30 35 ns Read Command Set-up Time tRCS 0 0 ns Read Command Hold Time tRCH 0 0 ns 8 Read Command Hold Time referenced to RAS tRRH 0 0 ns 8 Write Command Set-up Time tWCS 0 0 ns 9 Write Command Hold Time tWCH 10 10 ns Write Command Hold Time from RAS tWCR 45 50 ns Write Command Pulse Width tWP 10 10 ns OE Command Hold Time tOEH 15 20 ns Write Command to RAS Lead Time tRWL 15 20 ns Write Command to CAS Lead Time tCWL 15 20 ns Data-in Set-up Time tDS 0 0 ns 10 Data-in Hold Time tDH 15 15 ns 10 Data-in Hold Time from RAS tDHR 50 55 ns OE to Data-in Delay Time tOED 15 20 ns CAS to WE Delay Time tCWD 35 45 ns 9 Column Address to WE Delay Time tAWD 50 60 ns 9 RAS to WE Delay Time tRWD 80 95 ns 9 CAS Precharge WE Delay Time tCPWD 55 65 ns 9 CAS Active Delay Time from RAS Precharge tRPC 10 10 ns RAS to CAS Set-up Time (CAS before RAS) tCSR 5 5 ns RAS to CAS Hold Time (CAS before RAS) tCHR 10 10 ns WE to RAS Precharge time (CAS before RAS) tWRP 10 10 ns tWRH 10 10 ns RAS to WE Set-up Time (Test mode) tWTS 10 10 ns RAS to WE Hold Time (Test mode) tWTH 10 10 ns WE Hold Time from RAS (CAS before RAS) 6/15 FEDD514400D-01 MSM514400D Notes: 1. A start-up delay of 200s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.), tRWD tRWD(Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet in a 2-bit parallel test function. CA0 is not used. In read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 7/15 FEDD514400D-01 MSM514400D TIMING CHART Read Cycle RAS tRC tRAS VIH tRP VIL tCSH tCRP CAS tRCD VIH tRAD VIL tRAL tAR tASR Address WE OE VIH VIL tRAH Row tCRP tRSH tCAS tASC tCAH Column tRCS VIH tRRH tAA VIL tOEA VIH VIL tCAC tRAC DQ tRCH tROH tOFF tOEZ tCLZ VOH Valid Data-out Open VOL "H" or "L" Write Cycle (Early Write) RAS tRC tRAS VIH tRP VIL tCSH tCRP CAS VIH WE OE DQ VIH VIL tCRP tRSH tCAS tRAD VIL tASR Address tRCD tAR tRAH tRAL tASC Row tCAH Column tCWL tWCS tWP VIH VIL tWC tWCR tRWL VIH VIL VIH VIL tDHR tDS tDH Valid Data-in Open "H" or "L" 8/15 FEDD514400D-01 MSM514400D Read Modify Write Cycle tRWC RAS tRAS VIH tRP VIL tCSH tCRP CAS VIH VIH VIL tCRP tRSH tCAS tRAD VIL tAR tASR Address tRCD tRAH tASC Row tCWL tRWL tCAH Colum tRCS tCWD tWP tRWD WE OE VIH VIL tAWD tAA tOEH tOEA VIH tOED VIL tCAC tRAC DQ VI/OH VI/OL tOEZ tCLZ Valid Data-out tDS tDH Valid Data-in "H" or "L" 9/15 FEDD514400D-01 MSM514400D Fast Page Mode Read Cycle RAS tAR VIH VIL CAS VIH VIL VIH VIL tCP tRAD tCSH tASC tCP tRAH Row tASC Column tCAH Column tRCS tRCH tRCS tRCH VIH VIL tAA tAA tAA tOEA VIH VIL tRAC tCPA tOFF tOEZ tCAC DQ tASC Column tRCH tCRP tRAL tCAH tOEA OE tRSH tCAS tCAS tCAH tRCS WE tRHCP tCAS tASR Address tPC tRCD tCRP tRP tRASP tCLZ VOH tCPA tOFF tCAC tOEZ tCLZ Valid Data-out VOL tRRH tOEA tOFF tCAC tOEZ tCLZ Valid Data-out Valid Data-out "H" or "L" Fast Page Mode Write Cycle (Early Write) tRP tRASP RAS CAS tAR VIH VIL tCRP VIH VIL tRAH tASC Row tWCR VIH VIL tCSH tCAH DQ VIL tCAH tASC Column tCWL tWCH tWP tRSH tCAS tCRP Column tRWL tCWL tWCS tRAL tCAH tWCH tWP tCWL tWCS tWP tWCH tDHR tDS VIH tASC Column tWCS WE tCP tCAS tRAD VIL tASR Address tCP tRCD tCAS VIH tRHPC tPC tDH Valid Data-in tDS tDH Valid Data-in tDS tDH Valid Data-in Note: OE = "H" or "L" "H" or "L" 10/15 FEDD514400D-01 MSM514400D Fast Page Mode Read Modify Write cycle tRASP RAS CAS tCSH VIH VIL tRCD VIL tCAH tCWL tASC Row tAR VIH tRCS tAWD VIL tWP tOEA tCAC tCWD tAWD tAWD VI/OL Out tCLZ tROH tDH tCPA tAA tDS tOED tOEZ tCAC tDS tCAC Out In tDH tOEA tOED tOEZ VI/OH tRWL tWP tWP tOEA tOEZ tCWL tCPWD tCWD tAA tDS tRCS tCPWD tOED VIL tRAL Column tCPA tDH VIH tASC tCWL tRWD tCWD tAA DQ tCAH Column tRAC OE tCRP tCAS tASC Column tRCS WE tCP tCAS tRAD VIL VIH tCP tCAS tRP tRSH tCAH VIH tRAH tASR Address tPRWC In Out In tCLZ tCLZ Note: In = Valid Data-in, Out = Valid Data-out "H" or "L" RAS-only Refresh Cycle tRC RAS tRAS VIH tRP VIL tCRP CAS Address DQ tRPC VIH VIL VIH VIL VOH VOL tASR tRAH Row tOFF Open Note: WE, OE = "H" or "L" "H" or "L" 11/15 FEDD514400D-01 MSM514400D CAS before RAS Refresh Cycle tRP RAS CAS WE tRC tRAS VIH tRPC tCP VIL tRP tCSR tRPC tCHR VIH VIL tWRP tWRH tWRP VIH VIL tOFF DQ VOH Open VOL Note: OE, Address = "H" or "L" "H" or "L" Hidden Refresh Read Cycle tRC RAS CAS VIH VIL tCRP VIH VIL tRCD tRSH Row tCAH Column tCAC VIH VIL DQ tRAL VIL VOL tWRP tWRH tOFF tOEA VIH VOH tRRH tAA tROH OE tRP tAR tRAH tASC tRCS WE tRP tRAD VIL VIH tRAS tCHR tASR Address tRC tRAS tRAC tOEZ tCLZ Open Valid Data-out "H" or "L" 12/15 FEDD514400D-01 MSM514400D Hidden Refresh Write Cycle tRC RAS CAS VIH VIL tCRP tRAS tRCD tRSH VIH tRAD VIL VIH VIL tRAH tRAL tASC Row tCAH Colum tAR tWCR WE tWP VIH VIL tWCH tWCS OE tWRP tWRH VIH VIL tDHR tDS DQ tRP tRP tCHR tASR Address tRC tRAS VIH tDH Valid Data-in VIL "H" or "L" Test Mode-in Cycle tRC tRP RAS CAS VIH VIL tRAS tRPC tCP tCSR VIL tWTS WE DQ tCHR VIH VIH VIL VIH VIL tWTH tOFF Open Note: OE, Address = "H" or "L" "H" or "L" 13/15 FEDD514400D-01 MSM514400D REVISION HISTORY Document No. FEDD514400D-01 Date Mar.8.2011 Page Previous Current Edition Edition - - Description First edition 14/15 FEDD514400D-01 MSM514400D NOTICE No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. 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