FEDD514400D-01
Issue Date: Mar. 8, 2011
MSM514400D
1,048,576-Word x 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
1/15
DESCRIPTION
The MSM514400D is a 1,048,576-word 4-bit dynamic RAM fabricated in LAPIS Semiconductor’s
silicon-gate CMOS technology. The MSM514400D achieves high integration, high-speed operation, and
low-power consumption because LAPIS Semiconductor manufactures the device in a quadruple-layer
polysilicon/double-layer metal CMOS process. The MSM514400D is available in a 26/20-pin plastic SOJ.
FEATURES
1,048,576-word 4-bit configuration
Single 5V power supply, 10% tolerance
Input : TTL compatible, low input capacitance
Output : TTL compatible, 3-state
Refresh : 1024 cycles/16 ms,
Fast page mode, read modify write capability
CAS before RAS refresh, hidden refresh, RAS-only refresh capability
Multi-bit test mode capability
Package options:
26/20-pin 300mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM514400D –xxJS)
xx indicates speed rank.
PRODUCT FAMILY
Access Time (Max.) Power Dissipation
Family tRAC t
AA t
CAC t
OEA
Cycle Time
(Min.) Operating (Max.) Standby (Max.)
MSM514400D-60 60ns 30ns 15ns 15ns 110ns 495mW
MSM514400D-70 70ns 35ns 20ns 20ns 130ns 440mW 5.5mW
FEDD514400D-01
MSM514400D
2/15
PIN CONFIGRATION (TOP VIEW)
Pin Name Function
A0–A9 Address Input
RAS Row Address Strobe
CAS Column Address Strobe
DQ1–DQ4 Data Input/Data Output
OE Output Enable
WE Write Enable
VCC Power Supply (5 V)
VSS Ground (0 V)
Note : The same power supply voltage must be provided to every VCC pin, and the
same GND voltage level must be provided to every VSS pin.
26/20-Pin Plastic SOJ
1
2
3
4
5
9
10
11
12
13
26
25
24
23
22
18
17
16
15
14
DQ2
WE
RAS
A9
DQ1 VSS
DQ4
DQ3
CAS
OE
A
8
A
7
A0
A1
A2
A3
VCC
A
6
A
5
A
4
FEDD514400D-01
MSM514400D
3/15
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Voltage on Any Pin Relative to VSS VT 1.0 to 7.0 V
Short Circuit Output Current IOS 50 mA
Power Dissipation PD* 1 W
Operating Temperature Topr 0 to 70 °C
Storage Temperature Tstg 55 to 150 °C
*: Ta = 25C
Recommended Operating Conditions
(Ta = 0 °C to 70 °C)
Parameter Symbol Min. Typ. Max. Unit
VCC 4.5 5.0 5.5 V
Power Supply Voltage VSS 0 0 0 V
Input High Voltage VIH 2.4 6.5 V
Input Low Voltage VIL 1.0 0.8 V
Capacitance
(Vcc = 5V 10%, Ta = 25°C, f=1MHz)
Parameter Symbol Typ. Max. Unit
Input Capacitance (A0 – A9) CIN1 6 pF
Input Capacitance (RAS, CAS, WE, OE) CIN2 7 pF
Output Capacitance (DQ1 – DQ4) CI/O 7 pF
FEDD514400D-01
MSM514400D
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DC Characteristics
(Vcc = 5V ± 10%, Ta = 0°C to 70°C)
MSM514400D
-60
MSM514400D
-70
Parameter Symbol Condition
Min. Max. Min. Max.
Unit Note
Output High Voltage VOH IOH = 5.0mA 2.4 VCC 2.4 VCC V
Output Low Voltage VOL I
OL = 4.2mA 0 0.4 0 0.4 V
Input Leakage Current ILI
0V VI 6.5V;
All other pins not
under test = 0V
10 10 10 10 A
Output Leakage Current ILO DQ disable
0V VO 5.5V 10 10 10 10 A
Average Power Supply
Current
(Operating)
ICC1 RAS, CAS cycling,
tRC = Min. 90 80 mA 1, 2
RAS, CAS = VIH 2 2
Power Supply Current
(Standby) ICC2 RAS, CAS
VCC 0.2V 1 1
mA 1
Average Power Supply
Current
(RAS-only Refresh)
ICC3
RAS cycling,
CAS = VIH,
tRC = Min.
90 80 mA 1, 2
Power Supply Current
(Standby) ICC5
RAS = VIH,
CAS = VIL,
DQ = enable
5 5 mA 1
Average Power Supply
Current
(CAS before RAS Refresh)
ICC6 RAS = cycling,
CAS before RAS 90 80 mA 1, 2
Average Power Supply
Current
(Fast Page Mode)
ICC7
RAS = VIL,
CAS cycling,
tPC = Min.
70 60 mA 1, 3
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while RAS = VIL.
3. The address can be changed once or less while CAS = VIH.
FEDD514400D-01
MSM514400D
5/15
AC Characteristic (1/2)
(Vcc = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3,11,12
MSM514400D-60 MSM514400D-70
Parameter Symbol
Min. Max. Min. Max.
unit Note
Random Read or Write Cycle Time tRC 110 130 ns
Read Modify Write Cycle Time tRWC 150 180 ns
Fast Page Mode Cycle Time tPC 40 45 ns
Fast Page Mode Read Modify Write
Cycle Time tPRWC 85 95 ns
Access Time from RAS tRAC 60 70 ns 4, 5, 6
Access Time from CAS tCAC 15 20 ns 4, 5
Access Time from Column Address tAA 30 35 ns 4, 6
Access Time from CAS Precharge tCPA 35 40 ns 4
Access Time from OE tOEA 15 20 ns 4
Output Low Impedance Time from CAS tCLZ 0 0 ns 4
CAS to Data Output Buffer Turn-off
Delay Time tOFF 0 15 0 20 ns 7
OE to Data Output Buffer Turn-off Delay
Time tOEZ 0 15 0 20 ns 7
Transition Time tT 3 50 3 50 ns 3
Refresh Period tREF 16 16 ns
RAS Precharge Time tRP 40 50 ns
RAS Pulse Width tRAS 60 10,000 70 10,000 ns
RAS Pulse Width (Fast Page Mode) tRASP 60 100,000 70 100,000 ns
RAS Hold Time tRSH 15 20 ns
RAS Hold Time referenced to OE tROH 15 20 ns
CAS Precharge Time
(Fast Page Mode) tCP 10 10 ns
CAS Pulse Width tCAS 15 10,000 20 10,000 ns
CAS Hold Time tCSH 60 70 ns
CAS to RAS Precharge Time tCRP 5 5 ns
RAS Hold Time from CAS Precharge tRHCP 35 40 ns
RAS to CAS Delay Time tRCD 20 45 20 50 ns 5
RAS to Column Address Delay Time tRAD 15 30 15 35 ns 6
Row Address Set-up Time tASR 0 0 ns
Row Address Hold Time tRAH 10 10 ns
Column Address Set-up Time tASC 0 0 ns
FEDD514400D-01
MSM514400D
6/15
AC Characteristic (2/2)
(Vcc = 5V ± 10%, Ta = 0°C to 70°C) Note1,2,3,11,12
MSM514400D -60 MSM514400D -70
Parameter Symbol
Min. Max. Min. Max.
unit Note
Column Address Hold Time tCAH 15 15 ns
Column Address Hold Time from RAS tAR 50 55 ns
Column Address to RAS Lead Time tRAL 30 35 ns
Read Command Set-up Time tRCS 0 0 ns
Read Command Hold Time tRCH 0 0 ns 8
Read Command Hold Time referenced
to RAS tRRH 0 0 ns 8
Write Command Set-up Time tWCS 0 0 ns 9
Write Command Hold Time tWCH 10 10 ns
Write Command Hold Time from RAS tWCR 45 50 ns
Write Command Pulse Width tWP 10 10 ns
OE Command Hold Time tOEH 15 20 ns
Write Command to RAS Lead Time tRWL 15 20 ns
Write Command to CAS Lead Time tCWL 15 20 ns
Data-in Set-up Time tDS 0 0 ns 10
Data-in Hold Time tDH 15 15 ns 10
Data-in Hold Time from RAS tDHR 50 55 ns
OE to Data-in Delay Time tOED 15 20 ns
CAS to WE Delay Time tCWD 35 45 ns 9
Column Address to WE Delay Time tAWD 50 60 ns 9
RAS to WE Delay Time tRWD 80 95 ns 9
CAS Precharge WE Delay Time tCPWD 55 65 ns 9
CAS Active Delay Time from RAS
Precharge tRPC 10 10 ns
RAS to CAS Set-up Time
(CAS before RAS) tCSR 5 5 ns
RAS to CAS Hold Time
(CAS before RAS) tCHR 10 10 ns
WE to RAS Precharge time
(CAS before RAS) tWRP 10 10 ns
WE Hold Time from RAS
(CAS before RAS)
tWRH 10 10 ns
RAS to WE Set-up Time (Test mode) tWTS 10 10 ns
RAS to WE Hold Time (Test mode) tWTH 10 10 ns
FEDD514400D-01
MSM514400D
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Notes: 1. A start-up delay of 200s is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume tT = 5ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition
times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
t
RCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD
(Max.) limit, then the access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
t
RAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD
(Max.) limit, then the access time is controlled by tAA.
7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit
condition and are not referenced to output voltage levels.
8. tRCH or tRRH must be satisfied for a read cycle.
9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early
write cycle and the data out will remain open circuit (high impedance) throughout the entire
cycle. If tCWD tCWD (Min.), tRWD tRWD(Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.),
then the cycle is a read modify write cycle and data out will contain data read from the selected
cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at
access time) is indeterminate.
10. These parameters are referenced to the CAS, leading edges in an early write cycle, and to the WE
leading edge in an OE control write cycle, or a read modify write cycle.
11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. The test mode specified in this data
sheet in a 2-bit parallel test function. CA0 is not used. In read cycle, if all internal bits are equal,
the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a
low level. The test mode is cleared and the memory device returned to its normal operating state
by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified
value. These parameters should be specified in test mode cycle by adding the above value to the
specified value in this data sheet.
FEDD514400D-01
MSM514400D
8/15
TIMING CHART
Read Cycle
Write Cycle (Early Write)
tOFF
tCLZ
tCAC
tOE
A
tASC
tRRH
tRAH tASR
tRAD
tRAL
tCRP
tCAH
tCRP tRCD
tRC
tRAS
tRP
tCSH
tRSH
tCAS
tRAC
t
AA
tRCS
tROH
tRCH
tOEZ
Row Column
Valid Data-out
O
p
en
R
A
S
VIH
VIL
C
A
S
VIH
VIL
Address VIH
VIL
WE
VIH
VIL
OE
VIH
VIL
DQ VOH
VOL
“H” or “L”
tAR
tCRP
tRP
tRWL
Valid Data-in
tDH
tDS
tWCS tWC
tCWL
t
A
SR tRAH tASC
tRC
tRAS
Row
tCSH
tCRP tRCD tRSH
tCAS
Column
tCAH
tRAD
tRAL
tWP
R
A
S
VIH
VIL
C
A
S
VIH
VIL
Address VIH
VIL
WE
VIH
VIL
OE
VIH
VIL
DQ VIH
VIL
“H” or “L”
Open
tAR
tWCR
tDHR
FEDD514400D-01
MSM514400D
9/15
Read Modify Write Cycle
tRWC
tRSH
tCAS
tCWL
tRWL
tCRP
tRP
tOED
tCWD
t
A
WD
tOEH
tWP
tOEZ
tCAC tDH
tDS
Valid
Data-out
Valid
Data-in
t
AA
tRWD
Row Colum
tRAC
tOE
A
tRCS
tCAH
t
A
SC t
A
SR tRAH
tRAD
tCRP tRCD
tCSH
tRAS
tCLZ
R
A
S
VIH
VIL
C
A
S
VIH
VIL
Address VIH
VIL
WE
VIH
VIL
OE
VIH
VIL
DQ VI/OH
VI/OL
“H” or “L”
tAR
FEDD514400D-01
MSM514400D
10/15
Fast Page Mode Read Cycle
Fast Page Mode Write Cycle (Early Write)
tCLZ
tOE
A
tRCS
tOEZ
tCAC
tRRH
tRCH
tRCS
tCP
A
tRCH
t
AA
tOE
A
tOFF
tOEZ tCLZ
tOFF
tCAH
tCAS
tRAL
t
A
SC
tRSH tCP
tCAH
tRP
tRHCP
Column
tCRP
tPC
tOFF tCAC
tCSH
tCAC tOEZ
tRAC
tOE
A
tRCH
tCP
A
t
AA
t
AA
t
CAH
t
A
SC
tRAH
tRAD
tRCS
t
A
SR t
A
SC
tCP
tCAS
tRASP
tCAS
tRCD
tCRP
tCLZ Valid
D
ata
-
out
Row Column Column
R
A
S
VIH
VIL
C
A
S
VIH
VIL
Address VIH
VIL
WE
VIH
VIL
OE
VIH
VIL
DQ VOH
VOL
“H” or “L”
Valid
D
ata
-
out
Valid
D
ata
-
out
tAR
tWP
tCWL
tWCH
t
A
SC
tCP
tPC
tRASP
Column
tRAL
tCRP
t
A
SC tCAH
tCAH
tCAS
tRSH tCP
tCAS
tRP
tRHPC
Column
tWP
t
WCH
tDH
tDS
tDH
tDS
Valid
Data-in
tWCS
tWCS
Valid
Data-in
tCWL
tCSH
tRAD
t
A
SR t
A
SC
tRAH
tRCD
tCRP
tCAS
tC
A
H
Row Column
tWP
tRWL
tWCH
tCWL
tDH tDS
tWCS
Valid
Data-in
“H” or “L”
R
A
S
VIH
VIL
C
A
S
VIH
VIL
Address VIH
VIL
WE
VIH
VIL
DQ
VIH
VIL
Note:
O
E= “H” or “L”
tAR
tWCR
tDHR
FEDD514400D-01
MSM514400D
11/15
Fast Page Mode Read Modify Write cycle
RAS-only Refresh Cycle
t
A
SR tRAH
tCRP tRPC
tRP
tRAS
tRC
tOFF
Row
R
AS VIH
VIL
C
A
S
VIH
VIL
VIH
VIL
Address
VOH
VOL
DQ
“H” or “L”
O
p
en
Note:
W
E
,
O
E= “H” or “L”
tDS
t
AA
tDH
tROH
tOE
A
tWP
tCP
A
tDS
tOEZ
tCPWD
tWP
tCWD
t
A
WD
tDH
t
A
WD
t
AA
tRAC
tRCS
tRCS
t
AA
tCP
A
tOE
A
tRWD
tCWD
t
A
SC
tRAH
t
A
SR
tRAD
tCSH
tCAS
tRASP
tCWL
tRCD tCP
tCAH
t
A
SC
Row Column
tRWL
tCWL
tRCS
Column
tCWL
tCWD
tRAL
tCAH
tCRP
tCP tCAS
tCLZ
tCAS
t
A
SC
tOED
tOEZ
tOED
tCAC
tOED
tDH
tOEZ
In
tWP
tDS
Column
tRP
tRSH
tCAH
Out
tCAC
tPRWC
tCAC
tCLZ tCLZ
t
A
WD
tOE
A
In In Out Out
tCPWD
R
A
S
VIH
VIL
C
A
S
VIH
VIL
A
ddress
VIH
VIL
WE
VIH
VIL
OE
VIH
VIL
DQ
VI/OH
VI/OL
“H” or “L”
Note: In = Valid Data-in, Out = Valid Data-out
tAR
FEDD514400D-01
MSM514400D
12/15
CAS before RAS Refresh Cycle
Hidden Refresh Read Cycle
tWRH tWRP tWRP
tOFF
tRPC
tRP
tRC
tRAS
tCHR
tCSR
tRP
tCP
tRPC
R
AS VIH
VIL
C
AS VIH
VIL
VOH
VOL
DQ O
p
en
Note:
O
E
,
Address = “H” or “L”
W
E VIH
VIL
“H” or “L”
tRAC
tCLZ
tOEZ
tROH
tOE
A
tCAC tRRH
t
AA
tRAL
tRCS
tCAH
tRAH t
A
SR t
A
SC
Column
tRAD
tRP
tRAS
tRC
tRP
tCHR
tRAS
tRSH
tRCD
tCRP
tRC
R
AS VIH
VIL
C
AS VIH
VIL
Address VIH
VIL
W
E VIH
VIL
O
E VIH
VIL
DQ VOH
VOL O
p
en
Row
Valid Data-out
“H” or “L”
tOFF tWRP tWRH
tAR
FEDD514400D-01
MSM514400D
13/15
Hidden Refresh Write Cycle
Test Mode-in Cycle
tOFF
tWTS tWTH
tCP
tRPC
tCSR
tRP
tCHR
tRAS
tRC
R
AS VIH
VIL
C
AS VIH
VIL
W
E VIH
VIL
DQ VIH
VIL
“H” or “L”
Open
Note:
O
E
,
Address = “H” or “L”
tDH
tDS
tWCH
tWCS
tRAL
tRAD
tCAH
tRAH
t
A
SR t
A
SC
tRCD
tCRP tRSH tRP
tCHR
tRP
tRAS
tRC tRC
tRAS
tWP
R
AS VIH
VIL
C
AS VIH
VIL
Address VIH
VIL
W
E VIH
VIL
O
E VIH
VIL
DQ VIH
VIL
Row Colum
Valid Data-in
“H” or “L”
tWRP tWRH
tAR
tWCR
tDHR
FEDD514400D-01
MSM514400D
14/15
REVISION HISTORY
Page
Document
No. Date Previous
Edition
Current
Edition
Description
FEDD514400D-01 Mar.8.2011 – – First edition
FEDD514400D-01
MSM514400D
15/15
NOTICE
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The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter
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Examples of application circuits, circuit constants and any other information contained herein illustrate the standard
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Great care was taken in ensuring the accuracy of the information specified in this document. However, should you
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The technical information specified herein is intended only to show the typical functions of and examples of
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