74HC/HCT75 MSI QUAD BISTABLE TRANSPARENT LATCH FEATURES _ TYPICAL Complementary Q and Q outputs SYMBOL | PARAMETER CONDITIONS UNIT Vcc and GND on the centre pins HC | HCT @ Output capability: standard on del : propagation delay - loc category: MSI tPHL/ nD to nO, nd Cy_ = 15 pF 11. | 12 | ns Vec=5v 'PLH LEp-n to nQ, nd wo| at | as GENERAL DESCRIPTION The 74HC/HCT75 are high-speed Cc) input capacitance 3.5 | 3.5 | pF Si-gate CMOS devices and are pin compatible with low power Schottky power dissipation TTL (LSTTL). They are specified in Pp capacitance per latch notes Tand2 | 42 | 42 | PF compliance with JEDEC standard no. 7A. 5 The 74HC/HCT75 have four bistable GND = 0 V: Tamb = 25 C; ty = ty = 6 ns latches. The two latches are simultaneously controlled by one of two active H1GH Notes rable Waputs (ke and LE3.4). h 1. Cpp is used to determine the dynamic power dissipation (Pp in wW): en _nis , the data enters the = tok 2 . latches and appears at the nQ outputs. PD . CPD x Vcc? x fi + 2 {CL x VCC" x fo) where: The nQ outputs follow the data inputs fi = input frequency in MHz CL = output load capacitance in pF (nD) as long as LEp.p is HIGH fo = output frequency in MHz Vcc = supply voltage in V (transparent). The data on the nD inputs = (CL x Vcc? x fg) = sum of outputs one set-up time prior to the 2. For HC the condition is Vj = GND to Vcc HIGH-to- LOW transition of the LE,., For HCT the condition is V| = GND to Vcc 1.5 V will be stored in the latches. The latched outputs remain stable as long as the PACKAGE OUTLINES LEp-n is LOW. 16-lead DIL; piastic (SOT38Z). . 164ead mini-pack; plastic (S016; SOT109A), PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1,14, 11,8 10 to 40 complementary latch outputs 2, 3,6, 7 1D to 4D data inputs 4 LE3.4 latch enable input, latches 3 and 4 {active HIGH) 5 Vcc positive supply voltage 12 GND ground (0 V) 13 LE1.2 latch enable input, latches 1 and 2 (active HIGH) 16, 15, 10, 9 1Q to 4Q atch outputs 3 aL U [16] 10 [rs 2 tip Rs LEq.2 102] jis] 20 oiip er is 20 [3 fa] 20 3 2ab15 pata LE3.4 [4 | ; 13] LE 1.2 * 2 20h 5 ' Voc [5] 12] sno 134 Le 4d, 20 [2 GE e30 glen ; | 9 ao] [10] 30 roa CP? _"?1 bh 8 4-8 45 [3 | 9] 40 LE3.4 5 | 40 7299145 la 7293146 _ Sa IZG31487.4 Fig. 1 Pin configuration. Fig. 2 Logic symbol. Fig. 3 IEC logic symbol. December 1990 193 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors.74HC/HCT75 FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES LEn.n | nD | nQ} nO H L L H data enabled H H H L data latched L X lq iq 2 2 Q 10] 16 1 1-2 3 CP _ a 1a] 1 L1 3 [20 D 0 2Q] 15 Lice _ gp 2ep4 L2 6 80 af 2ape 3-4 4 cP _ ={| 30fFf 11 L3 a 7 440 boa 4a] 9 Lice _ =| 40| 8 l4 7293148 Fig. 4 Functional diagram. H = HIGH voltage level L = LOW voltage level q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW LE,_, transition X = don't care a o ot in) Ll cp LATCH LE3.4 > cp LATCH el ao > o tcp LATCH 4 Fig. 5 Logic diagram. 2a 3a 4Q 7293149.1 194 March 1988 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors.Quad bistable transparent latch 74HC/HCT75 MSI DC CHARACTERISTICS FOR 74HC For the DC characteristics see chapter HCMOS tamily characteristics, section Family specifications. Output capability: standard lec category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tp =tg = 6 ns; C_ = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL | PARAMETER UNIT | Voc | WAVEFORMS +25 40 to +85 | 40to +125 Vv min. | typ. | max. / min. | max. | min. | max. . 33 110 140 165 2.0 tPHL/ propagation delay 12 | 22 28 33 | ns 4.5 | Fig. 6 PLH nD to nO 10 | 19 24 28 6.0 : 39 | 120 150 180 2.0 PHL/ _|_ Propagation delay 14 | 24 30 36 |ns | 45 | Fig 7 tPLH nD to nG 14 | 20 26 31 6.0 . 33 | 120 150 180 2.0 tPHL/ _|_ Propagation delay 12 | 24 30 36 | ns 45 | Fig.8 *PLH LEp-n tonQ 10 | 20 26 31 6.0 . 39 | 125 155 190 2.0 tPHL! propagation delay 14 | 25 31 38 | ns 4.5 | Fig. 8 tPLH LEp-n tonQ 11 | 24 26 32 6.0 19 | 75 95 110 2.0 tTHL! output transition time : 7 15 19 22 ns 4.5 | Figs6 and7 tTLH 6 13 16 19 6.0 . 80 17 100 120 2.0 tw enable pulse width 16 |6 20 24 ns 45 Fig, 8 HIGH 14/5 17 20 6.0 : 60 14 75 90 2.0 teu set-up time 12 |5 15 18 ns 4.5 Fig. 9 nD to LEn-n 10 | 4 13 15 6.0 . 3 -8 3 3 2.0 th hold time 3 -3 3 3 ns 45 | Fig.9 nD to LEn-n 3 2 3 3 6.0 March 1988 195 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors.74HC/HCT75 MSI DC CHARACTERISTICS FOR 74HCT For the DC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: standard lec category: MSI Note to HCT types The value of additional quiescent supply current (Alec) for a unit load of 1 is given in the family specifications, To determine Alcg per input, multiply this value by the unit load coefficient shown in the table below, UNIT LOAD INPUT | COEFFICIENT nD 0.75 LEn-n 1.00 AC CHARACTERISTICS FOR 74HCT GND =0 Vi t, =t = 6 ns; C, = 50 pF Tamb (C) TEST CONDITIONS 74HCT SYMBOL | PARAMETER UNIT | Vv. WAVEFORMS cc +25 40 to +85| 40to +125 Vv min. | typ. | max.| min.| max.| min. | max. HL Propagation delay 15 | 28 35 42 |ns | 45 | Fig6 PHL propagation delay 15 | 28 38 42 |ns | 45 | Fig.7 PHL! propagation ow 13 | 28 35 42 | ns 45 | Fig 8 n-n PHL propagation delay 15 | 30 38 45 |ns | 45 | Fig 8 n-n THU output transition time 7 15 19 22 ns 45 Figs 6 and 7 tw epee pulse width 16 |4 20 24 ns | 45 | Fig.8 set-up time . teu nD t0 LEnin 12 |4 15 18 ns 4.5 | Fig.9 hold time . th nD to LEp.n 3) 1-2 3 3 ns 4.5 Fig. 9 196 March 1988 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors.Quad bistable transparent latch 74HC/HCT75 MSI AC WAVEFORMS nD (INPUT nD INPUT nQ OUTPUT nQ OUTPUT 7293160 TTHL 7293151 THLE! | > TTLH Fig. 6 Waveforms showing the data input (nD) to Fig. 7 Waveforms showing the data input (nD) to output (nQ) propagation delays and the output output (nQ) propagation delays and the output transition times. transition times. P7 nD INPUT \ Ff nD INPUT V7 | f LA LE gig INPUT LE gen INPUT nQ OUTPUT O= D | | by 7293163 nd OUTPUT nQ@ OUTPUT Fig. 9 Waveforms showing the data set-up and 7293187 *TLH a STHL hold times for nD input to LE,.,, input. Fig. 8 Waveforms showing the latch enable input Note to Fig. 9 {LEn-n) pulse width, the latch enable input to The shaded areas indicate when the input is outputs (nQ, nQ) propagation delays and the permitted to change for predictable output output transition times. performance. Note to AC waveforms (1) HC : Vi = 50%; Vj = GND to Vcc. HCT: Vy = 1.3V; Vy = GND to 3V. 197 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors.