TABLE OF CONTENTS GENERAL DESCRIPTION ...........................................................................................................................1 FEATURES ...................................................................................................................................................1 ORDERING INFORMATION.........................................................................................................................2 BLOCK DIAGRAM........................................................................................................................................3 SSD1301TR1 PIN ASSIGNMENT ................................................................................................................4 PIN DESCRIPTION .......................................................................................................................................6 FUNCTIONAL BLOCK DESCRIPTIONS .....................................................................................................8 Command Decoder and Command Interface ......................................................................................8 MPU Parallel 6800-series Interface.......................................................................................................8 MPU Parallel 8080-series Interface.......................................................................................................8 MPU Serial Interface...............................................................................................................................8 COMMAND TABLE ....................................................................................................................................12 COMMAND DESCRIPTIONS .....................................................................................................................14 MAXIMUM RATINGS..................................................................................................................................17 DC CHARACTERISTICS ............................................................................................................................17 AC CHARACTERISTICS ............................................................................................................................18 APPLICATION EXAMPLE.................................................................................................... 22 SSD1301TR1 TAB PACKAGE DIMENSION...............................................................................23 APPENDIX I ................................................................................................................................................25 SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA SSD1301 Advance Information OLED/PLED Segment/Common Driver with Controller CMOS SSD1301 is a single-chip CMOS OLED/PLED driver with controller for organic/polymer light emitting diode dot-matrix graphic display system. SSD1301 consists of 132 high voltage/current driving output pins for driving 132 segments and 64 commons plus 1 icon line driving common. This IC is designed for Common Cathode type OLED panel. SSD1301 displays data directly from its internal 132x65 bit Graphic Display Data RAM (GDDRAM). Data/Commands are sent from general MCU through a pin selectable 6800-/8080-series 2 compatible Parallel Interface or Serial Peripheral Interface or I C Interface. SSD1301 embeds a contrast control function and an on-chip oscillator for reducing the number of external components. FEATURES Support max. 132 x (64+1) matrix panel Power supply to logic system, 2.4V-3.5V Power supply to OLED system, 7.0V-16.5V Segment output maximum current: 400uA Common sink maximum current: 50mA Half range and full range current mode selection Low current sleep mode (<5.0uA) External current reference control by external resistor 256 steps contrast control on monochrome passive OLED panel On-Chip Oscillator Programmable Frame Rate Solomon Systech Limited's Proprietary OLED Driving Scheme 8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface, Serial Peripheral Interface and 2 I C Interface Embedded 132 x 65 bit SRAM display buffer Row re-mapping and Column re-mapping Vertical scrolling Support Partial display Wide range of operating temperatures: -30 to 85 C This document contains information on a new product. Specifications and information herein are subject to change without notice. Copyright a 2001 SOLOMON Systech Limited Rev 1.1 11/2001 ORDERING INFORMATION SOLOMON Ordering Part Number Package Form SSD1301TR1 TAB Rev 1.1 11/2001 SSD1301 2 BLOCK DIAGRAM ICONS ROW0~ROW63 SEG0~SEG131 SEG current source/ COM switch (65 +132) Bit Latch Display Timing Generator M VDD OLED Driving DOF# M/S# CL CLS VEE Current Control Block Oscillator VREF IREF GDDRAM 132 x 65 Bits Command Decoder VDD VSS Command Interface R/W# C68/80# SP# RES# P/S# CS1# CS2 D/C# E (RD#) (WR#) Parallel/Serial Interface D7 D6 D5 D4 D3 D2 D1 D0 [SDA] [SCK] Figure 1 - Block Diagram SSD1301U/SSD1301Z 3 Rev 1.1 11/2001 SOLOMON SSD1301TR1 PIN ASSIGNMENT Figure 2 - SSD1301TR1 pin assignment (Copper View) SOLOMON Rev 1.1 11/2001 SSD1301 4 PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PIN NAME NC VEE IREF VREF VSS VDD VSS SP# P/ S# C68/ 80# VSS CLS M/ S# VDD D7 D6 D5 D4 D3 D2 D1 D0 VDD E(RD#) R/ W# D/ C# RES# VDD CS2 CS1# VSS DOF# CLS M VEE NC NC NC NC ICONS COM63 COM61 COM59 COM57 COM55 COM53 COM51 COM49 COM47 COM45 COM43 COM41 COM39 COM37 COM35 COM33 COM31 COM29 COM27 COM25 PIN NO 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN NAME COM23 COM21 COM19 COM17 COM15 COM13 COM11 COM9 COM7 COM5 COM3 COM1 NC SEG131 SEG130 SEG129 SEG128 SEG127 SEG126 SEG125 SEG124 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 PIN NO 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 PIN NAME SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 PIN NO 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 PIN NAME SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 ICONS COM0 COM2 COM4 COM6 COM8 COM10 COM12 COM14 COM16 COM18 COM20 COM22 COM24 COM26 COM28 COM30 COM32 COM34 COM36 COM38 COM40 COM42 COM44 COM46 COM48 COM50 COM52 COM54 COM56 COM58 COM60 COM62 NC NC PIN NO 241 PIN NAME NC Table 1 : SSD1301TR1 pin assignment SSD1301U/SSD1301Z 5 Rev 1.1 11/2001 SOLOMON PIN DESCRIPTION M, DOF# These pins are No Connection pins. Nothing should be connected to these pins, nor they are connected together. These pins should be left open individually. CL This pin is the system clock input. When internal clock is enabled, this pin should be left open. Nothing should be connected to this pin. When internal oscillator is disabled, this pin receives display clock signal from external clock source. CS1#, CS2 These pins are the chip select inputs. The chip is enabled for MCU communication only when CS1# is pulled low and CS2 is pulled high. RES# This pin is reset signal input. When the pin is low, initialization of the chip is executed. D/C# This pin is Data/Command control pin. When the pin is pulled high, the data at D7-D0 is treated as display data. When the pin is pulled low, the data at D7-D0 will be transferred to the command register. For detail relationship to MCU interface signals, please refer to the Timing Characteristics Diagrams. R/W#(WR#) This pin is MCU interface input. When interfacing to an 6800-series microprocessor, this pin will be used as Read/Write (R/W#) selection input. Read mode will be carried out when this pin is pulled high and write mode when low. When 8080 interface mode is selected, this pin will be the Write (WR#) input. Data write operation is initiated when this pin is pulled low and the chip is selected. E (RD#) This pin is MCU interface input. When interfacing to a 6800-series microprocessor, this pin will be used as the Enable (E) signal. Read/write operation is initiated when this pin is pulled high and the chip is selected. When connecting to an 8080-microprocessor, this pin receives the Read (RD#) signal. Data read operation is initiated when this pin is pulled low and the chip is selected. D7-D0 These pins are 8-bit bi-directional data bus to be connected to the microprocessor's data bus. When serial mode is selected, D7 will be the serial data input SDA and D6 will be the serial clock input SCK. When I2C mode is selected, D4 will be the clock signal (SCL) and D5 will be the salve address (SA0). If read register status and write data are necessary, D0 should be connected with D1 as SDA bus. If only write data is necessary, D1 will be SDA bus and D0 should be left open. VDD Power Supply pin. This is also the reference for the OLED driving voltages. It must be connected to external source. VDD1 Internally connected to VDD for pull high purpose. VDD2 Internally connected to VDD. VSS Ground. It also acts as a reference for the logic pins. It must be connected to external ground. VSS1 Internally connected to VSS for pull low purpose. VEE This is the most negative voltage supply pin of the chip. It is supplied externally. M/S# This pin is the selection input. This pin must be pulled high to enable the chip function. SOLOMON Rev 1.1 11/2001 SSD1301 6 CLS This pin is internal clock enable. When this pin is pulled high, internal clock is enabled. The internal clock will be disabled when it is pulled low, an external clock source must be connected to CL pin for normal operation. C68/80# This pin is MCU parallel interface selection input. When the pin is pulled high, 6800 series interface is selected and when the pin is pulled low, 8080 series interface is selected. If Serial Interface is selected (P/S# and SP# pulled low), the setting of this pin is ignored, but must be connected to a known logic (either high or low). P/S# This pin is parallel interface selection input. When this pin is pulled high, parallel interface mode is selected. When this pin and SP# pins are pulled low, serial interface is selected. Note: Read data operation is only available in parallel mode. ROW0-ROW63 These pins provide the Common switch signals to the OLED panel. SEG0-SEG131 These pins provide the OLED segment driving signals. The output voltage level of these pins is in high impedance stage when display is off. ICONS There are two ICONS pin on the chip. They are the common pin for the icon row. Both pins output exactly the same signal. The reason for duplicating the pin is to enhance the flexibility of the OLED layout. VREF This pin is the reference for OLED driving voltages. It is supplied externally. IREF This pin is current reference pin. A resistor should be connected between this pin and VEE. SP# This pin is serial interface selection input. When this pin and P/S# pulled low, serial interface mode is selected. TESTIN, TESTOUT They are reserved pins. TESTIN must be connected to VSS and TESTOUT must be left open. Note: Refer to Appendix I for the configuration of I2C Interface. SSD1301U/SSD1301Z 7 Rev 1.1 11/2001 SOLOMON FUNCTIONAL BLOCK DESCRIPTIONS Command Decoder and Command Interface This module determines whether the input data is interpreted as data or command. Data is interpreted based upon the input of the D/C# pin. If D/C# pin is high, data is written to Graphic Display Data RAM (GDDRAM). If it is low, the input at D7-D0 is interpreted as a Command and it will be decoded and be written to the corresponding command register. MPU Parallel 6800-series Interface The parallel interface consists of 8 bi-directional data pins (D0-D7), R/W#(WR#), D/C#, E (RD#), CS1# and CS2. R/W#(WR#) input High indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the status register. RW#/ (WR#) input Low indicates a write operation to Display Data RAM or Internal Command Registers depending on the status of D/C# input. The E (RD#) input serves as data latch signal (clock) when high provided that CS1# and CS2 are low and high respectively. Refer to Figure 8 of parallel timing characteristics for Parallel Interface Timing Diagram of 6800-series microprocessors. In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 3 below. R/ W#(WR#) E(RD#) Data bus N Write column address n Dummy read Data read1 n+1 n+2 Data read2 Data read3 Figure 3 : Display Data Read Back Procedure - Insertion of Dummy Read MPU Parallel 8080-series Interface The parallel interface consists of 8 bi-directional data pins (D0-D7), E (RD#), R/W#(WR#), D/C#, CS1# and CS2. The E (RD#) input serves as data read latch signal (clock) when low, provided that CS1# and CS2 are low and high respectively. Display data or status register read is controlled by D/C#. R/W# (WR#) input serves as data write latch signal (clock) when high provided that CS1# and CS2 are low and high respectively. Display data or command register write is controlled by D/C#. Refer to Figure 8 of parallel timing characteristics for Parallel Interface Timing Diagram of 8080-series microprocessor. Similar to 6800-series interface, a dummy read is also required before the first actual display data read. MPU Serial Interface The serial interface consists of serial clock SCK, serial data SDA, D/C#, CS1# and CS2. SDA is shifted into an 8-bit shift register on every rising edge of SCL in the order of D7, D6, ... D0. D/C# is sampled on every eighth clock and the data byte in the shift register is written to the Display Data RAM or command register in the same clock. SOLOMON Rev 1.1 11/2001 SSD1301 8 Oscillator Circuit This module is an On-Chip low power RC oscillator circuitry (Figure 4). The oscillator generates the clock for the Display Timing Generator. Oscillator enable enable Oscillation Circuit enable Buffer (CL) Internal Resistor OSC1 OSC2 Figure 4 : Oscillator Circuit OLED Driving Current Control Block This block is used to divide the incoming power sources into the different levels of internal use voltage and current. VEE and VDD are external power supplies. VREF is reference voltage, which is used to deliver a reference voltage for Seg Cells. IREF is a reference current source for Seg Cells current drivers. Graphic Display Data RAM (GDDRAM) The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 132 x 65 = 8580 bits. Figure 5 on page 12 is a description of the GDDRAM address map. For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software. For vertical scrolling of the display, an internal register storing display start line can be set to control the portion of the RAM data to be mapped to the display. Figure 5 on page 12 shows the case in which the display start line register is set to 38h. For those GDDRAM out of the display common range, they could still be accessed, for either preparation of vertical scrolling data or even for the system usage. Reset Circuit 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. When RES# input is low, the chip is initialized with the following status: Display is OFF 132x64 [Not included ICONS line] Display Mode Normal segment and display data column address mapping(SEG0 mapped to address 00H) Read-modify-write mode is OFF Shift register data clear in serial interface Display start line is set at display RAM address 0 Column address counter is set at 0 Page address is set at 0 Normal scan direction of the COM outputs Contrast control register is set at 20H Test mode is OFF Current mode is set to half range current mode 197 Bit Latch A register carries the display signal information. In 132x65 display mode, data will be fed to the Seg/Com Cell and output to the required voltage/current level respectively. Seg/Com Cell Seg current source drivers deliver 132 current sources to drive OLED panel. It uses current source to drive the SegCell where the driving current can be adjusted from 0 to 400 uA with 256 steps. Com cell is the voltage scanning pulse as shown in Figure 6. SSD1301U/SSD1301Z 9 Rev 1.1 11/2001 SOLOMON Column address 00H Column address 83H (83H) Segment Remap Enabled (00H) COM SCAN MODE NORMAL (REMAPPED) ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ page 0 page 1 page 2 page 3 page 4 page 5 page 6 page 7 page 8 LSB [D0] MSB LSB [D7] MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ 38H ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ ........................................ COM8 (COM55) COM63 (COM0) COM0 (COM63) COM7 (COM56) ICONS (LSB) SEG0 SEG131 Note: The configuration in parentheses represent the remapping of Rows and Columns Figure 5 : Graphic Display Data RAM (GDDRAM) Address Map with Display Start Line set to 38h. SOLOMON Rev 1.1 11/2001 SSD1301 10 M TIME SLOT 1 2 3 4 5 ... * N+1 1 2 3 4 5 ...* N+1 1 2 3 4 5 ...* N+1 1 2 COM0 VDD VEE COM1 VDD VEE SEG0 SEG1 . . . SEG131 *N is the number of multiplex ratio not included Icon. N+1 is the number of multiplex ratio including the icon. Segment ISEG FOR "ON" Current Source Off ISEG ISEG300uA 0 A ISEG FOR "OFF" B A: reset and pre-charge B: current drive Figure 6 : OLED Driving Waveform SSD1301U/SSD1301Z 11 Rev 1.1 11/2001 SOLOMON COMMAND TABLE Table 2 : Command Table (D/C# =0, R/W#(WR#)=0, E (RD#)=1) Bit Pattern Command Description 0000X3X2X1X0 Set Lower Column Address Set the lower nibble of the column address register using X3X2X1X0 as data bits. The initial display line register is reset to 0000b after POR. 0001X3X2X1X0 Set Higher Column Address Set the higher nibble of the column address register using X3X2X1X0 as data bits. The initial display line register is reset to 0000b after POR. 01X5X4X3X2X1X0 Set Display Start Line Set display RAM display start line register from 0-63 using X5X4X3X2X1X0. Display start line register is reset to 000000 during POR. Double byte command to select 1 out of 256 contrast steps. Contrast increases as X7X6X5X4X3X2X1X0 is increased from 00000000b to 11111111b. X7X6X5X4X3X2X1X0 =10000000b after POR 10000001 X7X6X5X4X3X2X1X0 Set Contrast Control Register 1010000X0 Set Segment Re-map X0=0: column address 00H is mapped to SEG0 (POR) X0=1: column address 83H is mapped to SEG0 1010010X0 Set Entire Display On/Off X0=0: normal display (POR) X0=1: entire display on 1010011X0 Set Normal/Inverse Display X0=0: normal display (POR) X0=1: inverse display 1010111X0 Set Display On/Off X0=0: turns off OLED panel (POR) X0=1: turns on OLED panel 1011X3X2X1X0 Set Page Address Set GDDRAM Page Address (0~8) for read/write using X3X2X1X0 1100X3 * * * Set COM Output Scan Direction X3=0: normal mode (POR) X3=1: remapped mode. COM0 to COM[N-1] becomes COM[N1] to COM0 in Multiplex ratio is equal to N. See Fig.5 as an example for N equal to 64. 11100000 Set Read-Modify-Write Mode 11100010 Software Reset 11101110 Set End of Read-Modify-Write Mode Exit Read-Modify-Write mode. RAM Column address before entering the mode will be restored. After POR, Read-modifywrite mode is OFF. NOP Command for No Operation Set Test Mode Reserved for IC testing. Do NOT use. Set Power Save Mode Sleep mode will be entered with compound commands 11100011 1111 * * * * ******** SOLOMON Read-Modify-Write mode will be entered in which the column address will not be increased during display data read. After POR, Read-modify-write mode is turned OFF Initialize internal status registers Rev 1.1 11/2001 SSD1301 12 Bit Pattern Command Description To select multiplex ratio N from 2 to the maximum multiplex ratio (POR value) (including icon line). Max. mux ratio: 65 N= X5X4X3X2X1X0+2, e.g. N=001111b+2=17 Fosc X4X3X2X1X0 =00001: 4x65 Set Multiplex Ratio 10101000 **X5X4X3X2X1X0 10101010 *10X4X3X2X1X0 Fosc X4X3X2X1X0 =11111: 6x65 (POR) Set Frame Frequency Fosc X4X3X2X1X0 =00011: 8x65 1101000X0 Set Icon Mode 11011010 ***1**X10 Set Current Mode X0=0: icon mode off (POR) X0=1: icon mode on X1=0: Select half range current mode (POR) X1=1: Select full range current mode Note: Remark "*" stands for "Don't Care" Table 3 : Read Command Table (D/C#=0, R/W#(WR#)=1, E(RD#)=1 for 6800 or E(RD#)=0 for 8080) Bit Pattern Command Description D7D6D5D4D3D2D1D0 D7=0: indicates the driver is ready for command. D7=1: indicates the driver is Busy. D6=0: indicates reverse segment mapping with column address D6=1: indicates normal segment mapping with column address D5=0: indicates the display is ON D5=1: indicates the display is OFF D4=0: initialization is not in progress D4=1: initialization is in progress after RES# or software reset Status Register Read Note: Patterns other than that given in Command Table are prohibited to enter to the chip as a command; otherwise, unexpected result will occur. Data Read / Write To read data from the GDDRAM, input High to R/W#(WR#) pin and D/C# pin for 6800-series parallel mode, Low to E (RD#) pin and High to D/ C# pin for 8080-series parallel mode. No data read is provided for serial mode. In normal data read mode, GDDRAM column address pointer will be increased by one automatically after each data read. However, no automatic increase will be performed in read-modify-write mode. Also, a dummy read is required before the first data read. See Figure 3 in Functional Description. To write data to the GDDRAM, input Low to R/W#(WR#) pin and High to D/C# pin for 6800-series parallel mode AND 8080series parallel mode. For serial interface mode, it is always in write mode. GDDRAM column address pointer will be increased by one automatically after each data write. It should be noted that, after the automatic column address increment, the pointer will NOT wrap round to 0 when overflow (>131). The increment of the pointer will stop at 131. Therefore, there is a need to re-initialize the pointer when progresses to another page address. Address Increment Table (Automatic) D/C# R/W#(WR#) Comment Address Increment 0 0 1 1 0 1 0 1 Write Command Read Status Write Data Read Data No No Yes Yes*1 *1. If read-data command is issued in read-modify-write mode, address increase is not applied. SSD1301 13 Rev 1.1 11/2001 SOLOMON COMMAND DESCRIPTIONS Set Lower Column Address This command specifies the lower nibble of the 8-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU. Set Higher Column Address This command specifies the higher nibble of the 8-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU. Set Display Start Line This command is to set Display Start Line register to determine starting address of display RAM to be displayed by selecting a value from 0 to 63. With value equals to 0, D0 of Page 0 is mapped to COM0. With value equals to 1, D1 of Page0 is mapped to COM0. The display start line values of 0 to 63 are assigned to Page 0 to 7. Set Contrast Control Register This command is to set Contrast Setting of the display. The chip has 256 contrast steps from 00 to FF. The segment output current increase with the increase of contrast step. See Fig 7a below. From Fig 7b, it shows that the output uniformity is better at highest contrast setting. Therefore, for both full range current mode and half range current mode, it is recommended choosing a higher contrast setting if possible. Segment current VS Contrast setting ISEG(Full current mode) Current unifromity VS Contrast setting ISEG(Half current mode) 450 20 400 CURRENT(uA) 350 16 300 12 250 200 8 150 100 4 50 0 0 0 00 0F 1F 2F 15 30 45 60 3F 4F 5F 6F 7F 8F 9F AF BF CF DF EF FF Figure 7a : Segment current vs Contrast setting 75 90 105 120 135 150 165 180 195 210 225 240 255 Contrast setting Contrast setting Figure 7b : Current uniformity vs Contrast setting Set Segment Re-map This command changes the mapping between the display data column address and segment driver. It allows flexibility in layout during OLED module assembly. Refer to Table 2. Set Entire Display On/Off This command forces the entire display, including the icon row, to be "ON" regardless of the contents of the display data RAM. This command has priority over normal/reverse display. This command will be used with "Set Display ON/OFF" command to form a compound command for entering power save mode. See "Set Power Save Mode". Set Normal/Reverse Display This command sets the display to be either normal/reverse. In normal display, a RAM data of 1 indicates an "ON" pixel while in reverse display, a RAM data of 0 indicates an "ON" pixel. In icon mode, the icon line is not reversed by this command. Set Display On/Off This command alternatively turns the display on and off. When display off is issued with entire display on, power save mode will be entered. See "Set Power Save Mode" for details. Set Page Address This command positions the page address to 0 to 8 possible positions in GDDRAM. Refer to Table 2. Set COM Output Scan Direction This command sets the scan direction of the COM output allowing layout flexibility in OLED module assembly. See Figure 5 on Page 12 for the relationship between turning on or off of this feature. In addition, the display will have immediate effect once this command is issued. That is, if this command is sent during normal display, the graphic display will have vertical flipping effect. Set Read-Modify-Write Mode This command puts the chip in read-modify-write mode in which: 1. The column address is saved before entering the mode 2. The column address is incremented by display data write but not by display data read SOLOMON Rev 1.1 11/2001 SSD1301 14 Table 4 : ROW pins assignment for COM signals in Programmable Multiplex Ratio Die Pad Name ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 ROW9 ROW10 ROW11 ROW12 ROW13 ROW14 ROW15 ROW16 ROW17 ROW18 ROW19 ROW20 ROW21 ROW22 ROW23 ROW24 ROW25 ROW26 ROW27 ROW28 ROW29 ROW30 ROW31 ROW32 ROW33 ROW34 ROW35 ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 ROW44 ROW45 ROW46 ROW47 ROW48 ROW49 ROW50 ROW51 ROW52 ROW53 ROW54 ROW55 ROW56 ROW57 ROW58 ROW59 ROW60 ROW61 ROW62 ROW63 64 Mux Com Signal Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 54 Mux Com Signal Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* 53 Mux Com Signal Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* 49 Mux Com Signal Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* 48 Mux Com Signal Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* 33 Mux Com Signal Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* 32 Mux Com Signal Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* 16 Mux Com Signal Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* Remark: *The ROW will output a Non-Select COM signal. SSD1301 15 Rev 1.1 11/2001 SOLOMON Software Reset This command causes some of the internal status of the chip to be initialized: 1. Read-Modify-Write mode is off 2. Display start line register is set to 0 3. Column address counter is set to 0 4. Page address is set to 0 5. Normal scan direction of the COM outputs Set End of Read-Modify-Write Mode This command relieves the chip from read-modify-write mode. The column address saved before entering read-modify-write mode will be restored. NOP No Operation Command Set Test Mode This command forces the driver chip into its test mode for internal testing of the chip. Under normal operation, user should NOT use this command. Set Power Save Mode To enter Sleep Mode, it should be done by using a double byte command composed of "Set Display ON/OFF" and "Set Entire Display ON/OFF" commands. When "Set Entire Display ON" is issued during display is OFF, Sleep Mode will be entered. For Sleep mode: 1. Internal oscillator and OLED power supply circuits are stopped 2. Segment and Common drivers output high impedance level 3. The display data and operation mode before sleep are held 4. Internal display RAM can still be accessed 5. Sleep Mode can be exited by the issue of a new software command or by pulling Low at hardware pin RES#. Status register Read This command is issued by setting D/C# Low during a data read (refer to Figure 8 and Figure 9 parallel interface waveform). It allows the MCU to monitor the internal status of the chip. No status read is provided for serial mode. Set Multiplex Ratio This command switches default 65 multiplex mode to any multiplex mode from 2 to 65. The output pads ROW0-ROW63 will be switched to corresponding COM signal. (See Table 4) Set Frame Frequency This command is used to select Frame Frequency. In SSD1301, there are three choices for frame frequency. Set Icon Mode This command enables or disables the icon mode. The default setting (POR) disables the icon mode. Set Current Mode This command is used to select half range current mode or full range current mode. In POR, half range current mode is default. SOLOMON Rev 1.1 11/2001 SSD1301 16 MAXIMUM RATINGS Table 5 : Maximum Ratings (Voltage Reference to VSS) Symbol VDD VEE Vin TA Tstg Parameter Supply Voltage Input voltage Operating Temperature Storage Temperature Range Value -0.3 to +4 0 to VDD-16.5 Vss-0.3 to Vdd+0.3 -30 to +85 -65 to +150 Unit V V V C C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description. DC CHARACTERISTICS Table 6 : DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = 25C) Symbol VEE VDD VOH VOL VIH VIL Parameter Operating Voltage Logic Supply Voltage High Logic Output Level Low Logic Output Level High Logic Input Level Low Logic Input Level ISLEEP Sleep mode Current IEE IDD Test Condition Iout =100uA, 3.3MHz Iout =100uA, 3.3MHz Iout =100uA, 3.3MHz Iout =100uA, 3.3MHz VDD=2.7V, IREF=8uA, Display On, no panel attached Contrast = FF VEE Supply Current VDD=2.7V, VEE=-9V, IREF=8uA, Frame rate = 85Hz, Contrast = FF, All one pattern, Display on, no loading Power Consumption (IDD +IEE) VDD - (VDD-VEE) IEE Contrast = AF VDD=2.7V, VEE=-9V, IREF=8uA, All one pattern, Display on, Segment pin under test is connected with a 20K resistive load to VEE. ISEG Half Range Current Mode VDD=2.7V, VEE=-9V, IREF=8uA, All one pattern, Display on, Segment pin under test is connected with a 20K resistive load to VEE. Max -4.6 3.5 VDD 0.1*VDD VDD 0.2*VDD Unit V V V V V V - 0.2 5 uA -680 -580 Contrast = AF Contrast = FF Full Range Current Mode Typ -9 2.7 - uA VDD Supply Current VDD=2.7V, VEE=-9V, IREF=8uA, Frame rate = 85Hz, Contrast = FF, All one pattern, Display on, no loading = Min -13.0 2.4 0.9*VDD 0 0.8*VDD 0 -480 - 600 700 uA Contrast = FF 500 350 400 450 Contrast = AF 220 270 320 Contrast = 5F 110 145 180 Contrast = 0F 0 25 50 Contrast = FF 157.5 180 202.5 Contrast = AF 99 121.5 144 Contrast = 5F 49.5 65.25 81 Contrast = 0F 0 11.25 22.5 - - 9 Contrast = 5F - - 13 VDD - VEE=11.7V, Iout=30mA; - 23 33 uA uA Dev = (ISEG - IMID)/IMID Segment output current uniformity IMID = (IMAX + IMIN)/2 Dev % ISEG[0:131] = Segment current at contrast = FF RON_C SSD1301 17 Common Output On Resistance Rev 1.1 11/2001 SOLOMON AC CHARACTERISTICS Table 7 : AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = 25C.) Symbol Parameter FOSC Oscillation Frequency of Display Timing Generator FFRM Frame Frequency for 65 MUX Mode Test Condition Min Typ Max Unit Vdd = 2.7V, IREF = 8uA 35 40 42 kHz 132x64 Graphic Display Mode, Display ON, Internal Oscillator Enabled 132x64 Graphic Display Mode, Display ON, Internal Oscillator Disabled, External clock with freq., Fext, feeding to CL pin. SOLOMON Rev 1.1 11/2001 Fosc 6x65 Hz Fext 6x65 Hz SSD1301 18 Table 8 : 6800-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -30 to 85C) Symbol Parameter tcycle Clock Cycle Time tAS Address Setup Time tAH Address Hold Time Write Data Setup Time tDHW Write Data Hold Time tDHR Read Data Hold Time tOH Output Disable Time tACC Access Time PW CSL Chip Select Low Pulse Width (read) Chip Select Low Pulse Width (write) PW CSH Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time tF Fall Time Typ Max Unit - - ns 0 - - ns 0 - - ns 40 - - ns 15 - - ns 20 - - ns - - 70 ns - - 140 ns 120 60 - - ns 60 60 - - ns - - 15 ns - - 15 ns 300 tDSW tR Min R/W D/C tAH tAS E tcyc le PW CS L PW C SH CS1 (CS2=1) tR tF t D SW D0 -D7 (Write data to driver) tDH W Valid Data t A CC D0-D 7 (Read data from driver) tDH R Valid Data tOH Figure 8 : 6800-series MPU Parallel Interface Characteristics SSD1301 19 Rev 1.1 11/2001 SOLOMON Table 9 : 8080-Series MPU Parallel Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -30 to 85C) Symbol Parameter tcycle Clock Cycle Time tAS Address Setup Time tAH Address Hold Time tDSW Write Data Setup Time tDHW Write Data Hold Time tDHR Read Data Hold Time tOH Output Disable Time tACC Access Time Chip Select Low Pulse Width (read) Chip Select Low Pulse Width (write) PW CSH Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time tF Fall Time Typ Max Unit - - ns 0 - - ns 0 - - ns 40 - - ns 15 - - ns 20 - - ns - - 70 ns - - 140 ns 120 60 - - ns 60 60 - - ns - - 15 ns - - 15 ns 300 PW CSL tR Min D/C tA H tAS CS1 (CS2=1) tcyc le PW CS L PWCSH RD WR tF tR tDS W D0-D7 (Write data to driver) tD HW Valid Data tAC C D0 -D7 (Read data from driver) tD HR Valid Data tOH Figure 9 : 8080-series MPU Parallel Interface Characteristics SOLOMON Rev 1.1 11/2001 SSD1301 20 Table 10 : Serial Interface Timing Characteristics (VDD - VSS = 2.4 to 3.5V, TA = -30 to 85C) Symbol Parameter tcycle Clock Cycle Time tAS Address Setup Time tAH Address Hold Time tCSS Chip Select Setup Time tCSH Chip Select Hold Time tDSW Write Data Setup Time tDHW Write Data Hold Time tCLKL Clock Low Time tCLKH Clock High Time tR Rise Time tF Fall Time Min Typ Max Unit - - ns 150 - - ns 150 - - ns 120 - - ns 60 - - ns 100 - - ns 100 - - ns 100 - - ns 100 - - ns - - 15 ns - - 15 ns 250 D/C tAS tAH tC SS CS1 (CS2=1) tCS H tc ycle tC LK L tC LKH SCK tF tR tDSW SDA tD HW Valid Data D/C CS1 (CS2=1) SDA D7 D6 D5 D4 D3 D2 D1 D0 SCK Figure 10 : Serial Interface Characteristics * When SP# is high, please refer to APPENDIX I for timing characteristics for Solomon Systech Limited internal use only. SSD1301 21 Rev 1.1 11/2001 SOLOMON Application Example The configuration for serial mode interface is shown in the following diagram: COM44 COM46 . . COM60 COM62 COM1 COM0 ICONS SEG0 . . . . . . . . . . . . SEG131 DISPLAY PANEL SIZE 132X64+ICON LINE COM47 COM49 . . COM63 ICONS SSD1301 VEE IREF VREF VDD VSS CS1# D7 D6 D/C# RES# VEE VDD C2 C3 VDD R1 C1 VEE VREF VDD VSS[GND] CS1# SDA SCK D/C# RES# VEE D0-D7: To MCU interface VREF: External voltage reference for pre-charge signal (VEE<VREF<VDD) IREF: Connect a 1% resistor to VEE and keep the current across the resistor at 8.0uA M/S#: Need to tie high for standalone system, refer to Pin Description M, CL, DOF# -NC for standalone CS2 - CS2 tied to high for serial bus R/W#, E, D0 - D5 - NC for serial bus interface CLS - pull high for internal oscillator C1, C2, C3: 4.7uF R1: Value=~1.2M to set IREF to 8.0uA C68/80# P/S# SP# 6800 parallel interface 1 1 X 8080 parallel interface 0 1 X Serial interface X 0 0 2 I C interface *Refer to Appendix I Note: X stands for don't care. SOLOMON Rev 1.1 11/2001 SSD1301 22 SSD1301TR1 TAB PACKAGE DIMENSION Note: 1. All dimensions are in mm unless specific 2. General Tolerance : +/-0.05m m 3. Cu Thickness : 25um 4. SN Plating : 0.35um SSD1301 23 Rev 1.1 11/2001 SOLOMON SOLOMON Rev 1.1 11/2001 SSD1301 24 APPENDIX I IIC TIMING DIAGRAM AND PIN CONNECTION PIN DESCRIPTION SP# This pin is serial interface selection input. When this pin and P/S# are pulled low, serial interface mode is selected. When it is pulled high and P/S# pin is pulled low, I2C interface mode is selected. FUNCTIONAL BLOCK DESCRIPTION MPU I2C Interface The I2C communication interface consists of slave address bit SA0 (D5), I2C-bus data signal SDA (D0 for output and D1 for input) and I2C-bus clock signal SCL (D4). Both the data and clock signals must be connected to pull-up resistors. There are also five input signals including, RES#, CS1#, P/S#, CS2, SP#, which is used for the initialization of device. a) b) c) Slave address bit (SA0) SSD1301 have to recognize the slave address before transmitting or receiving any information by the I2C-bus. The device will responds to the slave address following by the slave address bit ("SA0" bit) and the read/write select bit ("R/W#" bit) with the following byte format, b7 b6 b5 b4 b3 b2 b1 b0 0 1 1 1 1 0 SA0 R/W# "SA0" bit provides an extension bit for the slave address. Either "0111100" or "0111101", can be selected as the slave address of SSD1301. "R/W#" bit determines the I2C-bus interface is operating at either write mode or read status mode. I2C-bus data signal (SDA) SDA acts as a communication channel between the transmitter and the receiver. The data and the acknowledgement are sent through the SDA. If SDA in is connected to the "SDA out", the device becomes fully IIC bus compatible. It should be noticed that the ITO track resistance and the pulled-up resistance at "SDA" pin becomes a voltage potential divider. As a result, the acknowledgement would not be possible to attain a valid logic 0 level in "SDA". The "SDA out" pin may be disconnected from the "SDA in" pin. With such arrangement, the acknowledgement signal will be ignored in the I2C-bus. I2C-bus clock signal (SCL) The transmission of information in the I2C-bus is following a clock signal, SCL. Each transmission of data bit is taken place during a single clock period of SCL. Command Decoder Input is directed to the command decoder based on the input of control byte which consists of a D/C# bit and a R/W# bit. For further information about the control byte, please refer to the section "I2C-bus Write data and read register status". If both the D/C# bit and the R/W# bit are low, the input signal is interpreted as a Command. It will be decoded and written to the corresponding command register. If the D/C# bit is high and the R/W# bit is low, input signal is written to Graphic Display Data RAM (GDDRAM). SSD1301 25 Rev 1.1 11/2001 SOLOMON I2C-bus Write data and read register status The I2C-bus interface gives access to write data and command into the device. Please refer to Figure 11 for the write mode of I2Cbus in chronological order. Note: Write mode Control byte SSD1301 Slave Address 0 0 0 0 0 0 ACK D/C# Co Slave Address P ACK ACK R/W# SA0 S Status bytes R/W# SA0 Read mode 0 1 1 1 1 0 n 0 bytes MSB ...................LSB 1 byte 0 1 1 1 1 0 Data byte P ACK m 0 words Slave Address ACK Data byte D/C# Co ACK Control byte ACK D/C# Co ACK SA0 R/W# S 0 1 1 1 1 0 Co - Continuation bit D/C# - Data / Command Selection bit ACK - Acknowledgement SA0 - Slave address bit R/W# - Read / Write Selection bit S - Start Condition / P - Stop Condition Control byte Figure 11 : I2C-bus data format Write mode 1) The master device initiates the data communication by a start condition. The definition of the start condition is shown in Figure 12. The start condition is established by pulling the SDA from high to low while the SCL stays high. 2) The slave address is following the start condition for recognition use. For the SSD1301, the slave address is either "b0111100" or "b0111101" by changing the SA0 to high or low. 3) The write mode is established by setting the R/W# bit to logic "0". 4) An acknowledgement signal will be generated after receiving one byte of data, including the slave address and the R/W# bit. Please refer to the Figure 13 for the graphical representation of the acknowledge signal. The acknowledge bit is defined as the SDA line is pulled down during the high period of the acknowledgement related clock pulse. 5) After the transmission of the slave address, either the control byte or the data byte may be sent across the SDA. A control byte mainly consists of Co and D/C# bits following by six "0" `s. a. If the Co bit is set as logic "0", the transmission of the following information will contain data bytes only. b. The D/C# bit determines the next data byte is acted as a command or a data. If the D/C# bit is set to logic "0", it defines the following data byte as a command. If the D/C# bit is set to logic "1", it defines the following data byte as a data which will be stored at the GDDRAM. The GDDRAM column address pointer will be increased by one automatically after each data write. 6) Acknowledge bit will be generated after receiving each control byte or data byte. SOLOMON Rev 1.1 11/2001 SSD1301 26 7) The write mode will be finished when a stop condition is applied. The stop condition is also defined in Figure 12. The stop condition is established by pulling the "SDA in" from low to high while the "SCL" stays high. tHSTART tSSTOP SDA SDA SCL SCL S P START condition STOP condition Figure 12 : Definition of the start and stop condition DATA OUTPUT BY TRANSMITTER Non-acknowledge DATA OUTPUT BY RECEIVER Acknowledge SCL FROM MASTER 1 2 8 9 S START Condition Clock pulse for acknowledgement Figure 13 : Definition of the acknowledgement condition SSD1301 27 Rev 1.1 11/2001 SOLOMON Please be noted that the transmission of the data bit has some limitations. 1. The data bit, which is transmitted during each SCL pulse, must keep at a stable state within the "high" period of the clock pulse. Please refer to the Figure 14 for graphical representations. Except in start or stop conditions, the data line can be switched only when the SCL is low. 2. Both the data line (SDA) and the clock line (SCL) should be pulled up by external resistors. SDA SCL data line is stable; data is valid Change of data is allow SEG1 Figure 14 : Definition of the data transfer condition Read mode (Read status register) 1) The master device firstly initiates the data communication by a start condition. The definition of the start condition is shown in Figure 12. 2) The slave address is following the start condition for recognition use. For the SSD1301, the slave address is either "b0111100" or "b0111101". 3) The read mode is established by setting R/W# bit to logic "1". The read mode allows the MCU to monitor the internal status of the chip. 4) An acknowledgement signal will be generated after sending one byte of data, including the slave address and the R/W# bit. Please refer to the Figure 13 for the graphical representation of the acknowledge signal. 5) The status of the register will be read at the next status byte. Please refer to the Read Command Table on page 15 for the explanation of the status byte. 6) The read mode will be finished when a stop condition is applied. The stop condition is also defined in Figure 12. SOLOMON Rev 1.1 11/2001 SSD1301 28 2 Table 11 : I C Interface Timing Characteristics (VDD-VSS=2.4 to 3.5V, TA=-30 to 85 C) Symb ol Parameter Min Typ Max Unit tcycle Clock Cycle Time 2.5 - - us tHSTART Start condition Hold Time 0.6 - - us tHD Data Hold Time 300 - - ns tSD Data Setup Time 100 - - ns tSSTART Start condition Setup Time (Only relevant for a repeated Start condition) 0.6 - - us tSSTOP Stop condition Setup Time 0.6 - - us tR Rise Time for data and clock pin - - 300 ns tF Fall Time for data and clock pin - - 300 ns tIDLE Idle Time before a new transmission can start 1.3 - - us // SDA // tIDLE tHD tHSTART tR tF tSSTART tSD tSSTOP SCL tCYCLE Figure 15 : I2C Interface Timing Characteristics SSD1301 29 Rev 1.1 11/2001 SOLOMON Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part. SOLOMON Rev 1.1 11/2001 SSD1301 30