TABLE OF CONTENTS
GENERAL DESCRIPTION ...........................................................................................................................1
FEATURES ...................................................................................................................................................1
ORDERING INFORMA TION.........................................................................................................................2
BLOCK DIAGRAM........................................................................................................................................3
SSD1301TR1 PIN ASSIGNMENT ................................................................................................................4
PIN DESCRIPTION.......................................................................................................................................6
FUNCTIONAL BLOCK DESCRIPTIONS.....................................................................................................8
Command Decoder and Command Interface......................................................................................8
MPU Parallel 6800-series Interface.......................................................................................................8
MPU Parallel 8080-series Interface.......................................................................................................8
MPU Serial Interface...............................................................................................................................8
COMMAND TABLE ....................................................................................................................................12
COMMAND DESCRIPTIONS .....................................................................................................................14
MAXIMUM RATINGS..................................................................................................................................17
DC CHA RACTERISTICS............................................................................................................. ...............17
AC CHARACTERISTICS............................................................................................................................18
APPLICATION EXAMPLE………………………………………………………………………………………. 22
SSD1301TR1 TAB PACKAGE DIMENSION………...…...…………………………………………………….23
APPENDIX I ................................................................................................................................................25
SOLOMON SYSTECH
SOLOMON SYSTECH SOLOMON SYSTECH
SOLOMON SYSTECH
SEMICONDUCT OR TECHNICAL DATA
This document c ontains informat i on on a new product . Specifi cations and i nformat i on herei n are subject to change without not i ce.
Copyright ã 2001 S O LOMON Systech Limit ed
Rev 1.1
11/2001
SSD1301
Advance Information
OLED/PLED Segment/Common Driver with Controller
CMOS
SSD1301 is a single-chip CMOS OLED/PLED driver with controller for organic/polymer light
emitting diode dot-matrix graphic display system. SSD1301 consists of 132 high voltage/current driving
output pins for driving 132 segments and 64 commons plus 1 icon line driving common. This IC is
designed for Common Cathode type OLED panel.
SSD1301 displays data directly from its internal 132x65 bit Graphic Display Data RAM
(GDDRAM). Data/Commands are sent from general MCU through a pin selectable 6800-/8080-series
compatible Parallel Interface or Serial Peripheral Interface or I2 C Interface.
SSD1301 em beds a c ontrast contr ol func tion and an on-chip osc illator f or reduc ing the num ber of
external components.
FEATURES
Support max. 132 x (64+1) matrix panel
Power supply to logic system, 2.4V-3.5V
Power supply to OLED system, 7.0V-16.5V
Segment output maximum current: 400uA
Common sink maximum current: 50mA
Half range and full range current mode selection
Low current sleep mode (<5.0uA)
External current reference control by external resistor
256 steps contrast control on monochrome passive OLED panel
On-Chip Oscillator
Programmable Frame Rate
Solomon Systech Limited’s Proprietary OLED Driving Scheme
8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface, Serial Peripheral Interface and
I2 C Interface
Embedded 132 x 65 bit SRAM display buffer
Row re-mapping and Column re-mapping
Vertical scrolling
Support Partial display
Wide range of operating temperatures: -30 to 85 °C
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ORDERING INFORMATION
Ordering Part Number Package Form
SSD1301TR1 TAB
SSD1301U/SSD1301Z
3 Rev 1.1
11/2001 SOLOMON
ROW0~ROW63 SEG0~SEG131 ICONS
SEG current source/ COM switch
(65 +132) Bit Lat ch
Display
Timing
Generator
Oscillator
GDDRAM
132 x 65 Bits
Command Decoder
Command Interface Parallel/Serial I nterface
OLED
Driving
Current
Control
Block
VDD
VEE
VREF
IREF
VDD
VSS
CL
CLS
M
DOF#
M/S#
D7 D6 D5 D4 D3 D2 D
1 D0
RES#
P/S#
CS1# CS2
D/C#
E
(RD#)
R/W#
(WR#)
C68/80#
[SDA][SCK]
SP#
BLOCK DIAG RAM
Figure 1 - Block Diagram
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SSD1301TR1 PIN ASSIGNMENT
Figure 2 – SSD1301TR1 pin assignm ent (Copper V iew)
SSD1301U/SSD1301Z
5 Rev 1.1
11/2001 SOLOMON
Table 1 : SSD1301TR1 pin assignm ent
PIN NO PIN NAME PIN NO PIN NAME PIN NO PIN NAME PIN NO PIN NAME PIN NO PIN NAME
1 NC 61 COM23 121 SEG84 181 SEG24 241 NC
2 VEE 62 COM21 122 SEG83 182 SEG23
3 IREF 63 COM19 123 SEG82 183 SEG22
4 VREF 64 COM17 124 SEG81 184 SEG21
5 VSS 65 COM15 125 SEG80 185 SEG20
6 VDD 66 COM13 126 SEG79 186 SEG19
7 VSS 67 COM11 127 SEG78 187 SEG18
8 SP# 68 COM9 128 SEG77 188 SEG17
9 P/ S# 69 COM7 129 SEG76 189 SEG16
10 C68/ 80# 70 COM5 130 SEG75 190 SEG15
11 VSS 71 COM3 131 SEG74 191 SEG14
12 CLS 72 COM1 132 SEG73 192 SEG13
13 M/ S# 73 NC 133 SEG72 193 SEG12
14 VDD 74 SEG131 134 SEG71 194 SEG11
15 D7 75 SEG130 135 SEG70 195 SEG10
16 D6 76 SEG129 136 SEG69 196 SEG9
17 D5 77 SEG128 137 SEG68 197 SEG8
18 D4 78 SEG127 138 SEG67 198 SEG7
19 D3 79 SEG126 139 SEG66 199 SEG6
20 D2 80 SEG125 140 SEG65 200 SEG5
21 D1 81 SEG124 141 SEG64 201 SEG4
22 D0 82 SEG123 142 SEG63 202 SEG3
23 VDD 83 SEG122 143 SEG62 203 SEG2
24 E(RD#) 84 SEG121 144 SEG61 204 SEG1
25 R/ W# 85 SEG120 145 SEG60 205 SEG0
26 D/ C# 86 SEG119 146 SEG59 206 ICONS
27 RES# 87 SEG118 147 SEG58 207 COM0
28 VDD 88 SEG117 148 SEG57 208 COM2
29 CS2 89 SEG116 149 SEG56 209 COM4
30 CS1# 90 SEG115 150 SEG55 210 COM6
31 VSS 91 SEG114 151 SEG54 211 COM8
32 DOF# 92 SEG113 152 SEG53 212 COM10
33 CLS 93 SEG112 153 SEG52 213 COM12
34 M 94 SEG111 154 SEG51 214 COM14
35 VEE 95 SEG110 155 SEG50 215 COM16
36 NC 96 SEG109 156 SEG49 216 COM18
37 NC 97 SEG108 157 SEG48 217 COM20
38 NC 98 SEG107 158 SEG47 218 COM22
39 NC 99 SEG106 159 SEG46 219 COM24
40 ICONS 100 SEG105 160 SEG45 220 COM26
41 COM63 101 SEG104 161 SEG44 221 COM28
42 COM61 102 SEG103 162 SEG43 222 COM30
43 COM59 103 SEG102 163 SEG42 223 COM32
44 COM57 104 SEG101 164 SEG41 224 COM34
45 COM55 105 SEG100 165 SEG40 225 COM36
46 COM53 106 SEG99 166 SEG39 226 COM38
47 COM51 107 SEG98 167 SEG38 227 COM40
48 COM49 108 SEG97 168 SEG37 228 COM42
49 COM47 109 SEG96 169 SEG36 229 COM44
50 COM45 110 SEG95 170 SEG35 230 COM46
51 COM43 111 SEG94 171 SEG34 231 COM48
52 COM41 112 SEG93 172 SEG33 232 COM50
53 COM39 113 SEG92 173 SEG32 233 COM52
54 COM37 114 SEG91 174 SEG31 234 COM54
55 COM35 115 SEG90 175 SEG30 235 COM56
56 COM33 116 SEG89 176 SEG29 236 COM58
57 COM31 117 SEG88 177 SEG28 237 COM60
58 COM29 118 SEG87 178 SEG27 238 COM62
59 COM27 119 SEG86 179 SEG26 239 NC
60 COM25 120 SEG85 180 SEG25 240 NC
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PIN DESCRIPTION
M, DOF#
These pins are No Connec tion pins . Not hing should be c onnect ed to t hese pi ns, nor they are c onnect ed toget her. Thes e pins
should be lef t open individuall y.
CL
This pin is the s yst em cl ock input. When i nternal c loc k i s enabled, thi s pin s hould be l eft open. Nothing should be connected to
this pin. When internal oscillator is disabled, this pin receives display cloc k signal from external clock s ource.
CS1#, CS2
These pins are t he chip s elect input s. The c hip is enabl ed for MCU comm unic ation only when CS1# is pulled low and CS 2 is
pulled high.
RES#
This pin is reset s i gnal i nput. When t he pi n i s low, initial i zat i on of the chip i s executed.
D/C#
This pin is Data/ Com m and cont rol pin. When t he pin is pulled hi gh, t he data at D7-D0 is t reated as displ ay data. When the pin
is pulled l ow, the dat a at D7-D0 will be transferred to the com mand regis ter. For detail relat ionship to MCU interf ace signals , please
refer to the Ti ming Charac t eri stic s Diagram s.
R/W#(WR#)
This pin is MCU interface input. When interfacing to an 6800-series microprocessor, this pin will be used as Read/Write
(R/W#) selec tion input. Read mode will be carried out when this pin is pulled high and write mode when low.
W hen 8080 interf ace m ode is select ed, t his pin will be the Write (WR#) input. Data write operation is init iated when this pin is
pulled low and the chip i s selec t ed.
E (RD#)
This pin is MCU interface input. When interfacing to a 6800-series microprocessor, this pin will be used as the Enable (E)
signal. Read/ write operation is i ni t i ated when this pin is pulled high and the chip is select ed.
W hen connecting to an 8080-m icroprocess or, this pin receives the Read (RD#) signal. Data read operation is initiated when
this pi n i s pulled low and the chip i s selec ted.
D7-D0
These pins are 8-bi t bi-direct ional data bus to be connec ted to the m icroproc essor’ s data bus. W hen serial mode is selec ted,
D7 will be the serial data input SDA and D6 will be the serial cloc k input SCK.
W hen I2C mode is s elected, D4 will be the c lock signal (S CL) and D5 will be the salve address (SA0). If read regis ter status
and write data are neces sary, D0 s hould be c onnect ed with D1 as SDA bus. If only write data i s nec ess ary, D1 will be SDA bus and
D0 should be left open.
VDD Power Supply pin. This i s also t he reference for t he OLED driving voltages . It must be connected t o external source.
VDD1
Internall y c onnected to V DD for pull high purpos e.
VDD2
Internall y c onnected to V DD.
VSS Ground. It also acts as a reference for the logi c pins. It must be c onnected to external ground.
VSS1
Internall y c onnected to V SS for pull low purpose.
VEE This is the most negative voltage supply pin of the chi p. It is supplied externally.
M/S#
This pin is the selection input . This pin must be pul l ed hi gh t o enabl e the chip function.
SSD1301U/SSD1301Z
7 Rev 1.1
11/2001 SOLOMON
CLS This pin is i nternal clock enable. When this pi n i s pulled high, i nternal clock is enabl ed.
The internal clock will be disabled when it is pulled low, an external clock source must be connected to CL pin for normal
operation.
C68/80#
This pin is MCU paral lel int erfac e s elec ti on i nput. When the pin is pulled hi gh, 6800 s eries i nterf ace i s s elect ed and when the
pin is pull ed l ow, 8080 s eri es interface is s el ected.
If Serial Interfac e is sel ected (P/S# and S P# pulled low), the s etting of this pi n is ignored, but mus t be connec ted to a known
logic (either high or low).
P/S#
This pin is parallel interface selection input. When this pin is pulled high, parallel interface mode is selected. When this pin and
SP# pins are pul l ed l ow, s eri al i nterface is selec ted.
Note: Read data operation is onl y avai l abl e i n paral l el mode.
ROW0-ROW63
These pins provi de the Common switc h signals t o the OLED panel.
SEG0-SEG131
These pins provide the OLED segment driving signals. The output voltage level of these pins is in high impedance stage when
display is off.
ICONS
There are two ICONS pin on the c hip. They are the comm on pin for the icon row. Bot h pins output exactly the sam e signal.
The reason for duplicat ing the pin is to enhanc e t he f l exibility of the OLED layout.
VREF This pin is the reference f or OLE D dri ving vol tages. I t is s uppl i ed externally.
IREF This pin is current ref erence pin. A resist or should be connec t ed between this pin and V EE.
SP# This pi n i s serial i nterface s el ection input . When this pin and P/ S # pul l ed l ow, s eri al i nt erface mode is s el ected.
TESTIN, TESTOUT
They are reserved pins. TESTI N must be connected t o V SS and TE S T OUT must be l ef t open.
Note: Refer to Appendix I for the configuration of I2C Interface.
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FUNCTIONAL BLOCK DE S CRIPTIONS
Command Decoder and Command Interface
This module determines whether the input data is interpreted as data or command. Data is interpreted based upon the input of
the D/C# pin.
If D/C# pi n is high, data i s written to Graphic Display Data RAM (GDDRA M). If it is low, the input at D7-D0 is interpret ed as a
Command and it will be decoded and be written to the c orresponding com mand regist er.
MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D0-D7), R/W#(WR#), D/C#, E (RD#), CS1# and CS2. R/W#(WR#)
input High indi cat es a read operat ion f rom the Graphic Dis play Dat a RAM (GDDRAM) or t he stat us regist er. RW#/ (W R#) input Low
indicates a write operation to Display Data RAM or Internal Command Registers depending on the status of D/C# input. The E (RD#)
input serves as data latc h signal (cloc k) when high provided that CS1# and CS2 are l ow and high respectivel y. Refer to Figure 8 of
parallel ti ming characteris tics f or Parallel I nt erface Timing Diagram of 6800-seri es mi croprocessors.
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is
internally perf ormed which requires the inserti on of a dummy read before the first actual display data read. Thi s is s hown in F i gure 3
below.
MPU Parallel 8080-series Interface
The parallel int erfac e cons ist s of 8 bi-di recti onal data pi ns (D0-D7), E (RD#), R/ W#(WR#), D/C#, CS1# and CS 2. The E (RD#)
input serves as data read lat ch s ignal (cloc k ) when low, provided that CS1# and CS 2 are low and high respectively. Display data or
stat us register read is cont rol l ed by D/C#.
R/W# (WR#) input serves as data write latch signal (clock) when high provided that CS1# and CS2 are low and high
respectively. Display data or command register write is controlled by D/C#. Refer to Figure 8 of parallel timing characteristics for
Parallel Interface Timing Diagram of 8080-series microprocessor. Similar to 6800-series interface, a dummy read is also required
before the fi rst actual displ ay data read.
MPU Serial Interface
The serial interface consists of serial clock SCK, serial data SDA, D/C#, CS1# and CS2. SDA is shifted into an 8-bit shift
register on every ri sing edge of SCL i n the order of D7, D6, ... D 0. D/C# is sampled on every eighth clock and the data byte in the shift
register i s written to the Display Data RAM or command regi ster in t he same clock .
Figure 3 : Display Data Read Back P r ocedure - I nserti on of Dummy Read
n+2
n+1
Write column address Dummy read Data read1
R/ W#(WR#)
Data bus N n
E(RD#)
Data read2 Data read3
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11/2001 SOLOMON
Oscillator Circuit
This module is an On-Chip low power RC oscillator circuitry (Figure 4). The oscillator generates the clock for the Display
Timing Generator.
Figure 4 : Oscillator Circuit
OLED Driving Current Control Block
This bloc k is used to divide the incom ing power sources into the different levels of internal use voltage and current. VEE and
VDD are external power supplies. VREF is reference voltage, which is used to deliver a reference voltage for Seg Cells. IREF is a
reference c urrent source for Seg Cells current drivers.
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 132 x 65 = 8580 bits.
Figure 5 on page 12 is a des cription of the GDDRAM address map.
For mechanical flexibility, re-m apping on both Segm ent and Comm on outputs c an be selected by software.
For vertical scrolling of the dis play, an internal register stori ng display start line can be set to control the portion of the RAM
data to be mapped to the di splay. Figure 5 on page 12 s hows t he case in which t he di splay start line regis ter is s et to 38h.
For thos e GDDRAM out of the dis play comm on range, they c ould still be acc essed, for either preparation of vertical scrolling
data or even for the system usage.
Reset Circuit
When RES# i nput is low, the chip is i ni tialized with the f ol l owing status:
1. Display is OFF
2. 132x64 [Not included I CONS line] Dis pl a y Mode
3. Normal segment and di splay data c ol umn address mappi ng(SEG0 m apped to address 00H)
4. Read-modif y-write mode is OFF
5. Shift regi ster data c l ear i n serial int erface
6. Display start l i ne i s set at displ ay RA M addres s 0
7. Column address counter is s et at 0
8. Page address i s set at 0
9. Normal scan direc t i on of the COM outputs
10. Contrast control regi ster is set at 20H
11. Test mode is OFF
12. Current mode is set to half range current mode
197 Bit Latch
A regis ter carries the display signal inform ation. I n 132x65 display mode, data will be fed to the S eg/Com Cell and output t o
the required volt age/current le vel respectively.
Seg/Com Cell
Seg c urrent s ource drivers deliver 132 c urrent sources to drive OLED panel . It uses current s ource to drive the SegCell where
the driving current can be adjus t ed from 0 t o 400 uA with 256 steps. Com cell is the voltage scanning pulse as shown in Figure 6.
(CL)
Oscillation Circuit
enable
enable
Buffer
Internal Resistor
OSC1 OSC2
Oscillator
enable
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10
Figure 5 : Graphic Display Data RAM (GDDRAM) Address Map with Display Start Line set to 38h.
…….. LSB
[
D0
]
………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. MSB
[
D7
]
………………………………….
…….. LSB ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. MSB ………………………………….
…….. LSB ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. MSB ………………………………….
…….. LSB ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. MSB ………………………………….
…….. LSB ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. MSB ………………………………….
…….. LSB ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. MSB ………………………………….
…….. LSB ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. MSB ………………………………….
…….. LSB 38H
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. ………………………………….
…….. MSB ………………………………….
…….. ………………………………….
Note: The c onfi
g
uration in
p
arentheses re
p
resent the rema
pp
in
g
of Rows and Co lumns
COM SCA N MO DE
COM0 (COM63)
COM63
(
COM0
)
ICONS
COM7 (COM56)
SEG131
Column address 83H
(00H)
COM8 (COM55)
NORMAL (REMAPPED)
Column address 00H
(83H) Segment Remap Enabled
page 8
SEG0
(
LSB
)
page 0
page 1
page 2
page 3
page 4
page 5
page 6
page 7
SSD1301U/SSD1301Z
11 Rev 1.1
11/2001 SOLOMON
SEG0
SEG1
.
.
.
SEG131
*N is the number of multipl ex ratio not
included I con.
N+1 is the number of multi pl ex ratio
including the icon.
Segment
ISEG≤300uA ISEG FOR “ON”
ISEG FOR “OFF”
0
A
B
A
: reset and pre-charge
B: current drive
Current Source Off
M
TIME SLOT
1 2 3 4 5 … * N+1 12345 …* N+1 12345 …* N+1 1 2
COM0
VDD
VEE
COM1
VDD
VEE
Figure 6 : OLED Driving Waveform
ISEG
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COMMAND TABLE
Table 2 : Com mand Table (D/ C# =0, R/W#(WR#)=0, E (RD#)=1)
Bit Pattern Command Description
0000X3X2X1X0
Set Lower Column A ddress
Set the lower nibble of the column address register using
X3X2X1X0 as data bits. The init ial display line register is reset to
0000b after PO R.
0001X3X2X1X0
Set Higher Col umn Addres s
Set the higher nibble of the column address register using
X3X2X1X0 as data bits. The init ial display line register is reset to
0000b after PO R.
01X5X4X3X2X1X0
Set Display St art Line
Set display RAM display start line register from 0-63 using
X5X4X3X2X1X0.
Display start li ne regi ster is reset to 000000 duri ng POR.
10000001
X7X6X5X4X3X2X1X0 Set Contrast Cont rol Regi ster
Double byte command to select 1 out of 256 contrast steps.
Contrast increases as X7X6X5X4X3X2X1X0 is increased from
00000000b to 11111111b. X7X6X5X4X3X2X1X0 =10000000b after
POR
1010000X0 Set Segm ent Re-map
X0=0: column address 00H is mapped to SEG0 (POR)
X0=1: column address 83H is mapped to SE G 0
1010010X0 Set Entire Display On/Off
X0=0: normal displ ay (POR)
X0=1: entire display on
1010011X0 Set Normal/Inverse Display
X0=0: normal displ ay (POR)
X0=1: inverse display
1010111X0 Set Display On/Off
X0=0: turns off OLED panel (P OR)
X0=1: turns on OLED panel
1011X3X2X1X0
Set Page A ddress
Set GDDRAM Page Address (0~8) for read/write using
X3X2X1X0
1100X3 * * *
Set COM Output Scan Direc t i on
X3=0: normal mode (POR)
X3=1: remapped mode. COM0 to COM[N-1] becomes COM[N-
1] to COM0 in Multiplex ratio is equal to N. See Fig.5 as
an example for N equal t o 64.
11100000 Set Read-Modify-Write Mode
Read-Modify-Write mode will be entered in which the column
address will not be increas ed during dis play dat a read. After
POR, Read-modify-write m ode i s turned OFF
11100010 Software Reset Initi al i ze internal status regis ters
11101110 Set End of Read-Modify-Wri te Mode Exit Read-Modify-Write mode. RAM Column address before
entering the mode will be restored. After POR, Read-modify-
write mode is OFF.
11100011
NOP Command for No Operati on
1111 * * * *
Set Test Mode Reserved for IC testing. Do NOT use.
* * * * * * * * Set Power Save Mode
Sleep m ode will be entered with compound commands
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13 Rev 1.1
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Bit Pattern Command Description
10101000
**X5X4X3X2X1X0 Set Multiplex Ratio
To select multiplex ratio N from 2 to the maximum multiplex
ratio (POR value) (i ncluding icon line).
Max. mux ratio: 65
N= X5X4X3X2X1X0+2, e.g. N=001111b+2=17
10101010
*10X4X3X2X1X0
Set Frame Frequency
X4X3X2X1X0 =00001: 4x65
osc
F
X4X3X2X1X0 =11111: 6x65
osc
F (POR)
X4X3X2X1X0 =00011: 8x65
osc
F
1101000X0 Set Icon Mode X0=0: icon mode off (POR)
X0=1: icon mode on
11011010
***1**X10 Set Current Mode X1=0: S el ect half range current m ode (POR)
X1=1: Select full range current mode
Note: Remark “*” s t ands for “Don’t Care”
Table 3 : Read Command Table (D/C#=0, R/W#(WR#)=1, E(RD#)=1 f or 6800 or E (RD#)=0 for 8080)
Bit Pattern
Command
Description
D7D6D5D4D3D2D1D0
Status Regist er Read
D7=0: indicates the driver is ready for comm and.
D7=1: indicates the driver is Busy.
D6=0: indicates reverse segment mapping with col umn address
D6=1: indicates normal segment mapping with c ol umn address
D5=0: indicat es the displ ay is ON
D5=1: indicates the display is OFF
D4=0: initialization is not in progress
D4=1: initial i zat i on i s in progress after RES # or software reset
Note: Patterns ot her than that given i n Command Table are prohibited to enter to t he chip as a c omm and; otherwise, unexpected
result will occur.
Data Read / Write
To read data from the GDDRAM, i nput High to R/W#(WR#) pin and D/C# pi n for 6800-series paral l el mode, Low to E (RD#)
pin and High to D/ C# pi n f o r 8080-series parall el mode. No dat a read i s provided for s eri al mode.
In normal data read mode, GDDRA M column address pointer will be increased by one automatically after each data read.
However, no automatic increase will be performed in read-modify-write mode.
Also, a dummy read is required before the firs t data read. See Figure 3 i n Functional Des cription.
To write data to the GDDRAM, input Low to R/W#(WR#) pin and High to D/C# pin for 6800-s eri es parallel mode AND 8080-
series parallel mode. For serial interf ace mode, it is always in write mode. GDDRAM colum n address pointer will be increased by
one autom at i cally aft er each data write.
It should be noted that, after the automatic column addres s increm ent, the pointer will NOT wrap round to 0 when overflow
(>131). The increment of the pointer will stop at 131. Theref ore, there is a need to re-init ialize t he pointer when progresses to
another page address .
Address Increment Table (Automatic)
D/C#
R/W#(WR#)
Comment
Address
Increment
0 0 Write Command No
0 1 Read Status No
1 0 Write Data Yes
1 1 Read Data Yes*1
*1. If read-data command is iss ued i n read-modif y-write mode, address increas e i s not applied.
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COMMAND DE SCRIPTIONS
Set Lower Column Address
This command specifies the lower nibble of the 8-bit column address of the display data RAM. The column address will be
incremented by each data access aft er i t is pre-s et by the MCU.
Set Higher Colum n Address
This com mand specifies the higher nibble of the 8-bit column addres s of the display data RAM. The column address will be
incremented by each data access aft er i t is pre-s et by the MCU.
Set Display Start Line
This com m and is to set Display Start Line register to determine starting addres s of dis pl ay RAM to be displa yed by select i ng
a value from 0 to 63. W ith value equals to 0, D0 of Page 0 is mapped to COM0. W it h value equals to 1, D1 of Page0 is m apped to
COM0. The display start li ne val ues of 0 to 63 are as signed to P age 0 t o 7.
Set Contrast Control Register
This com mand is to set Contras t Setting of the display. The c hip has 256 contrast steps from 00 to FF. The segment output
current increase with the increas e of contras t s tep. See Fig 7a bel ow. From Fig 7b, i t shows that the output unif ormi ty is bett er at
highest contrast setting. Therefore, for both full range current mode and half range current mode, it is recommended choosing a
higher contrast set ting if pos sible.
Figure 7a : Segment current vs Contrast setting Figure 7b : Current uniformity v s Contrast setting
Set Segm en t Re-map
This command changes the mapping between the display data column address and segment driver. It allows flexibility in
layout during OLED module as sembly. Refer to Table 2.
Set Entire Display On/Off
This command forces the entire display, including the icon row, to be “ON” regardless of the contents of the display data RAM.
This com m and has priorit y over normal/ reverse display. This com m and will be used with “Set Display ON/OFF” comm and to form a
com pound command for ent eri ng power save mode. See “Set Power Save Mode”.
Set Normal/ Reverse Di splay
This comm and sets the dis play to be eit her normal/ reverse. I n normal dis play, a RA M data of 1 indic ates an “ON” pixel while
in reverse dis pl a y, a RAM data of 0 indicates an “ON” pi xel. I n i con mode, the icon li ne i s not reversed by this c omm and.
Set Displ ay On/Off
This com mand alt ernatively turns t he display on and off . W hen display off is issued with enti re display on, power save mode
will be entered. See “Set P ower Save Mode” for details.
Set Page Address
This comm and positions the page address to 0 to 8 pos sible posi t i ons in GDDRAM. Ref er t o Tabl e 2.
Set COM Output S can Di rection
This command sets the scan direction of the COM output allowing layout flexibility in OLED module assembly. See
Figure 5 on Page 12 for t he rel at i onship between turning on or off of this feature.
In addition, the display will have immediate effect once this command is issued. That is, if this command is sent during normal
display, the graphic dis play will have vertical flipping effect.
Set Read-M o d ify-Write Mod e
This comm and puts the chip in read-m odi fy-write mode in which:
1. The column address i s saved before entering the mode
2. The column address is increment ed by di splay data write but not by di splay data read
Segment current VS Contrast setting
0
50
100
150
200
250
300
350
400
450
00 0F 1F 2F 3F 4F 5F 6F 7F 8F 9F AF BF CF DF EF FF
Contrast setting
CURRENT(uA)
ISEG(Full current mode) ISEG(Half current mode)
Current unifrom i ty VS Contrast setting
0
4
8
12
16
20
0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255
Contrast setting
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Table 4 : ROW pins assi gnment f or COM s i gnal s in Programmabl e Mult i pl ex Ratio
Die Pad Name 64 Mux Com
Signal Output 54 Mux Com
Signal Output 53 Mux Com
Signal Output 49 Mux Com
Signal Output 48 Mux Com
Signal Output 33 Mux Com
Signal Output 32 Mux Com
Signal Output 16 Mux Com
Signal Output
ROW0 COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0
ROW1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1
ROW2 COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2
ROW3 COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3
ROW4 COM4 COM4 COM4 COM4 COM4 COM4 COM4 COM4
ROW5 COM5 COM5 COM5 COM5 COM5 COM5 COM5 COM5
ROW6 COM6 COM6 COM6 COM6 COM6 COM6 COM6 COM6
ROW7 COM7 COM7 COM7 COM7 COM7 COM7 COM7 COM7
ROW8 COM8 COM8 COM8 COM8 COM8 COM8 COM8 COM8
ROW9 COM9 COM9 COM9 COM9 COM9 COM9 COM9 COM9
ROW10 COM10 COM10 COM10 COM10 COM10 COM10 COM10 COM10
ROW11 COM11 COM11 COM11 COM11 COM11 COM11 COM11 COM11
ROW12 COM12 COM12 COM12 COM12 COM12 COM12 COM12 COM12
ROW13 COM13 COM13 COM13 COM13 COM13 COM13 COM13 COM13
ROW14 COM14 COM14 COM14 COM14 COM14 COM14 COM14 COM14
ROW15 COM15 COM15 COM15 COM15 COM15 COM15 COM15 COM15
ROW16 COM16 COM16 COM16 COM16 COM16 COM16 COM16 NON-SELECT*
ROW17 COM17 COM17 COM17 COM17 COM17 COM17 COM17 NON-SELECT*
ROW18 COM18 COM18 COM18 COM18 COM18 COM18 COM18 NON-SELECT*
ROW19 COM19 COM19 COM19 COM19 COM19 COM19 COM19 NON-SELECT*
ROW20 COM20 COM20 COM20 COM20 COM20 COM20 COM20 NON-SELECT*
ROW21 COM21 COM21 COM21 COM21 COM21 COM21 COM21 NON-SELECT*
ROW22 COM22 COM22 COM22 COM22 COM22 COM22 COM22 NON-SELECT*
ROW23 COM23 COM23 COM23 COM23 COM23 COM23 COM23 NON-SELECT*
ROW24 COM24 COM24 COM24 COM24 COM24 COM24 COM24 NON-SELECT*
ROW25 COM25 COM25 COM25 COM25 COM25 COM25 COM25 NON-SELECT*
ROW26 COM26 COM26 COM26 COM26 COM26 COM26 COM26 NON-SELECT*
ROW27 COM27 COM27 COM27 COM27 COM27 COM27 COM27 NON-SELECT*
ROW28 COM28 COM28 COM28 COM28 COM28 COM28 COM28 NON-SELECT*
ROW29 COM29 COM29 COM29 COM29 COM29 COM29 COM29 NON-SELECT*
ROW30 COM30 COM30 COM30 COM30 COM30 COM30 COM30 NON-SELECT*
ROW31 COM31 COM31 COM31 COM31 COM31 COM31 COM31 NON-SELECT*
ROW32 COM32 COM32 COM32 COM32 COM32 COM32 NON-SELECT* NON-SELECT*
ROW33 COM33 COM33 COM33 COM33 COM33 NON-SELECT* NON-SELECT* NON-SELECT*
ROW34 COM34 COM34 COM34 COM34 COM34 NON-SELECT* NON-SELECT* NON-SELECT*
ROW35 COM35 COM35 COM35 COM35 COM35 NON-SELECT* NON-SELECT* NON-SELECT*
ROW36 COM36 COM36 COM36 COM36 COM36 NON-SELECT* NON-SELECT* NON-SELECT*
ROW37 COM37 COM37 COM37 COM37 COM37 NON-SELECT* NON-SELECT* NON-SELECT*
ROW38 COM38 COM38 COM38 COM38 COM38 NON-SELECT* NON-SELECT* NON-SELECT*
ROW39 COM39 COM39 COM39 COM39 COM39 NON-SELECT* NON-SELECT* NON-SELECT*
ROW40 COM40 COM40 COM40 COM40 COM40 NON-SELECT* NON-SELECT* NON-SELECT*
ROW41 COM41 COM41 COM41 COM41 COM41 NON-SELECT* NON-SELECT* NON-SELECT*
ROW42 COM42 COM42 COM42 COM42 COM42 NON-SELECT* NON-SELECT* NON-SELECT*
ROW43 COM43 COM43 COM43 COM43 COM43 NON-SELECT* NON-SELECT* NON-SELECT*
ROW44 COM44 COM44 COM44 COM44 COM44 NON-SELECT* NON-SELECT* NON-SELECT*
ROW45 COM45 COM45 COM45 COM45 COM45 NON-SELECT* NON-SELECT* NON-SELECT*
ROW46 COM46 COM46 COM46 COM46 COM46 NON-SELECT* NON-SELECT* NON-SELECT*
ROW47 COM47 COM47 COM47 COM47 COM47 NON-SELECT* NON-SELECT* NON-SELECT*
ROW48 COM48 COM48 COM48 COM48 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT*
ROW49 COM49 COM49 COM49 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT*
ROW50 COM50 COM50 COM50 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT*
ROW51 COM51 COM51 COM51 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT*
ROW52 COM52 COM52 COM52 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT*
ROW53 COM53 COM53 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT*
ROW54 COM54 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT*
ROW55 COM55 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT*
ROW56 COM56 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT*
ROW57 COM57 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT*
ROW58 COM58 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT*
ROW59 COM59 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT*
ROW60 COM60 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT*
ROW61 COM61 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT*
ROW62 COM62 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT*
ROW63 COM63 NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT* NON-SELECT*
Remark:
*The ROW will output a Non-Select COM si gnal.
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Software Reset
This comm and causes some of the internal status of the chip t o be i nitialized:
1. Read-Modify-Write mode is off
2. Display start li ne register i s set t o 0
3. Column address counter is s et to 0
4. Page address i s set t o 0
5. Normal scan direc t i on of the COM outputs
Set End of Read-Modify-Write M ode
This com mand relieves t he chip from read-m odify-write mode. The column addres s saved before entering read-modify-write
mode will be restored.
NOP No Operation Comm and
Set Test Mode
This comm and forces the driver chip into its test mode for internal testing of the chip. Under norm al operation, user should
NOT use this command.
Set Pow er S ave Mode
To enter S l eep Mode, i t should be done by us i ng a doubl e byte com mand composed of “Set Disp l ay ON/ O FF” and “S et Entire
Display ON/OFF” commands . When “Set E ntire Display ON” is issued during display is OFF, S l eep Mode will be entered.
For Sleep m ode:
1. Internal oscillator and OLED power supply circuits are st opped
2. Segment and Common drivers output high impedance level
3. The display dat a and operat i on mode before sleep are held
4. Internal display RAM can still be accessed
5. Sleep Mode can be exited by the iss ue of a new sof t ware command or by pulling Low at hardware pin RES#.
Status register Read
This command is is sued by setting D/C# Low during a data read (ref er t o Fi gure 8 and Fi gure 9 paral l el i nterface waveform). It
allows the MCU to monitor t he i nt ernal status of the c hi p. No status read is provi ded f or serial mode.
Set Multiplex Ratio
This com mand switches def ault 65 multiplex mode to any m ultiplex mode from 2 t o 65. The output pads ROW0-ROW 63 will
be switched to corresponding COM si gnal . (See Table 4)
Set Frame Frequency
This command is used to selec t Frame Frequency. In SSD1301, there are t hree choices for fram e frequency.
Set Icon Mode
This comm and enabl es or disables the ic on mode. The def aul t setting (POR) disables the icon mode.
Set Current Mode
This command is used to select half range current mode or full range current mode. In POR, half range current mode is
default.
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MAXIMUM RATINGS
Table 5 : Maximum Ratings (Voltage Reference to VSS)
Symbol Parameter Value Unit
VDD -0.3 to +4 V
VEE Supply Voltage 0 to VDD-16.5 V
Vin Input voltage Vss-0.3 to Vdd+0.3 V
TA Operating Temperature -30 to +85 ºC
Tstg Storage Temperature Range -65 to +150 ºC
*Maximum Rat i ngs are those val ues beyond which damage t o the device may occ ur. Functional operation should be restricted to
the limits i n the Elec t ri cal Charact eri stic s tables or Pin Desc ri pt i on.
DC CHARACTERISTICS
Table 6 : DC Characteristi cs (Unless otherwise s pecified, Voltage Referenced to V SS, VDD = 2. 4 to 3.5V, TA = 25°C)
Symbol Parameter Test Condition Min Typ Max Unit
VEE Operating Voltage -13.0 -9 -4.6 V
VDD Logic Supply Voltage 2.4 2.7 3.5 V
VOH High Logic Output Level Iout =100uA, 3.3MHz 0.9*VDD - VDD V
VOL Low Logic Output Level Iout =100uA, 3.3MHz 0 - 0.1*VDD V
VIH High Logic Input Level Iout =100uA, 3.3MHz 0.8*VDD - VDD V
VIL Low Logic Input Level Iout =100uA, 3.3MHz 0 - 0.2*VDD V
ISLEEP Sleep mode Current VDD=2.7V, IREF=8uA,
Display On, no panel
attached - 0.2 5 uA
Contrast = FF -680 -580
IEE
VEE Supply Current
VDD=2.7V, VEE=-9V, IREF=8uA, Frame rate =
85Hz, Contrast = FF, All one pattern, Display on, no
loading Contrast = AF -480 uA
Contrast = FF - 600 700
IDD
VDD Supply Current
VDD=2.7V, VEE=-9V, IREF=8uA, Frame rate =
85Hz, Contrast = FF, All one pattern, Display on, no
loading
Power Consumption =
(IDD +IEE) VDD - (VDD-VEE) IEE
Contrast = AF 500
uA
Contrast = FF 350 400 450
Contrast = AF 220 270 320
Contrast = 5F 110 145 180
Full Range Current Mode
VDD=2.7V, VEE=-9V, IREF =8uA,
All one pattern, Display on,
Segment pin under test is connected with a 20KΩ
resistive l oad to VEE. Contrast = 0F 0 25 50
uA
Contrast = FF 157.5 180 202.5
Contrast = AF 99 121.5 144
Contrast = 5F 49.5 65.25 81
ISEG Half Range Current Mode
VDD=2.7V, VEE=-9V, IREF =8uA,
All one pattern, Display on,
Segment pin under test is connected with a 20KΩ
resistive l oad to VEE. Contrast = 0F 0 11.25 22.5
uA
Dev = (ISEG – IMID)/IMID
IMID = (IMAX + IMIN)/2
ISEG[0:131] = Segment
current at contrast = FF
- - ±9
Dev Segment output current uniformity
Contrast = 5F - - ±13
%
RON_C Common Output On Resistance VDD - VEE=11.7V,
Iout=30mA; - 23 33
Ω
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AC CHARACTERISTICS
Table 7 : AC Charac teristi cs (Unles s otherwise specified, Voltage Referenced to VSS, VDD = 2. 4 to 3.5V, T A = 25° C.)
Symbol Parameter Test Condition Min Typ Max Unit
FOSC Oscillati on Frequency of
Display Timing Generator Vdd = 2.7V, IREF = 8uA
35 40 42 kHz
FFRM
Frame Frequenc y f or
65 MUX Mode
132x64 Graphic Display Mode, Di splay ON,
Internal Osc illat or E nabled
132x64 Graphic Display Mode, Di splay ON,
Internal Oscillator Disabled, External clock with
freq., Fext, feeding t o CL pi n.
6x65
osc
F
6x65
ext
F
Hz
Hz
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Table 8 : 6800-Series MPU Parallel I nterface Ti ming Characteristi cs (VDD - VSS = 2.4 to 3. 5V , TA = -30 to 85°C)
Symbol Parameter Min Typ Max Unit
tcycle
Clock Cycle Time 300
- - ns
tAS
Address S etup Time 0 - - ns
tAH
Address Hol d Ti me 0 - - ns
tDSW
Write Data S etup Time 40 - - ns
tDHW
Write Data Hold Time 15 - - ns
tDHR
Read Data Hold Time 20 - - ns
tOH
Output Dis abl e Ti me - - 70 ns
tACC
Access Time - - 140 ns
PWCSL
Chip Selec t Low Pulse Widt h (read)
Chip Selec t Low Pulse Width (write)
120
60 - - ns
PWCSH
Chip Selec t High Puls e Width (read)
Chip Selec t High Pulse Width (write)
60
60 - - ns
tR
Rise Time - - 15 ns
tF
Fall Time - - 15 ns
Figure 8 : 6800-seri es MPU Paral lel Interface Characteri sti cs
Valid Data
tcycle
tDSW
tAS tAH
tDHR
tACC
CS1
D/C
D0-D7
E
Valid Data
D0-D7
(Wr ite data to d ri ver)
(R ead data from dr iv e r )
tDHW
PWCS L PWCSH
tFtR
R/W
(CS2=1)
tOH
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Table 9 : 8080-Series MPU Parallel I nterface Ti ming Characteristi cs (VDD - VSS = 2.4 to 3. 5V , TA = -30 to 85°C)
Symbol Parameter Min Typ Max Unit
tcycle
Clock Cycle Time 300
- - ns
tAS
Address S etup Time 0 - - ns
tAH
Address Hol d Ti me 0 - - ns
tDSW
Write Data S etup Time 40 - - ns
tDHW
Write Data Hold Time 15 - - ns
tDHR
Read Data Hold Time 20 - - ns
tOH
Output Dis abl e Ti me - - 70 ns
tACC
Access Time - - 140 ns
PWCSL
Chip Selec t Low Pulse Widt h (read)
Chip Selec t Low Pulse Width (write)
120
60 - - ns
PWCSH
Chip Selec t High Puls e Width (read)
Chip Selec t High Pulse Width (write)
60
60 - - ns
tR
Rise Time - - 15 ns
tF
Fall Time - - 15 ns
Figure 9 : 8080-seri es MPU Paral lel Interface Characteri stics
Vali d Data
tcycle
tDSW
tAS tAH
tDHR
tACC
WR
D0-D7
Val id D a ta
D0-D7
(Wri te da ta to driver)
(R e ad da ta fro m dr i ver )
tDHW
PWCS L
PW
CSH
tFtR
(CS2=1)
tOH
D/C
CS1
RD
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Table 10 : Serial Interfac e Ti ming Characteristi cs (VDD - V SS = 2.4 to 3.5V, TA = -30 to 85°C)
Symbol Parameter Min Typ Max Unit
tcycle
Clock Cycle Time 250
- - ns
tAS
Address S etup Time 150 - - ns
tAH
Address Hol d Ti me 150 - - ns
tCSS
Chip Select Setup Time 120 - - ns
tCSH
Chip Select Hold Time 60 - - ns
tDSW
Write Data S etup Time 100 - - ns
tDHW
Write Data Hold Time 100 - - ns
tCLKL
Clock Low Tim e 100 - - ns
tCLKH
Clock Hi gh T i me 100 - - ns
tR
Rise Time - - 15 ns
tF
Fall Time - - 15 ns
Figure 10 : Serial Interface Characteri sti cs
* When SP# is high, pleas e refer to APPENDIX I for timing characterist ics for Solom on Sys t ech Limit ed internal use only.
Valid Data
tcycle
tDSW
tAS tAH
SCK
D/C
SDA
CS1
tDHW
tCLKL tCLKH
tFtR
(CS2=1) tCSS tCSH
D6D7 D4D5 D2D3 D0D1
SDA
D/C
SCK
CS1
(CS2=1)
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The configurat i on for serial mode interface is shown in the following diagram:
D0-D7: To MCU interface
VREF: External voltage reference for pre-charge s i gnal (VEE<VREF<VDD)
IREF: Connect a 1% res i stor to VEE and keep the current across the resistor at 8. 0uA
M/S#: Need to tie high for standalone s ys tem, refer to Pin Descript i on
M, CL, DOF# –NC for s tandalone
CS2 – CS2 ti ed to high for s eri al bus
R/W#, E , D0 – D5 – NC for seri al bus interf ace
CLS – pull high for internal oscillator
C1, C2, C3: 4.7uF
R1: Value=~1.2MΩ to set IREF to 8.0uA
Application Example
DISPLAY PANEL SIZE
132X64+ICON LINE
SSD1301
VEE VREF VDD VSS[GND] CS1# SDA SCK D/C# RES# VEE
VEE IREF VREF VDD VSS CS1# D7 D6 D/C# RES# VEE
VDD VDD
COM44
COM46
.
.
COM60
COM62
COM47
COM49
.
.
COM63
ICONS
COM0
ICONS
SEG0
.
.
.
.
.
.
.
.
.
.
.
.
SEG131
COM1
C68/80# P/S# SP#
6800 parallel int erface 1 1 X
8080 parallel int erface 0 1 X
Serial int erface X 0 0
I2C interfac e *Refer to Appendi x I
Note: X stands f o r don’ t care.
C1
C2 C3
R1
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SSD1301TR1 TAB PACKAGE DIMENSION
Note:
1 . A ll dime n s io n s a re in mm u nless spec if ic
2. Gen eral T oleran ce : +/-0.05m m
3. Cu Th ickness : 25um
4. SN Plating : 0.35um
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AP P ENDIX I IIC TIMING DIAGRAM AND PIN CONNECTION
PIN DESCRIPTION
SP# This pin i s s eri al interf ace sel ection i nput. When thi s pin and P/S # are pul l ed l ow, s eri al i nterface mode is selected. When it is
pulled high and P/ S# pin is pul led l ow, I 2C in t erface mode is s el ected.
FUNCTIONAL BLOCK DESCRIPTION
MPU I2C Interface
The I2C communication interface consists of slave address bit SA0 (D5), I2C-bus data signal SDA (D0 for output and D1 for input) and
I2C-bus cloc k signal SCL (D4). Both t he data and cloc k signals mus t be connected to pull-up res i stors. There are also fi ve i nput
signals i ncluding, RES#, CS1#, P/S #, CS2, SP#, which is used for the initializat i on of device.
a) Slave address bit (SA0)
SSD1301 have to recognize the s l ave address before t ransmi tting or rece i ving any i nformation by the I2C-bus. The device
will responds to the s lave address following by the slave addres s bit (“SA0” bit) and the read/write select bit (“R/W#” bit)
with the foll owing byte format ,
b7 b6 b5 b4 b3 b2 b1 b0
0 1 1 1 1 0 SA0 R/W#
“SA0” bit provi des an extension bit for the sl ave address. E i ther “0111100” or “0111101”, can be select ed as the slave
address of S SD1301.
“R/W#” bit determi nes the I2C-bus i n t erface is operating at eit her write mode or read st atus mode.
b) I2C-bus data signal (SDA )
SDA act s as a communicati on channel between the trans mitter and the recei ver. The dat a and the acknowledgement are
sent t hrough t he SDA. I f SDA in is connected to the “SDA out”, the devi ce becom es fully I IC bus compati bl e.
It shoul d be noticed t hat the ITO t rack resi stance and the pulled-up resistance at “SDA” pin becomes a vol tage potential
divider. A s a result, the acknowledgement would not be possible t o attain a vali d l ogi c 0 level in “S DA”.
The “SDA out” pin may be disconnected from the “SDA in” pin. With suc h arrangement, the acknowledgement signal will
be ignored in the I 2C-bus .
c) I2C-bus clock signal (SCL)
The transmission of information in the I2C-bus is following a clock signal, SCL. Each transmission of data bit is taken place
during a single clock peri od of SCL.
Command Decoder
Input is di rected to the com mand decoder based on the input of control byt e which consis ts of a D/ C# bi t and a R/W# bit. For further
information about the control byte, pleas e refer to the s ection “I2C-bus Write data and read regi ster status”. If both t he D/ C# bit and
the R/W# bit are low, the input signal is interpreted as a Command. It will be decoded and written to t he c orresponding com mand
register. If t he D/C# bit is high and the R/W# bit is low, input s i gnal i s written to Graphic Displ ay Data RAM (GDDRAM).
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I2C-bus Write data and read regi st er st atus
The I2C-bus int erf ace gives ac cess to write data and comm and i nt o the device. P l ease refer to Fi gure 11 f or the write mode of I2C-
bus in chronol ogi cal order.
Figure 11 : I2C-bus data format
Write mode
1) The mas ter device ini t i ates the dat a communication by a st art condition. The definit i on of the start condition i s shown in
Figure 12. The start condition is established by pulling the S DA from high to low while the SCL stays high.
2) The slave address is f ol l owing the start c ondi tion for recogni tion use. For t he SSD1301, t he slave address i s either
“b0111100” or “b0111101” by changing the S A0 to high or low.
3) The write mode is establi shed by setting the R/W# bit to l ogi c “0”.
4) An acknowledgem ent signal will be generated after receiving one byte of data, including the sl ave addres s and the R/W#
bit. P l ease refer to t he Fi gure 13 f or the graphical representation of the ack nowledge si gnal . The acknowledge bit i s
defined as t he SDA line is pulled down during the high period of the acknowledgem ent related c l ock pulse.
5) After the transmission of the slave address, either the control byte or the data byte may be sent across the SDA. A control
byte m ai nl y consis ts of Co and D/ C# bi ts fol l owing by s i x “0” ‘s.
a. If the Co bit is set as logic “0”, the transmission of the following information will contain data bytes only.
b. The D/C# bit det ermines the next data byte is acted as a c ommand or a data. I f the D/C# bit is s et to logic “0”, it
defines the following data byte as a command. If the D/C# bit is set to logic “1”, it defines the following data byte
as a data which will be stored at the GDDRAM. The GDDRAM colum n addres s pointer will be increased by one
autom at i cally aft er each data write.
6) Acknowledge bit will be generated after receiving each control byt e or dat a byt e.
0 1 1 1 1 0
SA0
P
Slave Addres s m ≥ 0 words n ≥ 0 bytes
MSB ……………….LSB
1 byte
Write mode
Slave Addres s
SSD1301
Slave Addres s
Read mode
R/W#
D/C#
Co
ACK
ACK
Control b
y
te Data b
y
te
ACK
Co
D/C#
Control b
y
te
ACK
Data b
y
te
ACK
S
0 1 1 1 1 0
0 1 1 1 1 0
S
SA0
ACK
Status bytes
ACK
P
SA0
R/W#
Co
D/C#
ACK
Control b
y
te
Note: Co – Continuation bit
D/C# – Data / Command Selec tion bit
ACK – Ac knowledgement
SA0 – Sl ave address bit
R/W# – Read / Write Sel ection bit
S – Start Condition / P – Stop Conditi on
0 0 0 0 0 0
0 1 1 1 1 0
R/W#
SSD1301
27 Rev 1.1
11/2001 SOLOMON
DATA OUTPUT
BY RECEIVER
DATA OUTPUT
BY TRANSMITTER
SCL FROM
MASTER
S
START
Condition Clock pulse for
acknowledgement
1 8 9
Non-acknowled
g
e
2
Acknowled
g
e
S
START condition
SDA
SCL
P
STOP c ondition
SDA
SCL
tHSTART tSSTOP
7) The write mode will be finished when a stop condit i on is applied. The stop c ondit i on is also defined in Figure 12. The stop
condition is established by pulling the “S DA in” from low to high while the “SCL” stays high.
Figure 12 : Definition of the start and stop condition
Figure 13 : Definition of the acknowledgement condition
SOLOMON Rev 1.1
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28
Please be not ed that the t ransmission of the data bit has some lim i tations.
1. The data bit, which is transmitted during each SCL pulse, must keep at a stable state within the “high” period of the
clock pulse. Please refer to the Figure 14 for graphical representations. Except in start or stop conditions, the data line
can be switc hed onl y when the S CL is low.
2. Both the data line (S DA) and the clock line (SCL) should be pull ed up by external resistors.
Figure 14 : Definition of the data transfer condition
Read mode (Read s tatus register)
1) The mas ter device fi rstly ini tiates the data comm uni cation by a s tart condition. The defi ni tion of the start condition is
shown in Figure 12.
2) The slave address is f ol l owing the start c ondi tion for recogni tion use. For t he SSD1301, the slave address i s either
“b0111100” or “b0111101”.
3) The read mode is establ i shed by sett i ng R/W# bit to logic “1”. The read mode allows t he MCU to monit or t he i nternal
status of the chip.
4) An acknowledgem ent signal will be generated after sending one byte of data, including the slave address and t he R/W#
bit. P l ease refer to t he Fi gure 13 for the graphical representation of the acknowledge signal.
5) The status of the register will be read at the next status byte. Please refer to the Read Command Table on page 15 for the
explanation of the s tatus byt e.
6) The read mode will be finished when a stop condition is applied. The stop conditi on is also defined in Figure 12.
Change
of data is
allow
SEG1
data line is
stable; data is
valid
SDA
SCL
SSD1301
29 Rev 1.1
11/2001 SOLOMON
Table 11 : I2C Interface Timing Characteristics (VDD-VSS=2.4 to 3.5V, TA=-30 to 85° C)
Symb
ol Parameter Min Typ Max Unit
tcycle Clock Cycle Time 2.5 - - us
tHSTART Start condi tion Hold Time 0.6 - - us
tHD Data Hold Time 300 - - ns
tSD Dat a Setup Time 100 - - ns
tSSTART Start c ondi tion Setup Ti me (Only relevant for a repeated Start
condition) 0.6 - - us
tSSTOP Stop condi t i on Setup Time 0.6 - - us
tR Rise Time for data and c l ock pin - - 300 ns
tF Fall Time f or dat a and clock pi n - - 300 ns
tIDLE Idle Time before a new transmi ssion c an start 1.3 - - us
Figure 15 : I2C In terface Tim ing Characteristics
// //
SDA
SCL
tHSTART
tCYCLE
tHD
tR
tF
tSD tSSTART tSSTOP
tIDLE
SOLOMON Rev 1.1
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30
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