● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
HV57009
Features
HVCMOS® technology
5.0V CMOS Logic
Output voltage up to -85V
Output current source control
16MHz equivalent data rate
Latched data outputs
Forward and reverse shifting options (DIR pin)
Diode to VDD allows efficient power recovery
Hi-Rel processing available
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Functional Block Diagram
64-Channel Serial to Parallel Converter
with P-Channel Open Drain Controllable Output Current
General Description
The HV57009 is a low-voltage serial to high-voltage parallel
converter with P-channel open drain outputs. This device has
been designed for use as a driver for plasma panels.
The device has two parallel 32-bit shift registers, permitting data
rates twice the speed of one (they are clocked together). There
are also 64 latches and control logic to perform the blanking of
the outputs. HVOUT1 is connected to the first stage of the first
shift register through the blanking logic. Data is shifted through
the shift registers on the logic low to high transition of the clock.
The DIR pin causes CCW shifting when connected to VSS, and
CW shifting when connected to VDD. A data output buffer is
provided for cascading devices. This output reflects the current
status of the last bit of the shift register (HVOUT64). Operation of
the shift register is not affected by the LE (latch enable), or the
BL (blanking) inputs. Transfer of data from the shift registers to
latches occurs when the LE input is high. The data in the latches
is stored when LE is low.
The HV570 has 64 channels of output constant current sourcing
capability. They are adjustable from 0.1 to 2.0mA through one
external resistor or a current source.
HVOUT1
HVOUT2
HVOUT3
•
•
•
HVOUT33
HVOUT34
HVOUT35
•
•
•
Latch
Latch
Latch
Latch
VDD
VSS
BLLE
CLK
DIR
VBP +IN -IN
HVOUT32
HVOUT64
DI/O2B
Note:
Each SR (shift register) provides 32 outputs. SR1 supplies outputs 1 to 32 and SR2 supplies outputs 33 to 64.
Programmable
Current
DI/O1B
SR2
I/O
DI/O2A DI/O1A
I/O
SR1
2
HV57009
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Ordering Information
Device
Package Options
80-Lead PQFP
20.00x14.00mm body
3.4mm height (max)
0.65mm pitch
Die
HV57009 HV57009PG-G HV57009X
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter Value
Supply voltage, VDD
1-0.5V to +7.5V
Output voltage , VNN
1VDD + 0.5V to -95V
Logic input levels1-0.3V to VDD +0.3V
Ground current21.5A
Continuous total power dissipation31200mW
Operating temperature range -40°C to +85°C
Storage temperature range -65°C to +150°C
Lead temperature4260°C
Recommended Operating Conditions
Sym Parameter Min Max Units
VDD Logic supply voltage 4.5 5.5 V
HVOUT HV output off voltage -85 VDD V
VIH High-level input voltage VDD -1.2V VDD V
VIL Low-level input voltage 0 1.2 V
fCLK Clock frequency per register DC 8.0 MHz
4.5
TAOperating free-air temperature -40 +85 °C
Notes:
Power-up sequence should be the following:
1. Connect ground
2. Apply VDD
3. Set all inputs to a known state
Power-down sequence should be the reverse of the above.
Pin Configuration
1
80
80-Lead PQFP (PG)
HV57009PG
LLLLLLLLLL
YYWW
CCCCCCCC AAA
L = Lot Number
YY = Year Sealed
WW = Week Sealed
C = Country of Origin
A = Assembler ID
= “Green” Packaging
Product Marking
80-Lead PQFP (PG)
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability.
Notes:
All voltages are referenced to VSS.
Duty cycle is limited by the total power dissipated in the package.
For operation above 25°C ambient derate linearly to maximum
operating temperature at 20mW/°C.
1.6mm (1/16inch) from case for 10 seconds
1.
2.
3.
4.
3
HV57009
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
DC Electrical Characteristics (All voltages are referenced to VSS, VSS = 0, TA = 25OC)
Sym Parameter Min Max Units Conditions
IDD VDD supply current - 15 mA VDD = VDD max, fCLK = 8.0MHz
INN High voltage supply current - -10 µA Outputs off, HVOUT = -85V
(total of all outputs)
IDDQ Quiescent VDD supply current - 100 µA All inputs = VDD,
except +IN = VSS = GND
VOH High level output Data Out VDD -0.5V - V IO = -100µA
HVOUT +1.0 VDD V IO = -2.0mA
VOL Low level output Data Out - +0.5 V IO = 100µA
IIH High-level logic input current - 1.0 µA VIH = VDD
IIL Low-level logic input current - -1.0 µA VIL = 0V
ICS High output source current
- -2.0
mA
VREF = 2.0V, REXT = 1.0KΩ,
see Figures 1a and 1b
-0.1 - VREF = 0.1V, REXT = 1.0KΩ,
see Figures 1a and 1b
ΔICS HV output source current for IREF = 2.0mA - 10 % VREF = 2.0V, REXT = 1.0KΩ
Note:
Current going out of the chip is considered negative.
AC Electrical Characteristics (Logic signal inputs and data inputs have tr, tf ≤ 5ns [10% and 90% points] for measurements)
Sym Parameter Min Max Units Conditions
fCLK Clock frequency DC 8.0 MHz Per register
4.5 When cascading devices
tWL, tWH Clock width high or low 62 - ns ---
tSU Data set-up time before clock rises 20 - ns ---
tHData hold time after clock rises 15 - ns ---
tON, tOFF Time from latch enable to HVOUT - 500 ns CL = 15pF
tDHL Delay time clock to data high to low - 150 ns CL = 15pF
tDLH Delay time clock to data low to high - 150 ns CL = 15pF
tDLE Delay time clock to LE low to high 45 - ns ---
tWLE LE pulse width 25 - ns ---
tSLE LE set-up time before clock rises 0 - ns ---
tr, tf
Max. allowable clock rise and fall time
(10% and 90% points) - 100 ns ---
4
HV57009
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Input and Output Equivalent Circuits
VDD
Input
Logic Inputs
Data Out
Logic Data Output
Input To Internal
Circuits
VSS
Analog Input
ICS
HVOUT
High Voltage Output
VDD
VSS
VDD
VSS
VDD
PCNTRL
Shift Register Operation
25 26 36 37
HVOUT32
•
•
•
•
•
HVOUT2
HVOUT1
HVOUT33
•
•
•
•
•
HVOUT63
HVOUT64
Pin
SR1
SR2
DIR = VDD; CW (HVOUT1→HVOUT64)
DIR = VSS; CCW (HVOUT64→HVOUT1)
CW
CW
DIR = VDD
DIR = VSS
DI/O1A DI/O2A DI/O2B DI/O1B
DI/O2A DI/O1A DI/O1B DI/O2B
5
HV57009
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Switching Waveforms
LE
HV
OUT
w/ data input
LOW
Previous I
O
= I
REF
Previous I
O
= 0
I
O
= 0
I
O
= I
REF
Data Valid50% 50%Data Input
CLK
Data Out
50% 50% 50%
t
SU
t
H
t
WL
t
WH
50%
t
DLH
t
DHL
50%
t
WLE
t
DLE
t
SLE
50% 50%
t
ON
10%
HV
OUT
w/ data input
HIGH
90%
90%
10%
t
OFF
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
HV
OUT
(off)
V
DD
HV
OUT
(off)
10%
90% 90%
10% 50%
t
f
t
r
Function Table
Function
Inputs Outputs
Data In CLK LE BL DIR Shift Reg HV Outputs Data Out
All O/P high X X X L X * ON *
Data falls through
(latches transparent)
L _↑_H H X L.....L ON L
H _↑_H H X H.....H OFF H
Data stored in latches X X L H X * Inversion of stored data *
I/O relation
DI/O1-2A _↑_H H H Qn→Qn+1 New ON or OFF DI/O1-2B
DI/O1-2A _↑_L H H Qn→Qn+1 Previous ON or OFF DI/O1-2B
DI/O1-2B _↑_L H L Qn→Qn-1 Previous ON or OFF DI/O1-2A
DI/O1-2B _↑_H H L Qn→Qn-1 New ON or OFF DI/O1-2A
Note:
* = dependent on previous stage’s state. See Figure 7 for DIN and DOUT pin designation for CW and CCW shift.
H = VDD (Logic)/VNN (HV Outputs)
L = VSS
6
HV57009
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Typical Current Programing Circuits
+IN -IN
R
D
*10KΩ
C
D
*390pF
HV57009
Logic
To other
outputs
-+
0.1µF
VREF
IOUT
HVOUT
VDD
0.1µF
VBP
IREF
REXT
+IN -IN
R
D
*10KΩ
C
D
*390pF
HV57009
Logic
To other
outputs
- +
VSS
Figure 1b: Positive Control
Figure 1a: Negative Control
VREF
IOUT
HVOUT
VDD
VBP
IREF
REXT
VSS
*Required if REXT > 10KΩ or REXT is replaced by a constant current source.
Since IOUT = IREF = │ VREF │ / REXT
Therefore:
If IOUT = 2.0mA and VREF = -5.0V → REXT = 2.5KΩ.
If IOUT = 1.0mA and REXT = 1.0KΩ → VREF = -1.0V.
If REXT >10KΩ, add series network RD and CD to ground for
stability as shown.
This control method behaves linearly as long as the opera-
tional amplifier is not saturated. However, it requires a nega-
tive power source and needs to provide a current IREF = IOUT
for each HV570 chip being controlled.
If HVOUT ≥ +1.0V, the HVOUT cascade may no longer oper-
ate as a perfect current source, and the output current will
diminish. This effect depends on the magnitude of the output
current.
Given IOUT and VREF, the REXT can be calculated by using:
REXT = VREF / IREF = VREF / IOUT
The intersection of a set of IOUT and VREF values can be lo-
cated in the graph shown below. The value picked for REXT
must always be in the shaded area for linear operation. This
control method has the advantage that VREF is positive, and
draws only leakage current. If REXT > 10KΩ, add series net-
work RD and CD to ground for stability as shown.
Note:
Lower reference current IREF
, results in higher distortion,
∆ICS, on the output.
HV570 I
OUT
vs. V
REF
0
1
2
3
4
0 1 2 3 4 5
VREF (Volts)
ITUO )Am(
0.5K0.1K 0.2K 1K 2K 3K
5K
7
HV57009
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Pin Function
Pin # Function
1 HVOUT24
2 HVOUT23
3 HVOUT22
4 HVOUT21
5 HVOUT20
6 HVOUT19
7 HVOUT18
8 HVOUT17
9 HVOUT16
10 HVOUT15
11 HVOUT14
12 HVOUT13
13 HVOUT12
14 HVOUT11
15 HVOUT10
16 HVOUT9
17 HVOUT8
18 HVOUT7
19 HVOUT6
20 HVOUT5
Pin # Function
21 HVOUT4
22 HVOUT3
23 HVOUT2
24 HVOUT1
25 DI/O1A
26 DI/O2A
27 NC
28 NC
29 LE
30 CLK
31 BL
32 VSS
33 DIR
34 VDD
35 -IN
36 DI/O2B
37 DI/O1B
38 NC
39 +IN
40 VBP
Pin # Function
41 HVOUT64
42 HVOUT63
43 HVOUT62
44 HVOUT61
45 HVOUT60
46 HVOUT59
47 HVOUT58
48 HVOUT57
49 HVOUT56
50 HVOUT55
51 HVOUT54
52 HVOUT53
53 HVOUT52
54 HVOUT51
55 HVOUT50
56 HVOUT49
57 HVOUT48
58 HVOUT47
59 HVOUT46
60 HVOUT45
Pin # Function
61 HVOUT44
62 HVOUT43
63 HVOUT42
64 HVOUT41
65 HVOUT40
66 HVOUT39
67 HVOUT38
68 HVOUT37
69 HVOUT36
70 HVOUT35
71 HVOUT34
72 HVOUT33
73 HVOUT32
74 HVOUT31
75 HVOUT30
76 HVOUT29
77 HVOUT28
78 HVOUT27
79 HVOUT26
80 HVOUT25
Notes:
Pin designation for DIR = VDD.
A 0.1µF capacitor is needed between VDD and VBP (pin 40) for better output current stability and to prevent transient cross-coupling between
outputs. See Figures 1a and 1b.
1.
2.
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com.
©2008 All rights reserved. Unauthorized use or reproduction is prohibited.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
8
HV57009
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV57009
A102908
80-Lead PQFP Package Outline (PG)
20.00x14.00mm body, 3.40mm height (max), 0.80mm pitch, 3.90mm footprint
Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ θ1
Dimen-
sion
(mm)
MIN 2.80* 0.25 2.55 0.30 23.65* 19.80* 17.65* 13.80* 0.80
BSC
0.73 1.95
REF 0.25
BSC
0O5O
NOM - - 2.80 - 23.90 20.00 17.90 14.00 0.88 3.5O-
MAX 3.40 0.50* 3.05 0.45 24.15* 20.20* 18.15* 14.20* 1.03 7O16O
JEDEC Registration MO-112, Variation CB-1, Issue B, Sept.1995.
* This dimension is not specified in the original JEDEC drawing. The value listed is for reference only.
Drawings not to scale.
Supertex Doc. #: DSPD-80PQFPPG, Version B101708.
1
80
Seating
Plane
Gauge
Plane
θ
L
L1
L2
View B
View B
θ1
b
e
Side View
A2
A
A1
E
E1
D
D1
Seating
Plane
Top View
Note 1
(Index Area
D1/4 x E1/4)
Note:
A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
1.
