CC400
SWRS050 Page 13 of 32
15. Microcontroller Interface
Used in a typical system,
CC400
will
interface to a microcontroller. This
microcontroller must be able to:
• Program the
CC400
into different
modes via the 3-wire serial interface
(PDATA, STROBE, CLOCK).
• Operate with the bidirectional data pin
DIO.
• Perform oversampling of the de-
modulator output (on pin DIO), recover
the clock corresponding to the actual
datarate, and perform data quali-
fication (on Manchester encoded
data).
• Data to be sent must be Manchester
encoded.
• Optionally the microcontroller can
monitor the frequency lock status from
pin LOCK.
• Optionally the microcontroller can
perform precharging of the receiver in
order to reduce the turn-on time (see
p.21).
15.1. Connecting the microcontroller
The microcontroller uses 3 output pins for
the serial interface (PDATA, STROBE and
CLOCK). A bi-directional pin is used for
data to be transmitted and data received
(DIO). Optionally another pin can be used
to monitor the LOCK signal. This signal is
logic level high when the PLL is in lock.
See Figure 7.
15.2. Data transmission
The data to be sent has to be Manchester
encoded (also known as bi-phase-level
coding). The Manchester code ensures
that the signal has a constant DC
component that is necessary for the FSK
demodulator. The Manchester code is
based on transitions; a “0” is encoded as a
low-to-high transition, a “1” is encoded as
a high-to-low transition. See Figure 6.
When the DIO is logic level high, the upper
FSK frequency is transmitted. The lower
frequency is transmitted when DIO is low.
Note that the receiver data output is
inverted when using low-side LO, which is
default using SmartRF Studio.
15.3. Data reception
The output of the demodulator (DIO) is a
digital signal (alternating between 0 V and
VDD). For small input signals, there will be
some noise on this signal, located at the
edges of the digital signal. The datarate of
this signal may be up to 9.6 kbps. Due to
the Manchester coding, the fundamental
frequency of the signal is also 9.6 kHz. An
oversampling of 4-8 times the frequency of
the demodulator-output is recommended.
I.e. the sampling frequency should be at
least 40-80 kHz for 9.6 kbps. For a lower
datarate the sampling frequency can be
reduced.
In a typical application the data output is
sampled by the microcontroller, and stored
in an accumulating register. The length of
this register will typically be 4-8 bits
(depending on the oversampling ratio).
The qualification of the data (decide
whether the signal is “0” or “1”) can be
based on comparing the number of 0’s
with the number of 1’s. See Application
Note AN008 “Oversampling and data
decision for the CC400/CC900” for more
details.
Time
TX
data
10110001101
Figure 6: Manchester encoding. Figure 7: Microcontroller interface.
CC400
PDATA
CLOCK
STROBE
DIO
LOCK
Micro-
controller