IRF1324S-7PPbF HEXFET(R) Power MOSFET Applications High Efficiency Synchronous Rectification in SMPS Uninterruptible Power Supply High Speed Power Switching Hard Switched and High Frequency Circuits VDSS 24V RDS(on) typ. max. 0.8m ID (Silicon Limited) 1.0m 429A ID (Package Limited) 240A Benefits Improved Gate, Avalanche and Dynamic dV/dt Ruggedness Fully Characterized Capacitance and Avalanche SOA Enhanced body diode dV/dt and dI/dt Capability Lead-Free Base Part Number Package Type IRF1324S-7PPbF D2Pak 7 Pin Absolute Maximum Ratings Symbol D2Pak 7 Pin G D S Gate Drain Source Standard Pack Form Quantity Tube 50 Tape and Reel Left 800 Orderable Part Number IRF1324S-7PPbF IRF1324STRL-7PP Parameter Max. ID @ TC = 25C Continuous Drain Current, VGS @ 10V (Silicon Limited) 429 ID @ TC = 100C ID @ TC = 25C Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Package Limited) 303 240 IDM PD @TC = 25C Pulsed Drain Current Maximum Power Dissipation 1640 300 VGS dv/dt TJ TSTG Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Units A W 2.0 20 1.6 -55 to + 175 W/C V V/ns C 300 Avalanche Characteristics EAS IAR EAR Single Pulse Avalanche Energy (Thermally Limited) Avalanche Current Repetitive Avalanche Energy Thermal Resistance Symbol RJC RJA Parameter Junction-to-Case Junction-to-Ambient 230 See Fig.14,15, 18a, 18b mJ A mJ Typ. Max. Units --- --- 0.50 40 C/W HEXFET(R) is a registered trademark of Infineon. *Qualification standards can be found at www.infineon.com 1 2015-10-15 IRF1324S-7PPbF Static @ TJ = 25C (unless otherwise specified) Parameter V(BR)DSS Drain-to-Source Breakdown Voltage Min. 24 Typ. Max. Units --- --- V Conditions VGS = 0V, ID = 250A V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient --- 0.023 --- V/C Reference to 25C, ID = 5mA RDS(on) Static Drain-to-Source On-Resistance --- 0.80 1.0 m VGS = 10V, ID = 160A VGS(th) Gate Threshold Voltage 2.0 --- 4.0 IDSS Drain-to-Source Leakage Current --- --- 20 --- --- 250 IGSS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage --- --- --- --- 200 -200 nA RG Gate Resistance --- 3.0 --- V A VDS = VGS, ID = 250A VDS =24V, VGS = 0V VDS =19V,VGS = 0V,TJ =125C VGS = 20V VGS = -20V Dynamic Electrical Characteristics @ TJ = 25C (unless otherwise specified) gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Forward Trans conductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 190 --- --- --- --- --- --- --- --- --- --- --- --- 180 47 58 122 19 240 86 93 7700 3380 1930 Coss eff.(ER) Effective Output Capacitance (Energy Related) --- Coss eff.(TR) Effective Output Capacitance (Time Related) Diode Characteristics Parameter Continuous Source Current IS (Body Diode) Pulsed Source Current ISM (Body Diode) VSD Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge IRRM ton Reverse Recovery Current Forward Turn-On Time VDS = 15V, ID = 160A ID = 75A VDS = 12V VGS = 10V 4780 --- S 252 --- --- nC --- --- --- ns --- --- --- --- --- pF --- VGS = 0V, VDS = 0V to 19V --- 4970 --- VGS = 0V, VDS = 0V to 19V Min. Typ. Max. Units --- --- 429 --- --- 1640 --- --- --- --- --- --- --- 71 74 83 92 2.0 1.3 107 110 120 140 --- VDD = 16V ID = 160A RG= 2.7 VGS = 10V VGS = 0V VDS = 19V = 1.0MHz, See Fig. 5 Conditions MOSFET symbol showing the A integral reverse p-n junction diode. V TJ = 25C,IS = 160A,VGS = 0V TJ = 25C VDD = 20V ns TJ = 125C IF = 160A, TJ = 25C di/dt = 100A/s nC TJ = 125C A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes: Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 240A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. (Refer to AN-1140) Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.018mH, RG = 25, IAS = 160A, VGS =10V. Part not recommended for use above this value. ISD 160A, di/dt 600A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS. When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994 R is measured at TJ approximately 90C. 2 2015-10-15 IRF1324S-7PPbF 1000 1000 VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V BOTTOM TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP BOTTOM 100 100 4.5V 10 0.1 60s PULSE WIDTH Tj = 175C 60s PULSE WIDTH Tj = 25C 1 10 4.5V 10 0.1 100 Fig. 1 Typical Output Characteristics 100 Fig. 2 Typical Output Characteristics 100 R DS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (A) 10 1.8 1000 T J = 175C 10 T J = 25C 1 VDS = 15V 60s PULSE WIDTH 2 3 4 5 6 7 8 ID = 160A VGS = 10V 1.6 1.4 1.2 1.0 0.8 0.6 0.1 -60 -40 -20 0 20 40 60 80 100 120 140160 180 9 T J , Junction Temperature (C) VGS, Gate-to-Source Voltage (V) Fig. 4 Normalized On-Resistance vs. Temperature Fig. 3 Typical Transfer Characteristics 100000 12.0 VGS = 0V, f = 1 MHZ C iss = Cgs + Cgd, C ds SHORTED C rss = Cgd VGS, Gate-to-Source Voltage (V) ID= 75A C oss = Cds + Cgd C, Capacitance (pF) 1 V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) C iss Coss 10000 Crss 1000 1 10 100 VDS , Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage 3 VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V 10.0 VDS = 19V VDS = 12V 8.0 6.0 4.0 2.0 0.0 0 50 100 150 200 QG, Total Gate Charge (nC) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 2015-10-15 IRF1324S-7PPbF 10000 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 1000 T J = 175C OPERATION IN THIS AREA LIMITED BY R DS (on) 1000 100 1msec 100 T J = 25C 10 10msec 10 Tc = 25C Tj = 175C Single Pulse VGS = 0V 1.0 0.5 1.0 1.5 2.0 2.5 0 1 VSD, Source-to-Drain Voltage (V) Limited By Package ID, Drain Current (A) 350 300 250 200 150 100 50 0 25 50 75 100 125 150 100 Fig 8. Maximum Safe Operating Area V(BR)DSS , Drain-to-Source Breakdown Voltage (V) 450 400 10 VDS , Drain-to-Source Voltage (V) Fig. 7 Typical Source-to-Drain Diode Forward Voltage 32 Id = 5mA 31 30 29 28 27 26 25 24 -60 -40 -20 0 20 40 60 80 100 120 140160 180 175 T J , Temperature ( C ) T C , Case Temperature (C) Fig 9. Maximum Drain Current vs. Case Temperature 1.4 Fig 10. Drain-to-Source Breakdown Voltage EAS , Single Pulse Avalanche Energy (mJ) 1000 1.2 1.0 Energy (J) DC 1 0.0 0.8 0.6 0.4 0.2 0.0 -5 0 5 10 15 20 VDS, Drain-to-Source Voltage (V) Fig 11. Typical COSS Stored Energy 4 100sec 25 ID 45A 80A BOTTOM 160A 900 TOP 800 700 600 500 400 300 200 100 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C) Fig 12. Maximum Avalanche Energy vs. Drain Current 2015-10-15 IRF1324S-7PPbF Thermal Response ( Z thJC ) C/W 1 D = 0.50 0.1 0.20 0.10 J 0.05 0.02 0.01 0.01 R1 R1 J 1 R2 R2 R3 R3 Ri (C/W) R4 R4 C 2 1 2 3 3 4 C 4 Ci= iRi Ci= iRi 1E-005 0.02070 0.000010 0.08624 0.000070 0.24491 0.001406 0.15005 0.009080 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc SINGLE PULSE ( THERMAL RESPONSE ) 0.001 1E-006 I (sec) 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 1000 Avalanche Current (A) Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse) 0.01 100 0.05 0.10 10 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 14. Avalanche Current vs. Pulse width 5 2015-10-15 IRF1324S-7PPbF Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.infineon.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long as Tjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 18a, 18b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 13, 14). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) EAR , Avalanche Energy (mJ) 250 TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 160A 200 150 100 50 0 25 50 75 100 125 150 175 PD (ave) = 1/2 ( 1.3*BV*Iav) = T/ ZthJC Iav = 2T/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav Starting T J , Junction Temperature (C) Fig 15. Maximum Avalanche Energy vs. Temperature VGS(th) , Gate threshold Voltage (V) 4.5 4.0 3.5 3.0 ID = 250A 2.5 ID = 1.0mA ID = 1.0A 2.0 1.5 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 200 T J , Temperature ( C ) Fig 16. Threshold Voltage vs. Temperature 6 2015-10-15 IRF1324S-7PPbF Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs V(BR)DSS 15V tp L VDS D.U.T RG IAS 20V tp DRIVER + V - DD A 0.01 Fig 18a. Unclamped Inductive Test Circuit Fig 19a. Switching Time Test Circuit I AS Fig 18b. Unclamped Inductive Waveforms Fig 19b. Switching Time Waveforms Id Vds Vgs Vgs(th) Qgs1 Qgs2 Fig 20a. Gate Charge Test Circuit 7 Qgd Qgodr Fig 20b. Gate Charge Waveform 2015-10-15 IRF1324S-7PPbF D2Pak - 7 Pin Package Outline (Dimensions are shown in millimeters (inches)) Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ 8 2015-10-15 IRF1324S-7PPbF D2Pak - 7 Pin Part Marking Information PART NUMBER INTERNATIONAL RECTIFIER LOGO F1324S-7P YWWP 17 ASSEMBLY LOT CODE 89 DATE CODE Y = YEAR W = WEEK P = LEADFREE D2Pak - 7 Pin Tape and Reel Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ 9 2015-10-15 IRF1324S-7PPbF Qualification Information Industrial (per JEDEC JESD47F guidelines) Qualification Level Moisture Sensitivity Level MSL1 D2-Pak 7 Pin (per JEDEC JSTD020D) Yes RoHS Compliant Qualification standards can be found at International Rectifier's web site: http//www.irf.com/ Applicable version of JEDEC standard at the time of product release. Revision History Date 4/8/2014 10/15/2015 Comments Added Ordering information table on page 1 Updated package outline on page 8 Updated part marking on page 9 Added Qualification table on page 10. Updated data sheet with new IR corporate template. Updated datasheet with corporate template Updated typo on GFS from "VDD =50V, ID =160A, Min= 270S to "VDD = 15V,ID =160A Min =190S on page 2. Corrected typo on Fig9 package limited from "160A" to "240A" on page 4. Published by Infineon Technologies AG 81726 Munchen, Germany (c) Infineon Technologies AG 2015 All Rights Reserved. IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer's compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. 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