TPS7A3301RGWR - NATIONAL SEMICONDUCTOR

Februa ry 199 7

Revised June 2000

NC7ST00 TinyLogic



HST 2-Input NAND Gate

NC7ST00

TinyLogic HST 2-Input NAND Gate

General Description

The NC7S T00 is a singl e 2-In put high pe rform ance C MOS

NAND Gate, with TTL-compatible inputs. Advanced Silicon

Gate CMOS fabrication assures high speed and low power

circuit operation. ESD protection diodes inherently guard

both inputs and output with respect to the VCC and GND

rails. High gain circuitry offers high noise immunity and

reduced sensitivity to input edg e rate. The TTL-compatible

inputs facilitate TTL to NMOS/CMOS interfacing. Device

performance is similar to MM74HCT but with 1/2 the output

current drive of HC/HCT.

Features

■Space saving SOT23 or SC70 5-lead package

■High Spee d; tPD <7 ns typ, VCC = 5V, CL = 15 pF

■Low Quiescent Power; ICC <1 µA typ, VCC = 5.5V

■Balanced Output Drive ; 2 mA IOL, −2 mA IOH

■TTL-compatible inputs

Ordering Code:

Logic Symbol

IEEE/IEC

Connection Diagram

(Top View)

Pin Descriptions Function Table

Y = AB

H = HIGH Lo gic Level

L = LOW Logic L ev el

TinyLogic is a t radema rk of Fair c hild Sem icond uc tor Co rporat ion.

Order Pac kage Product Code Package Description Supplied As

Number Number Top Mark

NC7ST00M5 MA05B 8S00 5-Lead SOT23, JEDEC MO-178, 1.6mm 250 Units on Tape and Reel

NC7ST00M5X MA05B 8S00 5-Lead SOT23, JEDEC MO-178, 1.6mm 3k Units on Tape and Reel

NC7ST00P5 MAA05A T00 5-Lead SC70, EIAJ SC-88a, 1.25mm Wide 250 Units on Tape and Reel

NC7ST00P5X MAA05A T00 5-Lead SC70, EIAJ SC-88a, 1.25mm Wide 3k Units on Tape and Reel

Pin Names Description

A, B Inputs

Y Output

Inputs Output

ABY

LLH

LHH

HLH

HHL

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NC7ST00

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions (Note 2)

Note 1: Absolute Maximum Ratings a re those va lues beyon d which d am-

age to the dev ice may occur. The databook specification s should be met,

without exception, to ensure that the design is reliable over its power sup-

ply, temperature, and output/input loading variables Fairchild does not rec-

ommend operation of circ uits outs ide the dat abook specificat ions.

Note 2: Unu s ed inputs m ust be he ld H I GH or LOW. They ma y not fl oat.

DC Electrical Characteristics

Supply Voltage (VCC)−0.5V to +7.0V

DC Input Diode Current (lIK)

VIN < −0.5V −20 mA

VIN ≥ VCC + 0.5V +20 mA

DC Input Voltage VIN −0.5V to VCC + 0.5V

DC Output Diode Current (IOK)

VOUT < −0.5V −20 mA

VOUT > VCC +0.5V +20 mA

Output Voltage (VOUT)−0.5V to VCC + 0.5V

DC Output Source or

Sink Current (IOUT)±12.5 mA

DC VCC or Ground Current per

Supply Pin (ICC or IGND)±25 mA

Stora ge Tem per atu re (T STG)−65°C to +150°C

Junct ion Tem per atu re (T J) 150°C

Lead Temperature (TL);

(Soldering, 10 second s) 26 0°C

Power Di ssipa ti on (PD) @ +85°C

SOT23- 5 200 mW

SC70-5 150 mW

Supply Voltag e 4.5V–5.5V

Input Voltage (VIN)0.0V–V

Output Voltage (VOUT)0V–V

Operating Temperature (TA)−40°C to +85°C

Input Rise and Fall Time (tr, tf)

VCC = 5.0V 0–500 ns

Thermal Resistance (θJA)

SOT23-5 300°C/W

SC70-5 425°C/W

Symbol Parameter VCC TA = +25°CT

A = −40°C to +85°CUnits Conditions

(V) MinTypMaxMinMax

VIH HIGH Level Input Voltage 4.5–5.5 2.0 2.0 V

VIL LOW Level Input Voltage 4.5–5.5 0.8 0.8 V

VOH HIGH Level Output Vo ltage 4.5 4.4 4.5 4.4 VIOH = −20 µA

4.5 4.18 4.35 4.13 IOH = −2 mA

VIN = VIL

VOL LOW Level Output Voltage 4.5 0 0.1 0.1 VIOL = 20 µA

4.5 0.10 0.26 0.33 IOL = 2 mA

VIN = VIH

IIN Input Leakage Current 5.5 ±0.1 ±1.0 µA0 ≤ VIN ≤ 5.5V

ICC Qui escent Supply Current 5.5 1.0 10.0 µAV

IN = VCC or GND

ICCT ICC per Input 5.5 2.0 2.9 mA One input VIN = 0.5V or 2.4V,

other input VCC or GND

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NC7ST00

AC Electrical Characteristics

Note 3: CPD is defined as the value of the int erna l equ ivale nt capa cit ance which is deriv ed fr om dyn amic opera ting curre nt. Curre nt cons umption (ICCD) at

no output loading and operating at 50% duty cycle. (See Figure 2). CPD is related to ICCD dynamic operating current by the expression:

ICCD = (CPD)(VCC)(fIN) + (ICCstatic).

AC Loading and Waveforms

CL include s l oad and str ay c apacitan ce

Input PRR = 1.0 MHz; t w = 500 ns

FIGURE 1. AC Test Circuit

Input = AC Wav efo r m; PRR = variable; Duty Cycle = 50 %

FIGURE 2. ICCD Test Circuit FIGURE 3. AC Waveforms

Symbol Parameter VCC T

A = +25°CT

A = −40°C to +85°CUnits Conditions Fig. No.

(V) Min Typ Max Min Max

tPLH, Propagation Delay 5.0 3.4 12

CL = 15 pF Figures

1, 3

tPHL 6.3 17

4.5 6.0 16 20 CL = 50 pF

11.5 27 31

5.5 4.1 14 18

11.2 26 30

tTLH, Output Transition Time 5.0 4 10 ns CL = 15 pF Figures

1, 3

tTHL 4.5 11 25 31 ns CL = 50 pF

5.5 10 21 26

CIN Input Capacitance Open 2 10 pF

CPD Power Dissipation Capacitance 5.0 6 pF (Note 3) Figure 2

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NC7ST00

Tape and Reel Specification

TAPE FORMAT

TAPE DIMENSIONS inches (millimeters)

Package Tape Number Cavity Cover Tape

Designator Section Cavities Status Status

Leader (Start End) 125 (typ) Empty Sealed

M5, P5 Carrier 250 Filled Sealed

Trailer (Hub End) 75 (typ) Empty Sealed

Leader (Start End) 125 (typ) Empty Sealed

M5X, P5X Carrier 3000 Filled Sealed

Trailer (Hub End) 75 (typ) Empty Sealed

Package Tape Size DIM A DIM B DIM F DIM KoDIM P1 DIM W

SC70-5 8 mm 0.093 0.096 0.138 ± 0.004 0.053 ± 0.004 0.157 0.315 ± 0.004

(2.35) (2.45) (3.5 ± 0.10) (1.35 ± 0.10) (4) (8 ± 0.1)

SOT23-5 8 mm 0.130 0.130 0.138 ± 0.002 0.055 ± 0.004 0.157 0.315 ± 0.012

(3.3) (3.3) (3.5 ± 0.05) ( 1.4 ± 0.11) (4) (8 ± 0.3)

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NC7ST00

Tape and Reel Specification (Continued)

REEL DIMENSIONS inches (millimeters)

Tape

Size ABCDN W1 W2 W3

8 mm 7.0 0.059 0.512 0.795 2.165 0.331 + 0.059/−0.000 0.567 W1 + 0.078/−0.039

(177.8) (1.50) (13.00) (20.20) (55.00) (8.40 + 1.5 0/−0.00) (14.40) (W1 + 2.00/−1.00)

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NC7ST00

Physical Dimensions inches (millimeters) unless otherwise noted

5-Lead SOT23, JEDEC MO-178, 1.6mm

Package Number MA05B

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NC7ST00 TinyLogic



HST 2-Input NAND Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

5-Lead SC70, EIAJ SC-88a, 1.25mm Wide

Package Number MAA05A

Fairchild does not assume an y responsibility fo r use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.