HCPL-3120/J312, HCNW3120 2.5 Amp Output Current IGBT Gate Drive Optocoupler Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The HCPL-3120 contains a GaAsP LED while the HCPLJ312 and the HCNW3120 contain an AlGaAs LED. The LED is optically coupled to an integrated circuit with a power output stage. These optocouplers are ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. The voltage and current supplied by these optocouplers make them ideally suited for directly driving IGBTs with ratings up to 1200 V/100 A. For IGBTs with higher ratings, the HCPL-3120 series can be used to drive a discrete power stage which drives the IGBT gate. The HCNW3120 has the highest insulation voltage of VIORM=1414Vpeak in the IEC/EN/DIN EN 60747-5-2. The HCPL-J312 has an insulation voltage of VIORM=891Vpeak and the VIORM=630Vpeak is also available with the HCPL-3120 (Option060). * 2.5 A maximum peak output current Functional Diagram 3750 Vrms for 1 min. for HCPL3120/J312 HCNW3120 HCPL-3120/J312 N/C 1 8 VCC 7 VO ANODE 2 ANODE 2 6 VO CATHODE 3 CATHODE 3 N/C 4 N/C 1 SHIELD 5 VEE N/C 4 SHIELD * 2.0 A minimum peak output current * 25 kV/s minimum Common Mode Rejection (CMR) at VCM = 1500 V * 0.5 V maximum low level output voltage (VOL) Eliminates need for negative gate drive * ICC = 5 mA maximum supply current * Under Voltage Lock-Out protection (UVLO) with hysteresis * Wide operating VCC range: 15 to 30Volts * 500 ns maximum switching speeds * Industrial temperature range: 40C to 100C * SafetyApproval: UL Recognized 5000 Vrms for 1 min. for HCNW3120 8 VCC CSA Approval 7 VO IEC/EN/DIN EN 60747-5-2 Approved 6 N/C VIORM= 630 Vpeak for HCPL3120 (Option 060) 5 VEE VIORM= 891 Vpeak for HCPLJ312 VIORM= 1414 Vpeak for HCNW3120 TRUTH TABLE Applications LED VCC - VEE "POSITIVE GOING" (i.e., TURN-ON) VCC - VEE "NEGATIVE GOING" (i.e., TURN-OFF) VO OFF 0 - 30 V 0 - 30 V LOW ON 0 - 11 V 0 - 9.5 V LOW ON 11 - 13.5 V 9.5 - 12 V TRANSITION ON 13.5 - 30 V 12 - 30 V HIGH * IGBT/MOSFET gate drive * AC/Brushless DC motor drives * Industrial inverters * Switch mode power supplies A 0.1 F bypass capacitor must be connected between pins 5 and 8. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Selection Guide Part Number HCPL-3120 HCPL-J312 HCNW3120 HCPL-3150* Output Peak Current ( IO) 2.5 A 2.5 A 2.5 A 0.6 A IEC/EN/DIN EN 60747-5-2 Approval VIORM=630 Vpeak VIORM=891 Vpeak VIORM=1414 Vpeak (Option 060) VIORM=630 Vpeak (Option 060) *The HCPL-3150 Data sheet available. Contact Avago sales representative or authorized distributor. Ordering Information HCPL-3120 and HCPL-J312 are UL recognized with 3750 Vrms for 1 minute per UL1577. HCNW3120 is UL Recognized with 5000 Vrms for 1 minute per UL1577. Option Part Number RoHS Compliant Non RoHS Compliant Package Surface Mount -000E No option 50 per tube -300E #300 50 per tube HCPL-3120 -500E -060E #500 300mil X X X DIP-8 #060 X 50 per tube -360E #360 X X X 50 per tube -560E #560 X X X 1000 per tube -000E X 50 per tube HCPL-J312 -300E No option 300mil #300 DIP-8 X X X 50 per tube -500E #500 X 1000 per reel -000E X 42 per tube HCNW3120 -300E No option 400mil #300 DIP-8 X X X 42 per tube -500E #500 X 750 per reel X X X Gull Wing Tape & Reel IEC/EN/DIN EN 60747-5-2 X X X X X X Quantity 1000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-3120-560E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant. Example 2: HCPL-3120 to order product of 300 mil DIP package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation `#XXX' is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use `-XXXE'. Package Outline Drawings HCPL-3120 Outline Drawing (Standard DIP Package) 7.62 0.25 (0.300 0.010) 9.65 0.25 (0.380 0.010) 8 TYPE NUMBER 7 6 5 6.35 0.25 (0.250 0.010) OPTION CODE* DATE CODE A XXXXZ YYWW 1 2 3 4 1.78 (0.070) MAX. 1.19 (0.047) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 5 TYP. 3.56 0.13 (0.140 0.005) 4.70 (0.185) MAX. 0.51 (0.020) MIN. 2.92 (0.115) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). 1.080 0.320 (0.043 0.013) * MARKING CODE LETTER FOR OPTION NUMBERS. "V" = OPTION 060 OPTION NUMBERS 300 AND 500 NOT MARKED. 0.65 (0.025) MAX. 2.54 0.25 (0.100 0.010) NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. HCPL-3120 Gull Wing Surface Mount Option 300 Outline Drawing LAND PATTERN RECOMMENDATION 9.65 0.25 (0.380 0.010) 8 7 6 1.016 (0.040) 5 6.350 0.25 (0.250 0.010) 1 2 3 10.9 (0.430) 4 1.27 (0.050) 1.19 (0.047) MAX. 1.780 (0.070) MAX. 9.65 0.25 (0.380 0.010) 7.62 0.25 (0.300 0.010) 3.56 0.13 (0.140 0.005) 1.080 0.320 (0.043 0.013) 0.635 0.25 (0.025 0.010) 0.635 0.130 2.54 (0.025 0.005) (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. 2.0 (0.080) + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 12 NOM. Package Outline Drawings HCPL-J312 Outline Drawing (Standard DIP Package) 7.62 0.25 (0.300 0.010) 9.80 0.25 (0.386 0.010) 8 TYPE NUMBER 7 6 5 6.35 0.25 (0.250 0.010) DATE CODE A XXXX YYWW 1 2 3 4 1.78 (0.070) MAX. 1.19 (0.047) MAX. 5 TYP. 3.56 0.13 (0.140 0.005) + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 4.70 (0.185) MAX. 0.51 (0.020) MIN. 2.92 (0.115) MIN. 1.080 0.320 (0.043 0.013) DIMENSIONS IN MILLIMETERS AND (INCHES). OPTION NUMBERS 300 AND 500 NOT MARKED. 0.65 (0.025) MAX. NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. 2.54 0.25 (0.100 0.010) HCPL-J312 Gull Wing Surface Mount Option 300 Outline Drawing LAND PATTERN RECOMMENDATION 9.80 0.25 (0.386 0.010) 8 7 6 1.016 (0.040) 5 6.350 0.25 (0.250 0.010) 1 2 3 10.9 (0.430) 4 1.27 (0.050) 1.19 (0.047) MAX. 1.780 (0.070) MAX. 9.65 0.25 (0.380 0.010) 7.62 0.25 (0.300 0.010) 3.56 0.13 (0.140 0.005) 1.080 0.320 (0.043 0.013) NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 0.635 0.25 (0.025 0.010) 0.635 0.130 2.54 (0.025 0.005) (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). 2.0 (0.080) 12 NOM. HCNW3120 Outline Drawing (8-Pin Wide Body Package) 11.00 MAX. (0.433) 11.15 0.15 (0.442 0.006) 8 7 6 9.00 0.15 (0.354 0.006) 5 TYPE NUMBER A HCNWXXXX DATE CODE YYWW 1 2 3 4 10.16 (0.400) TYP. 1.55 (0.061) MAX. 7 TYP. + 0.076 0.254 - 0.0051 + 0.003) (0.010 - 0.002) 5.10 MAX. (0.201) 3.10 (0.122) 3.90 (0.154) 0.51 (0.021) MIN. 2.54 (0.100) TYP. 1.78 0.15 (0.070 0.006) 0.40 (0.016) 0.56 (0.022) DIMENSIONS IN MILLIMETERS (INCHES). NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. HCNW3120 Gull Wing Surface Mount Option 300 Outline Drawing 11.15 0.15 (0.442 0.006) 8 7 6 LAND PATTERN RECOMMENDATION 5 9.00 0.15 (0.354 0.006) 1 2 3 13.56 (0.534) 4 1.3 (0.051) 2.29 (0.09) 12.30 0.30 (0.484 0.012) 1.55 (0.061) MAX. 11.00 MAX. (0.433) 4.00 MAX. (0.158) 1.78 0.15 (0.070 0.006) 2.54 (0.100) BSC 0.75 0.25 (0.030 0.010) 1.00 0.15 (0.039 0.006) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. + 0.076 0.254 - 0.0051 + 0.003) (0.010 - 0.002) 7 NOM. Solder Reflow Temperature Profile 300 PREHEATING RATE 3 C + 1 C/-0.5 C/SEC. REFLOW HEATING RATE 2.5 C 0.5 C/SEC. 200 PEAK TEMP. 245 C PEAK TEMP. 240 C TEMPERATURE (C) 2.5 C 0.5 C/SEC. 30 SEC. 160 C 150 C 140 C PEAK TEMP. 230 C SOLDERING TIME 200 C 30 SEC. 3 C + 1 C/-0.5 C 100 PREHEATING TIME 150 C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 0 50 100 150 TIME (SECONDS) NOTE: NON-HALIDE FLUX SHOULD BE USED. Recommended Pb-Free IR Profile tp Tp TEMPERATURE TL Tsmax * 260 +0/-5 C TIME WITHIN 5 C of ACTUAL PEAK TEMPERATURE 15 SEC. 217 C 150 - 200 C RAMP-UP 3 C/SEC. MAX. RAMP-DOWN 6 C/SEC. MAX. Tsmin ts PREHEAT 60 to 180 SEC. 25 tL 60 to 150 SEC. t 25 C to PEAK TIME NOTES: THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 C, Tsmin = 150 C NOTE: NON-HALIDE FLUX SHOULD BE USED. * RECOMMENDED PEAK TEMPERATURE FOR WIDEBODY 400mils PACKAGE IS 245 C 200 250 Regulatory Information Agency/Standard HCPL-3120 HCPL-J312 HCNW3120 Underwriters Laboratory (UL) Recognized under UL 1577, Component Recognition Program, Category, File E55361 Compliant Compliant Compliant Canadian Standards Association (CSA) File CA88324, per Component Acceptance Notice #5 Compliant Compliant Compliant IEC/EN/DIN EN 60747-5-2 Compliant Option 060 Compliant Compliant Insulation and Safety Related Specifications Parameter Symbol HCPL- 3120 Value HCPL- J312 HCNW 3120 Units Conditions Minimum External L(101) 7.1 7.4 9.6 mm Air Gap (Clearance) Measured from input terminals to output terminals, shortest distance through air. Minimum External L(102) 7.4 8.0 10.0 mm Tracking (Creepage) Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal 0.08 0.5 1.0 mm Plastic Gap (Internal Clearance) Insulation thickness between emitter and detector; also known as distance through insulation. Tracking Resistance (Comparative Tracking Index) DIN IEC 112/VDE 0303 Part 1 CTI >175 >175 >200 Volts Isolation Group IIIa IIIa IIIa Material Group (DIN VDE 0110, 1/89, Table 1) All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creep-age and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics Description Symbol HCPL-3120 Option 060 HCPL-J312 HCNW3120 Unit Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 150 V rms I-IV I-IV I-IV for rated mains voltage 300 V rms I-IV I-IV I-IV for rated mains voltage 450 V rms I-III I-III I-IV for rated mains voltage 600 V rms I-III I-IV for rated mains voltage 1000 V rms I-III Climatic Classification 55/100/21 55/100/21 55/100/21 Pollution Degree (DIN VDE 0110/1.89) 2 2 2 Maximum Working Insulation Voltage 630 891 1414 VIORM Vpeak Input to Output Test Voltage, Method b* VPR 1181 1670 2652 Vpeak VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5pC Input to Output Test Voltage, Method a* VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, Partial Discharge < 5pC VPR 945 1336 2121 Vpeak Highest Allowable Overvoltage* VIOTM 6000 6000 8000 Vpeak (Transient Overvoltage, tini = 10 sec) Safety Limiting Values - maximum values allowed in the event of a failure, also see Figure 37. Case Temperature TS 175 175 150 C Input Current IS INPUT 230 400 400 mA Output Power PS OUTPUT 600 600 700 mW Insulation Resistance at TS, VIO = 500 V RS 109 109 109 *Refer to the IEC/EN/DIN EN 60747-5-2 section (page 1-6/8) of the Isolation Control Component Designer's Catalog for a detailed description of Method a/b partial discharge test profiles. Note: These optocouplers are suitable for "safe electrical isolation" only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. Surface mount classification is Class A in accordance with CECC 00802. Absolute Maximum Ratings ParameterSymbol Min. Max. Units Storage Temperature TS -55 125 C Operating Temperature TA -40 100 C Average Input Current IF(AVG) 25 mA Peak Transient Input Current (<1 s pulse width, 300 pps) IF(TRAN) 1.0 A Reverse Input Voltage HCPL-3120 VR 5 Volts HCPL-J312 HCNW3120 5 Note 1 "High" Peak Output Current IOH(PEAK) 2.5 A 2 "Low" Peak Output Current IOL(PEAK) 2.5 A 2 Supply Voltage (VCC - VEE) 35 Volts Input Current (Rise/Fall Time) tr(IN) /tf(IN) 500 ns Output Voltage VO(PEAK) VCC Volts Output Power Dissipation PO 250 mW 3 Total Power Dissipation PT 295 mW 4 0 0 Lead Solder Temperature HCPL-3120 260C for 10 sec., 1.6 mm below seating plane HCPL-J312 HCNW3120 260C for 10 sec., up to seating plane Solder Reflow Temperature Profile See Package Outline Drawings section Recommended Operating Conditions ParameterSymbol Min. Max. Units Power Supply Voltage 15 30 Volts 16 mA (VCC - VEE) Input Current (ON) HCPL-3120 7 HCPL-J312 IF(ON) HCNW3120 10 Input Voltage (OFF) VF(OFF) -3.6 0.8 V Operating Temperature TA -40 100 C Electrical Specifications (DC) Over recommended operating conditions (TA = -40 to 100C, for HCPL-3120, HCPL-J312 IF(ON) = 7 to 16mA, for HCNW3120 IF(ON) = 10 to 16mA, VF(OFF) = -3.6 to 0.8 V, VCC = 15 to 30 V, VEE = Ground) unless otherwise specified. ParameterSymbolDevice Min. Typ.* Max. High Level Output IOH Current 0.5 1.5 UnitsTest Conditions Fig. Note A VO = (VCC - 4 V) 2, 3, 5 2 2.0 A VO = (VCC - 15 V) 17 0.5 A VO = (VEE + 2.5 V) 5, 6, 5 VO = (VEE + 15 V) 18 2 High Level Output VOH (VCC - 4) (VCC - 3) V IO = -100 mA Voltage 1, 3, 19 6, 7 Low Level Output VOL 0.1 0.5 V IO = 100 mA Voltage 4, 6, 20 High Level Supply ICCH 2.5 5.0 mA Current Output Open, IF = 7 to 16 mA 7, 8 Low Level Supply ICCL 2.5 5.0 mA Current Output Open, VF = -3.0 to +0.8 V Threshold Input IO = 0 mA, 9, 15, VO > 5 V 21 16 Low Level Output IOL Current 2.0 HCPL-3120 2.3 HCPL-J312 1.0 High HCNW3120 2.3 VFHL Input Forward VF Voltage HCPL-3120 8.0 V 1.2 V IF = 10 mA mV/C IF = 10 mA V IR = 10 A 1.5 1.8 1.95 HCPL-J312 HCNW3120 1.6 Temperature HCPL-3120 -1.6 Coefficient of Forward Voltage HCPL-J312 HCNW3120 -1.3 Input Reverse BVR mA 0.8 VF/TA 5.0 A Current Low to Threshold Input Voltage High to Low IFLH 2.0 HCPL-3120 5 Breakdown Voltage HCPL-J312 HCNW3120 3 Input Capacitance HCPL-3120 60 HCPL-J312 HCNW3120 70 CIN pF UVLO Threshold VUVLO+ 11.0 12.3 13.5 V VUVLO- 9.5 UVLO Hysteresis UVLOHYS 10.7 1.6 *All typical values at TA = 25C and VCC - VEE = 30 V, unless otherwise noted. 10 12.0 IR = 100 A f = 1 MHz, VF = 0 V VO > 5 V, IF = 10 mA 22, 34 Switching Specifications (AC) Over recommended operating conditions (TA = -40 to 100C, for HCPL-3120,HCPL-J312 IF(ON) = 7 to 16mA, for HCNW3120 IF(ON) = 10 to 16mA, VF(OFF) = -3.6 to 0.8 V, VCC = 15 to 30 V, VEE = Ground) unless otherwise specified. ParameterSymbol Min. Typ.* Max.Units Test ConditionsFig.Note Propagation Delay Time tPLH 0.10 0.30 0.50 s to High Output Level Rg = 10 , Cg = 10 nF, 10, 11, 16 12, 13, Propagation Delay Time tPHL 0.10 0.30 0.50 s to Low Output Level f = 10 kHz, Duty Cycle = 50% 14, 23 Pulse Width Distortion PWD 0.3 s 17 Propagation Delay Difference Between Any Two Parts PDD (tPHL - tPLH) 0.35 s 35, 36 12 Rise Time tr 0.1 s 23 Fall Time tf 0.1 s UVLO Turn On Delay tUVLO ON 0.8 s UVLO Turn Off Delay tUVLO OFF 0.6 -0.35 VO > 5 V, IF = 10 mA 22 VO < 5 V, IF = 10 mA Output High Level Common |CMH| 25 35 kV/s Mode Transient Immunity TA = 25C, IF = 10 to 16 mA, VCM = 1500 V, VCC = 30 V Output Low Level Common |CML| 25 35 kV/s Mode Transient Immunity TA = 25C, VCM = 1500 V, VF = 0 V, VCC = 30 V *All typical values at TA = 25C and VCC - VEE = 30 V, unless otherwise noted. 11 24 13, 14 13, 15 Package Characteristics Over recommended temperature (TA = -40 to 100C) unless otherwise specified. Parameter Symbol Device Min. Input-Output Momentary VISO HCPL-3120 3750 Withstand Voltage** HCPL-J312 HCNW3120 Typ. Max. UnitsTest Conditions RH < 50%, 8, 11 3750 t = 1 min., 9, 11 5000 TA = 25C 10, 11 1012 VI-O = 500 VDC 11 Resistance RI-O (Input-Output) HCPL-3120 HCPL-J312 HCNW3120 VRMS 1012 1013 TA = 25C 1011 TA = 100C HCPL-3120 0.6 f = 1 MHz (Input-Output) HCPL-J312 0.8 HCNW3120 0.5 Capacitance CI-O pF 0.6 LED-to-Case Thermal qLC 467 C/W Resistance Thermocouple located at center LED-to-Detector Thermal qLD 442 C/W Resistance underside of package Detector-to-Case Thermal Resistance Fig. Note qDC 126 28 C/W *All typicals at TA = 25C. **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage." Notes: 1. Derate linearly above 70C free-air temperature at a rate of 0.3 mA/C. 2. Maximum pulse width = 10 s, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum = 2.0 A. See Applications section for additional details on limiting IOH peak. 3. Derate linearly above 70C free-air temperature at a rate of 4.8 mW/C. 4. Derate linearly above 70C free-air temperature at a rate of 5.4 mW/C. The maximum LED junction tem-perature should not exceed 125C. 5. Maximum pulse width = 50 s, maximum duty cycle = 0.5%. 6. In this test VOH is measured with a dc load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps. 7. Maximum pulse width = 1 ms, maximum duty cycle = 20%. 8. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 4500 Vrms for 1 second (leakage detection current limit, II-O 5 A). 9. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 4500 Vrms for 1 second (leakage detection current limit, II-O 5 A). 10. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 6000 Vrms for 1 second (leakage detection current limit, II-O 5 A). 11. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 12. The difference between tPHL and tPLH between any two HCPL-3120 parts under the same test condition. 13. Pins 1 and 4 need to be connected to LED common. 14. Common mode transient immunity in the high state is the maximum tolerable dVCM /dt of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO>15.0V ). 15. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO<1.0V ). 16. This load condition approximates the gate load of a 1200 V/75A IGBT. 17. Pulse Width Distortion (PWD) is defined as |tPHL-tPLH| for any given device. 12 -3 -4 -40 -20 0 20 40 60 80 100 1.8 1.6 1.4 1.2 1.0 -40 -20 TA - TEMPERATURE - C IOL - OUTPUT LOW CURRENT - A VOL - OUTPUT LOW VOLTAGE - V 80 100 0.20 0.15 0.10 0.05 -20 0 20 40 60 80 100 3 2 1 0 -40 -20 0 20 40 60 80 100 ICC - SUPPLY CURRENT - mA 3.0 2.5 VCC = 30 V VEE = 0 V IF = 10 mA for ICCH IF = 0 mA for ICCL 80 TA - TEMPERATURE - C Figure 7. ICC vs. temperature. HCPL-3120 fig 7 0 0.5 100 ICCH ICCL 3.0 2.5 IF = 10 mA for ICCH IF = 0 mA for ICCL TA = 25 C VEE = 0 V 2.0 1.5 15 20 1.0 1.5 2.0 2.5 IOH - OUTPUT HIGH CURRENT - A VF(OFF) = -3.0 to 0.8 V VCC = 15 to 30 V VEE = 0 V 3 2 1 0 100 C 25 C -40 C 0 0.5 1.0 1.5 HCPL-3120 fig 6 3.5 60 -6 Figure 6. VOL vs. IOL. HCPL-3120 fig 5-new ICCH ICCL 40 IF = 7 to 16 mA VCC = 15 to 30 V VEE = 0 V -5 25 VCC - SUPPLY VOLTAGE - V Figure 8. ICC vs. VCC. HCPL-3120 fig 8 2.0 IOL - OUTPUT LOW CURRENT - A Figure 5. IOL vs. temperature. 3.5 20 -4 4 VF (OFF) = -3.0 TO 0.8 V VOUT = 2.5 V VCC = 15 TO 30 V VEE = 0 V HCPL-3120 fig 4-new 0 -3 HCPL-3120 fig 3 TA - TEMPERATURE - C Figure 4. VOL vs. temperature. 1.5 -40 -20 100 C 25 C -40 C -2 Figure 3. VOH vs. IOH. 4 VF (OFF) = -3.0 TO 0.8 V IOUT = 100 mA VCC = 15 TO 30 V VEE = 0 V TA - TEMPERATURE - C ICC - SUPPLY CURRENT - mA 60 -1 HCPL-3120 fig 2 0.25 13 40 Figure 2. IOH vs. temperature. HCPL-3120 fig 1 2.0 20 TA - TEMPERATURE - C Figure 1. VOH vs. temperature. 0 -40 0 (VOH - VCC ) - OUTPUT HIGH VOLTAGE DROP - V -2 IF = 7 to 16 mA VOUT = (VCC - 4 V) VCC = 15 to 30 V VEE = 0 V VOL - OUTPUT LOW VOLTAGE - V -1 2.0 IF = 7 to 16 mA IOUT = -100 mA VCC = 15 to 30 V VEE = 0 V IOH - OUTPUT HIGH CURRENT - A (VOH - VCC ) - HIGH OUTPUT VOLTAGE DROP - V 0 30 2.5 4 3 2 1 0 -40 -20 0 20 40 60 80 100 TA - TEMPERATURE - C HCPL-J312 5 VCC = 15 TO 30 V VEE = 0 V OUTPUT = OPEN 4 3 2 1 0 -40 -20 0 20 40 60 80 100 TA - TEMPERATURE - C IFLH - LOW TO HIGH CURRENT THRESHOLD - mA VCC = 15 TO 30 V VEE = 0 V OUTPUT = OPEN IFLH - LOW TO HIGH CURRENT THRESHOLD - mA IFLH - LOW TO HIGH CURRENT THRESHOLD - mA HCPL-3120 5 HCNW3120 5 VCC = 15 TO 30 V VEE = 0 V OUTPUT = OPEN 4 3 2 1 0 -40 -20 0 20 40 60 80 100 TA - TEMPERATURE - C Figure 9. IFLH vs. temperature. HCPL-3120 fig 9b-new HCPL-3120 fig 9a 500 400 TPLH TPHL 300 200 100 15 20 25 400 300 200 TPLH TPHL 100 30 6 8 Figure 10. Propagation delay vs. VCC. Tp - PROPAGATION DELAY - ns Tp - PROPAGATION DELAY - ns 500 VCC = 30 V, VEE = 0 V TA = 25 C IF = 10 mA Cg = 10 nF DUTY CYCLE = 50% f = 10 kHz 200 TPLH TPHL 0 10 20 30 40 50 Rg - SERIES LOAD RESISTANCE - Figure 13. Propagation delay vs. Rg. HCPL-3120 fig 13 14 14 16 300 200 TPLH TPHL 100 0 20 40 60 80 Cg - LOAD CAPACITANCE - nF Figure 14. Propagation delay vs. Cg. HCPL-3120 fig 14 300 200 TPLH TPHL 100 -40 -20 0 20 40 60 80 100 TA - TEMPERATURE - C HCPL-3120 fig 12 VCC = 30 V, VEE = 0 V TA = 25 C IF = 10 mA Rg = 10 DUTY CYCLE = 50% f = 10 kHz 400 400 IF = 10 mA VCC = 30 V, VEE = 0 V Rg = 10 , Cg = 10 nF DUTY CYCLE = 50% f = 10 kHz Figure 12. Propagation delay vs. temperature. HCPL-3120 fig 11 300 100 12 Figure 11. Propagation delay vs. IF. HCPL-3120 fig 10 400 10 IF - FORWARD LED CURRENT - mA VCC - SUPPLY VOLTAGE - V 500 500 VCC = 30 V, VEE = 0 V Rg = 10 , Cg = 10 nF TA = 25 C DUTY CYCLE = 50% f = 10 kHz Tp - PROPAGATION DELAY - ns IF = 10 mA TA = 25 C Rg = 10 Cg = 10 nF DUTY CYCLE = 50% f = 10 kHz Tp - PROPAGATION DELAY - ns Tp - PROPAGATION DELAY - ns 500 HCPL-3120 fig 9c-new 100 30 VO - OUTPUT VOLTAGE - V VO - OUTPUT VOLTAGE - V 25 20 15 10 5 0 HCPL-J312 35 0 1 2 3 4 30 25 20 15 10 5 0 5 IF - FORWARD LED CURRENT - mA 0 1 2 3 4 5 IF - FORWARD LED CURRENT - mA Figure 15. Transfer characteristics. HCPL-3120 fig 15 HCPL-3120 1000 100 IF + 10 VF - 1.0 0.1 0.01 0.001 1.10 1.20 1.30 1.40 1.50 HCPL-J312/HCNW3120 1000 TA = 25C IF - FORWARD CURRENT - mA IF - FORWARD CURRENT - mA HCPL-3120 fig 15b TA = 25C 100 IF + VF - 10 1.0 0.1 0.01 0.001 1.2 1.60 VF - FORWARD VOLTAGE - VOLTS 1.3 1.4 1.5 Figure 16. Input current vs. forward voltage. HCPL-3120 fig 16a HCPL-3120 fig 16b 1 8 0.1 F 2 + - 7 IF = 7 to 16 mA 6 IOH 4 5 Figure 17. IOH test circuit. HCPL-3120 fig 17 15 4V + VCC = 15 - to 30 V 3 1.6 1.7 VF - FORWARD VOLTAGE - VOLTS 1 8 2 7 0.1 F 3 6 1 8 2 7 0.1 F IOL + VCC = 15 - to 30 V 2.5 V + - VOH IF = 7 to 16 mA + VCC = 15 - to 30 V 3 6 100 mA 4 5 4 Figure 18. IOL Test circuit. Figure 19. VOH Test circuit. HCPL-3120 fig 18 1 HCPL-3120 fig 19 8 0.1 F 2 1 3 6 4 5 8 0.1 F 100 mA 7 2 + VCC = 15 - to 30 V 7 IF VOL Figure 20. VOL Test circuit. 3 6 4 5 Figure 21. IFLH Test circuit. HCPL-3120 fig 20 HCPL-3120 fig 21 1 8 0.1 F 2 7 IF = 10 mA 3 6 4 5 Figure 22. UVLO test circuit. HCPL-3120 fig 22 16 5 VO > 5 V + - VCC VO > 5 V + VCC = 15 - to 30 V 1 8 0.1 F IF = 7 to 16 mA + 10 KHz - 500 50% DUTY CYCLE 2 + - 7 IF VCC = 15 to 30 V tr tf VO 3 6 90% 10 50% VOUT 10 nF 4 10% 5 tPLH tPHL Figure 23. tPLH, tPHL, tr, and tf test circuit and waveforms. HCPL-3120 fig 23 VCM IF 5V + - 1 t 0.1 F A B V 8 2 VO 6 4 5 VCC = 30 V VO VOH SWITCH AT A: IF = 10 mA - SWITCH AT B: IF = 0 mA VCM = 1500 V Figure 24. CMR test circuit and waveforms. HCPL-3120 fig 24 17 t t + - VO + VCM 0V 7 3 = VOL Applications Information Eliminating Negative IGBT Gate Drive (Discussion applies to HCPL-3120, HCPL-J312, and HCNW3120) To keep the IGBT firmly off, the HCPL-3120 has a very low maximum VOL specification of 0.5V. The HCPL-3120 realizes this very low VOL by using a DMOS transistor with 1 (typical) on resistance in its pull down circuit. When the HCPL-3120 is in the low state, the IGBT gate is shorted to the emitter by Rg + 1. Minimizing Rg and the lead inductance from the HCPL-3120 to the IGBT gate and emitter (possibly by mounting the HCPL- HCPL-3120 +5 V 1 270 CONTROL INPUT 74XXX OPEN COLLECTOR 8 0.1 F 2 7 3 6 4 5 Figure 25. Recommended LED drive and application circuit. HCPL-3120 fig 25 18 3120 on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure 25. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the HCPL-3120 input as this can result in unwanted coupling of transient signals into the HCPL-3120 and degrade performance. (If the IGBT drain must be routed near the HCPL-3120 input, then the LED should be reverse-biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the HCPL3120.) + - VCC = 18 V + HVDC Rg Q1 3-PHASE AC Q2 - HVDC Selecting the Gate Resistor (Rg) to Minimize IGBT Switching Losses. (Discussion applies to HCPL-3120, HCPL-J312 and HCNW3120) For the circuit in Figure 26 with IF (worst case) = 16mA, Rg = 8, Max Duty Cycle = 80%, Qg = 500 nC, f=20 kHz and TA max = 85 C: Step 1: Calculate Rg Minimum from the IOL Peak Specifica tion. The IGBT and Rg in Figure 26 can be analyzed as a simple RC circuit with a voltage supplied by the HCPL3120. (VCC - VEE - VOL) Rg -------------- IOLPEAK (VCC - VEE - 2 V) = -------------- IOLPEAK (15 V + 5 V - 2 V) = -------------- 2.5 A = 7.2 @ 8 The VOL value of 2V in the previous equation is a conservative value of VOL at the peak current of 2.5A (see Figure 6). At lower Rg values the voltage supplied by the HCPL-3120 is not an ideal voltage step. This results in lower peak currents (more margin) than predicted by this analysis. When negative gate drive is not used VEE in the previous equation is equal to zero volts. PE= 16 mA * 1.8 V * 0.8 = 23 mW Step 2: Check the HCPL-3120 Power Dissipation and Increase Rg if Necessary. The HCPL-3120 total power dissipation (PT ) is equal to the sum of the emitter power (PE) and the output power (PO): PT= PE + PO PO= 4.25 mA * 20 V + 5.2 J * 20 kHz = 85 mW + 104 mW = 189 mW > 178 mW (PO(MAX) @ 85C = 250 mW-15C*4.8 mW/C) The value of 4.25 mA for ICC in the previous equation was obtained by derating the ICC max of 5 mA (which occurs at -40C) to ICC max at 85C (see Figure 7). Since PO for this case is greater than PO(MAX), Rg must be increased to reduce the HCPL-3120 power dissipation. PO(SWITCHING MAX) = PO(MAX) - PO(BIAS) = 178 mW - 85 mW = 93 mW PO(SWITCHINGMAX) ESW(MAX) = -------------- f 93 mW = -------- = 4.65 W 20 kHz For Qg = 500 nC, from Figure 27, a value of ESW = 4.65 W gives a Rg = 10.3 . PE= IF * VF * Duty Cycle PO= PO(BIAS) + PO (SWITCHING) = ICC * (VCC - VEE)+ ESW(RG, QG) * f HCPL-3120 +5 V 1 270 CONTROL INPUT 74XXX OPEN COLLECTOR 8 0.1 F 2 7 3 6 + - Q1 VEE = -5 V 3-PHASE AC 5 Q2 Figure 26. HCPL-3120 typical application circuit with negative IGBT gate drive. HCPL-3120 fig 26 19 + HVDC Rg + - 4 VCC = 15 V - HVDC Thermal Model (Discussion applies to HCPL-3120, HCPLJ312 and HCNW3120) The steady state thermal model for the HCPL-3120 is shown in Figure 28. The thermal resistance values given in this model can be used to calculate the temperatures at each node for a given operating condition. As shown by the model, all heat generated flows through qCA which raises the case temperature TC accordingly. The value of qCA depends on the conditions of the board design and is, therefore, determined by the designer. The value of qCA=83C/W was obtained from thermal measure ments using a 2.5 x 2.5 inch PC board, with small traces (no ground plane), a single HCPL-3120 soldered into the center of the board and still air. The absolute maximum power dissipation derating specifications assume a qCAvalue of 83C/W. From the thermal mode in Figure 28 the LED and detector IC junction temperatures can be expressed as: PE ParameterDescription IF LED Current VF LED On Voltage Duty Cycle Maximum LED Duty Cycle PO Parameter Description ICC Supply Current VCC Positive Supply Voltage VEE Negative Supply Voltage ESW(Rg,Qg) Energy Dissipated in the HCPL-3120 for each IGBT Switching Cycle (See Figure 27) f Switching Frequency qLC * qDC + PD *(-------------- + qCA) + TA qLC + qDC + qLD qLC * qDC TJD = PE (-------------- + qCA) qLC + qDC + qLD + PD * (qDC||(qLD + qLC) + qCA) + TA Inserting the values for qLC and qDC shown in Figure 28 gives: TJE = PE * (256C/W + qCA) + PD * (57C/W + qCA) + TA TJD = PE * (57C/W + qCA) + PD * (111C/W + qCA) + TA For example, given PE = 45 mW, PO = 250 mW, TA = 70C and qCA= 83C/W: TJE = PE * 339C/W + PD * 140C/W + TA = 45 mW * 339C/W + 250 mW * 140C/W + 70C = 120C TJD = PE * 140C/W + PD * 194C/W + TA = 45 mW * 140C/W + 250 mW * 194C/W + 70C = 125C TJE and TJD should be limited to 125C based on the board layout and part placement (qCA) specific to the application. 20 Esw - ENERGY PER SWITCHING CYCLE - J TJE = PE @ (qLC||(qLD + qDC) + qCA) 14 Qg = 100 nC Qg = 500 nC Qg = 1000 nC 12 10 VCC = 19 V VEE = -9 V 8 6 4 2 0 0 10 20 30 40 50 Rg - GATE RESISTANCE - Figure 27. Energy dissipated in the HCPL-3120 for each IGBT switching cycle. HCPL-3120 fig 27 LD = 442 C/W TJE TJD LC = 467 C/W DC = 126 C/W TC CA = 83 C/W* TA TJE = LED junction temperature TJD T= IC junction temperature = LED JUNCTION TEMPERATURE JEdetector = DETECTOR IC JUNCTION TEMPERATURE JDcase TC TT= temperature measured at the center of the package bottom C = CASE TEMPERATURE MEASURED AT THE qLC = LED-to-case thermal resistance CENTER OF THE PACKAGE BOTTOM = LED-TO-CASE THERMAL RESISTANCE LC LED-to-detector qLD = thermal resistance LD = LED-TO-DETECTOR THERMAL RESISTANCE qDC = detector-to-case thermal resistance DC = DETECTOR-TO-CASE THERMAL RESISTANCE = CASE-TO-AMBIENT thermal THERMAL resistance RESISTANCE qCA = CAcase-to-ambient * WILL DEPEND ON THE BOARD DESIGN AND *qCACA willTHE depend on the board design and the placement of the part. PLACEMENT OF THE PART. Figure 28. Thermal model. LED Drive Circuit Considerations for Ultra High CMR Performance. (Discussion applies to HCPL-3120, HCPL-J312, HCPL-3120 fig 28 and HCNW3120) Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 29. The HCPL-3120 improves CMR perform-ance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins 5-8 as shown in Figure30. This capacitive coupling causes 1 2 CLEDP perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off ) during common mode transients. For example, the recommended application circuit (Figure 25), can achieve 25kV/s CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections. 8 1 7 2 6 3 5 4 CLEDO1 8 CLEDP 7 CLEDO2 3 CLEDN 4 Figure 29. Optocoupler input to output capacitance model for unshielded optocouplers. HCPL-3120 fig 29 21 CLEDN SHIELD 6 5 Figure 30. Optocoupler input to output capacitance model for shielded optocouplers. HCPL-3120 fig 30 CMR with the LED On (CMRH). A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of 10 mA provides adequate margin over the maximum IFLH of 5mA to achieve 25kV/ s CMR. RSAT and VSAT of the logic gate. As long as the low state voltage developed across the logic gate is less than VF(OFF), the LED will remain off and no common mode failure will occur. The open collector drive circuit, shown in Figure 32, cannot keep the LED off during a +dVcm/dt transient, since all the current flowing through CLEDN must be supplied by the LED, and it is not recommended for applica-tions requiring ultra high CMRL performance. Figure 33 is an alternative drive circuit which, like the recommended applica-tion circuit (Figure 25), does achieve ultra high CMR performance by shunting the LED in the off state. CMR with the LED Off (CMRL). A high CMR LED drive circuit must keep the LED off (VFVF(OFF)) during common mode transients. For example, during a -dVcm/dt transient in Figure 31, the current flowing through CLEDP also flows through the +5 V 1 8 2 + VSAT - 0.1 F CLEDP 7 + - VCC = 18 V 1 ILEDP 3 6 CLEDN 4 8 +5 V 5 SHIELD Rg *** CLEDP 2 *** 3 Q1 7 6 CLEDN ILEDN * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING -dVCM/dt. 4 5 SHIELD + - VCM Figure 31. Equivalent circuit for figure 25 during common mode transient. Figure 32. Not recommended open collector drive circuit. HCPL-3120 fig 31 HCPL-3120 fig 32 1 8 +5 V 2 3 4 CLEDP CLEDN SHIELD 7 6 5 VO - OUTPUT VOLTAGE - V 14 12 (12.3, 10.8) 10 (10.7, 9.2) 8 6 4 2 0 (10.7, 0.1) 0 5 10 (12.3, 0.1) 15 20 (VCC - VEE ) - SUPPLY VOLTAGE - V Figure 33. Recommended LED drive circuit for ultra-high CMR. Figure 34. Under voltage lock out. HCPL-3120 fig 34 HCPL-3120 fig 33 22 Under Voltage Lockout Feature. (Discussion applies to HCPL-3120, HCPL-J312, and HCNW3120) The HCPL-3120 contains an under voltage lockout (UVLO) feature that is designed to protect the IGBT under fault conditions which cause the HCPL-3120 supply voltage (equivalent to the fully-charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in a low resistance state. When the HCPL-3120 output is in the high state and the supply voltage drops below the HCPL3120 VUVLO- threshold (9.5<VUVLO- < 12.0) the opto coupler output will go into the low state with a typical delay, UVLO Turn Off Delay, of 0.6s. IPM Dead Time and Propagation Delay Specifications. (Discussion applies to HCPL-3120, HCPL-J312, and HCNW3120) The HCPL-3120 includes a Propagation Delay Difference (PDD) specification intended to help designers minimize "dead time" in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q1 and Q2 in Figure 25) are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails. When the HCPL-3120 output is in the low state and the supply voltage rises above the HCPL-3120 VUVLO+ threshold (11.0<VUVLO+ < 13.5) the optocoupler output will go into the high state (assumes LED is "ON") with a typical delay, UVLO Turn On Delay of 0.8 s. ILED1 ILED1 VOUT1 VOUT1 Q1 ON Q1 ON Q1 OFF Q1 OFF Q2 ON VOUT2 Q2 OFF Q2 ON VOUT2 ILED2 ILED2 tPHL MIN Q2 OFF tPHL MAX tPLH MIN tPHL MAX tPLH MIN tPLH MAX (tPHL-tPLH) MAX PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. PDD* MAX MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN) = (tPHL MAX - tPLH MIN) - (tPHL MIN - tPLH MAX) = PDD* MAX - PDD* MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure 36. Waveforms for dead time. HCPL-3120 fig 36 23 Figure 35. Minimum LED skew for zero dead time. HCPL-3120 fig 35 To minimize dead time in a given design, the turn on of LED2 should be delayed (relative to the turn off of LED1) so that under worst-case con-ditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure 35. The amount of delay necessary to achieve this conditions is equal to the maximum value of the propagation delay difference specification, PDDMAX, which is specified to be 350ns over the operating temperature range of 40C to 100C. 800 HCPL-3120 OPTION 060eHCPL-J312 PS (mW) IS (mA) FOR HCPL-3120 OPTION 060 IS (mA) FOR HCPL-J312 700 600 500 400 300 200 100 0 0 25 50 75 100 125 150 175 200 TS - CASE TEMPERATURE - C OUTPUT POWER - PS, INPUT CURRENT - IS OUTPUT POWER - PS, INPUT CURRENT - IS Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specifications as shown in Figure 36. The maximum dead time for the HCPL-3120 is 700ns (= 350ns -(-350ns)) over an operating temperature range of -40C to 100C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. HCNW3120 1000 PS (mW) IS (mA) 900 800 700 600 500 400 300 200 100 0 0 25 50 75 100 125 150 175 TS - CASE TEMPERATURE - C Figure 37. Thermal derating curve, dependence of safety limiting value with case temperature per IEC/EN/DIN EN 60747-5-2. HCPL-3120 fig 37a For product information and a complete list of distributors, please go to our website: HCPL-3120 fig 37b www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright (c) 2005-2008 Avago Technologies. All rights reserved. Obsoletes AV01-0622EN AV02-0161EN - July 4, 2008