12-Bit, 20 MSPS/40 MSPS/65 MSPS
Dual A/D Converter
AD9238
Rev. C
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FEATURES
Integrated dual 12-bit ADC
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 70 dB (to Nyquist, AD9238-65)
SFDR = 80.5 dBc (to Nyquist, AD9238-65)
Low power: 300 mW/channel at 65 MSPS
Differential input with 500 MHz, 3 dB bandwidth
Exceptional crosstalk immunity > 85 dB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
Output datamux option
APPLICATIONS
Ultrasound equipment
Direct conversion or IF sampling receivers
WB-CDMA, CDMA2000, WiMAX
Battery-powered instruments
Hand-held scopemeters
Low cost, digital oscilloscopes
GENERAL DESCRIPTION
The AD9238 is a dual, 3 V, 12-bit, 20 MSPS/40 MSPS/65 MSPS
analog-to-digital converter (ADC). It features dual high
performance sample-and-hold amplifiers (SHAs) and an
integrated voltage reference. The AD9238 uses a multistage
differential pipelined architecture with output error correction
logic to provide 12-bit accuracy and to guarantee no missing
codes over the full operating temperature range at up to
65 MSPS data rates. The wide bandwidth, differential SHA
allows for a variety of user-selectable input ranges and offsets,
including single-ended applications. It is suitable for various
applications, including multiplexed systems that switch full-
scale voltage levels in successive channels and for sampling
inputs at frequencies well beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available and can
compensate for wide variations in the clock duty cycle, allowing
the converter to maintain excellent performance. The digital
output data is presented in either straight binary or twos
complement format. Out-of-range signals indicate an overflow
condition, which can be used with the most significant bit to
determine low or high overflow.
FUNCTIONAL BLOCK DIAGRAM
VIN+_A
VIN–_A
REFT_A
REFB_A
VREF
SENSE
AGND
REFT_B
REFB_B
VIN+_B
VIN–_B
OTR_A
D11_A TO D0_A
OEB_A
MUX_SELECT
CLK_A
CLK_B
DCS
SHARED_REF
PWDN_A
PWDN_B
DFS
OTR_B
D11_B TO D0_B
OEB_B
AVDD AGND
DRVDD DRGND
12
AD9238
12
0.5V
OUTPUT
MUX/
BUFFERS
12
12 OUTPUT
MUX/
BUFFERS
CLOCK
DUTY CYCLE
STABILIZER
MODE
CONTROL
ADC
SHA
SHA
02640-001
ADC
Figure 1.
Fabricated on an advanced CMOS process, the AD9238 is available
in a Pb-free, space saving, 64-lead LQFP or LFCSP and is
specified over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. Pin-compatible with the AD9248, 14-bit 20MSPS/
40 MSPS/65 MSPS ADC.
2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS
allow flexibility between power, cost, and performance to
suit an application.
3. Low power consumption: AD9238-65: 65 MSPS = 600 mW,
AD9238-40: 40 MSPS = 330 mW, and AD9238-20: 20 MSPS =
180 mW.
4. Typical channel isolation of 85 dB @ fIN = 10 MHz.
5. The clock duty cycle stabilizer (AD9238-20/AD9238-40/
AD9238-65) maintains performance over a wide range of
clock duty cycles.
6. Multiplexed data output option enables single-port operation
from either Data Port A or Data Port B.
AD9238
Rev. C | Page 2 of 48
TABLE OF CONTENTS
Specifications ..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications .......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 6
Absolute Maximum Ratings ............................................................ 7
Explanation of Test Levels ........................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions............................ 8
Ter m in ol og y .................................................................................... 10
Typical Performance Characteristics ........................................... 11
Equivalent Circuits ......................................................................... 15
Theory of Operation ...................................................................... 16
Analog Input ............................................................................... 16
Clock Input and Considerations .............................................. 17
Power Dissipation and Standby Mode ..................................... 18
Digital Outputs ........................................................................... 18
Timing .......................................................................................... 18
Data Format ................................................................................ 19
Voltage Reference ....................................................................... 19
AD9238 LQFP Evaluation Board ................................................. 21
Clock Circuitry ........................................................................... 21
Analog Inputs ............................................................................. 21
Reference Circuitry .................................................................... 21
Digital Control logic .................................................................. 21
Outputs ........................................................................................ 21
LQFP Evaluation Board Bill of Materials (BOM) .................. 23
LQFP Evaluation Board Schematics ........................................ 24
LQFP PCB Layers ....................................................................... 28
Dual ADC LFCSP PCB .................................................................. 34
Power Connector ........................................................................ 34
Analog Inputs ............................................................................. 34
Optional Operational Amplifier .............................................. 34
Clock ............................................................................................ 34
Voltage Reference ....................................................................... 34
Data Outputs ............................................................................... 34
LFCSP Evaluation Board Bill of Materials (BOM) ................ 35
LFCSP PCB Schematics ............................................................. 36
LFCSP PCB Layers ..................................................................... 39
Thermal Considerations ............................................................ 44
Outline Dimensions ....................................................................... 45
Ordering Guide .......................................................................... 46
REVISION HISTORY
11/10—Rev. B to Rev. C
Changes to Absolute Maximum Ratings Section ......................... 7
Added Figure 4; Renumbered Sequentially .................................. 8
Changes to Analog Input Section ................................................. 16
Deleted Note 1 from Dual ADC LFCSP PCB Section ............... 34
Changes to Outline Dimensions ................................................... 45
4/05—Rev. A to Rev. B
Changes to Format and Layout ........................................ Universal
Added LFCSP ..................................................................... Universal
Changes to Features and Applications ........................................... 1
Changes to General Description and Product Highlights .......... 1
Changes to Figure 1 .......................................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Added Digital Specifications ........................................................... 6
Moved Switching Specifications to ................................................ 6
Changes to Pin Function Descriptions .......................................... 8
Changes to Terminology Section ................................................. 10
Changes to Figure 29 ...................................................................... 15
Changes to Clock Input and Considerations Section ................ 17
Changes to Figure 33 ...................................................................... 18
Changes to Data Format Section .................................................. 19
Added AD9238 LQFP Evaluation Board Section ...................... 21
Added Dual ADC LFCSP PCB Section ....................................... 34
Added Thermal Considerations Section ..................................... 44
Updated Outline Dimensions ....................................................... 45
Changes to Ordering Guide .......................................................... 46
AD9238
Rev. C | Page 3 of 48
9/03—Rev. 0 to Rev. A
Changes to DC Specifications ........................................................ 2
Changes to Switching Specifications ............................................. 3
Changes to AC Specifications ......................................................... 4
Changes to Figure 1 .......................................................................... 4
Changes to Ordering Guide ............................................................ 5
Changes to TPCs 2, 3, and 6 ........................................................... 8
Changes to Clock Input and Considerations Section ................ 13
Added Text to Data Format Section ............................................ 15
Changes to Figure 9 ........................................................................ 16
Added Evaluation Board Diagrams Section ............................... 17
Update Outline Dimensions ......................................................... 24
2/03—Revision 0: Initial Version
AD9238
Rev. C | Page 4 of 48
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 1.
Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65
Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full VI 12 12 12 Bits
ACCURACY
No Missing Codes Guaranteed Full VI 12 12 12 Bits
Offset Error Full VI ±0.30 ±1.2 ±0.50 ±1.1 ±0.50 ±1.1 % FSR
Gain Error1 Full IV ±0.30 ±2.2 ±0.50 ±2.4 ±0.50 ±2.5 % FSR
Differential Nonlinearity (DNL)2 Full V ±0.35 ±0.35 ±0.35 LSB
25°C I ±0.35 ±0.9 ±0.35 ±0.8 ±0.35 ±1.0 LSB
Integral Nonlinearity (INL)2 Full V ±0.45 ±0.60 ±0.70 LSB
25°C I ±0.40 ±1.4 ±0.50 ±1.4 ±0.55 ±1.75 LSB
TEMPERATURE DRIFT
Offset Error Full V ±4 ±4 ±6 μV/°C
Gain Error Full V ±12 ±12 ±12 ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode) Full VI ±5 ±35 ±5 ±35 ±5 ±35 mV
Load Regulation @ 1.0 mA Full V 0.8 0.8 0.8 mV
Output Voltage Error (0.5 V Mode) Full V ±2.5 ±2.5 ±2.5 mV
Load Regulation @ 0.5 mA Full V 0.1 0.1 0.1 mV
INPUT REFERRED NOISE
Input Span = 1 V 25°C V 0.54 0.54 0.54 LSB rms
Input Span = 2.0 V 25°C V 0.27 0.27 0.27 LSB rms
ANALOG INPUT
Input Span = 1.0 V Full IV 1 1 1 V p-p
Input Span = 2.0 V Full IV 2 2 2 V p-p
Input Capacitance3 Full V 7 7 7 pF
REFERENCE INPUT RESISTANCE Full V 7 7 7 kΩ
POWER SUPPLIES
Supply Voltages
AVDD Full IV 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V
DRVDD Full IV 2.25 3.0 3.6 2.25 3.0 3.6 2.25 3.0 3.6 V
Supply Current
IAVDD2 Full V 60 110 200 mA
IDRVDD2 Full V 4 10 14 mA
PSRR Full V ±0.01 ±0.01 ±0.01 % FSR
POWER CONSUMPTION
DC Input4 Full V 180 330 600 mW
Sine Wave Input2 Full VI 190 212 360 397 640 698 mW
Standby Power5 Full V 2.0 2.0 2.0 mW
MATCHING CHARACTERISTICS
Offset Error 25°C V ±0.1 ±0.1 ±0.1 % FSR
Gain Error 25°C V ±0.05 ±0.05 ±0.05 % FSR
1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
2 Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure for the equivalent analog input structure. 29
4 Measured with dc input at maximum clock rate.
5 Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).
AD9238
Rev. C | Page 5 of 48
AC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 2.
Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65
Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR)
fINPUT = 2.4 MHz 25°C V 70.4 70.4 70.3 dB
fINPUT = 9.7 MHz Full V 70.2 dB
25°C IV 69.7 70.4 dB
fINPUT = 19.6 MHz Full V 70.1 dB
25°C IV 69.7 70.3 dB
fINPUT = 32.5 MHz Full V 69.3 dB
25°C IV 68.7 70.0 dB
fINPUT = 100 MHz 25°C V 68.7 68.3 67.6 dB
SIGNAL-TO-NOISE AND DISTORTION
RATIO (SINAD)
fINPUT = 2.4 MHz 25°C V 70.2 70.2 70.1 dB
fINPUT = 9.7 MHz Full V 70.1 dB
25°C IV 69.3 70.2 dB
fINPUT = 19.6 MHz Full V 69.9 dB
25°C IV 69.4 70.1 dB
fINPUT = 32.5 MHz Full V 68.9 dB
25°C IV 68.1 69.1 dB
fINPUT = 100 MHz 25°C V 67.9 67.9 66.6 dB
EFFECTIVE NUMBER OF BITS (ENOB)
fINPUT = 2.4 MHz 25°C V 11.5 11.5 11.4 Bits
fINPUT = 9.7 MHz Full V 11.4 Bits
25°C IV 11.3 11.5 Bits
fINPUT = 19.6 MHz Full V 11.4 Bits
25°C IV 11.3 11.4 Bits
fINPUT = 32.5 MHz Full V 11.2 Bits
25°C IV 11.1 11.3 Bits
fINPUT = 100 MHz 25°C V 11.1 11.1 10.9 Bits
WORST HARMONIC (SECOND or THIRD)
fINPUT = 9.7 MHz Full V −84.0 dBc
fINPUT = 19.6 MHz Full V −85.0 dBc
fINPUT = 35 MHz Full V −80.0 dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fINPUT = 2.4 MHz 25°C V 86.0 86.0 86.0 dBc
fINPUT = 9.7 MHz Full V 84.0 dBc
25°C I 76.1 86.0 dBc
fINPUT = 19.6 MHz Full V 85.0 dBc
25°C I 76.7 86.0 dBc
fINPUT = 32.5 MHz Full V 80.0 dBc
25°C I 72.5 80.5 dBc
fINPUT = 100 MHz 25°C V 75.0 dBc
CROSSTALK Full V −85.0 −85.0 −85.0 dB
AD9238
Rev. C | Page 6 of 48
DIGITAL SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 3.
Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65
Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage Full IV 2.0 2.0 2.0 V
Low Level Input Voltage Full IV 0.8 0.8 0.8 V
High Level Input Current Full IV −10 +10 −10 +10 −10 +10 μA
Low Level Input Current Full IV −10 +10 −10 +10 −10 +10 μA
Input Capacitance Full IV 2 2 2 pF
LOGIC OUTPUTS1
High Level Output Voltage Full IV DRVDD −
0.05
DRVDD −
0.05
DRVDD −
0.05
V
Low Level Output Voltage Full IV 0.05 0.05 0.05 V
1 Output voltage levels measured with capacitive load only on each output.
SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 4.
Test AD9238BST/BCP-20 AD9238BST/BCP-40 AD9238BST/BCP-65
Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit
SWITCHING PERFORMANCE
Maximum Conversion Rate Full VI 20 40 65 MSPS
Minimum Conversion Rate Full V 1 1 1 MSPS
CLK Period Full V 50.0 25.0 15.4 ns
CLK Pulse-Width High1 Full V 15.0 8.8 6.2 ns
CLK Pulse-Width Low1 Full V 15.0 8.8 6.2 ns
DATA OUTPUT PARAMETER
Output Delay2 (tPD) Full VI 2 3.5 6 2 3.5 6 2 3.5 6 ns
Pipeline Delay (Latency) Full V 7 7 7 Cycles
Aperture Delay (tA) Full V 1.0 1.0 1.0 ns
Aperture Uncertainty (tJ) Full V 0.5 0.5 0.5 ps rms
Wake-Up Time3 Full V 2.5 2.5 2.5 ms
OUT-OF-RANGE RECOVERY TIME Full V 2 2 2 Cycles
1 The AD9238-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 24).
2 Output delay is measured from clock 50% transition to data 50% transition, with a 5 pF load on each output.
3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
N–1
NN+1 N+2
N+3
N+4 N+5 N+6 N+7
N+8
ANALOG
INPUT
CLOCK
DATA
OUT N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N
MIN 2.0ns,
MAX 6.0ns
tPD
=
02640-002
Figure 2. Timing Diagram
AD9238
Rev. C | Page 7 of 48
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are limiting values to be applied
individually, and beyond which the serviceability of the circuit
may be impaired. Functional operability is not necessarily implied.
Exposure to absolute maximum rating conditions for an extended
period may affect device reliability.
Table 5.
Parameter Rating
ELECTRICAL
AVDD to AGND −0.3 V to +3.9 V
DRVDD to DRGND −0.3 V to +3.9 V
AGND to DRGND −0.3 V to +0.3 V
AVDD to DRVDD −3.9 V to +3.9 V
Digital Outputs to DRGND −0.3 V to DRVDD + 0.3 V
OEB, DFS, CLK, DCS, MUX_SELECT,
SHARED_REF to AGND
−0.3 V to AVDD + 0.3 V
VINA, VINB to AGND −0.3 V to AVDD + 0.3 V
VREF to AGND −0.3 V to AVDD + 0.3 V
SENSE to AGND −0.3 V to AVDD + 0.3 V
REFB, REFT to AGND −0.3 V to AVDD + 0.3 V
PDWN to AGND −0.3 V to AVDD + 0.3 V
ENVIRONMENTAL1
Operating Temperature −40°C to +85°C
Junction Temperature 150°C
Lead Temperature (10 sec) 300°C
Storage Temperature −65°C to +150°C
1 Typical thermal impedances: 64-lead LQFP, θJA = 54°C/W; 64-lead LFCSP, θJA
= 26.4°C/W with heat slug soldered to ground plane. These measurements
were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7.
EXPLANATION OF TEST LEVELS
I 100% production tested.
II 100% production tested at 25°C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range;
100% production tested at temperature extremes for
military devices.
ESD CAUTION
AD9238
Rev. C | Page 8 of 48
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64 63 62 61 60 55 54 53 52 51 50 4959 58 57 56
PIN 1
IDENTIFIER
64-LEAD LQFP
TOP VIEW
(Not to Scale)
D4_A
D3_A
D2_A
D1_A
D0_A (LSB)
DNC
DNC
DRGND
OTR_B
D11_B (MSB)
D10_B
D9_B
D8_B
D7_B
D6_B
AD9238
AGND
AVDD
REFT_A
REFB_A
VREF
SENSE
REFB_B
AGND
VIN–_B
VIN+_B
VIN+_A
VIN–_A
AVDD
REFT_B
CLK_A
SHARED_REF
MUX_SELECT
OEB_A
D11_A (MSB)
D10_A
D9_A
D8_A
DRGND
D7_A
D6_A
D5_A
CLK_B
DCS
DFS
PDWN_B
OEB_B
DNC
D0_B (LSB)
D1_B
D2_B
DRGND
D3_B
D4_B
D5_B
DNC
AGND
AGND
AVDD
DRVDD
DRVDD
AVDD
PDWN_A
OTR_A
DRVDD
DNC = DO NOT CONNECT
02640-003
Figure 3. 64-Lead LQFP Pin Configuration
64-LEAD LFCSP
TOP VIEW
(Not to Scal e)
D4_A
D3_A
D2_A
D1_A
D0_A (L S B)
DNC
DNC
DRGND
OTR_B
D11_B (MS B)
D10_B
D9_B
D8_B
D7_B
D6_B
AD9238
AGND
AVDD
REFT_A
REFB_A
VREF
SENSE
REFB_B
AGND
VIN–_B
VIN+_B
VIN+_A
VIN–_A
AVDD
REFT_B
CLK_A
SHARED_REF
MUX_SELECT
OEB_A
D11_A (MSB)
D10_A
D9_A
D8_A
DRGND
D7_A
D6_A
D5_A
CLK_B
DCS
DFS
PDWN_B
OEB_B
DNC
D0_B (L S B)
D1_B
D2_B
DRGND
D3_B
D4_B
D5_B
DNC
AGND
AGND
AVDD
DRVDD
DRVDD
AVDD
PDWN_A
OTR_A
DRVDD
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NOTES
1. THERE ISAN EXPOSED PAD THAT MUST CONNECT TO AGND.
2. DNC = DO NOT CONNECT.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
02640-103
Figure 4. 64-Lead LFCSP Pin Configuration
AD9238
Rev. C | Page 9 of 48
Table 6. 64-Lead LQFP and 64-Lead LFCSP Pin Function Descriptions
Pin No. Mnemonic Description
1, 4, 13, 16 AGND Analog Ground.
2 VIN+_A Analog Input Pin (+) for Channel A.
3 VIN–_A Analog Input Pin (−) for Channel A.
5, 12, 17, 64 AVDD Analog Power Supply.
6 REFT_A Differential Reference (+) for Channel A.
7 REFB_A Differential Reference (−) for Channel A.
8 VREF Voltage Reference Input/Output.
9 SENSE Reference Mode Selection.
10 REFB_B Differential Reference (−) for Channel B.
11 REFT_B Differential Reference (+) for Channel B.
14 VIN−_B Analog Input Pin (−) for Channel B.
15 VIN+_B Analog Input Pin (+) for Channel B.
18 CLK_B Clock Input Pin for Channel B.
19 DCS Enable Duty Cycle Stabilizer (DCS) Mode (Tie High to Enable).
20 DFS Data Output Format Select Bit (Low for Offset Binary, High for Twos Complement).
21 PDWN_B Power-Down Function Selection for Channel B:
Logic 0 enables Channel B.
Logic 1 powers down Channel B. (Outputs static, not High-Z.)
22 OEB_B Output Enable Bit for Channel B:
Logic 0 enables Data Bus B.
Logic 1 sets outputs to High-Z.
23, 24, 42, 43 DNC Do Not Connect Pins. Should be left floating.
25 to 27,
30 to 38
D0_B (LSB) to
D11_B (MSB)
Channel B Data Output Bits.
28, 40, 53 DRGND Digital Output Ground.
29, 41, 52 DRVDD Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 μF capacitor.
Recommended decoupling is 0.1 μF capacitor in parallel with 10 μF.
39 OTR_B Out-of-Range Indicator for Channel B.
44 to 51,
54 to 57
D0_A (LSB) to
D11_A (MSB)
Channel A Data Output Bits.
58 OTR_A Out-of-Range Indicator for Channel A.
59 OEB_A Output Enable Bit for Channel A:
Logic 0 enables Data Bus A.
Logic 1 sets outputs to High-Z.
60 PDWN_A Power-Down Function Selection for Channel A:
Logic 0 enables Channel A.
Logic 1 powers down Channel A. (Outputs static, not High-Z.)
61 MUX_SELECT
Data Multiplexed Mode. (See Data Format section for how to enable; high setting disables
output data multiplexed mode).
62 SHARED_REF
Shared Reference Control Bit (Low for Independent Reference Mode, High for Shared
Reference Mode).
63 CLK_A Clock Input Pin for Channel A.
EP For the 64-Lead LFCSP only, there is an exposed pad that must connect to AGND.
AD9238
Rev. C | Page 10 of 48
TERMINOLOGY
Aperture Delay
SHA performance measured from the rising edge of the clock
input to when the input signal is held for conversion.
Aperture Jitter
The variation in aperture delay for successive samples, which is
manifested as noise on the input to the ADC.
Integral Nonlinearity (INL)
Deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1½ LSB beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4,096
codes must be present over all operating ranges.
Offset Error
The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN−. Offset error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value ½ LSB
above negative full scale. The last transition should occur at an
analog value 1½ LSB below the nominal full scale. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
Temper ature D rift
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at
TMIN or TMAX.
Power Supply Rejection
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal, expressed as a
percentage or in decibels relative to the peak carrier signal (dBc).
Signal-to-Noise and Distortion (SINAD) Ratio
The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.
Effective Number of Bits (ENOB)
Using the following formula
ENOB = (SINAD − 1.76)/6.02
ENOB for a device for sine wave inputs at a given input
frequency can be calculated directly from its measured SINAD.
Signal-to-Noise Ratio (SNR)
The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in dB.
Spurious-Free Dynamic Range (SFDR)
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal, which may or may not be a
harmonic.
Nyquist Sampling
When the frequency components of the analog input are below
the Nyquist frequency (fCLOCK/2), this is often referred to as
Nyquist sampling.
IF Sampling
Due to the effects of aliasing, an ADC is not limited to Nyquist
sampling. Higher sampled frequencies are aliased down into the
first Nyquist zone (DC − fCLOCK/2) on the output of the ADC.
The bandwidth of the sampled signal should not overlap
Nyquist zones and alias onto itself. Nyquist sampling
performance is limited by the bandwidth of the input SHA and
clock jitter (jitter adds more noise at higher input frequencies).
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
Crosstalk
Coupling onto one channel being driven by a (−0.5 dBFS) signal
when the adjacent interfering channel is driven by a full-scale
signal. Measurement includes all spurs resulting from both
direct coupling and mixing components.
AD9238
Rev. C | Page 11 of 48
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD, DRVDD = 3.0 V, T = 25°C, AIN differential drive, full scale = 2 V, unless otherwise noted.
–120 10 15 20 25 30
50
–100
–80
–60
–40
–20
0
SECOND
HARMONIC
FREQUENCY (MHz)
CROSSTALK
MAGNITUDE (dBFS)
THIRD
HARMONIC
02640-004
Figure 5. Single-Tone FFT of Channel A Digitizing fIN = 12.5 MHz
While Channel B Is Digitizing fIN = 10 MHz
–120 10
dB
15 20 25 3050
–100
–80
–60
–40
–20
0
FREQUENCY (MHz)
CROSSTALK
SECOND
HARMONIC
02640-005
Figure 6. Single-Tone FFT of Channel A Digitizing fIN = 70 MHz
While Channel B Is Digitizing fIN = 76 MHz
–120 10
dB
15 20 25 3050
–100
–80
–60
–40
–20
0
SECOND
HARMONIC
FREQUENCY (MHz)
CROSSTALK
02640-006
Figure 7. Single-Tone FFT of Channel A Digitizing fIN = 120 MHz
While Channel B is Digitizing fIN = 126 MHz
ADC SAMPLE RATE (MSPS)
90
55
40
SFDR/SNR (dBc)
85
80
75
70
65
60
45 50 55 60 65
95
100
SNR
SFDR
50
02640-007
Figure 8. AD9238-65 Single-Tone SNR/SFDR vs. FS with fIN = 32.5 MHz
ADC SAMPLE RATE (MSPS)
90
55
40
SFDR/SNR (dBc)
85
80
75
70
65
60
95
100
SNR
SFDR
50 35302520
SNR
SNR
02640-008
Figure 9. AD9238-40 Single-Tone SNR/SFDR vs. FS with fIN = 20 MHz
ADC SAMPLE RATE (MSPS)
90
55
SFDR/SNR (dBc)
85
80
75
70
65
60
95
100
5005101520
SFDR
SNR
02640-009
Figure 10. AD9238-20 Single-Tone SNR/SFDR vs. FS with fIN = 10 MHz
AD9238
Rev. C | Page 12 of 48
INPUT AMPLITUDE (dBFS)
90
SFDR/SNR (dBc)
80
70
60
100
SNR
SFDR
50
–35
SNR
SNR
40 –30 –25 –20 –15 –10 –5 0
02640-010
Figure 11. AD9238-65 Single-Tone SNR/SFDR vs. AIN with fIN = 32.5 MHz
INPUT AMPLITUDE (dBFS)
90
SFDR/SNR (dBc)
80
70
60
100
SNR
SFDR
50
–35
SNR
SNR
40 –30 –25 –20 –15 –10 –5 0
02640-011
Figure 12. AD9238-40 Single-Tone SNR/SFDR vs. AIN with fIN = 20 MHz
INPUT AMPLITUDE (dBFS)
90
SFDR/SNR (dBc)
80
70
60
100
SNR
SFDR
50
–35
SNR
SNR
40 –30 –25 –20 –15 –10 –5 0
02640-012
Figure 13. AD9238-20 Single-Tone SNR/SFDR vs. AIN with fIN = 10 MHz
INPUT FREQUENCY (MHz)
90
SFDR/SNR (dBc)
85
80
75
95
SNR
SFDR
70
0
SNR
65 20 40 60 80 100 120 140
02640-013
Figure 14. AD9238-65 Single-Tone SNR/SFDR vs. fIN
90
85
80
75
95
SNR
SFDR
70
0
SNR
SNR
65 20 40 60 80 100 120 140
INPUT FREQUENCY (MHz)
SFDR/SNR (dBc)
02640-014
Figure 15. AD9238-40 Single-Tone SNR/SFDR vs. fIN
90
85
80
75
95
SNR
SFDR
70
0
SNR
SNR
65 20 40 60 80 100 120 140
INPUT FREQUENCY (MHz)
SFDR/SNR (dBc)
02640-015
Figure 16. AD9238-20 Single-Tone SNR/SFDR vs. fIN
AD9238
Rev. C | Page 13 of 48
–120 10
MAGNITUDE (dBFS)
15 20 25 3050
–100
–80
–60
–40
–20
0
FREQUENCY (MHz)
02640-016
Figure 17. Dual-Tone FFT with fIN1 = 45 MHz and fIN2 = 46 MHz
–120 10 15 20 25 3050
–100
–80
–60
–40
–20
0
MAGNITUDE (dBFS)
FREQUENCY (MHz)
02640-017
Figure 18. Dual-Tone FFT with fIN1 = 70 MHz and fIN2 = 71 MHz
–120 10 15 20 25 3050
–100
–80
–60
–40
–20
0
MAGNITUDE (dBFS)
FREQUENCY (MHz)
02640-018
Figure 19. Dual-Tone FFT with fIN1 = 200 MHz and fIN2 = 201 MHz
INPUT AMPLITUDE (dBFS)
95
SFDR/SNR (dBFS)
90
85
80
100 SNR
SFDR
75
–24
SNR
SNR
70
–21 –18 –15 –12 –9 –6
65
60
02640-019
Figure 20. Dual-Tone SNR/SFDR vs. AIN with fIN1 = 45 MHz and fIN2 = 46 MHz
INPUT AMPLITUDE (dBFS)
95
SFDR/SNR (dBFS)
90
85
80
100
SNR
SFDR
75
–24
SNR
SNR
70
–21 –18 –15 –12 –9 –6
65
60
02640-020
Figure 21. Dual-Tone SNR/SFDR vs. AIN with fIN1 = 70 MHz and fIN2 = 71 MHz
INPUT AMPLITUDE (dBFS)
95
SFDR/SNR (dBFS)
90
85
80
100
SNR
SFDR
75
–24
SNR
70
–21 –18 –15 –12 –9 –6
65
60
02640-021
Figure 22. Dual-Tone SNR/SFDR vs.
AIN with fIN1 = 200 MHz and fIN2 = 201 MHz
AD9238
Rev. C | Page 14 of 48
CLOCK FREQUENCY
SINAD (dBc)
72
70
74
0
68 20 40 60
SINAD –65
SINAD –40
SINAD –20
12.0
11.5
11.0
02640-022
Figure 23. SINAD vs. FS with Nyquist Input
DUTY CYCLE (%)
85
SINAD/SFDR (dBc)
80
75
70
95
65
30
60
40 45 50 55 60 65
55
50
DCS ON (SINAD)
DCS ON (SFDR)
DCS OFF (SINAD)
DCS OFF (SFDR)
90
35
02640-023
Figure 24. SINAD/SFDR vs. Clock Duty Cycle
TEMPERATURE (°C)
80
SINAD/SFDR (dB)
78
76
74
84
72
–50
70
0 50 100
68
66
SINAD
SFDR
82
02640-024
Figure 25. SINAD/SFDR vs. Temperature with fIN = 32.5 MHz
SAMPLE RATE (MSPS)
500
AVDD POWER (mW)
400
300
200
600
100 0102030405060
–65
–40
–20
02640-025
Figure 26. Analog Power Consumption vs. FS
CODE
0.6
–0.8
INL (LSB)
0.4
0.2
0
–0.2
–0.4
–0.6
0.8
1.0
–1.0 150010005000 2000 2500 3000 3500 4000
02640-026
Figure 27. AD9238-65 Typical INL
CODE
0.6
–0.8
DNL (LSB)
0.4
0.2
0
–0.2
–0.4
–0.6
0.8
1.0
–1.0 150010005000 2000 2500 3000 3500 4000
02640-027
Figure 28. AD9238-65 Typical DNL
AD9238
Rev. C | Page 15 of 48
EQUIVALENT CIRCUITS
AVDD
V
IN+_A, VIN–_A,
V
IN+_B, VIN–_B
02640-062
Figure 29. Equivalent Analog Input Circuit
DRVDD
02640-063
Figure 30. Equivalent Digital Output Circuit
AVDD
CLK_A, CLK_B
DCS, DFS,
MUX_SELECT,
SHARED_REF
02640-064
Figure 31. Equivalent Digital Input Circuit
AD9238
Rev. C | Page 16 of 48
THEORY OF OPERATION
The AD9238 consists of two high performance ADCs that are
based on the AD9235 converter core. The dual ADC paths are
independent, except for a shared internal band gap reference
source, VREF. Each of the ADC paths consists of a proprietary
front end SHA followed by a pipelined switched-capacitor
ADC. The pipelined ADC is divided into three sections,
consisting of a 4-bit first stage, followed by eight 1.5-bit stages,
and a final 3-bit flash. Each stage provides sufficient overlap to
correct for flash errors in the preceding stages. The quantized
outputs from each stage are combined through the digital
correction logic block into a final 12-bit result. The pipelined
architecture permits the first stage to operate on a new input
sample, while the remaining stages operate on preceding samples.
Sampling occurs on the rising edge of the respective clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC and a residual multiplier to drive the next
stage of the pipeline. The residual multiplier uses the flash ADC
output to control a switched-capacitor digital-to-analog
converter (DAC) of the same resolution. The DAC output is
subtracted from the stage’s input signal and the residual is
amplified (multiplied) to drive the next pipeline stage. The
residual multiplier stage is also called a multiplying DAC
(MDAC). One bit of redundancy is used in each one of the
stages to facilitate digital correction of flash errors. The last
stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be
configured as ac- or dc-coupled in differential or single-ended
modes. The output-staging block aligns the data, carries out the
error correction, and passes the data to the output buffers. The
output buffers are powered from a separate supply, allowing
adjustment of the output voltage swing.
ANALOG INPUT
The analog input to the AD9238 is a differential, switched-
capacitor, SHA that has been designed for optimum perfor-
mance while processing a differential input signal. The SHA
input accepts inputs over a wide common-mode range. An
input common-mode voltage of midsupply is recommended to
maintain optimal performance.
The SHA input is a differential, switched-capacitor circuit. In
Figure 32, the clock signal alternatively switches the SHA
between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC input;
therefore, the precise values are dependent on the application.
In IF undersampling applications, any shunt capacitors should
be removed. In combination with the driving source
impedance, they limit the input bandwidth. For best dynamic
performance, the source impedances driving VIN+ and VIN−
should be matched such that common-mode settling errors are
symmetrical. These errors are reduced by the common-mode
rejection of the ADC.
5pF
5pF
T
T
VIN+
V
IN–
CPAR T
T
H
H
CPAR
02640-065
Figure 32. Switched-Capacitor Input
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as:
REFT = ½(AV D D + VREF)
REFB = ½ (AV D D −VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
The equations above show that the REFT and REFB voltages are
symmetrical about the midsupply voltage and, by definition, the
input span is twice the value of the VREF voltage.
The internal voltage reference can be pin-strapped to fixed
values of 0.5 V or 1.0 V or adjusted within the same range as
discussed in the Internal Reference Connection section.
Maximum SNR performance is achieved with the AD9238 set
to the largest input span of 2 V p-p. The relative SNR
degradation is 3 dB when changing from 2 V p-p mode to
1 V p-p mode.
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined as:
VCMMIN = VREF/2
VCMMAX = (AV DD + VREF)/2
AD9238
Rev. C | Page 17 of 48
The minimum common-mode input level allows the AD9238 to
accommodate ground-referenced inputs. Although optimum
performance is achieved with a differential input, a single-
ended source may be driven into VIN+ or VIN−. In this
configuration, one input accepts the signal, while the opposite
input should be set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal may be
applied to VIN+, while a 1 V reference is applied to VIN−. The
AD9238 then accepts an input signal varying between 2 V and
0 V. In the single-ended configuration, distortion performance
may degrade significantly as compared to the differential case.
However, the effect is less noticeable at lower input frequencies and
in the lower speed grade models (AD9238-40 and AD9238-20).
Differential Input Configurations
As previously detailed, optimum performance is achieved while
driving the AD9238 in a differential input configuration. For
baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9238. This is especially true in IF
under-sampling applications where frequencies in the 70 MHz
to 200 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration, as shown in Figure 33.
AD9238
VINA
VINB
AVDD
AGND
2
V p-p
50Ω
50Ω
10pF
10pF
49.9Ω
1kΩ
1kΩ
0.1μF
02640-032
Figure 33. Differential Transformer Coupling
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is a
degradation in SFDR and distortion performance due to the
large input common-mode swing. However, if the source
impedances on each input are matched, there should be little
effect on SNR performance.
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be
sensitive to the clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9238 provides separate clock inputs for each channel.
The optimum performance is achieved with the clocks operated
at the same frequency and phase. Clocking the channels
asynchronously may degrade performance significantly. In
some applications, it is desirable to skew the clock timing of
adjacent channels. The AD9238’s separate clock inputs allow for
clock timing skew (typically ±1 ns) between the channels
without significant performance degradation.
The AD9238 contains two clock duty cycle stabilizers, one for
each converter, that retime the nonsampling edge, providing an
internal clock with a nominal 50% duty cycle. When proper
track-and-hold times for the converter are required to maintain
high performance, maintaining a 50% duty cycle clock is
particularly important in high speed applications. It may be
difficult to maintain a tightly controlled duty cycle on the input
clock on the PCB (see Figure 24). DCS can be enabled by tying
the DCS pin high.
The duty cycle stabilizer uses a delay-locked loop to create the
nonsampling edge. As a result, any changes to the sampling
frequency require approximately 2 μs to 3 μs to allow the DLL
to acquire and settle to the new rate.
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (fINPUT) due only to aperture jitter (tJ) can be
calculated as
()
⎥
⎥
⎦
⎤
⎢
⎢
⎣
⎡
×××
×=
j
INPUT tf
SNR π2
1
log20
In the equation, the rms aperture jitter, tJ, represents the root-
sum square of all jitter sources, which includes the clock input,
analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
For optimal performance, especially in cases where aperture
jitter may affect the dynamic range of the AD9238, it is important
to minimize input clock jitter. The clock input circuitry should
use stable references; for example, use analog power and ground
planes to generate the valid high and low digital levels for the
AD9238 clock input. Power supplies for clock drivers should be
separated from the ADC output driver supplies to avoid modulating
the clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated from
another type of source (by gating, dividing, or other methods), it
should be retimed by the original clock at the last step.
AD9238
Rev. C | Page 18 of 48
A single channel can be powered down for moderate power
savings. The powered-down channel shuts down internal
circuits, but both the reference buffers and shared reference
remain powered on. Because the buffer and voltage reference
remain powered on, the wake-up time is reduced to several
clock cycles.
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD9238 is proportional to its
sampling rates. The digital (DRVDD) power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The digital drive current can be
calculated by
DIGITAL OUTPUTS
IDRVDD = VDRVDD × CLOAD × fCLOCK × N
The AD9238 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
where N is the number of bits changing, and CLOAD is the average
load on the digital pins that changed.
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increases with clock frequency.
Either channel of the AD9238 can be placed into standby mode
independently by asserting the PDWN_A or PDWN_B pins. The data format can be selected for either offset binary or twos
complement. See the Data Format section for more information.
It is recommended that the input clock(s) and analog input(s)
remain static during either independent or total standby, which
results in a typical power consumption of 1 mW for the ADC.
Note that if DCS is enabled, it is mandatory to disable the clock
of an independently powered-down channel. Otherwise,
significant distortion results on the active channel. If the clock
inputs remain active while in total standby mode, typical power
dissipation of 12 mW results.
TIMING
The AD9238 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propa-
gation delay (tPD) after the rising edge of the clock signal. Refer
to Figure 2 for a detailed timing diagram.
The internal duty cycle stabilizer can be enabled on the AD9238
using the DCS pin. This provides a stable 50% duty cycle to
internal circuits.
The minimum standby power is achieved when both channels
are placed into full power-down mode (PDWN_A = PDWN_B =
HI). Under this condition, the internal references are powered
down. When either or both of the channel paths are enabled after a
power-down, the wake-up time is directly related to the recharging
of the REFT and REFB decoupling capacitors and to the duration
of the power-down. Typically, it takes approximately 5 ms to
restore full operation with fully discharged 0.1 μF and 10 μF
decoupling capacitors on REFT and REFB.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9238.
These transients can detract from the converter’s dynamic
performance. The lowest typical conversion rate of the AD9238
is 1 MSPS. At clock rates below 1 MSPS, dynamic performance
may degrade.
B–8 A–7 B–7 A–6 B–6 A–5 B–5 A–4 B–4 A–3 B–3 A–2 B–2 A–1 B–1 A0B0A1
A–1 A0A1A2A3A4A5A6
A7
A8
B–1 B0B1B2B3B4B5B6
B7
B8
ANALOG INPUT
ADC A
ANALOG INPUT
ADC B
CLK_A = CLK_B =
MUX_SELECT
D0_A TO
D11_A
t
PD
t
PD
02640-066
Figure 34. Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT
AD9238
Rev. C | Page 19 of 48
DATA FORMAT
The AD9238 data output format can be configured for either
twos complement or offset binary. This is controlled by the data
format select pin (DFS). Connecting DFS to AGND produces
offset binary output data. Conversely, connecting DFS to AVDD
formats the output data as twos complement.
The output data from the dual ADCs can be multiplexed onto a
single 12-bit output bus. The multiplexing is accomplished by
toggling the MUX_SELECT bit, which directs channel data to
the same or opposite channel data port. When MUX_SELECT
is logic high, the Channel A data is directed to the Channel A
output bus, and the Channel B data is directed to the Channel B
output bus. When MUX_SELECT is logic low, the channel data
is reversed, that is the Channel A data is directed to the
Channel B output bus, and the Channel B data is directed to the
Channel A output bus. By toggling the MUX_SELECT bit,
multiplexed data is available on either of the output data ports.
If the ADCs run with synchronized timing, this same clock can
be applied to the MUX_SELECT pin. Any skew between CLK_A,
CLK_B, and MUX_SELECT can degrade ac performance. It is
recommended to keep the clock skew <100 pS. After the
MUX_SELECT rising edge, either data port has the data for its
respective channel; after the falling edge, the alternate channel’s
data is placed on the bus. Typically, the other unused bus would
be disabled by setting the appropriate OEB high to reduce
power consumption and noise. Figure 34 shows an example of
multiplex mode. When multiplexing data, the data rate is two
times the sample rate. Note that both channels must remain
active in this mode and that each channel’s power-down pin
must remain low.
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD9238. The input range can be adjusted by varying the reference
voltage applied to the AD9238, using either the internal
reference with different external resistor configurations or an
externally applied reference voltage. The input span of the ADC
tracks reference voltage changes linearly. If the ADC is being
driven differentially through a transformer, the reference voltage
can be used to bias the center tap (common-mode voltage).
The shared reference mode allows the user to connect the references
from the dual ADCs together externally for superior gain and
offset matching performance. If the ADCs are to function
independently, the reference decoupling can be treated
independently and can provide superior isolation between the dual
channels. To enable shared reference mode, the SHARED_REF
pin must be tied high and the external differential references
must be externally shorted. (REFT_A must be externally
shorted to REFT_B, and REFB_A must be shorted to REFB_B.)
Internal Reference Connection
A comparator within the AD9238 detects the potential at the
SENSE pin and configures the reference into four possible states,
which are summarized in Table 7. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 35), setting VREF to 1 V. Connecting the
SENSE pin to VREF switches the reference amplifier output to
the SENSE pin, completing the loop and providing a 0.5 V
reference output. If a resistor divider is connected, as shown in
Figure 36, the switch is again set to the SENSE pin. This puts
the reference amplifier in a noninverting mode with the VREF
output defined as
VREF = 0.5 × (1 + R2/R1)
In all reference configurations, REFT and REFB drive the ADC
core and establish its input span. The input range of the ADC
always equals twice the voltage at the reference pin for either an
internal or an external reference.
VIN+
VIN–
10μF
10μF
0.1μF
0.1μF
REFT
ADC
CORE
SELECT
LOGIC
SENSE
0.1μF0.5V
AD9238
REFB
0.1μF
VREF
02640-034
Figure 35. Internal Reference Configuration
Table 7. Reference Configuration Summary
Selected Mode SENSE Voltage Resulting VREF (V) Resulting Differential Span (V p-p)
External Reference AVDD N/A 2 × External Reference
Internal Fixed Reference VREF 0.5 1.0
Programmable Reference 0.2 V to VREF 0.5 × (1 + R2/R1) 2 × VREF (See Figure 36)
Internal Fixed Reference AGND to 0.2 V 1.0 2.0
AD9238
Rev. C | Page 20 of 48
External Reference Operation
The use of an external reference may be necessary to
enhance the gain accuracy of the ADC or to improve thermal
drift characteristics. When multiple ADCs track one another, a
single reference (internal or external) may be necessary to
reduce gain matching errors to an acceptable level. A high
precision external reference may also be selected to provide
lower gain and offset temperature drift. Figure 37 shows the
typical drift characteristics of the internal reference in both
1 V and 0.5 V modes. When the SENSE pin is tied to AVDD,
the internal reference is disabled, allowing the use of an
external reference. An internal reference buffer loads the
external reference with an equivalent 7 kΩ load. The internal
buffer still generates the positive and negative full-scale
references, REFT and REFB, for the ADC core. The input span
is always twice the value of the reference voltage; therefore, the
external reference must be limited to a maximum of 1 V. If the
internal reference of the AD9238 is used to drive multiple
converters to improve gain matching, the loading of the
reference by the other converters must be considered. Figure 38
depicts how the internal reference voltage is affected by loading.
VIN+
VIN–
VREF
10μF
10μF
10μF
0.1μF
0.1μF
REFT
ADC
CORE
SELECT
LOGIC
SENSE
0.5V
AD9238
REFB
0.1μF
R1
R2
02640-035
Figure 36. Programmable Reference Configuration
TEMPERATURE (°C)
0.2
VREF ERROR (%)
1.2
1.0
0.8
0.6
0.4
0
–40 –30 –20 –10 010 20 30 40 50 60 70 80
VREF = 1V
VREF = 0.5V
02640-067
Figure 37. Typical VREF Drift
LOAD (mA)
–0.20
ERROR (%)
0.05
0
–0.05
–0.10
–0.15
–0.2500.5 1.0 1.5 2.0 2.5 3.0
0.5V ERROR
1V ERROR
02640-068
Figure 38. VREF Accuracy vs. Load
AD9238
Rev. C | Page 21 of 48
AD9238 LQFP EVALUATION BOARD
The evaluation board supports both the AD9238 and AD9248
and has five main sections: clock circuitry, inputs, reference
circuitry, digital control logic, and outputs. A description of
each section follows. Table 8 shows the jumper settings and
notes assumptions in the comment column.
Four supply connections to TB1 are necessary for the evaluation
board: the analog supply of the DUT, the on-board analog
circuitry supply, the digital driver DUT supply, and the on-
board digital circuitry supply. Separate analog and digital
supplies are recommended, and on each supply 3 V is nominal.
Each supply is decoupled on-board, and each IC, including the
DUT, is decoupled locally. All grounds should be tied together.
CLOCK CIRCUITRY
The clock circuitry is designed for a low jitter sine wave source
to be ac-coupled and level shifted before driving the 74VHC04
hex inverter chips (U8 and U9) whose output provides the clock
to the part. The POT (R32 and R31) on the level shifting
circuitry allows the user to vary the duty cycle if desired. The
amplitude of the sine wave must be large enough for the trip
points of the hex inverter and within the supplies to avoid noise
from clipping. To ensure a 50% duty cycle internal to the part,
the AD9238-65 has an on-chip duty cycle stabilizer circuit that
is enabled by putting in Jumper JP11. The duty cycle stabilizer
circuitry should only be used at clock rates above 40 MSPS.
Each channel has its own clock circuitry, but normally both
clock pins are driven by a single 74VHC04, and the solder
Jumper JP24 is used to tie the clock pins together. When the
clock pins are tied together and only one 74VHC04 is being
used, the series termination resistor for the other channel must
be removed (either R54 or R55, depending on which inverter is
being used).
A data capture clock for each channel is created and sent to the
output buffers in order to be used in the data capture system if
needed. Jumpers JP25 and JP26 are used to invert the data clock
if necessary and can be used to debug data capture timing
problems.
ANALOG INPUTS
The AD9238 achieves the best performance with a differential
input. The evaluation board has two input options for each
channel, a transformer (XFMR) and an AD8138, both of which
perform single-ended-to-differential conversions. The XFMR
allows for the best high frequency performance, and the AD8138 is
ideal for dc evaluation, low frequency inputs, and driving an
ADC differentially without loading the single-ended signal.
The common-mode level for both input options is set to
midsupply by a resistor divider off the AVDD supply but can
also be overdriven with an external supply using the (test
points) TP12, TP13 for the AD8138s and TP14, TP15 for the
XFMRs. For low distortion of full-scale input signals when
using an AD8138, put JP17 and JP22 in Position B and put an
external negative supply on TP10 and TP11.
For best performance, use low jitter input sources and a high
performance band-pass filter after the signal source, before the
evaluation board (see Figure 39). For XFMR inputs, use solder
Jumpers JP13, JP14 for Channel A and JP20, JP21 for Channel B.
For AD8138 inputs, use solder Jumpers JP15, JP16 for Channel
A and JP18, JP19 for Channel B. Remove all solder from the
jumpers not being used.
REFERENCE CIRCUITRY
The evaluation board circuitry allows the user to select a reference
mode through a series of jumpers and provides an external
reference if necessary. Refer to Table 9 to find the jumper settings
for each reference mode. The external reference on the board is
a simple resistor divider/zener diode circuit buffered by an
AD822 (U4). The POT (R4) can be used to change the level of
the external reference to fine adjust the ADC full scale.
DIGITAL CONTROL LOGIC
The digital control logic on the evaluation board is a series of
jumpers and pull-down resistors used as digital inputs for the
following pins on the AD9238: the power-down and output
enable bar for each channel, the duty cycle restore circuitry, the
twos complement output mode, the shared reference mode, and
the MUX_SELECT pin. Refer to Table 8 for normal operating
jumper positions.
OUTPUTS
The outputs of the AD9238 (and the data clock discussed earlier)
are buffered by 74VHC541s (U2, U3, U7, U10) to ensure the
correct load on the outputs of the DUT, as well as the extra drive
capability to the next part of the system. The 74VHC541s are
latches, but on this evaluation board, they are wired and
function as buffers. JP30 can be used to tie the data clocks
together if desired. If the data clocks are tied, R39 or R40 must
be removed, depending on which clock circuitry is being used.
AD9238
Rev. C | Page 22 of 48
Table 8. PCB Jumpers
JP Description
Normal
Setting Comment
1 Reference Out 1 V Reference Mode
2 Reference In 1 V Reference Mode
3 Reference Out 1 V Reference Mode
4 Reference Out 1 V Reference Mode
5 Reference Out 1 V Reference Mode
6 Shared Reference Out
7 Shared Reference Out
8 PDWN B Out
9 PDWN A Out
10 Shared Reference Out
11 Duty Cycle In Duty Cycle Restore On
12 Twos Complement Out
13 Input In Using XFMR Input
14 Input In Using XFMR Input
15 Input Out Using XFMR Input
16 Input Out Using XFMR Input
17 AD8138 Supply A Using XFMR Input
18 Input Out Using XFMR Input
19 Input Out
20 Input In
21 Input In
22 AD8138 Supply A
23 Mux Select Out
24 Tie Clocks In Using One Signal for Clock
25 Data Clock A
26 Data Clock Out Using One Signal for Clock
27 Mux Select In
28 OEB_A Out
29 Mux Select Out
30 Data Clock Out
35 OEB_B Out
Table 9. Reference Jumpers
Reference Mode JP1 JP2 JP3 JP4 JP5
1 V Internal Out In Out Out Out
0.5 V Internal Out Out In Out Out
External In Out Out Out In
AD9238
EVALUATION BOARD
SINE SOURCES
LOW JITTER
(HP8644)
SINE SOURCE
LOW JITTER
(HP8644)
BAND-PASS
FILTERS OUTPUT
BUFFERS
INPUT
CIRCUITRY
CLOCK
CIRCUITRY
AD9238
02640-060
REFERENCE MODE
SELECTION/EXTERNAL
REFERENCE/CONTROL
LOGIC
Figure 39. PCB Test Setup
AD9238
Rev. C | Page 23 of 48
LQFP EVALUATION BOARD BILL OF MATERIALS (BOM)
Table 10.
No. Quantity Reference Designator Device Package Value
1 18 C1, C2, C11, C12, C27, C28, C33, C34, C50, C51, C73 to C76, C87 to C90 Capacitors ACASE 10 μF
2 23 C3 to C10, C29 to C31, C56, C61 to C65, C77, C79, C80, C84 to C86 Capacitors 0805 0.1 μF
3 7 C13, C15, C18, C19, C21, C23, C25 Capacitors 0603 0.001 μF
4 15 C6, C14, C16, C17, C20, C22, C24, C26, C32, C35 to C40 Capacitors 0603 0.1 μF
5 4 C41 to C44 Capacitors DCASE 22 μF
6 4 C45 to C48 Capacitors 1206 0.1 μF
7 2 C49, C53 Capacitors ACASE 6.3 V
8 2 C52, C57 Capacitors 0201 0.01 μF
9 4 C54, C55, C68, C69 Capacitors 0805
10 4 C58, C59, C70, C71 Capacitors 0603 DNP
11 2 C60, C72 Capacitors 0603 20 pF
12 1 D1 AD1580 SOT-23CAN 1.2 V
13 1 J1 SAM080UPM
14 14 JP1 to JP5, JP8 to JP12, JP23, JP28, JP29, JP35 JPRBLK02
15 13 JP6, JP7, JP13, JP14 to JP16, JP18 to JP21, JP24, JP27, JP30 JPRSLD02
16 4 JP17, JP22, JP25, JP26 JPRBLK03
17 4 L1 to L4 IND1210 LC1210 10 μH
18 6 R1, R2, R13, R14, R23, R27 Resistors 1206 33 Ω
19 1 R3 Resistor 1206 5.49 kΩ
20 1 R4 Resistor RV3299UP 10 kΩ
21 7 R5, R6, R38, R41, R43, R44, R51 Resistors 0805 5 kΩ
22 6 R7, R8, R19, R20, R52, R53 Resistors 1206 49.9 Ω
23 8 R9, R18, R29, R30, R47 to R50 Resistors 0805 1 kΩ
24 6 R10, R12, R15, R24, R25, R28 Resistors 1206 499 Ω
25 2 R11, R26 Resistors 1206 523 Ω
26 4 R16, R17, R21, R22 Resistors 1206 40 Ω
27 2 R31, R32 Resistors RV3299W 10 kΩ
28 4 R33 to R35, R42 Resistors 0805 500 Ω
29 2 R36, R37 Resistors 1206 10 kΩ
30 2 R39, R40 Resistors 0805 22 Ω
31 2 R54, R55 Resistors 1206 0 Ω
32 16 RP1 to RP16 Resistor Pack RCA74204 22 Ω
33 6 S1 to S6 SMA200UP
34 2 T1, T2 DIP06RCUP T1-1T
35 1 TB1 TBLK06REM
36 4 TP1, TP3, TP5, TP7 LOOPTP RED
37 4 TP2, TP4, TP6, TP8 LOOPTP BLK
38 7 TP9, TP12 to TP17 LOOPMINI WHT
39 2 TP10, TP11 LOOPMINI RED
40 1 U1 64LQFP7X7 AD9238
41 4 U2, U3, U7, U10 SOL20 74VHC541
42 1 U4 SOIC-8 AD822
43 2 U5, U6 SO8NC7 AD8138
44 2 U8, U9 TSSOP-14 74VHC04
AD9238
Rev. C | Page 24 of 48
LQFP EVALUATION BOARD SCHEMATICS
B
TP8
BLK
TP2
BLK
AVDDIN AVDD
RED
TP1
10μHL2
DUTAVDDIN
TB1 DUTAVDD
TP3
RED
10μHL1
BLK
TP4
RED
TP5
10μHL4
DVDDIN
AGND
TB1
AGND
DRVDDIN
TB1
TB1
TB1
DVDD
DUTDRVDD
TP7RED
BLK
TP6
10μHL3
R2
33Ω
AGND;7
AVDD;14
U8 12
U8 AGND;7
AVDD;14
10
U8 8
JP26
3
2
WHT
TP16
74VHC04
74VHC04
74VHC04
B
13
11
9
JP25
2
13 R1
33Ω
JP24
R54
0Ω
TP17
WHT
CLKAO
U9 AGND;7
AVDD;14
12
AGND;7
AVDD;14
U9 10
74VHC04
74VHC04
U9
AGND;7
AVDD;14
9
74VHC04
U9 AGND;7
AVDD;14
3
AGND;7
AVDD;14
U9 6
AGND;7
AVDD;14
U9 2
1
74VHC04
74VHC04
74VHC04
R53
49.9Ω
S6 R32
10kΩ
R42
500Ω
C84
0.1μF
CLKA CW
CW
R31
10kΩ
AVDD
R34
500Ω
R35
500Ω
C77
0.1μF
R52
49.9Ω
C73
10μF
6.3V
S5
C79
0.1μF
CLKB
AVDD
C74
10μF
6.3V
C80
0.1μF
U8 AGND;7
AVDD;14
5
AGND;7
AVDD;14
U8 43
U8 AGND;7
AVDD;14
74VHC04
74VHC04
74VHC04
AGND;7
AVDD;14
1
DATACLKB
13
11
AVDD
R33
500Ω
DUTCLKA
5
DATACLKA
DUTCLKB
C42
22μF
25V
C46
0.1μF
C41
22μF
25V
C45
0.1μF
C44
22μF
25V
C48
0.1μF
C43
22μF
F25V
C47
0.1μF
R55
0Ω
8
4
A
A1
2
1
2
3
TB1
5
4
6
6
02640-038
Figure 40. Evaluation Board Schematic
AD9238
Rev. C | Page 25 of 48
R20
49.9Ω
R8
49.9Ω
R19
49.9Ω
R7
49.9Ω
C59
DNP
C58
DNP
C71
DNP
C70
DNP
0.1μF
C65
C64
0.1μF
R18
1kΩR50
1kΩ
R29
1kΩR9
1kΩ
R30
1kΩ
R47
1kΩ
C85
0.1μF
C63
0.1μF
C68
VAL
C69
VAL
VAL C55
VAL C54
C56
0.1μF
C62
0.1μF
C61
0.1μF
C53
10V
6.3V
C49
10V
6.3V
R21
40Ω
R22
40ΩR23
33Ω
JP18
JP19
R24
499Ω
R25
499Ω
JP22
2
S4
JP20
JP21
T1
T1–1T
6
4
1
2
3
JP14
JP13
S2
R14
33Ω
VIN+_A
VIN–_A
VIN+_B
VIN–_B
JP17
2
3
1
499Ω
R12
JP16
JP15
R13
33Ω
R17
40Ω
R27
33Ω
T1–1T
T2 3
2
1
4
6
S3
TP11
RED
R16
40Ω
C87
10μF
6.3V
TP12
WHT
TP13
WHT
TP14
WHT
TP15
WHT
U6
1
8
6
3
2
4
5
U5
5
42
3
6
8
1
C88
10μF
6.3V
C50
10μF
6.3V
C51
10μF
6.3V
R49
1kΩ
R48
1kΩ
R15
499Ω
C86
0.1μF
R10
499Ω
S1
R11
523Ω
R26
523Ω
R28
499
C60
20pF
C72
20PF
NC = 5
NC = 5
AD8138
AD8138
XFMR INPUT B
XFMR INPUT A
S
P
SP
SHEET 3
SHEET 3
A
–IN
+IN
VEE
VCC
VOC
VO+
VO–
AVDD
AVDD
AVDD AVDD
AVDD
AMP INPUT A
AMP INPUT B
–IN
+IN
VEE
VCC
VOC
VO+
VO–
B
B
A
TP10
RED
C89
10μF
6.3V
C90
10μF
6.3V
13
O
O
OO
02640-B-039
AVDD
Figure 41. Evaluation Board Schematic (Continued)
AD9238
Rev. C | Page 26 of 48
DUTAVDD
AVDD
AVDD
R36
10kΩ
JP6
R41
5kΩR51
5kΩ
AVDD
C1
10μF
6.3V
AVDD
R44
5kΩ
C34
10μF
6.3V
VIN+_B
VIN–_B
VIN–_A
OTRA
DA13
DA12
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
OTRB
DB13
DB12
DB11
DB10
DB9
DB7
DB6
DB5
DB4
DB3
DB2
DB1
D1
2
1
DUTAVDD
DUTDRVDD
R4
10kΩ
DB0
DB8
DA0
AGND;4
AVDD;8
U4
2
1
3
AGND;4
AVDD;8
U4 OUT
57
6
VIN+_A
C35
0.1μF
C37
0.1μFC38
0.1μFC36
0.1μF
R3
5.49kΩ
R5
5kΩ
C30
0.1μF
C29
0.1μF
0.1μF
R43
5kΩR6
5kΩ
R38
5kΩ
U1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
32
31
30
29
28
27
26
25
48
24
1
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
C12
10μF
6.3V
TP9
WHT
JP7
AVDD
CLKAO
DUTCLKB
DUTCLKA
R37
10kΩ
C52
0.01μF
1.2V
AD822
AD822
AD9238
VIN+_A
VIN–_A
AVSS2
AVDD2
REFT_A
REFB_A
VREF
SENSE
REFB_B
REFT_B
AVDD3
AVSS3
VIN–_B
VIN+_B
AVSS4
AVDD4
CLK_B
DUTYEN
DFS
PDWN_B
DNC
D3_A
D2_A
D1_A
D0_A
DNC
DNC
DRVDD2
DRVSS2
OTR_B
(MSB)D11_B
D10_B
D9_B
D8_B
D7_B
D6_B
AVSS1
DNC
D4_A
D0_B
D1_B
D2_B
DRVSS1
DRVDD1
D3_B
D4_B
D5_B
D5_A
D6_A
D7_A
DRVDD3
DRVSS3
D8_A
D9_A
D10_A
(MSB)D11_A
OTR_A
PDWN_A
MUXSELECT
SHAREDREF
CLK_A
AVDD1
OEB_A
OEB_B
C31
JP11
JP12
JP2
JP3
JP4
JP1
C57
0.01μF
JP5
C32
0.1μF
C39
0.1μFC40
0.1μF
C33
10μF
6.3V
CW
JP35
JP8
C24
0.1μFC25
0.001μFC26
0.1μFC13
0.001μFC14
0.1μF
C11
10μF
6.3V
C23
0.001μF
JP23
JP27
JP29
JP28
JP10
C22
0.1μF
C15
0.001μFC17
0.1μF
C18
0.001μFC19
0.001μF
C20
0.1μFC21
0.001μF
C16
0.1μF
JP9
C2
10μF
6.3V
AVDD
+IN
–IN
OUT
+IN
–IN
02640-040
Figure 42. Evaluation Board Schematic (Continued)
AD9238
Rev. C | Page 27 of 48
4
2
2RP11
DVDD
U10
182
11
12
13
14
15
16
17
20
10
19
1
9
8
7
6
5
4
3
U7
3
4
5
6
7
8
9
1
19 10
20
17
16
15
14
13
12
11
2
DA13
DA12
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
RP10
4RP10 6
3
RP4 63 RP42
RP3
4RP3 63 RP3
2RP3 81 RP2
4RP2 63 RP22 RP2 81 RP14 RP1 63 RP1
2
C3
0.1μFC10
0.1μFC9
0.1μFC8
0.1μF
RP4 81
RP4
4
OTRA
DA0
RP102 RP10 81 RP94 RP9 6
5
7
5
3RP9
2
RP9 8
7
5
7
5
7
1
RP12
4RP12 63 RP12
RP12 81 RP11
RP11 63 RP11
C28
10μF
6.3V
81
C75
10μF
6.3V
JP30
R39
22Ω
R40
22Ω
DATACLKA
DATACLKB
RP1 22Ω81
A2
A3
A4
A5
A6
A7
A8
G1
G2 GND
VCC
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A1 Y1
74VHC541
A2
A3
A4
A5
A6
A7
A8
G1
G2 GND
VCC
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A1 Y1
74VHC541
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
SAM080UPM
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
A8 Y8
22Ω
SAM080UPM
18
2
2
3
1
4
3
4
4
4
2
2
22Ω
2
4
2
4
2
4
2
1
19
1
911
DVDD
C7
0.1μFC6
0.1μFC5
0.1μFC4
0.1μFC27
10μF
6.3V
C76
10μF
6.3V
18
2
11
12
13
14
15
16
17
10
20
9
8
7
6
5
4
3
U3
3
4
5
6
7
8
1
19 10
20
17
16
15
14
13
12
2
DA13
DA12
DA11
DA10
DA9
DA8
DA6
DA5
DA4
DA3
DA2
DA1
DA0
RP14
RP14 6
3
RP8 6
3
54
RP8
RP7
RP7 6
3RP7
RP7 8
1RP6
RP6 63 RP6
RP6 8
1RP5
RP5 6
3RP5
RP8 8
1
OTRB
RP14
RP14 81 RP13
RP13 6
5
7
5
7
3RP13
RP13 8
1
RP16
RP16
RP16 7
8
6
5
RP16
RP15 5
6
RP15
RP15 7
A2
A3
A4
A5
A6
A7
G1
G2 GND
VCC
Y2
Y3
Y4
Y5
Y6
Y7
A1 Y1
74VHC541
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
RP5 22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω
22Ω18
RP8 22Ω
1
DA7 RP15 8
22Ω
13
11
9
7
5
3
1
39
37
35
33
31
29
27
25
23
21
19
17
15
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
53
51
49
47
45
43
41
79
77
75
73
71
69
67
65
63
61
59
57
55
80
78
76
74
72
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42
5
7
7
5
7
5
7
5
J1
HEADER UP MALE NO SHROUD
U2
A2
A3
A4
A5
A6
A7
A8
G2
G1 GND
VCC
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A1 Y1
74VHC541
J1
HEADER UP MALE NO SHROUD
8
7
5
7
5
7
5
7
02640-041
Figure 43. Evaluation Board Schematic (Continued)
AD9238
Rev. C | Page 28 of 48
LQFP PCB LAYERS
02640-046
Figure 44. PCB Top Side Silkscreen
AD9238
Rev. C | Page 29 of 48
02640-042
Figure 45. PCB Top Layer
AD9238
Rev. C | Page 30 of 48
02640-044
Figure 46. PCB Ground Plane
AD9238
Rev. C | Page 31 of 48
02640-045
Figure 47. PCB Split Power Plane
AD9238
Rev. C | Page 32 of 48
02640-043
Figure 48. PCB Bottom Layer
AD9238
Rev. C | Page 33 of 48
0
2640-047
Figure 49. PCB Bottom Silkscreen
AD9238
Rev. C | Page 34 of 48
DUAL ADC LFCSP PCB
The LFCSP PCB requires a low jitter clock source, analog sources,
and power supplies. The PCB interfaces directly with Analog
Devices standard dual-channel data capture board (HSC-ADC-
EVAL-DC), which together with ADI’s ADC Analyzer™ software
allows for quick ADC evaluation.
POWER CONNECTOR
Power is supplied to the board via three detachable 4-lead
power strips.
Table 11. Power Connector
Terminal Comments
VCC1 3.0 V Analog supply for ADC
VDD1 3.0 V Output supply for ADC
VDL1 3.0 V Supply circuitry
VREF Optional external VREF
+5 V Optional op amp supply
−5 V Optional op amp supply
1VCC, VDD, and VDL are the minimum required power connections.
ANALOG INPUTS
The evaluation board accepts a 2 V p-p analog input signal
centered at ground at two SMB connectors, Input A and
Input B. These signals are terminated at their respective
transformer primary side. T1 and T2 are wideband RF
transformers that provide the single-ended-to-differential
conversion, allowing the ADC to be driven differentially,
minimizing even-order harmonics. The analog signals can be
low-pass filtered at the transformer secondary to reduce high
frequency aliasing.
OPTIONAL OPERATIONAL AMPLIFIER
The PCB has been designed to accommodate an optional
AD8139 op amp that can serve as a convenient solution for
dc-coupled applications. To use the AD8139 op amp, remove
C14, R4, R5, C13, R37, and R36. Place R22, R23, R30, and R24.
CLOCK
The clock inputs are buffered on the board at U5 and U6. These
gates provide buffered clocks to the on-board latches, U2 and
U4, ADC input clocks, and DRA and DRB that are available at
the output Connector P3, P8. The clocks can be inverted at the
timing jumpers labeled with the respective clocks. The clock
paths also provide for various termination options. The ADC
input clocks can be set to bypass the buffers at P2 to P9 and
P10, P12. An optional clock buffer U3, U7 can also be placed.
The clock inputs can be bridged at TIEA, TIEB (R20, R40) to
allow one to clock both channels from one clock source; however,
optimal performance is obtained by driving J2 and J3.
Table 12. Jumpers
Terminal Comments
OEB A Output Enable for A Side
PDWN A Power-Down A
MUX Mux Input
SHARED REF Shared Reference Input
DR A Invert DR A
LATA Invert A Latch Clock
ENC A Invert Encode A
OEB B Output Enable for B Side
PDWN B Power-Down B
DFS Data Format Select
SHARED REF Shared Reference Input
DR B Invert DR B
LATB Invert B Latch Clock
ENC B Invert Encode B
VOLTAGE REFERENCE
The ADC SENSE pin is brought out to E41, and the internal
reference mode is selected by placing a jumper from E41 to
ground (E27). External reference mode is selected by placing a
jumper from E41 to E25 and E30 to E2. R56 and R45 allow for
programmable reference mode selection.
DATA OUTPUTS
The ADC outputs are latched on the PCB at U2 and U4. The
ADC outputs have the recommended series resistors in line to
limit switching transient effects on ADC performance.
AD9238
Rev. C| Page 35 of 48
LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM)
Table 13.
No. Quantity Reference Designator Device Package Value
1 2 C1, C3 Capacitors 0201 20 pF
2 7 C2, C5, C7, C9, C10, C22, C36 Capacitors 0805 10 μF
3 44 C4, C6, C8, C11 to C15, C20, C21,
C24 to C27, C29 to C35, C39 to C61
Capacitors 0402 0.1 μF
4 6 C16 to C19, C37, C38 Capacitors TAJD 10 μF
5 2 C23, C28 Capacitors 0201 0.1 μF
6 6 J1 to J6 SMBs
7 3 P1, P4, P11 Power Connector Posts Z5.531.3425.0 Wieland
8 3 P1, P4, P11 Detachable Connectors 25.602.5453.0 Wieland
9 2 P31, P8 Connectors
10 4 R1, R2, R32, R34 Resistors 0402 36 Ω
11 6 R3, R7, R11, R14, R51, R61 Resistors 0402 50 Ω
12 4 R4, R5, R36, R37 Resistors 0402 33 Ω
13 9 R9, R10, R12, R13, R20, R35, R38, R40, R43 Resistors 0402 0 Ω
14 6 R15, R16, R18, R26, R29, R31 Resistors 0402 499 Ω
15 2 R17, R25 Resistors 0402 525 Ω
16 27 R19, R21, R27, R28, R39, R41, R44,
R46 to R49, R52, R54, R55, R57 to R60, R62 to R70
Resistors 0402 1 kΩ
17 4 R22 to R24, R30 Resistors 0402 40 Ω
18 2 R45, R56 Resistors 0402 10 kΩ
19 1 R50 Resistor 0402 22 Ω
20 8 RZ1 to RZ6, RZ9, RZ10 Resistor Pack 220 Ω
21 2 T1, T2 Transformers AWT-1WT Mini-Circuits®
22 1 U1 AD9238 LFCSP-64
23 2 U2, U4 SN74LVCH16373A TSSOP-48
24 2 U32, U7 SN74LVC1G04 SOT-70
25 2 U5, U6 SN74VCX86 SO-14
26 2 U11, U12 AD8139 SO-8/EP
27 4 R6, R8, R33, R42 Resistors 0402 100 Ω
1 P3 and P8 implemented as one 80-pin connector SAMTEC TSW-140-08-L-D-RA.
2 U3 and U7 not placed.
AD9238
Rev. C | Page 36 of 48
LFCSP PCB SCHEMATICS
D7_A D7A
49
D8_A D8A
50
D9_A D9A
51
DRVDD2 52
DRGND2 53
D10_A D10A
54
D11_A D11A
55
D12_A D12A
56
D13_A D13A
57
OTR_A OTRA
58
OEB_A 59
PDWN_A 60
MUX_SEL 61
SH_REF 62
CLK_A 63
AVDD5 VD
64
EPAD 65
D7B D7_B
32
D6B 31 D5_B
30 DRVDD
29 DRGND
28
D4B D4_B
27
D3B D3_B
26
D2B D2_B
25
D1B 24
23
22
21
20 DCS
19
ENCB
D6_B
D1_B
D0_B
OEB_B
PDWN_B
DFS
CLK_B
D6_A D6A
48
D5_A D5A
47
D4_A D4A
46
D3_A D3A
45
D2_A D2A
44
D1_A D1A
43
D0_A D0A
42
DRVDD1 41
DRGND1 40
OTR_B OTRB
39
D13_B D13B
38
D12_B D12B
37
D11_B D11B
36
D10_B D10B
35
D9_B D9B
34
D8_B D8B
33
1AGND
2VIN_A
3VIN_AB
4AGND1
VD 5AVDD1
6REFT_A
7REFB_A
VREF
8VREF
SENSE
9SENSE
10 REFB_B
11 REFT_B
VD 12 AVDD2
13 AGND2
14 VIN_BB
15 VIN_B
16 AGND3
VCC 14
4B 13
4A 12
4Y 11
3B 10
3A 9
3Y 8
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
GND 7
2Y 6
2B 5
2A 4
1Y 3
1B 2
1A 1
3Y
3A
3B
4Y
4A
4B
VCC
8
9
10
11
12
13
14
18
VD AVDD3
17
D0B
D5B
+
+ + + ++
ENCA
VREF
C30
0.1
μ
F
R45
10k
Ω
R56
10k
Ω
E2
E27
E25
E30
E41
VD
C11
0.1
μ
F
SENSE
EXT_VREF C2
10
μ
F
VREF AND SENSE CIRCUI T
MUX
R35
0
Ω
R38
0
Ω
R20
0
Ω
R40
0
Ω
R14
50
Ω
J5
TIEB
TIEA
TO TIE CLOCKS TOGETHER
C4
0.1
μ
F
VDD
VDD C6
0.1
μ
F
E22
E24
VD
R67
1k
Ω
R68
1k
Ω
R70
1k
Ω
R69
1k
Ω
E21
E40
VD
E26
E29
VD E31E33
VD
PADS TO SHORT
REFERENCES TOGETHER
P15
P16
P18
P17
REFTA
REFTB
REFBA
REFBB
REFB_B
REFT_B
AMPOUTB
R36
33
Ω
R37
33
Ω
AMPOUTBB
C3
20pF
C28
0.1μF
C7
10μF
C54
0.1μF
C23
0.1μF
C5
10μF
C55
0.1μF
C24
0.1μF
C26
0.1μF
C29
0.1μF
C27
0.1μF
H3
MTHOLE6
H1
MTHOLE6
H2
MTHOLE6
H4
MTHOLE6
4123 4123 4123
P5
P6
P7
VD
VDD
VDL
C37
10μF
C38
10μF
C16
10μF
C17
10μF
C18
10μF
C19
10μFC39
0.1μF
C43
0
.
1μF
C44
0
.
1μF
C45
0
.
1μF
+5V –5V
EXT_VREFVDLVDD
VD
P11 P4 P1
E34 E16VD
VD
R55
1k
Ω
E37E38
R48
1k
Ω
0
Ω
R12
0
Ω
R13
E35
E36VD
R49
1kΩ
C41
0.1
μ
F
VD
VD
J2
ENCODE B R51
50Ω
C42
0.1μF
R54
1kΩ
R52
1kΩ
P2 P9
U3
P13
ENCB
VD
VD
C22
10μF
C57
0.1μF
R6
100
Ω
R8
100
Ω
TIEB
1
2
3
5
4
SN74LVC1G04
NC
A
GND
VCC
Y
1
2
3
5
4
SN74LVC1G04
NC
A
GND
VCC
Y
P10 P12
C36
10μF
C58
0.1μF
ENCA
VD
VD R33
100
Ω
R42
100
Ω
R50
22
Ω
R43
0
Ω
U1
E13 E12VD
VD
R47
1k
Ω
E15
E14
R46
1k
Ω
0
Ω
R9
0
Ω
R10
CLKLATB
DRB
DRA
CLKLATA
J6
R61
50
Ω
C56
0.1
μ
F
VD
J3
ENCODE A
R11
50Ω
C40
0.1μF
R41
1kΩ
TIEA
R39
1kΩ
VD
C25
0.1μF
E3
E4VD
R44
1kΩP14
E6
E5
VD
E20
E18
VD
E9
E7
VD
R66
1k
Ω
R65
1kΩ
R64
1k
Ω
E10
E17
R63
1k
Ω
R62
1k
Ω
VD
VDD
C8
0.1μF
MUX
DUT CLOCK SELECTABLE
TO BE DIRECT OR BUFFERED
74LCX86
74LCX86
R4
33
Ω
J1
AIN B
C13
0.1
μ
F
R59
1k
Ω
R7
50
Ω
AMPINB
C10
10
μ
F
C12
0.1
μ
F
E43
E42
C9
10
μ
F
C31
0.1
μ
F
R57
1k
Ω
1
2
3
6
5
4
CTAPB
R5
33
Ω
1
2
3
6
5
4
CTAPA
AMPOUTAB
AMPOUTA
C14
0.1
μ
F
AMPINA
R3
50
Ω
J4
C1
20pF
VD
–5V +5V VD VDD VDL EXT_VREF
CTAPA
R58
1k
Ω
VD
VD
R60
1k
Ω
CTAPB
T1
T2
SEE
BELOW
DUT CLOCK SELECTABLE
TO BE DIRECT OR
BUFFERED
U5
U6
U7
AIN A
02640-069
Figure 50. PCB Schematic (1 of 3)
AD9238
Rev. C | Page 37 of 48
R8
R7
R6
R5
R4
R3
R1
R2
8
7
6
5
4
3
1
216
15
14
13
12
11
10
9
220
220
220
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
HEADER40
220
SN74LVCH16373A
U2
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
GND
LE1
LE2
VCC
OE1
OE2
VCC
VCC
VCC
GND
GND
GND GND
GND
GND
GND
220
R8
R7
R6
R5
R4
R3
R1
R2
220
220
220
SN74LVCH16373A
U4
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
GND
LE1
LE2
VCC
OE1
OE2
VCC
VCC
VCC
GND
GND
GND GND
GND
GND
GND
Q = OUTPUT
D = INPUT
47
46
44
43
41
40
38
37
2
3
5
6
8
9
11
12
36
35
33
32
30
29
27
26
13
14
16
17
19
20
22
23
4
10
15
21
45
39
34
28
48
25
7
18
42
31
1
24
CLKLATB
CLKLATB
CLKLATA
VDL
VDL
VDL
RZ6
RSO16ISO
RZ5
RSO16ISO
8
7
6
5
4
3
1
216
15
14
13
12
11
10
9
RZ4
RSO16ISO
8
7
6
5
4
3
1
216
15
14
13
12
11
10
9
RZ3
RSO16ISO
47
46
44
43
41
40
38
37
2
3
5
6
8
9
11
12
36
35
33
32
30
29
27
26
13
14
16
17
19
20
22
23
4
10
15
21
45
39
34
28
48
25
7
18
42
31
1
24
8
7
6
5
4
3
1
216
15
14
13
12
11
10
9
RZ1
RSO16ISO
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
P3
RZ9
RSO16ISO
RZ10
RSO16ISO
D9Q
D8Q
D7Q
D6Q
D5Q
D4Q
D3Q
D2Q
D1Q
D9P
D8P
D7P
D6P
D5P
D4P
D3P
D2P
D1P
D8A
D9A
D2A
D3A
D4A
D5A
D6A
D7A
D0A
D1A
GND
D9P
D8P
D7P
D6P
D5P
D4P
D3P
D2P
D1P
D0P
GND
DRA
DRB
OTRA
D13A
D12A
D11A
D10A
D7B
D9B
D8B
OTRB
D13B
D12B
D11B
D10B
DORP
D13P
D12P
D11P
D10P
DORQ
D13Q
D12Q
D11Q
D10Q
D9Q
D0Q
D8Q
D1Q
D2Q
D6Q
D7Q
D3Q
D4Q
D5Q
D13P
D12P
D11P
D10P
D0P
DORP
D13Q
D12Q
D11Q
D10Q
D0Q
DORQ
VDL
VDL VDL
VDL
CLKLATA
8
7
6
5
4
3
1
216
15
14
13
12
11
10
9
RZ2
RSO16ISO
D5B
D6B
D4B
D3B
D2B
D1B
D0B
R8
R7
R6
R5
R4
R3
R1
R2
R8
R7
R6
R5
R4
R3
R1
R2
R8
R7
R6
R5
R4
R3
R1
R2
Q = OUTPUT
D = INPUT
R8
R7
R6
R5
R4
R3
R1
R2
8
7
6
5
4
3
1
216
15
14
13
12
11
10
9
R8
R7
R6
R5
R4
R3
R1
R2
8
7
6
5
4
3
1
216
15
14
13
12
11
10
9
R8
R7
R6
R5
R4
R3
R1
R2
8
7
6
5
4
3
1
216
15
14
13
12
11
10
9
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
HEADER40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
P8
VDL
C49
0.1μF
C48
0.1μF
C47
0.1μF
C46
0.1μF
C53
0.1μF
C52
0.1μF
C51
0.1μF
C50
0.1μF
39 39
VDL
02640-070
Figure 51. PCB Schematic (2 of 3)
AD9238
Rev. C | Page 38 of 48
+IN
+OUT
–IN
–OUT
EPAD
NC V+
V– VOCM
AD8139
C20
0.1μF
8
4
1
5
9
736 2
U12
C35
0.1μF
R29
499Ω
R30
40Ω
R25
525Ω
AMPOUTB AMPOUTBB
+5V
–5V
AMPINB
C34
0.1μF
R28
1kΩ
R27
1kΩ
VD
R24
40Ω
+IN
+OUT
–IN
–OUT
EPAD
NC V+
V– VOCM
AD8139
C21
0.1μF
8
4
1
5
9
736 2
U11
C32
0.1μF
R17
525Ω
R22
40Ω
R16
499Ω
AMPOUTAB AMPOUTA
+5V
–5V
AMPINA
C33
0.1μF
R19
1kΩ
R21
1kΩ
VD
R23
40Ω
OP AMP INPUT OFF PIN 1 OF TRANSFORMER
02640-071
R31
499ΩC61
R26
499Ω
C15
R15
499Ω
C60
R18
499Ω
C59
Figure 52. PCB Schematic (3 of 3)
AD9238
Rev. C | Page 39 of 48
LFCSP PCB LAYERS
02640-072
Figure 53. PCB Top-Side Silkscreen
AD9238
Rev. C | Page 40 of 48
02640-073
Figure 54. PCB Top-Side Copper Routing
AD9238
Rev. C | Page 41 of 48
02640-074
Figure 55. PCB Ground Layer
AD9238
Rev. C | Page 42 of 48
02640-075
Figure 56. PCB Split Power Plane
AD9238
Rev. C | Page 43 of 48
02640-076
Figure 57. PCB Bottom-Side Copper Routing
AD9238
Rev. C | Page 44 of 48
02640-077
Figure 58. PCB Bottom-Side Silkscreen
02640-078
THERMAL CONSIDERATIONS
The AD9238 LFCSP has an integrated heat slug that improves
the thermal and electrical properties of the package when locally
attached to a ground plane at the PCB. A thermal (filled) via array
to a ground plane beneath the part provides a path for heat to
escape the package, lowering junction temperature. Improved
electrical performance also results from the reduction in package
parasitics due to proximity of the ground plane. Recommended
array is 0.3 mm vias on 1.2 mm pitch. θJA = 26.4°C/W with this
recommended configuration. Soldering the slug to the PCB is a
requirement for this package.
Figure 59. Thermal Via Array
AD9238
Rev. C | Page 45 of 48
OUTLINE DIMENSIONS
COMP LIANT TO JEDEC STANDARDS MS-026- BBD
051706-A
TOP V IEW
(PINS DOWN)
1
16
17 33
32
48
4964
0.23
0.18
0.13
0.40
BSC
LEAD PITCH
1.60
MAX
0.75
0.60
0.45
VIEW A
PIN 1
0.20
0.09
1.45
1.40
1.35
0.08
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
7°
3.5°
0°
0.15
0.05
9.20
9.00 SQ
8.80
7.20
7.00 SQ
6.80
Figure 60. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-1)
Dimensions shown in millimeters
PIN 1
INDICATOR
TOP
VIEW 8.75
BSC SQ
9.00
BSC SQ
1
64
16
17
49
48
32
33
0.50
0.40
0.30
0.50 BS C 0.20 REF
12° M AX 0.80 MAX
0.65 TYP
1.00
0.85
0.80
7.50
REF
0.05 M A X
0.02 NOM
0.60 M A X
0.60 M A X
*4.85
4.70 SQ
4.55
EXPOSED PAD
(BOTTO M VI EW )
*COM PLI ANT TO JE DE C S TANDARDS MO-220-V M MD- 4
EXCEP T FOR EXP OSED PAD DIMENS ION
082908-B
SEATING
PLANE
PIN 1
INDICATOR
0.30
0.25
0.18
FOR PROP E R CONNECT ION O F
THE EX POSE D P AD, REF ER TO
THE PIN CONFIGURATI ON AND
FUNCT ION DE S CRIPTIO NS
SECTION OF THIS DATA SHEET.
Figure 61. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-1)
Dimensions shown in millimeters
AD9238
Rev. C | Page 46 of 48
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9238BST-20 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1
AD9238BSTZ-20 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1
AD9238BSTZRL-20 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1
AD9238BST-40 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1
AD9238BSTRL-40 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1
AD9238BSTZ-40 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1
AD9238BSTZRL-40 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1
AD9238BST-65 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1
AD9238BSTRL-65 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1
AD9238BSTZ-65 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1
AD9238BSTZRL-65 –40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-1
AD9238BCPZ-20 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1
AD9238BCPZRL-20 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1
AD9238BCPZ-40 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1
AD9238BCPZRL-40 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1
AD9238BCPZ-65 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1
AD9238BCPZRL-65 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-1
AD9238BCP-65EBZ Evaluation Board
1 Z = RoHS Compliant Part.
AD9238
Rev. C | Page 47 of 48
NOTES
AD9238
Rev. C | Page 48 of 48
NOTES
©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02640–0–11/10(C)
