SN54ACT16373, 74ACT16373
16-BIT D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS122C − MARCH 1990 − REVISED SEPTEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DMembers of the Texas Instruments
Widebust Family
DInputs Are TTL-Voltage Compatible
D3-State Bus Driving True Outputs
DFull Parallel Access for Loading
DFlow-Through Architecture Optimizes
PCB Layout
DDistributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
DEPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
D500-mA Typical Latch-Up Immunity at
125°C
DPackage Options Include Shrink
Small-Outline (DL) 300-mil Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The SN54ACT16373 and 74ACT16373 are 16-bit
D-type transparent latches with 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers. These devices can be used as
two 8-bit latches or one 16-bit latch. The Q outputs
of the latches follow the data (D) inputs if enable
C is taken high. When C is taken low, the Q outputs
are latched at the levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low
logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
in a bus-organized system without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The 74ACT16373 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The SN54ACT16373 is characterized for operation over the full military temperature range of −55°C to 125°C.
The 74ACT16373 is characterized for operation from −40°C to 85°C.
Copyright © 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1C
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2C
SN54ACT16373 . . . WD PACKAGE
74ACT16373 . . . DL PACKAGE
(TOP VIEW)
SN54ACT16373, 74ACT16373
16-BIT D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS122C − MARCH 1990 − REVISED SEPTEMBER 1996
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS OUTPUT
OE C D
OUTPUT
Q
L H H H
LHL L
LLX Q
0
H X X Z
logic symbol†
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1OE
2OE
1EN
1
C1
48
1C
1D
47
1D1 46
1D2 44
1D3 43
1D4
1Q1
2
1Q2
3
1Q3
5
1Q4
6
2
41
1D5 40
1D6 38
1D7 37
1D8
1Q5
8
1Q6
9
1Q7
11
1Q8
12
3D
36
2D1 35
2D2 33
2D3 32
2D4
2Q1
13
2Q2
14
2Q3
16
2Q4
17
30
2D5 29
2D6 27
2D7 26
2D8
2Q5
19
2Q6
20
2Q7
22
2Q8
23
4
2EN
24
C4
25
2C
1
1
SN54ACT16373, 74ACT16373
16-BIT D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS122C − MARCH 1990 − REVISED SEPTEMBER 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1OE
1C
1D1
To Seven Other Channels
1Q1
2OE
2C
2D1 2Q1
To Seven Other Channels
1
48
47
24
25
36
C1
1D
132
C1
1D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC)±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC)±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC)±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DL package 1.2 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
SN54ACT16373 74ACT16373
UNIT
MIN MAX MIN MAX UNIT
VCC Supply voltage (see Note 4) 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
IOH High-level output current −24 −24 mA
IOL Low-level output current 24 24 mA
Dt/DvInput transition rise or fall rate 0 10 0 10 ns/V
TAOperating free-air temperature −55 125 −40 85 °C
NOTES: 3. Unused inputs should be tied to VCC through a pullup resistor of approximately 5 kW or greater to prevent them from floating.
4. All VCC and GND pins must be connected to the proper voltage supply.
SN54ACT16373, 74ACT16373
16-BIT D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS122C − MARCH 1990 − REVISED SEPTEMBER 1996
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
TA = 25°C SN54ACT16373 74ACT16373
UNIT
PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT
I50 A
4.5 V 4.4 4.4 4.4
IOH = −50 mA5.5 V 5.4 5.4 5.4
I24 mA
4.5 V 3.94 3.7 3.8
VOH IOH = −24 mA 5.5 V 4.94 4.7 4.8 V
IOH = −50 mA{5.5 V 3.85
IOH = −75 mA{5.5 V 3.85
I50 A
4.5 V 0.1 0.1 0.1
IOL = 50 mA5.5 V 0.1 0.1 0.1
I24 mA
4.5 V 0.36 0.5 0.44
VOL IOL = 24 mA 5.5 V 0.36 0.5 0.44 V
IOL = 50 mA{5.5 V 1.65
IOL = 75 mA{5.5 V 1.65
IIVI = VCC or GND 5.5 V ±0.1 ±1±1mA
IOZ VO = VCC or GND 5.5 V ±0.5 ±10 ±5mA
ICC VI = VCC or GND, IO = 0 5.5 V 8 160 80 mA
DICC}One input at 3.4 V,
Other inputs at GND or VCC 5.5 V 0.9 1 1 mA
CiVI = VCC or GND 5 V 4.5 pF
CoVI = VCC or GND 5 V 12 pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V to VCC.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25°C SN54ACT16373 74ACT16373
UNIT
MIN MAX MIN MAX MIN MAX UNIT
twPulse duration, LE high 4 4 1 ns
tsu Setup time, data before LE↓1 1 1 ns
thHold time, data after LE↓5 5 5 ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO TA = 25°C SN54ACT16373 74ACT16373
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT) MIN TYP MAX MIN MAX MIN MAX UNIT
tPLH
D
Q
3.8 7.9 9.4 3.8 11.8 3.8 11.1
ns
tPHL
D Q 3.1 8.2 9.7 3.1 13 3.1 12.3 ns
tPLH
LE
Q
4.6 9.3 10.8 4.6 13.7 4.6 12.8
ns
tPHL
LE Q 4.5 9.1 10.5 4.5 13 4.5 12.2 ns
tPZH
OE
Q
3.1 8 9.5 3.1 13 3.1 12.1
ns
tPZL
OE Q3.8 9.4 11.1 3.8 15.1 3.8 14.2 ns
tPHZ
OE
Q
5.3 8.6 9.9 5.3 11 5.3 10.7
ns
tPLZ
OE Q4.3 7.4 8.7 4.3 9.8 4.3 9.4 ns
SN54ACT16373, 74ACT16373
16-BIT D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS122C − MARCH 1990 − REVISED SEPTEMBER 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per latch
Outputs enabled
C50 pF
f 1 MHz
43
pF
Cpd Power dissipation capacitance per latch Outputs disabled CL = 50 pF, f = 1 MHz 4.5 pF
PARAMETER MEASUREMENT INFORMATION
50% VCC
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V 1.5 V
3 V
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2 × VCC
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
[ VCC
0 V
50% VCC 20% VCC
50% VCC
80% VCC
[ 0 V
3 V
GND
Open
VOLTAGE WAVEFORMS
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
3 V
0 V
1.5 V 1.5 V
tw
VOLTAGE WAVEFORMS
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
74ACT16373DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
74ACT16373DLR SSOP DL 48 1000 367.0 367.0 55.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
WD (R-GDFP-F**) CERAMIC DUAL FLATPACK
4040176/D 10/97
48 LEADS SHOWN
48
48
25
56
0.610
(18,80)
0.710
(18,03)
0.7400.640
0.390 (9,91)
0.370 (9,40)
0.870 (22,10)
1.130 (28,70)
1
A
0.120 (3,05)
0.075 (1,91)
LEADS**
24
NO. OF
A MIN
A MAX (16,26)
(15,49)
0.025 (0,635)
0.009 (0,23)
0.004 (0,10)
0.370 (9,40)
0.250 (6,35)
0.370 (9,40)
0.250 (6,35)
0.014 (0,36)
0.008 (0,20)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA
GDFP1-F56 and JEDEC MO-146AB
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