MC100EPT25DTG - ON SEMICONDUCTOR - Datasheet.Directory

August, 2008 − Rev. 16

1Publication Order Number:

MC100EPT25/D

MC100EPT25

-3.3V / -5V Differential ECL

to +3.3V LVTTL Translator

Description

The MC100EPT25 is a Differential ECL to LVTTL translator. This

device requires +3.3 V, −3.3 V to −5.2 V, and ground. The small

outline 8−lead package and the single gate of the EPT25 make it ideal

for applications which require the translation of a clock or data signal.

The VBB output allows the EPT25 to also be used in a single−ended

input mode. In this mode the VBB output is tied to the D input for a

inverting buffer or the D input for a non−inverting buffer. If used, the

VBB pin should be bypassed to ground with at least a 0.01 mF

capacitor.

Features

•1.1 ns Typical Propagation Delay

•Maximum Frequency > 275 MHz Typical

•Operating Range: VCC = 3.0 V to 3.6 V;

VEE = −5.5 V to −3.0 V; GND = 0 V

•24 mA TTL Outputs

•Q Output Will Default LOW with Inputs Open or at VEE

•VBB Output

•Open Input Default State

•Safety Clamp on Inputs

•Pb−Free Packages are Available

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

M = Date Code

G= Pb−Free Package

SOIC−8

D SUFFIX

CASE 751

MARKING DIAGRAMS*

TSSOP−8

DT SUFFIX

CASE 948R

ALYWG

KA25

http://onsemi.com

*For additional marking information, refer to

Application Note AND8002/D.

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

ORDERING INFORMATION

8KPT25

ALYW

DFN8

MN SUFFIX

CASE 506AA

3V MG

(Note: Microdot may be in either location)

MC100EPT25

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GND

VCC

Figure 1. 8−Lead Pinout (Top View) and Logic Diagram

NCD

VBB

VEE

LVTTL

LVECL/ECL

Table 1. PIN DESCRIPTION

D*, D* Differential ECL Input Pair

FUNCTION

LVTTL Output

VCC

VBB Output Reference Voltage

Positive Supply

GND Ground

VEE Negative Supply

NC No Connect

* Pins will default LOW when left open.

(DFN8 only) Thermal exposed pad

must be connected to a sufficient

thermal conduit. Electrically connect

to the most negative supply (GND) or

leave unconnected, floating open.

Table 2. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor 75 kW

Internal Input Pullup Resistor N/A

ESD Protection Human Body Model

Machine Model

Charged Device Model

> 4 kV

> 200 V

> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg

SOIC−8

TSSOP−8

DFN8

Level 1

Level 3

Level 1

Flammability Rating Oxygen Index: 28 to 34 UL−94 V−0 @ 0.125 in

Transistor Count 111 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

MC100EPT25

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Table 3. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC Positive Power Supply GND = 0 V VEE = −5.0 V 3.8 V

VEE Negative Power Supply GND = 0 V VCC = +3.3 V −6 V

VIN Input Voltage GND = 0 V 0 to VEE V

IBB VBB Sink/Source ± 0.5 mA

TAOperating Temperature Range −40 to +85 °C

Tstg Storage Temperature Range −65 to +150 °C

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

8 SOIC

190

130

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board 8 SOIC 41 to 44 °C/W

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

8 TSSOP

185

140

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board 8 TSSOP 41 to 44 °C/W

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

DFN8

129

°C/W

Tsol Wave Solder Pb

Pb−Free

<2 to 3 sec @ 248°C

<2 to 3 sec @ 260°C

265

°C

qJC Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

Table 4. NECL DC CHARACTERISTICS VCC = 3.3 V; VEE = −5.5 V to −3.0 V; GND = 0.0 V (Note 3)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 8.0 16 25 8.0 16 25 8.0 16 25 mA

VIH Input HIGH Voltage Single−Ended −1225 −880 −1225 −880 −1225 −880 mV

VIL Input LOW Voltage Single−Ended −1945 −1625 −1945 −1625 −1945 −1625 mV

VBB Output Voltage Reference −1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Note 4)

VEE + 2.0 0.0 VEE + 2.0 0.0 VEE + 2.0 0.0 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.5 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

3. Input parameters vary 1:1 with GND.

4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

MC100EPT25

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Table 5. TTL OUTPUT DC CHARACTERISTICS VCC = 3.3 V; VEE = −5.5 V to −3.0 V; GND = 0.0 V; TA = −40°C to 85°C

Symbol Characteristic Condition Min Typ Max Unit

VOH Output HIGH Voltage IOH = −3.0 mA 2.2 V

VOL Output LOW Voltage IOL = 24 mA 0.5 V

ICCH Power Supply Current 6 10 14 mA

ICCL Power Supply Current 7 12 17 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V; VEE = −5.5 V to −3.0 V; GND = 0.0 V (Note 5)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

fmax Maximum Frequency

(See Figure 2 Fmax/JITTER)

275 275 275 MHz

tPLH, tPHL Propagation Delay to Output Differential

(Cross−Point to 1.5 V)

500 950 1300 800 950 1600 800 960 1600 ps

tSKPP Device−to−Device Skew (Note 6) 500 500 500 ps

tJITTER Random Clock Jitter (RMS)

(See Figure 2 Fmax/JITTER)

0.2 < 1 0.2 < 1 0.2 < 1 ps

VPP Input Voltage Swing (Differential) 150 800 1200 150 800 1200 150 800 1200 mV

Output Rise/Fall Times Q, Q

(0.8 V − 2.0 V)

300

900

474

1160

600

1400

300

900

459

1100

600

1400

300

900

457

1100

600

1400

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

5. Measured with a 750 mV 50% duty−cycle clock source. RL = 500 W to GND and CL = 20 pF to GND. Refer to Figure 3.

6. Skews are measured between outputs under identical conditions.

400

800

1200

1600

2000

2400

2800

25 100 175 250 325 400 475 550 625

Figure 2. Fmax/Jitter

FREQUENCY (MHz)

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

(JITTER)

VOH

VOL  0.5 V

VOUTpp (mV)

JITTEROUT ps (RMS)

MC100EPT25

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Figure 3. TTL Output Loading Used for Device Evaluation

CHARACTERISTIC TEST

CL*R

AC TEST LOAD

GND

*CL includes

fixture

capacitance

APPLICATION

TTL RECEIVER

ORDERING INFORMATION

Device Package Shipping†

MC100EPT25D SOIC−898 Units / Rail

MC100EPT25DG SOIC−8

(Pb−Free)

98 Units / Rail

MC100EPT25DR2 SOIC−82500 / Tape & Reel

MC100EPT25DR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

MC100EPT25DT TSSOP−8100 Units / Rail

MC100EPT25DTG TSSOP−8

(Pb−Free)

100 Units / Rail

MC100EPT25DTR2 TSSOP−82500 / Tape & Reel

MC100EPT25DTR2G TSSOP−8

(Pb−Free)

2500 / Tape & Reel

MC100EPT25MNR4 DFN8 1000 / Tape & Reel

MC100EPT25MNR4G DFN8

(Pb−Free)

1000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Resource Reference of Application Notes

AN1405/D −ECL Clock Distribution Techniques

AN1406/D −Designing with PECL (ECL at +5.0 V)

AN1503/D −ECLinPSt I/O SPiCE Modeling Kit

AN1504/D −Metastability and the ECLinPS Family

AN1568/D −Interfacing Between LVDS and ECL

AN1672/D −The ECL Translator Guide

AND8001/D −Odd Number Counters Design

AND8002/D −Marking and Date Codes

AND8020/D −Termination of ECL Logic Devices

AND8066/D −Interfacing with ECLinPS

AND8090/D −AC Characteristics of ECL Devices

MC100EPT25

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PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AJ

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

MC100EPT25

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PACKAGE DIMENSIONS

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A2.90 3.10 0.114 0.122

B2.90 3.10 0.114 0.122

C0.80 1.10 0.031 0.043

D0.05 0.15 0.002 0.006

F0.40 0.70 0.016 0.028

G0.65 BSC 0.026 BSC

L4.90 BSC 0.193 BSC

M0 6 0 6

____

SEATING

PLANE

PIN 1

DETAIL E

2X L/2

−U−

U0.15 (0.006) T

0.10 (0.004) V S

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

8x REFK

IDENT

K0.25 0.40 0.010 0.016

TSSOP−8

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948R−02

ISSUE A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

MC100EPT25

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PACKAGE DIMENSIONS

DFN8

CASE 506AA−01

ISSUE D

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994 .

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

ÇÇÇ

C0.10

PIN ONE

2 X

REFERENCE

2 X

TOP VIEW

SIDE VIEW

BOTTOM VIEW

(A3)

C0.10

C0.08

8 X

SEATING

PLANE

e/2 e

8 X

NOTE 3

8 X 0.10 C

0.05 C

ABB

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.20 0.30

D2.00 BSC

D2 1.10 1.30

E2.00 BSC

E2 0.70 0.90

e0.50 BSC

K0.20 −−−

L0.25 0.35

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

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PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

MC100EPT25/D

ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).

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