1
Data sheet acquired from Harris Semiconductor
SCHS085E – Revised September 2003
CD4541B
CMOS Programmable Timer
High Voltage Types (20V Rating)
Features
• Low Symmetrical Output Resistance, Typically 100Ω
at VDD = 15V
• Built-In Low-Power RC Oscillator
• Oscillator Frequency Range . . . . . . . . . . DC to 100kHz
• External Clock (Applied to Pin 3) can be Used Instead
of Oscillator
• Operates as 2N Frequency Divider or as a Single-
Transition Timer
•Q/
Q Select Provides Output Logic Level Flexibility
• AUTO or MASTER RESET Disables Oscillator During
Reset to Reduce Power Dissipation
• Operates With Very Slow Clock Rise and Fall Times
• Capable of Driving Six Low Power TTL Loads, Three
Low-Power Schottky Loads, or Six HTL Loads Over
the Rated Temperature Range
• Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V, and 15V Parametric Ratings
• Meets All Requirements of JEDEC Standard No. 13B,
“Standard Specifications for Description of ‘B’ Series
CMOS Devices”
Description
CD4541B programmable timer consists of a 16-stage binary
counter, an oscillator that is controlled by external R-C compo-
nents (2 resistors and a capacitor), an automatic power-on
reset circuit, and output control logic. The counter increments
on positive-edge clock transitions and can also be reset via the
MASTER RESET input.
Pinout
CD4541B
(CERDIP, PDIP, SOIC, SOP, TSSOP)
TOP VIEW
The output from this timer is the Q or Q output from the 8th,
10th, 13th, or 16th counter stage. The desired stage is chosen
using time-select inputs A and B (see Frequency Select Table).
The output is available in either of two modes selectable via the
MODE input, pin 10 (see Truth Table). When this MODE input is
a logic “1”, the output will be a continuous square wave having
a frequency equal to the oscillator frequency divided by 2N.
With the MODE input set to logic “0” and after a MASTER
RESET is initiated, the output (assuming Q output has been
selected) changes from a low to a high state after 2N-1 counts
and remains in that state until another MASTER RESET pulse
is applied or the MODE input is set to a logic “1”.
Timing is initialized by setting the AUTO RESET input (pin 5) to
logic “0” and turning power on. If pin 5 is set to logic “1”, the
AUTO RESET circuit is disabled and counting will not start until
after a positive MASTER RESET pulse is applied and returns
to a low level. The AUTO RESET consumes an appreciable
amount of power and should not be used if low-power operation
is desired. For reliable automatic power-on reset, VDD should
be greater than 5V.
The RC oscillator, shown in Figure 2, oscillates with a
frequency determined by the RC network and is calculated
using:
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
R
TC
C
TC
R
S
NC
AUTO RESET
MASTER RESET
V
SS
V
DD
B
A
NC
MODE
Q/Q SELECT
OUTPUT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Ordering Information
PART NUMBER
TEMP. RANGE
(oC) PACKAGE
CD4541BF3A -55 to 125 14 Ld CERDIP
CD4541BE -55 to 125 14 Ld PDIP
CD4541BM -55 to 125 14 Ld SOIC
CD4541BMT -55 to 125 14 Ld SOIC
CD4541BM96 -55 to 125 14 Ld SOIC
CD4541BNSR -55 to 125 14 Ld SOP
CD4541BPW -55 to 125 14 Ld TSSOP
CD4541BPWR -55 to 125 14 Ld TSSOP
f
= 1
2.3 RTCCTC
-----------------------------------Where f is between 1kHz
and 100kHz
and RS10k≥Ωand 2RTC
≈
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
[
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(
CD45
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emi-
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on-
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Functional Diagram
FREQUENCY SELECTION TABLE
TRUTH TABLE
12
13
1
2
3
5
6
10
9
A
B
R
TC
C
TC
R
S
AR
MR
MODE
Q/Q
SELECT
8Q
V
DD
= PIN 14
V
SS
= PIN 7
N
P
N
P
12 13
†A†B
8-STAGE
COUNTER
1 OF 3
MUX
OSC
3
2
1
†RS
†CTC
†RTC
R
R
PWR ON
RESET
6
5
RESET†
MANUAL RESET†
R
210 213
216
OR
28
8
Q
R
10
†MODE
VDD = 14
VSS = 7 NC = 4, 11
9
†Q/Q SELECT
VSS
VDD
8-STAGE
COUNTER
†All inputs are protected by CMOS Protection Network.
FIGURE 1.
AUTO
AB
NO. OF
STAGES N COUNT 2N
0 0 13 8192
0 1 10 1024
1 0 8 256
1 1 16 65536
PIN
STATE
01
5 Auto Reset On Auto Reset Disable
6 Master Reset Off Master Reset On
9 Output Initially Low After
Reset (Q)
Output Initially High After
Reset (Q)
10 Single Transition Mode Recycle Mode
FIGURE 2. RC OSCILLATOR CIRCUIT
RS
3
CTC
RTC
2
1
INTERNAL
RESET
TO CLOCK
CKT
CD4541B
3
Absolute Maximum Ratings Thermal Information
DC Supply - Voltage Range, VDD
Voltages Referenced to VSS Terminal . . . . . . . . . . -0.5V to +20V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . ±10mA
Device Dissipation Per Output Transistor
For TA = Full Package Temperature Range
(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Operating Conditions
Temperature Range TA. . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range
For TA = Full Package Temperature Range . . . . . 3V (Min), 18V (Typ)
Package Thermal Impedance, θJA (see Note 1)
PDIP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80oC/W
SOIC package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86oC/W
SOP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76oC/W
TSSOP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113oC/W
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range (TSTG) . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s)
At Distance 1/16in ±1/32in (1.59mm ±0.79mm)
from case for 10s Maximum . . . . . . . . . . . . . . . . . . . . . . . . 265oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
Electrical Specifications
PARAMETER
CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC)
UNITS
VO
(V)
VIN
(V)
VDD
(V) -55 -40 85 125
25
MIN TYP MAX
Quiescent Device
Current,
(Note 2) IDD (Max)
- 0, 5 5 5 5 150 150 - 0.04 5 μA
- 0, 10 10 10 10 300 300 - 0.04 10 μA
- 0, 15 15 20 20 600 600 - 0.04 20 μA
- 0, 20 20 100 100 3000 3000 - 0.08 100 μA
Output Low (Sink)
Current lOL (Min)
0.4 0, 5 5 1.9 1.85 1.26 1.08 1.55 3.1 - mA
0.5 0, 10 10 5 4.8 3.3 2.8 4 8 - mA
1.5 0, 15 15 12.6 12 8.4 7.2 10 20 - mA
Output High (Source)
Current, IOH (Min)
4.6 0, 5 5 -1.9 -1.85 -1.26 -1.08 -1.55 -3.1 - mA
2.5 0, 5 5 -6.2 -6 -4.1 -3 -5 -10 - mA
9.5 0, 10 10 -5 -4.8 -3.3 -2.8 -4 -8 - mA
13.5 0, 15 15 -12.6 -12 -8.4 -7.2 -10 -20 - mA
Output Voltage:
Low-Level, VOL (Max)
- 0, 5 5 - 0.05 - 0 0.05 V
- 0, 10 10 - 0.05 - 0 0.05 V
- 0, 15 15 - 0.05 - 0 0.05 V
Output Voltage:
High-Level, VOH (Min)
- 0, 5 5 - 4.95 4.95 5 - V
- 0, 10 10 - 9.95 9.95 10 - V
- 0, 15 15 - 14.95 14.95 15 - V
Input Low Voltage,
VIL (Max)
0.5, 4.5 - 5 - 1.5 - - 1.5 V
1, 9 - 10 - 3 - - 3 V
1.5, 13.5 - 15 - 4 - - 4 V
CD4541B
4
Input High Voltage,
VIH (Min)
0.5, 4.5 - 5 - 3.5 3.5 - - V
1, 9 - 10 - 7 7 - - V
1.5, 13.5 - 15 - 11 11 - - V
Input Current, lIN (Max) - 0, 18 18 ±0.1 ±0.1 ±1±1-±10-5 ±0.1 μA
NOTE:
2. With AUTO RESET enabled, additional current drain at 25oC is:
7μA (Typ), 200μA (Max) at 5V;
30μA (Typ), 350μA (Max) at 10V;
80μA (Typ), 500μA (Max) at 15V
Dynamic Electrical Specifications TA = 25oC, Input tr, tf = 20ns, CL = 50pF, RL = 200kΩ
PARAMETER SYMBOL VDD (V) MIN TYP MAX UNITS
Propagation Delay Times
Clock to Q
(28) tPHL, tPLH 5 - 3.5 10.5 μs
10 - 1.25 3.8 μs
15 - 0.9 2.9 μs
(216) tPHL, tPLH 5-6.018μs
10 - 3.5 10 μs
15 - 2.5 7.5 μs
Transition Time tTHL 5 - 100 200 ns
10 - 50 100 ns
15 - 40 80 ns
tTHL 5 - 180 360 ns
10 - 90 180 ns
15 - 65 130 ns
MASTER RESET, CLOCK
Pulse Width
5 900 300 - ns
10 300 100 - ns
15 225 85 - ns
Maximum Clock Pulse Input
Frequency
fCL 5 - 1.5 - MHz
10 - 4 - MHz
15 - 6 - MHz
Maximum Clock Pulse Input
Rise or Fall time
tr,t
f5, 10, 15 Unlimited μs
Electrical Specifications (Continued)
PARAMETER
CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC)
UNITS
VO
(V)
VIN
(V)
VDD
(V) -55 -40 85 125
25
MIN TYP MAX
CD4541B
5
Digital Timer Application
A positive pulse on MASTER RESET resets the counters
and latch. The output goes high and remains high until the
number of pulses, selected by A and B, are counted. This
circuit is retriggerable and is as accurate as the input fre-
quency. If additional accuracy is desired, an external clock
can be used on pin 3. A setup time equal to the width of the
one-shot output is required immediately following initial
power up, during which time the output will be high.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
RTC
RSAR
MR
INPUT
B
A
t
OUTPUT
VDD
CTC
FIGURE 3. DIGITAL TIMER APPLICATION CIRCUIT
CD4541B
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CD4541BE ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD4541BEE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD4541BF ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
CD4541BF3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
CD4541BM ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4541BM96 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4541BM96E4 ACTIVE SOIC D 14 TBD Call TI Call TI
CD4541BM96G4 ACTIVE SOIC D 14 TBD Call TI Call TI
CD4541BME4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4541BMG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4541BMT ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4541BMTE4 ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4541BMTG4 ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4541BNSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4541BNSRE4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4541BNSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4541BPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4541BPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4541BPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
CD4541BPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4541BPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD4541BPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD4541B, CD4541B-MIL :
•Catalog: CD4541B
•Military: CD4541B-MIL
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 3
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CD4541BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4541BMT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4541BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4541BPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD4541BM96 SOIC D 14 2500 367.0 367.0 38.0
CD4541BMT SOIC D 14 250 367.0 367.0 38.0
CD4541BNSR SO NS 14 2000 367.0 367.0 38.0
CD4541BPWR TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 2
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