SN54AHCT541, SN74AHCT541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS269M - DECEMBER 1995 - REVISED JANUARY 2000 D D D D EPIC (Enhanced-Performance Implanted CMOS) Process Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs SN54AHCT541 . . . J OR W PACKAGE SN74AHCT541 . . . DB, DGV, DW, N, OR PW PACKAGE (TOP VIEW) OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 SN54AHCT541 . . . FK PACKAGE (TOP VIEW) A2 A1 OE1 VCC description The 'AHCT541 octal buffers/drivers are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout. A3 A4 A5 A6 A7 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 Y1 Y2 Y3 Y4 Y5 A8 GND Y8 Y7 Y6 The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide noninverted data when they are not in the high-impedance state. OE2 D To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54AHCT541 is characterized for operation over the full military temperature range of -55C to 125C. The SN74AHCT541 is characterized for operation from -40C to 85C. FUNCTION TABLE (each buffer/driver) INPUTS A OUTPUT Y OE1 OE2 L L L L L L H H H X X Z X H X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54AHCT541, SN74AHCT541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS269M - DECEMBER 1995 - REVISED JANUARY 2000 logic symbol OE1 OE2 A1 A2 A3 A4 A5 A6 A7 A8 & 1 EN 19 2 18 1 3 17 4 16 5 15 6 14 7 13 8 12 9 11 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OE1 OE2 A1 1 19 2 18 Y1 To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mA Package thermal impedance, JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54AHCT541, SN74AHCT541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS269M - DECEMBER 1995 - REVISED JANUARY 2000 recommended operating conditions (see Note 3) SN54AHCT541 SN74AHCT541 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 V Input voltage 0 5.5 0 5.5 V VO IOH Output voltage 0 0 VCC -8 V High-level output current VCC -8 mA IOL t/v Low-level output current 8 8 mA 20 20 ns/V High-level input voltage 2 2 0.8 Input transition rise or fall rate V V TA Operating free-air temperature -55 125 -40 85 C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VOH IOH = -50 mA IOH = -8 mA 45V 4.5 VOL IOL = 50 mA IOL = 8 mA 45V 4.5 II IOZ VI = VCC or GND VO = VCC or GND ICC VI = VCC or GND, IO = 0 One input at 3.4 V, Other inputs at VCC or GND ICC Ci VI = VCC or GND VO = VCC or GND MIN 4.4 TA = 25C TYP MAX 4.5 3.94 SN54AHCT541 MIN MAX SN74AHCT541 MIN 4.4 4.4 3.8 3.8 MAX UNIT V 0.1 0.1 0.1 0.36 0.44 0.44 V 0 V to 5.5 V 0.1 1* 1 mA 5.5 V 0.25 2.5 2.5 mA 5.5 V 4 40 40 mA 5.5 V 1.35 1.5 1.5 mA 10 pF 5V 2 10 Co 5V 4 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 pF 3 SN54AHCT541, SN74AHCT541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS269M - DECEMBER 1995 - REVISED JANUARY 2000 switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A Y CL = 15 pF tPZH tPZL OE Y CL = 15 pF tPHZ tPLZ OE Y CL = 15 pF tPLH tPHL A Y CL = 50 pF tPZH tPZL OE Y CL = 50 pF tPHZ tPLZ OE Y CL = 50 pF MIN TA = 25C TYP MAX SN54AHCT541 SN74AHCT541 MIN MAX MIN MAX 4.1* 6* 1* 6.5* 1 6.5 3.7* 5.5* 1* 6.5* 1 6.5 5* 7* 1* 8* 1 8 5* 7* 1* 8* 1 8 4.5* 7* 1* 8* 1 8 4.5* 7* 1* 8* 1 8 6.2 8.5 1 9.5 1 9.5 6 8.5 1 9.5 1 9.5 7.5 10 1 12 1 12 7.5 10 1 12 1 12 7 10 1 12 1 12 7 10 1 12 1 12 tsk(o) CL = 50 pF * On products compliant to MIL-PRF-38535, this parameter is not production tested. ** On products compliant to MIL-PRF-38535, this parameter does not apply. 1** 1 UNIT ns ns ns ns ns ns ns operating characteristics, VCC = 5 V, TA = 25C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 f = 1 MHz TYP 12 UNIT pF SN54AHCT541, SN74AHCT541 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS269M - DECEMBER 1995 - REVISED JANUARY 2000 PARAMETER MEASUREMENT INFORMATION RL = 1 k From Output Under Test Test Point From Output Under Test S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ VCC 50% VCC tPZH tPLH 50% VCC 3V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH - 0.3 V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated