For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX1536 constant-off-time, pulse-width-modulated
(PWM) step-down DC-to-DC converter is ideal for use in
+5.0V and +3.3V to low voltages for notebook and sub-
notebook computers. The MAX1536 features an internal
PMOS power switch and internal synchronous rectifica-
tion for high efficiency and reduced component count. No
external Schottky diode is required across the internal
synchronous rectifier switch. The internal 54mΩPMOS
power switch and 47mΩNMOS synchronous-rectifier
switch easily deliver continuous load currents up to 3.6A.
The MAX1536 produces dynamically adjustable output
voltages for chipsets and graphics processor cores using
a logic-level control signal. The MAX1536 achieves effi-
ciencies as high as 96%.
The MAX1536 uses a unique current-mode, constant-off-
time, PWM control scheme. It has selectable Idle
ModeTM to maintain high efficiency during light-load
operation, or fixed-PWM mode for low output ripple. The
programmable constant-off-time architecture allows a
wide range of switching frequencies up to 1.4MHz, opti-
mizing performance trade-offs between efficiency, output
switching noise, component size, and cost. The
MAX1536 features a digital soft-start to limit surge cur-
rents during startup, a 100% duty-cycle mode for low-
dropout operation, and a low-power shutdown mode that
disconnects the input from the output and reduces supply
current below 1µA. The MAX1536 is available in a 28-pin
thin QFN package with an exposed backside pad.
________________________Applications
Features
♦Dynamically Selectable Output Voltage from
+0.7V to VIN
♦Internal PMOS/NMOS Switches
54mΩ/47mΩOn-Resistance at VIN = +4.5V
63mΩ/53mΩOn-Resistance at VIN = +3.0V
♦+3.0V to +5.5V Input Voltage Range
♦1.4MHz Maximum Switching Frequency
♦2V ±0.75% Reference Output
♦Constant-Off-Time PWM Operation
♦Selectable Idle Mode/PWM Operation at Light
Loads
♦100% Duty Factor in Dropout
♦Digital Soft-Start Inrush Current Limiting
♦<1µA Typical Shutdown Supply Current
♦<750µA Quiescent Supply Current
♦Thermal Shutdown
♦1% VOUT Accuracy Over Line and Load
♦External Reference Input
♦Power-Good Window Comparator
♦Selectable Power-Good Blanking Time During
Output-Voltage Transition
19-2729; Rev 0; 1/03
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
________________________________________________________________ Maxim Integrated Products 1
Minimal Operating Circuit
Ordering Information
Idle Mode is a trademark of Maxim Integrated Products, Inc.
PART
TEMP RANGE
PIN-PACKAGE
MAX1536ETI
-40oC to +85oC
28 Thin QFN 5mm x 5mm
MAX1536
IN
VCC
SKIP
TOFF
PGOOD
SHDN
COMP
LX
FB
PGND
AGND
REF
REFIN
VIN
+3.0V TO +5.5V
VOUT
+0.7V TO VIN
Pin Configuration
IN
LX
IN
SHDN
SKIP
FB
COMP
LX
IN
IN
PGOOD
FBLANK
VCC
AGND
PGND
LX
N.C.
LX
PGND
PGNDREF
REFIN
OD
OD
GATE
TOFF
N.C.
TOP VIEW
THIN QFN
PGND
28
27
26
25
24
23
22
8
9
10
11
12
13
14
15
16
17
18
19
20
21
7
6
5
4
3
2
1
MAX1536
EXPOSED PADDLE
Chipset/Graphics Cores
with Dual-Supply Voltages
Active Termination Buses
Notebook Computers
DDR Memory Termination
EVALUATION KIT
AVAILABLE
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = VCC = VSHDN = +3.3V, VREFIN = +1.5V, SKIP = AGND, TA= 0°C to +85°C, unless otherwise noted. Typical
values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC, IN, SHDN, SKIP to AGND ................................-0.3V to +6V
OD, OD, GATE, PGOOD to AGND...........................-0.3V to +6V
COMP, FB, REF to AGND.........................................-0.3V to +6V
TOFF, REFIN, FBLANK to AGND .............................-0.3V to +6V
IN to VCC ...............................................................-0.3V to +0.3V
PGND to AGND .................................................... -0.3V to +0.3V
LX to PGND ................................................ -0.3V to (VIN + 0.3V)
LX Current (Note 1).............................................................±5.7A
REF Short Circuit to AGND.........................................Continuous
Continuous Power Dissipation (TA= +70°C)
28-Pin Thin QFN (derated 20.8mW/°C above +70°C;
part mounted on 1in2of 1oz copper) .........................1667mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
UNITS
PWM CONTROLLER
Input Voltage
VIN, VCC
3.0
5.5
V
Output Adjust Range VOUT
VREFIN VIN
V
TA = +25°C to +85°C
-3 0
+3
Feedback Voltage Accuracy VFB -
VREFIN
VCC = VIN = +3.0V to
+5.5V, ILOAD = 0 TA = 0°C to +85°C-40
+4
mV
Feedback Load Regulation ILOAD = 0 to 3.5A, VCC = VIN = +3.0V to +5.5V,
SKIP = VCC 0.3 %
FB Input Bias Current IFB VFB = 1.01 × VREFIN -50
+50
nA
Dropout VDO VCC = VIN = +3.0V, ILOAD = 3A, FB = AGND 189
330
mV
VCC = VIN = +4.5V, ILOAD = 0.5A 54 90
PMOS Switch On-Resistance
RPMOS
VCC = VIN = +3.0V, ILOAD = 0.5A 63
110
mΩ
VCC = VIN = +4.5V, ILOAD = 0.5A 47 80
NMOS Switch On-Resistance
RNMOS
VCC = VIN = +3.0V, ILOAD = 0.5A 53 90 mΩ
Maximum Output Current
IOU T
(
R M S
)
(Note 2)
3.6
A
Current-Limit Threshold ILIMIT (Note 3) 4.0 4.8
5.5
A
Idle Mode Current Threshold SKIP = AGND
0.21 0.60 1.00
A
Zero-Cross Current Threshold
SKIP = AGND 200 mA
Switching Frequency fSW (Note 2)
1.4
MHz
RTOFF = 30.1kΩ
0.24 0.30 0.37
RTOFF = 110kΩ
0.85 1.00 1.15
Off-Time tOFF VFB ≥ 0.3 × VREFIN
RTOFF = 499kΩ3.8 4.5
5.2
µs
Extended Off-Time VFB < 0.3 × VREFIN 4 × tOFF µs
On-Time tON (Note 2) 0.3 µs
Soft-Start Time (Note 3)
3 × 256
Cycles
Quiescent Supply Current
ICC + IIN
SKIP = AGND, VFB = 1.01 × VREFIN 350
750
µA
Note 1: LX has clamp diodes to PGND and IN. Thermal limits dictate the maximum continuous current through these diodes.
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = VCC = VSHDN = +3.3V, VREFIN = +1.5V, SKIP = AGND, TA= 0°C to +85°C, unless otherwise noted. Typical
values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
UNITS
ICC + IIN
SHDN = AGND; current into VCC and IN;
LX = 0 or +3.3V 0.2 20
IIN SHDN = AGND; current into IN; LX = 0 0.2 20
Shutdown Supply Currents
ILX SHDN = AGND; current into LX; LX = +3.3V 0.1 20
µA
REFERENCE
REF Voltage VREF VCC = VIN = +3.0V to +5.5V
1.985 2.000 2.015
V
REF Load Regulation IREF = -1µA to +50µA 10 mV
REFIN Input Voltage Range
VREFIN
V
C C = V
IN = + 3.0V to + 5.5V , V
C C
> V
RE F IN
+ 1.35V 0.7
2.0
V
REFIN Input Bias Current
IREFIN
VREFIN = 1.5V, VFB = 1.01 × VREFIN -50
+50
nA
FAULT DETECTION
Thermal Shutdown
TSHDN
Rising, hysteresis = 15°C 165 °C
VCC and VIN rising, hysteresis 60mV typical 2.4 2.6
2.8
VCC - VREFIN, VCC rising, hysteresis 60mV typical
0.9
1.35
Undervoltage Lockout
Threshold
VCC - VFB, VCC rising, hysteresis 60mV typical 0.9
1.35
V
PGOOD Lower Trip Threshold
No load, falling edge, hysteresis = 1% (Note 4)
-12.5
-10
-8.0
%
PGOOD Upper Trip Threshold
No load, rising edge, hysteresis = 1% (Note 4)
+8.0 +10 +12.5
%
PGOOD Propagation Delay
tPGOOD
FB forced 2% beyond PGOOD trip threshold 5 µs
PGOOD Output Low Voltage ISINK = 1mA
0.1
V
PGOOD Leakage Current High-impedance state, forced to +5.5V 1 µA
FBLANK = VCC
112
150
188
FBLANK = open or AGND 75 100
125
Fault Blanking Time
tFBLANK
FBLANK = REF 37 50 63
µs
INPUTS AND OUTPUTS
SHDN, SKIP, GATE, VIN = VCC = +3.3V,
rising edge, hysteresis = 100mV 0.9 1.3
1.6
Logic Input Threshold
V SHDN,
V SKIP,
VGATE
SHDN, SKIP, GATE, VIN = VCC = +5.0V,
rising edge, hysteresis = 100mV
1.15 1.55 1.95
V
Logic Input Current SHDN, SKIP, GATE
-0.5 +0.5
µA
FBLANK = VCC VCC - 0.2
FBLANK = REF 1.8
2.2
FBLANK = open 0.8
1.2
FBLANK Logic Thresholds
VFBLANK
FBLANK = AGND
0.2
V
FBLANK Input Current
IFBLANK
FBLANK forced to AGND or VCC -5
+5
µA
OD On-Resistance ROD GATE = VCC 10 25 Ω
OD Leakage Current GATE = AGND, VOD = +5.5V -50
+50
nA
OD On-Resistance R OD GATE = AGND 10 25 Ω
OD Leakage Current GATE = VCC, V OD = +5.5V -50
+50
nA
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = VCC = VSHDN = +3.3V, VREFIN = +1.5V, SKIP = AGND, TA= -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
Input Voltage
VIN, VCC
3.0
5.5
V
Feedback Voltage Accuracy VFB -
VREFIN
VCC = VIN = +3.0V to +5.5V, ILOAD = 0 -4
+4
mV
FB Input Bias Current IFB VFB = 1.01 × VREFIN -50
+50
nA
Dropout VDO VCC = VIN = +3.0V, ILOAD = 3A, FB = AGND
330
mV
VCC = VIN = +4.5V, ILOAD = 0.5A 90
PMOS Switch On-Resistance
RPMOS
VCC = VIN = +3.0V, ILOAD = 0.5A
110
mΩ
VCC = VIN = +4.5V, ILOAD = 0.5A 80
NMOS Switch On-Resistance
RNMOS
VCC = VIN = +3.0V, ILOAD = 0.5A 90 mΩ
Maximum Output Current
IOU T
(
R M S
)
(Note 2)
3.6
A
Current-Limit Threshold ILIMIT (Note 3) 4.0
5.7
A
Idle Mode Current Threshold SKIP = AGND
0.21 1.00
A
Switching Frequency fSW (Note 2)
1.4
MHz
RTOFF = 30.1kΩ
0.24 0.37
RTOFF = 110kΩ
0.85 1.15
Off-Time tOFF VFB ≥ 0.3 × VREFIN
RTOFF = 499kΩ3.8
5.2
µs
On-Time tON (Note 2) 0.3 µs
Quiescent Supply Current
ICC + IIN
SKIP = AGND, VFB = 1.01 × VREFIN
750
µA
ICC + IIN
SHDN = AGND; current into VCC and IN;
LX = 0 or +3.3V 20
IIN SHDN = AGND; current into IN; LX = 0 20
Shutdown Supply Currents
ILX SHDN = AGND; current into LX; LX = +3.3V 20
µA
REFERENCE
REF Voltage VREF VCC = VIN = +3.0V to +5.5V
1.98 2.02
V
REFIN Input Voltage Range
VREFIN
VCC = VIN = +3.0V to +5.5V,
VCC > VREFIN + 1.35V 0.7
2.0
V
FAULT DETECTION
PGOOD Lower Trip Threshold
No load, falling edge, hysteresis = 1% (Note 4)
-12.5
-8 %
PGOOD Upper Trip Threshold
No load, rising edge, hysteresis = 1% (Note 4) +8
+12.5
%
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
_______________________________________________________________________________________ 5
Note 2: Guaranteed by design and not production tested.
Note 3: To limit input surge currents, the current-limit threshold is set to 25% of its final value (25% x 4.8A = 1.2A) when the
MAX1536 is enabled or powered up. The current-limit threshold is increased by 25% every 256 LX cycles. The current-limit
threshold is at its final level of 4.8A after 768 LX cycles. See the Internal Soft-Start Circuit section.
Note 4: The upper and lower PGOOD thresholds are expressed as a ratio of VFB with respect to VREFIN.
Note 5: Specifications to -40°C are guaranteed by design and are not production tested.
VV
Vx
FB REFIN
REFIN
-100%
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = VCC = VSHDN = +3.3V, VREFIN = +1.5V, SKIP = AGND, TA= -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUTS AND OUTPUTS
SHDN, SKIP, GATE, VIN = VCC = +3.3V,
rising edge, hysteresis = 100mV 0.9
1.6
Logic Input Threshold
V S HDN,
V S KIP,
V GATE
SHDN, SKIP, GATE, VIN = VCC = +5.0V,
rising edge, hysteresis = 100mV
1.15 1.95
V
FBLANK = VCC VCC - 0.2
FBLANK = REF 1.8
2.2
FBLANK = open 0.8
1.2
FBLANK Logic Thresholds
VFBLANK
FBLANK = AGND
0.2
V
OD On-Resistance ROD GATE = VCC 25 Ω
OD On-Resistance R O DGATE = AGND 25 Ω
100
0
0.001 0.01 0.1 1 10
EFFICIENCY vs. OUTPUT CURRENT
(VIN = 5V, L = 1.5µH)
20
MAX1536 toc01
OUTPUT CURRENT (A)
EFFICIENCY (%)
40
60
80
70
50
30
10
90
VOUT = 0.7V
RTOFF = 200kΩ
VOUT = 1.8V
RTOFF = 93.1kΩ
VOUT = 2.5V
RTOFF = 54.9kΩ
PWM MODE
IDLE MODE
1.806
1.794
0.001 0.1 10.01 10
OUTPUT VOLTAGE vs. OUTPUT CURRENT
(VIN = 5V, L = 1.5µH)
MAX1536 toc02
OUTPUT CURRENT (A)
OUTPUT VOLTAGE (V)
1.796
1.798
1.800
1.802
1.804
RTOFF = 93.1kΩ
PWM MODE IDLE MODE
100
0
0.001 0.01 0.1 1 10
EFFICIENCY vs. OUTPUT CURRENT
(VIN = 3.3V, L = 1.2µH)
20
MAX1536 toc03
OUTPUT CURRENT (A)
EFFICIENCY (%)
40
60
80
70
50
30
10
90
VOUT = 0.7V
RTOFF = 165kΩ
VOUT = 1.8V
RTOFF = 75kΩ
VOUT = 2.5V
RTOFF = 42.2kΩ
PWM MODE
IDLE MODE
Typical Operating Characteristics
(MAX1536 Circuit of Figure 1, TA = +25°C, unless otherwise noted.)
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
6 _______________________________________________________________________________________
1.806
1.794
0.001 0.1 10.01 10
OUTPUT VOLTAGE vs. OUTPUT CURRENT
(VIN = 3.3V, L = 1.2µH)
MAX1536 toc04
OUTPUT CURRENT (A)
OUTPUT VOLTAGE (V)
1.796
1.798
1.800
1.802
1.804
RTOFF = 75kΩ
PWM MODE IDLE MODE
100
0
0.001 0.01 0.1 1 10
EFFICIENCY vs. OUTPUT CURRENT
(VOUT = 1.8V, fSW = 300kHz)
20
MAX1536 toc05
OUTPUT CURRENT (A)
EFFICIENCY (%)
40
60
80
70
50
30
10
90
VIN = 5V
L = 3.3µH
RTOFF = 221kΩ
VIN = 3.3V
L = 2.2µH
RTOFF = 147kΩ
PWM MODE
IDLE MODE
100
0
0.001 0.01 0.1 1 10
EFFICIENCY vs. OUTPUT CURRENT
(VIN = 3.3V, VOUT = 1.8V)
20
MAX1536 toc06
OUTPUT CURRENT (A)
EFFICIENCY (%)
40
60
80
70
50
30
10
90
L = 3.3µH
RTOFF = 178kΩ
fSW ≈ 250kHz
L = 1.5µH
RTOFF = 85kΩ
fSW ≈ 500kHz
PWM MODE
IDLE MODE
L = 0.8µH
RTOFF = 41.2kΩ
fSW ≈ 1000kHz
SWITCHING FREQUENCY vs. OUTPUT CURRENT
MAX1536 toc07
OUTPUT CURRENT (A)
fSW (kHz)
4321
100
200
300
400
500
600
700
800
900
1000
0
05
PWM MODE
IDLE MODE
VIN = 5.0V
VIN = 3.3V
VOUT = 1.8V
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (PWM MODE)
MAX1536 toc08
INPUT VOLTAGE (V)
IIN (mA)
ICC (mA)
4.54.03.5
5
10
15
20
25
0
0.2
0.4
0.6
0.8
1.0
0
3.0 5.0
VOUT = 1.8V
IIN
ICC
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (IDLE MODE)
MAX1536 toc09
INPUT VOLTAGE (V)
IIN (µA)
ICC (µA)
4.54.03.5
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
1.05
0.95
305
310
315
320
325
330
335
340
345
350
300
3.0 5.0
VOUT = 1.8V
IIN
ICC
Typical Operating Characteristics (continued)
(MAX1536 Circuit of Figure 1, TA = +25°C, unless otherwise noted.)
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(MAX1536 Circuit of Figure 1, TA = +25°C, unless otherwise noted.)
STARTUP AND SHUTDOWN
(HEAVY LOAD)
MAX1536 toc10
400µs/div
VSHDN
5V/div
VPGOOD
5V/div
ILX
2A/div
VOUT
1V/div
VIN = 3.3V, VOUT = 1.8V, RLOAD = 0.5Ω
STARTUP AND SHUTDOWN
(LIGHT LOAD)
MAX1536 toc11
400µs/div
VSHDN
5V/div
VPGOOD
5V/div
ILX
1A/div
VOUT
1V/div
VIN = 3.3V, VOUT = 1.8V, RLOAD = 3Ω
LOAD-TRANSIENT RESPONSE
(PWM MODE)
MAX1536 toc12
20µs/div
IOUT
2A/div
ILX
2A/div
VOUT
50mV/div
VLX
5V/div
VIN = 3.3V, VOUT = 1.8V, IOUT = 0.1A TO 3A TO 0.1A
LOAD-TRANSIENT RESPONSE
(IDLE MODE)
MAX1536 toc13
20µs/div
IOUT
2A/div
ILX
2A/div
VOUT
50mV/div
VLX
5V/div
VIN = 3.3V, VOUT = 1.8V, IOUT = 0.1A TO 3A TO 0.1A
DYNAMIC OUTPUT-VOLTAGE TRANSITION
(IDLE MODE)
MAX1536 toc14
20µs/div
VGATE
5V/div
VLX
5V/div
VOUT
200mV/div
VREFIN
200mV/div
ILX
5A/div
0
VIN = 3.3V, VOUT = 1.5V TO 1.8V TO 1.5V,
FBLANK = REF, ILOAD = 0.1A
REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1536 toc15
TEMPERATURE (°C)
VREF (V)
603510-15
1.997
1.998
1.999
2.000
2.001
2.002
1.996
-40 85
VIN = 3.3V IREF = 0
IREF = 50µA
IREF = 25µA
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
8 _______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1, 21,
24, 26
LX Inductor Connection. Connection for the drains of the PMOS power switch and NMOS synchronous-rectifier
switch. Connect all LX pins together.
2, 3,
19, 20
IN Power Input. Power input for the internal PMOS switch. Connect all IN pins together.
4
SHDN
Shutdown Control Input. Drive SHDN low to disable the reference, control circuitry, and internal MOSFETs.
Drive SHDN high or connect to VCC for normal operation.
5
SKIP
Pulse-Skipping Control Input. Connect SKIP to VCC for low-noise, forced-PWM mode. Connect SKIP to AGND
for high-efficiency Idle Mode.
6 FB Feedback Input. The voltage at REFIN sets the feedback regulation voltage (VFB = VREFIN).
7
COMP
Integrator Compensation. Connect a 470pF capacitor from COMP to VCC for integrator compensation.
See the Integrator Amplifier section.
8, 25
N.C. No Connection. Not internally connected. Connecting pin 25 to LX eases PC board layout.
9
TOFF
Off-Time Select Input. Sets the PMOS power switch off-time during constant off-time operation. Connect a
resistor from TOFF to AGND to adjust the PMOS switch off-time. See the Programming the No-Load Switching
Frequency and Off-Time section.
10
GATE
Buffered OD and OD Control Input. A logic low on GATE forces OD low and OD high impedance. A logic high
on GATE forces OD high impedance and OD low.
11 OD Open-Drain Output. A logic low on GATE forces OD high impedance. A logic high on GATE forces OD low.
12 OD Inverted Open-Drain Output. A logic low on GATE forces OD low. A logic high on GATE forces OD high
impedance.
13
REFIN
External Reference Input. The voltage at REFIN sets the feedback regulation voltage (VFB = VREFIN).
14 REF +2.0V Reference Voltage Output. Bypass REF to AGND with a minimum capacitance of 0.22µF. REF supplies
up to 50µA for external loads. The internal reference turns off in shutdown.
15
AGND
Analog Ground. Connect backside pad to AGND.
16 VCC Analog Power Input. Power input to the internal analog circuitry. Bypass VCC with a 10Ω and 2.2µF (min)
lowpass filter (Figure 1).
17
FBLANK
Fault-Blanking Control Input. FBLANK is a four-level logic input that enables or disables fault blanking, and sets
the minimum forced-PWM operation time (tFBLANK). Enabling fault blanking forces PGOOD high for the selected
time period after a transition is detected on GATE. Additionally, the controller enters forced-PWM mode for the
duration of tFBLANK anytime GATE changes states. Connect FBLANK to the following pins to select tFBLANK and
fault blanking:
VCC = 150µs (typ), fault blanking enabled
Open = 100µs (typ), fault blanking enabled
REF = 50µs (typ), fault blanking enabled
AGND = 100µs (typ), fault blanking disabled
18
PGOOD
Open-Drain Power-Good Output. PGOOD is low during soft-start, in shutdown, and when the output voltage is
more than 10% (typ) above or below the normal regulation point. After the soft-start, PGOOD becomes high
impedance if the output is in regulation. PGOOD is blanked—forced into a high-impedance state—when
FBLANK is enabled and a transition is detected on GATE.
22, 23,
27, 28
PGND
Power Ground. Internally connected to the source of the internal NMOS synchronous-rectifier switch.
Connect all PGND pins together.
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
_______________________________________________________________________________________ 9
Standard Application Circuit
The MAX1536 standard application circuit (Figure 1)
generates a dynamically adjustable output voltage typical
of graphic processor core requirements. See Table 1
for component selections. Table 2 lists the component
manufacturers.
Detailed Description
The MAX1536 synchronous, current-mode, constant-
off-time, PWM DC-to-DC converter steps down an input
voltage (VIN) from +3.0V to +5.5V to an output voltage
from +0.7V to VIN. The MAX1536 output delivers up to
3.6A of continuous current. An internal 54mΩPMOS
power switch and an internal 47mΩNMOS synchro-
nous rectifier switch improve efficiency, reduce compo-
nent count, and eliminate the need for an external
Schottky diode (Figure 2).
Modes of Operation
The MAX1536 has two modes of operation: constant-
off-time PWM mode, and pulse-skipping Idle Mode.
The logic level on the SKIP input and the current
through the PMOS switch determine the MAX1536
mode of operation.
Forced-PWM mode keeps the switching frequency rel-
atively constant and is desirable in applications that
must always keep the frequency of conducted and
radiated emissions in a narrow band. Visit Maxim’s
website at www.maxim-ic.com for more information on
how to control electromagnetic interference (EMI).
Pulse-skipping Idle Mode has a dynamic switching fre-
quency under light loads and is desirable in applica-
tions that require high efficiency at light loads.
Forced-PWM Mode (
SKIP
= VCC)
Connect SKIP to VCC to force the MAX1536 to operate
in low-noise, constant-off-time PWM mode. Constant-
off-time PWM architecture provides a relatively con-
stant switching frequency (see the Frequency Variation
with Output Current section). A single resistor (RTOFF)
sets the PMOS power switch off-time that results in a
switching frequency up to 1.4MHz optimizing perfor-
mance trade-offs in efficiency, switching noise, compo-
nent size, and cost.
PWM mode regulates the output voltage by increasing
the PMOS switch on-time to increase the amount of energy
transferred to the load per cycle. At the end of each off-
time, the PMOS switch turns on and remains on until the
output is in regulation or the current through the switch
increases to the 4.8A current limit. When the PMOS
switch turns off, it remains off for the programmed off-
time (tOFF), and the NMOS synchronous switch turns on.
The NMOS switch remains on until the end of tOFF. Since
either the NMOS or the PMOS switch is always on in
PWM mode, the inductor current is continuous.
Idle Mode (
SKIP
= AGND)
Connect SKIP to AGND to allow the MAX1536 to auto-
matically switch between high-efficiency Idle Mode
under light loads and PWM mode under heavy loads.
The transition from PWM mode to Idle Mode occurs
when the load current is half the Idle Mode current
threshold (600mA typ).
In Idle Mode operation, the switching frequency is
reduced to increase efficiency. The inductor current is
discontinuous in this mode and the MAX1536 only initi-
ates an LX switching cycle when VFB < VREFIN. When
VFB falls below VREFIN, the PMOS switch turns on and
remains on until output is in regulation and the current
through the switch increases to the Idle Mode current
threshold (600mA typ). When the PMOS switch turns
off, the NMOS synchronous switch turns on and remains
on until the current through the switch decreases to the
zero-cross-current threshold of 200mA.
100% Duty-Cycle Operation
When the input voltage drops near the output voltage,
the LX duty cycle increases until the PMOS switch is on
continuously. The dropout voltage in 100% duty cycle
is the output current multiplied by the on-resistance of
the internal PMOS switch and parasitic resistance in
the inductor. The PMOS switch remains on continuously
as long as the current limit is not reached.
Internal Soft-Start Circuit
Soft-start allows a gradual increase of the current-limit
level at startup to reduce input surge currents. When
the MAX1536 is enabled or powered up, its current-
limit threshold is set to 25% of its final value (25% of
4.8A = 1.2A). The current-limit threshold is increased
by 25% every 256 LX cycles. The current-limit thresh-
old reaches its final level of 4.8A after 768 LX cycles or
when the output voltage is in regulation, whichever
occurs first. Additionally, when VFB < 0.3 ×VREFIN, the
PMOS switch remains off for the extended off-time of 4 ×
tOFF. As a result of this soft-start feature, the main output
capacitor charges up relatively slowly. The exact time of
the output rise depends on the nominal switching fre-
quency, output capacitance, and the load current. See
the startup waveforms in the Typical Operating
Characteristics.
Short-Circuit/Overload Protection
The MAX1536 can sustain a constant short circuit or
overload. Under a short-circuit or overload condition,
when VFB < 0.3 ×VREFIN, the MAX1536 uses an
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
10 ______________________________________________________________________________________
LX
FB
PGND
AGND
REF
REFIN
OD
OD
GATE
IN
FBLANK
VCC
SKIP
TOFF
PGOOD
SHDN
COMP
MAX1536
OFF
IDLE MODE
RTOFF
75kΩ
POWER GOOD
PWM MODE
100kΩ
10Ω
2.2µF
CIN
2 X 10µF
+6.3V X5R
CCOMP
470pF
VIN
+3.0V TO +5.5V
VFB(HIGH)
ON
VFB(LOW)
R1
R2
R3
RA
RB
CREF
0.22µF
CREFIN
470pF
L1
1.2µH, SUMIDA
CDR7D28MN-1R2
COUT
100µF, +6.3V
POSCAP
VOUT
+0.7V TO VIN
VOUT = VFB
(
1 + RA
)
RB
VFB(HIGH) = VREF
(
R2 + R3
)
R1 + R2 + R3
VFB(LOW) = VREF
(
R2
)
R1 + R2
Table 1. Recommended Component Values (IOUT = 3.6A)
VIN (V)
VOUT (V)
FULL-LOAD SWITCHING
FREQUENCY
fPWM (kHz)
L (µH)
R
TOF F ( k Ω)
R1 (kΩ)
R2 (kΩ)
R3 (kΩ)
RA (kΩ)
RB (kΩ)
5 3.3* 1020 1.2 30.1 Short Open Open 6.49 10
5 2.5* 1020 1.2 47.5 Short Open Open 2.49 10
5
1.8/1.5**
820/900 1.2 78.7 20 60.4 121 Short Open
5 0.7* 450 1.2 200 130 69.8 Short Short Open
3.3 2.5* 640 1.0 30.1 Short Open Open 2.49 10
3.3
1.8/1.5**
840/1030 1.0 49.9 20 60.4 121 Short Open
3.3 0.7* 660 1.0 121 130 69.8 Short Short Open
*In single-output voltage applications, OD,
OD
, and GATE are general-purpose gates. If OD and
OD
are not used, connect GATE to
AGND and leave OD and
OD
open.
**The output voltage changes between two set points depending on VGATE. See the Setting Dynamic Output Voltages with REFIN section.
Figure 1. MAX1536 Standard Application Circuit
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
______________________________________________________________________________________ 11
extended off-time to control the current. Operation dur-
ing a short-circuit or overload is similar to forced-PWM
mode except the off-time is 4 ×tOFF. At the end of each
off-time, the PMOS switch turns on and remains on until
the output is in regulation or the current through the
switch increases to the 4.8A current limit. When the
PMOS switch turns off, it remains off for four times the
programmed off-time (tOFF), and the NMOS synchro-
nous switch turns on. Since either the NMOS or the
PMOS switch is always on, the inductor current is con-
tinuous. The RMS inductor current during a short circuit
remains below the 4.8A current-limit threshold. The
MAX1536 operates using the extended off-time until the
short-circuit or overload is removed and VFB > 0.3 ×
VREFIN. Prolonged short circuit or overload can result in
thermal shutdown.
Table 2. Component Manufacturers
SUPPLIER COMPONENT PHONE WEBSITE
Coilcraft Inductors 800-322-2645 (USA) www.coilcraft.com
Coiltronics Inductors 561-752-5000 (USA) www.coiltronics.com
Kemet Capacitors 408-986-0424 (USA) www.kemet.com
Sanyo Capacitors 818-998-7322 (USA) www.sanyo.com
Sumida Inductors 408-982-9660 (USA) www.sumida.com
Taiyo Yuden Capacitors 03-3667-3408 (Japan),
408-573-4150 (USA) www.t-yuden.com
TDK Capacitors 847-803-6100 (USA),
81-3-5201-7241 (Japan) www.component.tdk.com
TOKO Inductors 858-675-8013 (USA) www.toko.com
Figure 2. MAX1536 Functional Diagram
PGOOD
COMPARATOR
Gm
MAX1536
FBLANK
DECODE AND
TIMER
2.0V
REF
TIMER
CURRENT
SENSE
PWM LOGIC
AND
DRIVERS
CURRENT
SENSE PGND
LX L
COUT
VOUT
+0.7V TO VIN
IN
CIN
VIN
VIN
+3.0V TO +5.5V
*FB
SHDN VCC
VCC
COMPPGOOD
REF
REFIN
OD
OD
GATE
FBLANK REF AGND TOFF SKIP
FB
SUMMING
COMPARATOR
*FOR VOUT > 2.0V, USE AN FB RESISTIVE DIVIDER
*FROM VOUT TO AGND.
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
12 ______________________________________________________________________________________
NONSYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
VIN
VOUT
CIN
COUT
L
SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
VIN
VOUT
CIN
COUT
L
SYNCHRONOUS
RECTIFIER
Figure 3. Step-Down Switching Regulator
Shutdown (
SHDN
)
Drive SHDN low to disable the MAX1536 and reduce
the supply current to less than 1µA. In shutdown, all cir-
cuitry and internal MOSFETs turn off, and the LX node
becomes high impedance. Drive SHDN high or con-
nect to VCC for normal operation.
Summing Comparator
Three signals are added together at the input of the
summing comparator (Figure 2): an output-voltage
error signal relative to the reference voltage, an inte-
grated output-voltage error signal, and the sensed
PMOS switch current. The transconductance amplifier
with an external capacitor between COMP and VCC
provides an integrated error signal. This integrator pro-
vides high DC accuracy without the need for a high-
gain amplifier (see the Integrator Amplifier section).
Power-Good Output (PGOOD)
PGOOD is an open-drain output that indicates if the
output voltage is in regulation. PGOOD is actively held
low in shutdown and during soft-start. After the soft-
start terminates, PGOOD becomes high impedance as
long as the output voltage is within ±10% of the nominal
regulation voltage.
Once the MAX1536 has started, PGOOD pulls low when
the output voltage drops 10% below or rises 10% above
the nominal regulation voltage. PGOOD returns to high
impedance when the output voltage regains regulation.
For logic-level output voltages, connect a 100kΩexternal
pullup resistor between PGOOD and VCC.
PGOOD is forced high impedance during the transition
period selected by FBLANK (see the Fault Blanking
section).
Fault Blanking (FBLANK)
The MAX1536 automatically enters forced-PWM opera-
tion for a predefined period following any GATE transi-
tion. The FBLANK control input determines how long the
MAX1536 maintains forced-PWM operation (Table 3).
When fault blanking is enabled (FBLANK = VCC, open,
or REF), the MAX1536 forces PGOOD to a high-imped-
ance state during the transition period selected by
FBLANK (Table 3). This prevents the PGOOD signal
from going low when the output-voltage change
(∆VOUT) cannot occur as fast as the change in REFIN
voltage (∆VREFIN).
Synchronous Rectification
In a nonsynchronous step-down regulator, an external
Schottky diode provides a path for current to flow when
the inductor is discharging. The MAX1536 synchronous
rectifier replaces the external Schottky diode with an
internal low-resistance NMOS switch reducing conduc-
tion losses and improving efficiency (Figure 3). There is
typically 40ns of delay between MOSFET transitions,
thus preventing cross conduction or “shoot through.”
FBLANK
FAULT BLANKING
TYPICAL FORCED-PWM
DURATION (µs)
VCC Enabled 150
Open Enabled 100
REF Enabled 50
AGND
Disabled 100
Table 3. FBLANK Configuration Table
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
______________________________________________________________________________________ 13
Thermal Shutdown
The MAX1536 features a thermal fault-protection circuit.
When the junction temperature rises above +165°C, a
thermal sensor shuts down the MAX1536 regardless of
VSHDN. The MAX1536 is reactivated after the junction
temperature cools to +150°C.
Thermal Resistance
Junction-to-ambient thermal resistance, θJA, is highly
dependent on the amount of copper area connected to
the exposed backside pad. Airflow over the board sig-
nificantly reduces θJA. For heat-sinking purposes, even-
ly distribute the copper area connected at the IC among
the high-current pins. Refer to the Maxim website
(www.maxim-ic.com) for QFN thermal considerations.
Power Dissipation
Power dissipation in the MAX1536 is dominated by
conduction losses in the two internal power switches.
Power dissipation due to supply current in the control
section and average current used to charge and dis-
charge the gate capacitance of the internal switches
(i.e., switching losses—PSL) is approximately:
PSL = C x VIN2x fSW
where:
C = 5nF.
fSW = switching frequency.
The combined conduction losses (PCL) in the two
power switches are approximated by:
PCL = IOUT2x RPMOS
where:
IOUT = load current.
RPMOS = PMOS switch on-resistance.
The junction-to-ambient thermal resistance required to
dissipate this amount of power is calculated by:
where:
θJA = junction-to-ambient thermal resistance.
TJ(MAX) = maximum junction temperature = +150°C.
TA(MAX) = maximum ambient temperature.
Design Procedure
For typical applications, use the recommended compo-
nent values in Table 1. For other applications, take the
following steps:
1) Select the desired PWM-mode switching frequency.
See Figure 4 for maximum operating frequency.
2) Select the constant off-time as a function of input
voltage, output voltage, and switching frequency.
3) Select RTOFF as a function of off-time.
4) Select the inductor as a function of output voltage,
off-time, and peak-to-peak inductor current.
Setting the Output Voltage
Setting VOUT with a Resistive Voltage-Divider at FB
The MAX1536 output voltage (VOUT) is set using FB
and REFIN (Figure 5). The MAX1536 regulates VFB to
be equal to VREFIN. Connect FB to a resistive voltage-
divider between VOUT and AGND to adjust VOUT from
+0.7V to VIN. Select an RBfrom 10kΩto 100kΩ, then
calculate RAbased on the desired VOUT:
θJA J MAX A MAX
SL CL
TT
PP
≤+
() ()
-
MAX1536
LX
PGND
FB
AGND
REF
REFIN
RB
10kΩ
RA
2.49kΩ
VOUT = VFB
(
1 + RA
)
RB
VREF = +2.0V
CREF
0.22µF
VOUT = +2.5V
VFB = VREFIN
Figure 5. Setting VOUT with a Resistive Voltage-Divider at FB
VIN (V)
FREQUENCY (kHz)
5.04.54.03.5
200
400
600
800
1000
1200
1400
1600
1800
0
3.0 5.5
VOUT = 1.5V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 1.0V
NO LOAD
Figure 4. Maximum Recommended Operating Frequency vs.
Input Voltage
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
14 ______________________________________________________________________________________
where VFB = VREFIN.
Setting Dynamic Output Voltages with REFIN
The MAX1536 regulates VFB to be equal to VREFIN.
Changing VREFIN allows for a dynamic output voltage
that changes between two set points (see the
Multioutput Voltage Settings section for information on
three or more output-voltage set points). Figure 1 shows
a dynamically adjustable resistive voltage-divider net-
work at REFIN. Keep VREFIN between 0.7V and 2V.
Keep VREFIN below VCC - 1.35V to avoid an undervolt-
age lockout condition. Toggling GATE switches in and
out the resistor connected between OD and AGND
changing VREFIN. A logic high on GATE turns on the
internal N-channel MOSFET, forcing OD to a low-imped-
ance state. A low logic on GATE turns off the internal N-
channel MOSFET, making OD high impedance. The
output voltage is determined by the following equations:
The MAX1536 automatically enters forced-PWM opera-
tion on the rising and falling edges of GATE, and
remains in forced-PWM mode for a minimum time
selected by FBLANK (Table 3). Forced-PWM operation
is required to ensure fast, accurate negative voltage
transitions when REFIN is lowered. Since forced-PWM
operation disables the zero-crossing comparator, the
inductor current can reverse under light loads, quickly
discharging the output capacitors. The MAX1536 also
forces PGOOD to a high-impedance state for the peri-
od selected by FBLANK (Table 3).
For a step-voltage change at REFIN, the rate of change
of the output voltage is limited by the inductor current
ramp, the total output capacitance, the current limit,
and the load during the transition. The voltage across
the inductor and the inductance limits the inductor cur-
rent ramp. The total output capacitance determines
how much current is needed to change the output volt-
age. Additional load current slows down the output volt-
age change during a positive REFIN voltage change,
and speeds up the output voltage change during a
negative REFIN voltage change.
Adding a capacitor across REFIN and AGND filters
noise and controls the rate of change of the REFIN volt-
age during dynamic transitions. With the additional
capacitance, the REFIN voltage slews between the two
set points with a time constant given by the equivalent
parallel resistance seen by the slew capacitor CREFIN.
As shown in Figure 1, the time constant for a positive
REFIN voltage transition is:
and the time constant for a negative REFIN voltage
transition is:
During a negative REFIN voltage transition, the MAX1536
sinks current to discharge the output capacitor and bring
the output voltage down to the new set point. The
MAX1536 does not have a negative current limit, so
τNEG must be set long enough to keep the sinking cur-
rent within the maximum current capability of the IC:
Programming the No-Load Switching
Frequency and Off-Time
The MAX1536 features a programmable PWM mode
switching frequency, which is set by the input and out-
put voltage and the value of RTOFF. RTOFF sets the
PMOS power switch off-time in PWM mode. Use the fol-
lowing equation to select the off-time according to the
desired no-load switching frequency in PWM mode:
where:
tOFF = the programmed off-time.
VIN = the input voltage.
VOUT = the output voltage.
fPWM = no-load switching frequency, PWM mode.
Select RTOFF according to the formula:
tVV
fxV
OFF IN OUT
PWM IN
=-
τNEG OUT OUT
SINK
SINK LIMIT
CxV
Iand I I≥≤
∆
τNEG REFIN
RxR
RRC=+
12
12
τPOS REFIN
RxR R
RR R C=+
()
++
123
12 3
VV R
R
VV
R
RR
VV
RR
RR R
OUT FB A
B
FB LOW REF
FB HIGH REF
=+
=+
=+
++
1
2
12
23
12 3
()
()
RR
V
V
AB
OUT
FB
=
-1
14 ______________________________________________________________________________________
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
______________________________________________________________________________________ 15
VTOFF is typically 1.1V and the recommended values
for RTOFF range from 30.1kΩto 499kΩfor off-times of
0.3µs to 4.5µs.
Frequency Variation with Output Current
The operating frequency of the MAX1536 in PWM mode
is determined primarily by tOFF (set by RTOFF), VIN, and
VOUT as shown in the following formula:
where:
VPMOS = the voltage drop across the internal PMOS
power switch, IOUT ×RPMOS.
VNMOS = the voltage drop across the internal NMOS
synchronous-rectifier switch, IOUT ×RNMOS.
As the output current increases, VNMOS and VPMOS
increase and the voltage across the inductor decreas-
es. This causes the frequency to drop. Approximate the
change in frequency with the following formula:
where RPMOS is the resistance of the internal MOSFETs
(54mΩ, typ).
Inductor Selection
The key inductor parameters must be specified: induc-
tor value (L) and peak current (IPEAK). The following
equation includes a constant, denoted as LIR, which is
the ratio of peak-to-peak inductor AC ripple current to
maximum DC load current. A higher value of LIR allows
smaller inductance but results in higher losses and rip-
ple. A good compromise between size and losses is
found at approximately a 25% ripple-current to load-
current ratio (LIR = 0.25), which corresponds to a peak-
inductor current 1.125 times the DC load current:
where:
IOUT = maximum DC load current.
LIR = ratio of peak-to-peak AC inductor current to DC
load current, typically 0.25.
The peak-inductor current at full load is 1.125 ×IOUT if
the above equation is used; otherwise, the peak current
is calculated by:
Choose an inductor with a saturation current at least as
high as the peak-inductor current. The inductor select-
ed should exhibit low losses at the chosen operating
frequency.
Capacitor Selection
The input-filter capacitor reduces peak currents and
noise at the voltage source. Use a low-ESR and low-
ESL capacitor located no further than 5mm from IN.
Select the input capacitor according to the RMS input
ripple-current requirements and voltage rating:
where IRIPPLE = input RMS current ripple.
The output-filter capacitor affects the output-voltage
ripple, output load-transient response, and feedback-
loop stability. For stable operation, the MAX1536
requires a minimum output ripple voltage of VRIPPLE ≥
1% ×VOUT.
The minimum ESR of the output capacitor is calculated by:
Stable operation requires the correct output-filter capaci-
tor. When choosing the output capacitor, ensure that:
Integrator Amplifier
An internal transconductance amplifier fine tunes the
output DC accuracy. A capacitor, CCOMP, from COMP
to VCC compensates the transconductance amplifier.
For stability, choose CCOMP = 470pF. A larger capaci-
tor value maintains a constant average output voltage,
but slows the loop response to changes in output volt-
age. A smaller capacitor value speeds up the loop
response to changes in output voltage but decreases
stability.
Ct
VxFx V
s
OUT OFF
OUT
≥µ
µ
79 1
1
ESR x L
tOFF
>1%
II
VVV
V
RIPPLE LOAD
OUT IN OUT
IN
=()-
II
Vxt
xL
PEAK OUT OUT OFF
=+
2
LVxt
I x LIR
OUT OFF
OUT
=
∆fIxR
Vxt
PWM OUT PMOS
IN OFF
=-
fVV V
tVV V
PWM IN OUT PMOS
OFF IN PMOS NMOS
=+
--
-()
Rt s
k
s
TOFF OFF
=−µ Ω
µ
(.)
.
007 110
100
Applications Information
Multioutput Voltage Settings
The MAX1536 is optimized to work in applications that
require two dynamic output voltages; however, discrete
logic or a DAC connected to REFIN allows three or
more dynamic output voltages.
Figure 6 shows an application circuit providing four
voltage levels using discrete logic. Switching resistors
in and out of the resistor network changes the voltage
at REFIN. An edge-detection circuit is added to trigger
a 1µs pulse on GATE to start the fault-blanking and
forced-PWM operation. GATE requires a minimum
pulse width of 500ns. The edge-detection circuit is not
required if the MAX1536 is always in PWM mode (SKIP
= VCC) and fault blanking is not necessary.
Active Bus Termination
Active bus termination power supplies generate a volt-
age rail that tracks a set reference. Active bus termina-
tion power supplies are unique because they source
and sink current. DDR memory architecture requires
active bus termination. In DDR memory architecture,
the termination voltage is set at exactly half the memory
supply voltage. Configure the MAX1536 to generate the
termination voltage using a resistor-divider at REFIN.
Force the MAX1536 to operate in PWM mode (SKIP =
VCC) to source and sink current. Figure 7 shows the
MAX1536 configured as a DDR termination regulator.
Connect GATE and FBLANK to AGND when unused.
Circuit Layout and Grounding
Good layout is necessary to achieve the intended out-
put power level, high efficiency, and low noise. Good
layout includes the use of a ground plane, careful com-
ponent placement, and correct routing of traces using
appropriate trace widths. Refer to the MAX1536 EV Kit
for layout reference.
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
16 ______________________________________________________________________________________
Figure 6. Multioutput Voltage Settings
MAX1536
GATE
AGND
REFIN
REF
OD
OD
B
A
1.5kΩ
1.5kΩ
1000pF
1000pF
C1 R2
R3
R4
R1
Figure 8. Source/Sink Waveforms
0
10µs/div
VIN = 3.3V, VOUT = 1.25V, IOUT = -1A TO +1A TO -1A
ILX
2A/div
VLX
5V/div
VOUT
50mV/div
0
Figure 7. Active Bus Termination
MAX1536
REFIN
AGND
OD
GATE
FBLANK
10kΩ
10kΩ
1000pF
1000pF
VDDQ
VCC
IN
FB
LX
PGND
COUT
CIN
VIN
L
OD
SKIP
VDDQ = DDR MEMORY SUPPLY VOLTAGE
VTT = TERMINATION SUPPLY VOLTAGE
VTT = VDDQ
2
The following points are in order of decreasing importance:
1) Minimize switched-current and high-current ground
loops. Connect the input capacitor’s ground, the out-
put capacitor’s ground, and PGND at a single point.
Connect the resulting island to AGND at only
one point.
2) Connect the input filter capacitor less than 5mm
away from IN. The connecting copper trace carries
large currents and must be at least 1mm wide,
preferably 2.5mm.
3) Place the LX node components as close together
and as near to the device as possible. This reduces
noise, resistive losses, and switching losses.
4) A ground plane is essential for optimal performance.
In most applications, the circuit is located on a multi-
layer board, and full use of the four or more layers is
recommended. Use the top and bottom layers for
interconnections and the inner layers for an uninter-
rupted ground plane. Avoid large AC currents
through the ground plane.
Chip Information
TRANSISTOR COUNT: 4305
PROCESS: BiCMOS
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
______________________________________________________________________________________ 17
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
18 ______________________________________________________________________________________
QFN THIN.EPS
D2
(ND-1) X e
e
D
C
PIN # 1
I.D.
(NE-1) X e
E/2
E
0.08 C
0.10 C
A
A1 A3
DETAIL A
0.15 C B
0.15 C A
DOCUMENT CONTROL NO.
21-0140
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
PROPRIETARY INFORMATION
APPROVAL
TITLE:
C
REV.
2
1
E2/2
E2
0.10 M C A B
PIN # 1 I.D.
b
0.35x45
L
D/2 D2/2
L
C
L
C
e e
L
CC
L
k
k
L
L
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MAX1536
3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
2
2
21-0140
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
COMMON DIMENSIONS EXPOSED PAD VARIATIONS
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
NOTES:
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
C
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm