LTC2411/LTC2411-1
1
2411fa
For more information www.linear.com/LTC2411
TYPICAL APPLICATION
FEATURES DESCRIPTION
24-Bit No Latency ∆Σ™ ADC
with Differential Input and
Reference in MSOP
The LT C
®
2411/LTC2411-1 are 2.7V to 5.5V micropower
24-bit differential ∆Σ analog-to-digital converters with
an integrated oscillator, 2ppm INL and 0.29ppm RMS
noise. They use delta-sigma technology and provide single
cycle settling time for multiplexed applications. Through
a single pin, the LTC2411 can be configured for better
than 110dB differential mode rejection at 50Hz or 60Hz
±2%, and the LTC2411-1 can provide better than 87dB
input differential mode rejection over the range of 49Hz
to 61.2Hz, or they can be driven by an external oscillator
for a user-defined rejection frequency. The LTC2411 and
LTC2411-1 are identical when driven by an external oscil-
lator. The internal oscillator requires no external frequency
setting components.
The converters accept any external differential reference
voltage from 0.1V to VCC for flexible ratiometric and re-
mote sensing measurement configurations. The full-scale
differential input range is from –0.5VREF to 0.5VREF. The
reference common mode voltage, VREFCM, and the input
common mode voltage, VINCM, may be independently set
anywhere within the GND to VCC range of the LTC2411/
LTC2411-1. The DC common mode input rejection is
better than 140dB.
The LTC2411/LTC2411-1 communicate through a flexible
3-wire digital interface that is compatible with SPI and
MICROWIRE protocols.
APPLICATIONS
n 24-Bit ADC in an MS10 Package
n Low Supply Current (200µA in Conversion Mode
and 4µA in Autosleep Mode)
n Differential Input and Differential Reference with
GND to VCC Common Mode Range
n 2ppm INL, No Missing Codes
n 4ppm Full-Scale Error and 1ppm Offset
n 0.29ppm Noise
n No Latency: Digital Filter Settles in a Single Cycle.
Each Conversion Is Accurate, Even After an
Input Step
n Single Supply 2.7V to 5.5V Operation
n Internal Oscillator—No External Components
Required
n 110dB Min, Pin Selectable 50Hz/60Hz Notch Filter
(LTC2411)
n Simultaneous 50Hz/60Hz Rejection (LTC2411-1)
n Direct Sensor Digitizer
n Weight Scales
n Direct Temperature Measurement
n Gas Analyzers
n Strain Gauge Transducers
n Instrumentation
n Data Acquisition
n Industrial Process Control
n 6-Digit DVMs
L, LT, LT C , LT M, Linear Technology and the Linear logo are registered trademarks and No
Latency ∆Σ is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
VCC FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
1 10
2
3
9
4
5
8
6
7
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
= INTERNAL OSC/50Hz REJECTION (LTC2411)
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION (LTC2411)
= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)
3-WIRE
SPI INTERFACE
1µF
2.7V TO 5.5V
LTC2411/
LTC2411-1
2411 TA01
VCC
LTC2411/
LTC2411-1
IN+
REF+VCC
REF–
VCC
GND FO
IN–
1µF
SCK
3-WIRE
SPI
INTERFACE
SDO
2411 TA02
CS
9
21
6 10
4
5
3
8
7
BRIDGE
IMPEDANCE
100Ω TO 10kΩ
LTC2411/LTC2411-1
2
2411fa
For more information www.linear.com/LTC2411
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) to GND ....................... –0.3V to 7V
Analog Input Pins Voltage
to GND ......................................–0.3V to (VCC + 0.3V)
Reference Input Pins Voltage
to GND ......................................–0.3V to (VCC + 0.3V)
Digital Input Voltage to GND .........–0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ....... –0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2411C ................................................ 0°C to 70°C
LTC2411I ............................................. –40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ...................300°C
(Notes 1, 2)
1
2
3
4
5
VCC
RE
F+
RE
F–
IN+
IN–
10
9
8
7
6
FO
SCK
SDO
CS
GND
TOP VIEW
MS10 PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 120°C/W
ORDER INFORMATION
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2411CMS#PBF LTC2411CMS#TRPBF LTNS 10-Lead Plastic MSOP 0°C to 70°C
LTC2411IMS#PBF LTC2411IMS#TRPBF LTNT 10-Lead Plastic MSOP –40°C to 85°C
LTC2411-1CMS#PBF LTC2411-1CMS#TRPBF LTWV 10-Lead Plastic MSOP 0°C to 70°C
LTC2411-1IMS#PBF LTC2411-1IMS#TRPBF LTNN 10-Lead Plastic MSOP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –0.5 • VREF ≤ VIN ≤ 0.5 • VREF (Note 5) l24 Bits
Integral Nonlinearity 4.5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V (Note 6)
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V (Note 6)
REF+ = 2.5V, REF– = GND, VINCM = 1.25V (Note 6)
l
1
2
6
14
ppm of VREF
ppm of VREF
ppm of VREF
Offset Error 2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN+ = IN– ≤ VCC (Note 14)
l5 20 µV
Offset Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN+ = IN– ≤ VCC
20 nV/°C
Positive Full-Scale Error 2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.75REF+, IN– = 0.25 • REF+
l4 12 ppm of VREF
Positive Full-Scale Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.75REF+, IN– = 0.25 • REF+0.04 ppm of VREF/°C
Negative Full-Scale Error 2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.25 • REF+, IN– = 0.75 • REF+
l4 12 ppm of VREF
LTC2411/LTC2411-1
3
2411fa
For more information www.linear.com/LTC2411
ELECTRICAL CHARACTERISTICS
CONVERTER CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Negative Full-Scale Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.25 • REF+, IN– = 0.75 • REF+0.04 ppm of VREF/°C
Total Unadjusted Error 4.5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V
REF+ = 2.5V, REF– = GND, VINCM = 1.25V
3
3
6
ppm of VREF
ppm of VREF
ppm of VREF
Output Noise 5V ≤ VCC ≤ 5.5V, REF+ = 5V, VREF– = GND,
GND ≤ IN– = IN+ ≤ 5V, (Note 13)
1.45 µVRMS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Common Mode Rejection DC 2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ 5V
l130 140 dB
Input Common Mode Rejection
60Hz ±2% (LTC2411)
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ 5V, (Note 7)
l140 dB
Input Common Mode Rejection
50Hz ±2% (LTC2411)
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ 5V, (Note 8)
l140 dB
Input Common Mode Rejection
49Hz to 61.2Hz (LTC2411-1)
2.5V < REF+ < VCC, REF– = GND,
GND < IN– = IN+ < VCC (Note 15)
l140 dB
Input Normal Mode Rejection
60Hz ±2% (LTC2411)
(Note 7) l110 140 dB
Input Normal Mode Rejection
50Hz ±2% (LTC2411)
(Note 8) l110 140 dB
Input Normal Mode Rejection
49Hz to 61.2Hz (LTC2411-1)
(Note 15) l87 dB
Reference Common Mode
Rejection DC
2.5V ≤ REF+ ≤ VCC, GND ≤ REF– ≤ 2.5V,
VREF = 2.5V, IN– = IN+ = GND
l130 140 dB
Power Supply Rejection, DC REF+ = 2.5V, REF– = GND, IN– = IN+ = GND 110 dB
Power Supply Rejection, 60Hz ±2%
(LTC2411)
REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 7) 120 dB
Power Supply Rejection, 50Hz ±2%
(LTC2411)
REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 8) 120 dB
Power Supply Rejection,
49Hz to 61.2Hz (LTC2411-1)
REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 15) 120 dB
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
ANALOG INPUT AND REFERENCE
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IN+Absolute/Common Mode IN+ Voltage lGND – 0.3V VCC + 0.3V V
IN–Absolute/Common Mode IN– Voltage lGND – 0.3V VCC + 0.3V V
VIN Input Differential Voltage Range
(IN+ – IN–)
l–VREF/2 VREF/2 V
REF+Absolute/Common Mode REF+ Voltage l0.1 VCC V
REF–Absolute/Common Mode REF– Voltage lGND VCC – 0.1V V
VREF Reference Differential Voltage Range
(REF+ – REF–)
l0.1 VCC V
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
LTC2411/LTC2411-1
4
2411fa
For more information www.linear.com/LTC2411
POWER REQUIREMENTS
ANALOG INPUT AND REFERENCE
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CS (IN+) IN+ Sampling Capacitance 6 pF
CS (IN–) IN– Sampling Capacitance 6 pF
CS (REF+) REF+ Sampling Capacitance 6 pF
CS (REF–) REF– Sampling Capacitance 6 pF
IDC_LEAK (IN+) IN+ DC Leakage Current CS = VCC = 5.5V, IN+ = GND l–10 1 10 nA
IDC_LEAK (IN–) IN– DC Leakage Current CS = VCC = 5.5V, IN– = GND l–10 1 10 nA
IDC_LEAK (REF+) REF+ DC Leakage Current CS = VCC = 5.5V, REF+ = 5V l–10 1 10 nA
IDC_LEAK (REF–) REF– DC Leakage Current CS = VCC = 5.5V, REF– = GND l–10 1 10 nA
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage
CS, FO
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 3.3V
l2.5
2.0
V
V
VIL Low Level Input Voltage
CS, FO
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
l0.8
0.6
V
V
VIH High Level Input Voltage
SCK
2.7V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 3.3V (Note 9)
l2.5
2.0
V
V
VIL Low Level Input Voltage
SCK
4.5V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 5.5V (Note 9)
l0.8
0.6
V
V
IIN Digital Input Current
CS, FO
0V ≤ VIN ≤ VCC l–10 10 µA
IIN Digital Input Current
SCK
0V ≤ VIN ≤ VCC (Note 9) l–10 10 µA
CIN Digital Input Capacitance
CS, FO
10 pF
CIN Digital Input Capacitance
SCK
(Note 9) 10 pF
VOH High Level Output Voltage
SDO
IO = –800µA lVCC – 0.5V V
V
VOL Low Level Output Voltage
SDO
IO = 1.6mA l0.4 V
V
VOH High Level Output Voltage
SCK
IO = –800µA (Note 10) lVCC – 0.5V V
V
VOL Low Level Output Voltage
SCK
IO = 1.6mA (Note 10) l0.4 V
V
IOZ Hi-Z Output Leakage
SDO
l–10 10 µA
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage l2.7 5.5 V
ICC Supply Current
Conversion Mode
Sleep Mode
Sleep Mode
CS = 0V (Note 12)
CS = VCC (Note 12)
CS = VCC, 2.7V ≤ VCC ≤ 3.3V (Note 12)
l
l
200
4
2
300
10
µA
µA
µA
LTC2411/LTC2411-1
5
2411fa
For more information www.linear.com/LTC2411
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7 to 5.5V unless otherwise specified.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2;
VIN = IN+ – IN–, VINCM = (IN+ + IN–)/2.
Note 4: FO pin tied to GND or to VCC or to external conversion clock source
with fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2% (external
oscillator).
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2% (external
oscillator).
Note 9: The converter is in external SCK mode of operation such that the
SCK pin is used as digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that the
SCK pin is used as digital output. In this mode of operation the SCK pin
has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
Note 15: FO = 0V (internal oscillator) or fEOSC = 139800Hz ±2% (external
oscillator).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fEOSC External Oscillator Frequency Range l2.56 500 kHz
tHEO External Oscillator High Period l0.25 390 µs
tLEO External Oscillator Low Period l0.25 390 µs
tCONV Conversion Time FO = 0V (LTC2411)
FO = VCC (LTC2411)
FO = 0V (LTC2411-1)
External Oscillator (Note 11)
l
l
l
l
130.86
157.03
143.78
133.53
160.23
146.71
136.20
163.44
149.64
ms
ms
ms
ms
20510/fEOSC (in kHz)
f ISCK Internal SCK Frequency Internal Oscillator (LTC2411) (Note 10)
Internal Oscillator (LTC2411-1) (Note 10)
External Oscillator (Notes 10, 11)
19.2
17.5
fEOSC/8
kHz
kHz
kHz
DISCK Internal SCK Duty Cycle (Note 10) l45 55 %
fESCK External SCK Frequency Range (Note 9) l2000 kHz
tLESCK External SCK Low Period (Note 9) l250 ns
tHESCK External SCK High Period (Note 9) l250 ns
tDOUT_ISCK Internal SCK 32-Bit Data Output Time Internal Oscillator (LTC2411) (Notes 10, 12)
Internal Oscillator (LTC2411-1) (Notes 10, 12)
External Oscillator (Notes 10, 11)
l
l
l
1.64
1.80
1.67
1.83
1.70
1.86
ms
ms
ms
256/fEOSC (in kHz)
tDOUT_ESCK External SCK 32-Bit Data Output Time (Note 9) l32/fESCK (in kHz) ms
t1CS ↓ to SDO Low Z l0 200 ns
t2CS ↑ to SDO High Z l0 200 ns
t3CS ↓ to SCK ↓(Note 10) l0 200 ns
t4CS ↓ to SCK ↑(Note 9) l50 ns
tKQMAX SCK ↓ to SDO Valid l220 ns
tKQMIN SDO Hold After SCK ↓(Note 5) l15 ns
t5SCK Set-Up Before CS ↓l50 ns
t6SCK Hold After CS ↓l50 ns
LTC2411/LTC2411-1
6
2411fa
For more information www.linear.com/LTC2411
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
Noise Histogram Long Term ADC Readings
RMS Noise
vs Input Differential Voltage
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
VIN (V)
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5
TUE (ppm OF V
REF
)
2411 G01
3
2
1
0
–1
–2
–3
TA = 25°C
VCC = 5V
REF+ = 5V
REF– = GND
VINCM = 2.5V
FO = GND
TA = –45°C
TA = 90°C
OUTPUT CODE (ppm OF VREF)
–2.0
NUMBER OF READINGS (%)
6
8
10
–0.5 0.5
2411 G07
4
2
0–1.5 –1.0 0
12
14
16
1
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
VINCM = 2.5V
FO = GND
TA = 25°C
GAUSSIAN
DISTRIBUTION
m = –0.647ppm
σ = 0.287ppm
VIN (V)
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5
INL (ppm OF V
REF
)
2411 G04
3
2
1
0
–1
–2
–3
TA = 25°C
TA = 90°C
VCC = 5V
REF+ = 5V
REF– = GND
VINCM = 2.5V
FO = GND
TA = –45°C
VIN (V)
–1.25 –0.75 –0.25 0.25 0.75
1.25
TUE (ppm OF V
REF
)
2411 G02
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
VCC = 5V
REF+ = 2.5V
REF– = GND
VINCM = 2.5V
FO = GND
TA = –45°C
TA = 90°C
TA = 25°C
TIME (HOURS)
0
–2.0
ADC READING (ppm OF V
REF
)
–1.5
–1.0
–0.5
0
1.0
510 15 20
2411 G08
25 30 35 40 45 50 55 60
0.5
VCC = 5V, VREF = 5V, VIN = 0V, VINCM = 2.5V,
FO = GND, TA = 25°C, RMS NOISE = 0.29ppm
INPUT DIFFERENTIAL VOLTAGE (V)
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5
RMS NOISE (ppm OF V
REF
)
2411 G09
0.5
0.4
0.3
0.2
0.1
0
TA = 25°C
VCC = 5V
VREF = 5V
VINCM = 2.5V
FO = GND
VIN (V)
–1.25 –0.75 –0.25 0.25 0.75
1.25
INL (ppm OF V
REF
)
2411 G05
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
VCC = 5V
REF+ = 2.5V
REF– = GND
VINCM = 2.5V
FO = GND
TA = 90°C
TA = –45°C
TA = 25°C
VIN (V)
–1.25
TUE (ppm OF V
REF
)
2
6
10
0.75
2411 G03
–2
–6
0
4
8
–4
–8
–10 –0.75 –0.25 0.25
1.25
TA = 90°C
VCC = 2.7V
REF+ = 2.5V
REF– = GND
VINCM = 1.25V
FO = GND
TA = –45°C
TA = 25°C
VIN (V)
–1.25
INL (ppm OF V
REF
)
2
6
10
0.75
2411 G06
–2
–6
0
4
8
–4
–8
–10 –0.75 –0.25 0.25
1.25
TA = 90°C
VCC = 2.7V
REF+ = 2.5V
REF– = GND
VINCM = 1.25V
FO = GND
TA = –45°C
TA = 25°C
LTC2411/LTC2411-1
7
2411fa
For more information www.linear.com/LTC2411
TYPICAL PERFORMANCE CHARACTERISTICS
RMS Noise vs VREF Offset Error vs VINCM Offset Error vs Temperature
Offset Error vs VCC Offset Error vs VREF +Full-Scale Error vs Temperature
RMS Noise vs VINCM RMS Noise vs Temperature RMS Noise vs VCC
VINCM (V)
–1
RMS NOISE (µV)
1.50
1.55
1.60
2 4
2411 G10
1.45
1.40
0 1 3 5 6
1.35
1.30
VCC = 5V
REF+ = 5V
REF– = GND
VIN = 0V
FO = GND
TA = 25°C
VREF (V)
0
1.30
RMS NOISE (µV)
1.35
1.40
1.45
1.50
1.55
1.60
1 2 3 4
2411 G13
5
VCC = 5V
REF– = GND
VIN = 0V
FO = GND
TA = 25°C
VCC (V)
2.7
OFFSET ERROR (ppm OF V
REF
)
0
3.5 4.3 4.7 5.5
2411 G16
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0 3.1 3.9 5.1
REF+ = 2.5V
REF– = GND
VIN = 0V
VINCM = GND
FO = GND
TA = 25°C
VINCM (V)
–1
OFFSET ERROR (ppm OF V
REF
)
0
134 6
2411 G14
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0 0 2 5
VCC = 5V
REF+ = 5V
REF– = GND
VIN = 0V
FO = GND
TA = 25°C
VREF (V)
0
OFFSET ERROR (ppm OF V
REF
)
0
125
2411 G17
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0 3 4
VCC = 5V
REF– = GND
VIN = 0V
VINCM = GND
FO = GND
TA = 25°C
TEMPERATURE (°C)
–45
1.30
RMS NOISE (µV)
1.35
1.45
1.50
1.55
–15 15 30 90
2411 G11
1.40
–30 0 45 60 75
1.60
VCC = 5V
VREF = 5V
VIN = 0V
VINCM = GND
FO = GND
VCC (V)
2.7
RMS NOISE (µV)
1.50
1.55
1.60
3.9 4.7
2411 G12
1.45
1.40
3.1 3.5 4.3 5.1 5.5
1.35
1.30
REF+ = 2.5V
REF– = GND
VIN = 0V
FO = GND
TA = 25°C
TEMPERATURE (°C)
–45
OFFSET ERROR (ppm OF V
REF
)
0
–15 15 30 90
2411 G15
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0 –30 0 45 60 75
VCC = 5V
VREF = 5V
VIN = 0V
VINCM = GND
FO = GND
TEMPERATURE (°C)
–45
–3
FULL-SCALE ERROR (ppm OF V
REF
)
–2
0
1
2
–15 15 30 90
2411 G18
–1
–30 0 45 60 75
3
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 2.5V
IN– = GND
FO = GND
LTC2411/LTC2411-1
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TYPICAL PERFORMANCE CHARACTERISTICS
PSRR vs Frequency at VCC
(LTC2411)
PSRR vs Frequency at VCC
(LTC2411)
PSRR vs Frequency at VCC
(LTC2411)
PSRR vs Frequency at VCC
(LTC2411-1)
PSRR vs Frequency at VCC
(LTC2411-1)
PSRR vs Frequency at VCC
(LTC2411-1)
+Full-Scale Error vs Temperature –Full-Scale Error vs Temperature –Full-Scale Error vs Temperature
TEMPERATURE (°C)
–45
FULL-SCALE ERROR (ppm OF V
REF
)
5
–15 15 30 90
2411 G19
4
3
2
1
0
–1
–2
–3
–4
–5 –30 0 45 60 75
VCC = 2.7V
REF+ = 2.5V
REF– = GND
IN+ = 1.25V
IN– = GND
FO = GND
FREQUECY AT VCC (Hz)
1
0
–20
–40
–60
–80
–100
–120
–140 1k 100k
2411 G31
10 100 10k
1M
REJECTION (dB)
VCC = 4.1V DC
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
FREQUENCY AT VCC (Hz)
1
–20
0
–40
–60
–80
–100
–120
–140 1k 100k
2411 G22
10 100 10k
1M
REJECTION (dB)
VCC = 4.1V DC
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
TEMPERATURE (°C)
–45
–3
–FULL-SCALE ERROR (ppm OF V
REF
)
–2
0
1
2
–15 15 30 90
2411 G20
–1
–30 0 45 60 75
3
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = GND
IN– = 2.5V
FO = GND
FREQUENCY AT VCC (Hz)
0
–140
REJECTION (dB)
–120
–80
–60
–40
0
20 100 140
2411 G32
–100
–20
80 200180 220
40 60 120 160
VCC = 4.1V DC ±1.4V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
FREQUENCY AT VCC (Hz)
6880
–60
–40
0
7030
2411 G33
–80
–100
6930 6980
7080
–120
–140
–20
REJECTION (dB)
VCC = 4.1V DC ±0.7V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
FREQUENCY AT VCC (Hz)
0
REJECTION (dB)
–60
–40
–20
120 180
2411 G23
–80
–100
30 60 150 210
–120
–140
0
90
240
VCC = 4.1V DC ±1.4V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
TEMPERATURE (°C)
–45
–FULL-SCALE ERROR (ppm OF V
REF
)
5
–15 15 30 90
2411 G21
4
3
2
1
0
–1
–2
–3
–4
–5 –30 0 45 60 75
VCC = 2.7V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = 1.25V
FO = GND
FREQUENCY AT VCC (Hz)
7600
–60
–40
0
7750
2411 G24
–80
–100
7650 7700
7800
–120
–140
–20
REJECTION (dB)
VCC = 4.1V DC ±0.7VP-P
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
LTC2411/LTC2411-1
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For more information www.linear.com/LTC2411
TYPICAL PERFORMANCE CHARACTERISTICS
Offset Error vs Output Data Rate
Resolution (NOISERMS ≤ 1LSB)
vs Output Data Rate
Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate
Conversion Current
vs Temperature
Conversion Current
vs Output Data Rate
Sleep Mode Current
vs Temperature
TEMPERATURE (°C)
–45
CONVERSION CURRENT (µA)
200
210
220
75
2411 G25
190
180
160 –15 15 45
–30 90
030 60
170
240
230
FO = GND
CS = GND
SCK = NC
SDO = NC VCC = 5.5V
VCC = 2.7V
VCC = 5V
VCC = 3V
OUTPUT DATA RATE (READINGS/SEC)
–120
OFFSET ERROR (ppm OF V
REF
)
–60
–20
40
–80
–100
–40
20
0
2411 G28
VCC = 5V
REF– = GND
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
TA = 25°C
VREF = 2.5V
VREF = 5V
02010
515 25
OUTPUT DATA RATE (READINGS/SEC)
0
SUPPLY CURRENT (µA)
450
550
650
2411 G26
350
250
400
500
600
300
200
150 2010
515
25
REF+ = VCC
REF– = GND
IN+ = GND
IN– = GND
TA = 25°C
SCK = NC
SDO = NC
CS = GND
FO = EXT OSC
VCC = 3V
VCC = 5V
OUTPUT DATA RATE (READINGS/SEC)
RESOLUTION (BITS)
20
21
2411 G29
19
18
22
VCC = 5V
REF– = GND
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
RES = LOG2(VREF/NOISERMS)
TA = 25°C
VREF = 2.5V
VREF = 5V
02010
515
25
TEMPERATURE (°C)
–45
SLEEP MODE CURRENT (µA)
1
2
3
75
2411 G27
0–15 15 45
–30
90
030 60
5
4
FO = GND
CS = VCC
SCK = NC
SDO = NC
VCC = 5.5V
VCC = 2.7V
VCC = 5V
VCC = 3V
OUTPUT DATA RATE (READINGS/SEC)
10
RESOLUTION (BITS)
14
18
22
12
16
20
2015
2411 G30
255 100
VCC = 5V
REF– = GND
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
RES = LOG2(VREF/INLMAX)
TA = 25°C
VREF = 2.5V
VREF = 5V
LTC2411/LTC2411-1
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PIN FUNCTIONS
VCC (Pin 1): Positive Supply Voltage. Bypass to GND
(Pin6) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
REF+ (Pin 2), REF– (Pin 3): Differential Reference Input.
The voltage on these pins can have any value between GND
and VCC as long as the reference positive input, REF+, is
more positive than the reference negative input, REF–, by
at least 0.1V.
IN+ (Pin 4), IN– (Pin 5): Differential Analog Input. The
voltage on these pins can have any value between
GND – 0.3V and VCC + 0.3V. Within these limits, the con-
verter bipolar input range (VIN = IN+ – IN–) extends from
–0.5 • (VREF) to 0.5 • (VREF). Outside this input range, the
converter produces unique overrange and underrange
output codes.
GND (Pin 6): Ground. Connect this pin to a ground plane
through a low impedance connection.
CS (Pin 7): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 8): Three-State Digital Output. During the Data
Output period, this pin is used as the serial data output.
When the chip select CS is HIGH (CS = VCC), the SDO pin
is in a high impedance state. During the Conversion and
Sleep periods, this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS LOW.
SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as the digital
output for the internal serial interface clock during the
Data Output period. In External Serial Clock Operation
mode, SCK is used as the digital input for the external se-
rial interface clock during the Data Output period. A weak
internal pull-up is automatically activated in Internal Serial
Clock Operation mode. The Serial Clock Operation mode
is determined by the logic level applied to the SCK pin at
power up or during the most recent falling edge of CS.
FO (Pin 10): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion time.
For the LTC2411, when the FO pin is connected to VCC
(FO = VCC), the converter uses its internal oscillator and
the digital filter first null is located at 50Hz. When the FO
pin is connected to GND (FO = 0V), the converter uses its
internal oscillator and the digital filter first null is located
at 60Hz. For the LTC2411-1, the converter provides simul-
taneous 50Hz/60Hz rejection with the FO pin connected to
GND. When FO is driven by an external clock signal with
a frequency fEOSC, the converters use this signal as their
system clock and the digital filter first null is located at a
frequency fEOSC/2560.
LTC2411/LTC2411-1
11
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FUNCTIONAL BLOCK DIAGRAM
TEST CIRCUIT
AUTOCALIBRATION
AND CONTROL
DAC
DECIMATING FIR
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
ADC
∑
∫∫∫
GND
VCC
IN+
IN–
SDO
SCK
RE
F+
RE
F–
CS
FO
(INT/EXT)
2411 FD
– +
+
–
Figure 1
1.69k
SDO
2411 TA03
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD
= 20pF
1.69k
SDO
2411 TA04
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
CLOAD
= 20pF
V
CC
LTC2411/LTC2411-1
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APPLICATIONS INFORMATION
CONVERTER OPERATION
Converter Operation Cycle
The LTC2411/LTC2411-1 are low power, delta-sigma
analog-to-digital converters with an easy-to-use 3-wire
serial interface (see Figure 1). Their operation is made
up of three states. The converter operating cycle begins
with the conversion, followed by the low power sleep state
and ends with the data output (see Figure 2). The 3-wire
interface consists of serial data output (SDO), serial clock
(SCK) and chip select (CS).
Initially, the LTC2411/LTC2411-1 perform a conversion.
Once the conversion is complete, the devices enter the
sleep state. While in this sleep state, power consumption
is reduced by an order of magnitude. The parts remain
in the sleep state as long as CS is HIGH. The conversion
result is held indefinitely in a static shift register while the
converter is in the sleep state.
Once CS is pulled LOW, the devices begin outputting the
conversion result. There is no latency in the conversion
result. The data output corresponds to the conversion
just performed. This result is shifted out on the serial data
out pin (SDO) under the control of the serial clock (SCK).
Data is updated on the falling edge of SCK allowing the
user to reliably latch data on the rising edge of SCK (see
Figure 3). The data output state is concluded once 32 bits
are read out of the ADC or when CS is brought HIGH. The
devices automatically initiate a new conversion and the
cycle repeats.
Through timing control of the CS and SCK pins, the
LTC2411/LTC2411-1 offer several flexible modes of
operation (internal or external SCK and free-running
conversion modes). These various modes do not require
programming configuration registers; moreover, they do
not disturb the cyclic operation described above. These
modes of operation are described in detail in the Serial
Interface Timing Modes section.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50 or 60Hz
plus their harmonics. The filter rejection performance is
directly related to the accuracy of the converter system
clock. The LTC2411/LTC2411-1 incorporate a highly
accurate on-chip oscillator. This eliminates the need for
external frequency setting components such as crystals
or oscillators. Clocked by the on-chip oscillator, the
LTC2411 achieves a minimum of 110dB rejection at the
line frequency (50Hz or 60Hz ±2%) and the LTC2411-1
achieves a minimum of 87dB rejection over 49Hz to 61.2Hz.
Ease of Use
The LTC2411/LTC2411-1 data output has no latency,
filter settling delay or redundant data associated with the
conversion cycle. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog voltages is easy.
The LTC2411/LTC2411-1 perform offset and full-scale
calibrations in every conversion cycle. This calibration
is transparent to the user and has no effect on the cyclic
operation described above. The advantage of continuous
calibration is extreme stability of offset and full-scale
readings with respect to time, supply voltage change and
temperature drift.
Power-Up Sequence
The LTC2411/LTC2411-1 automatically enter an internal
reset state when the power supply voltage VCC drops
below approximately 1.9V. This feature guarantees the
Figure 2. LTC2411/LTC2411-1 State Transition Diagram
CONVERT
SLEEP
DATA OUTPUT
2411 F02
TRUE
FALSE CS = LOW
AND
SCK
LTC2411/LTC2411-1
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APPLICATIONS INFORMATION
integrity of the conversion result and of the serial interface
mode selection. (See the 2-wire I/O sections in the Serial
Interface Timing Modes section.)
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 1ms. The POR
signal clears all internal registers. Following the POR signal,
the LTC2411/LTC2411-1 start a normal conversion cycle
and follow the succession of states described above. The
first conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
Reference Voltage Range
The LTC2411/LTC2411-1 accept a truly differential external
reference voltage. The absolute/common mode voltage
specification for the REF+ and REF– pins covers the entire
range from GND to VCC. For correct converter operation, the
REF+ pin must always be more positive than the REF– pin.
The LTC2411/LTC2411-1 can accept a differential reference
voltage from 0.1V to VCC. The converter output noise is
determined by the thermal noise of the front-end circuits,
and, as such, its value in nanovolts is nearly constant with
reference voltage. A decrease in reference voltage will not
significantly improve the converter’s effective resolution.
On the other hand, a reduced reference voltage will improve
the converter’s overall INL performance. A reduced refer-
ence voltage will also improve the converter performance
when operated with an external conversion clock (external
FO signal) at substantially higher output data rates.
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the IN+ and IN– input pins
extending from GND – 0.3V to VCC + 0.3V. Outside
these limits, the ESD protection devices begin to turn
on and the errors due to input leakage current increase
rapidly. Within these limits, the LTC2411/LTC2411-1 con-
vert the bipolar differential input signal, VIN = IN+ – IN–,
from –FS = –0.5 • VREF to +FS = 0.5 • VREF where VREF =
REF+ – REF–. Outside this range the converter indicates
the overrange or the underrange condition using distinct
output codes.
Input signals applied to IN+ and IN– pins may extend by
300mV below ground and above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ and IN– pins without affecting the performance
of the device. In the physical layout, it is important to main-
tain the parasitic capacitance of the connection between
these series resistors and the corresponding pins as low
as possible; therefore, the resistors should be located as
close as practical to the pins. In addition, series resistors
will introduce a temperature dependent offset error due
to the input leakage current. A 1nA input leakage current
will develop a 1ppm offset error on a 5k resistor if VREF =
5V. This error has a very strong temperature dependency.
Output Data Format
The LTC2411/LTC2411-1 serial output data stream is 32
bits long. The first 3 bits represent status information
indicating the sign and conversion state. The next 24 bits
are the conversion result, MSB first. The remaining 5 bits
are sub LSBs beyond the 24-bit level that may be included
in averaging or discarded without loss of resolution. The
third and fourth bits together are also used to indicate
an underrange condition (the differential input voltage
is below –FS) or an overrange condition (the differential
input voltage is above +FS).
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign
indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0,
this bit is LOW.
Bit 28 (fourth output bit) is the most significant bit (MSB) of
the result. This bit in conjunction with Bit 29 also provides
the underrange or overrange indication. If both Bit 29 and
Bit 28 are HIGH, the differential input voltage is above +FS.
LTC2411/LTC2411-1
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APPLICATIONS INFORMATION
If both Bit 29 and Bit 28 are LOW, the differential input
voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2411/LTC2411-1 Status Bits
Input Range
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
VIN ≥ 0.5 • VREF 0011
0V ≤ VIN < 0.5 • VREF 0010
–0.5 • VREF ≤ VIN < 0V 0 0 0 1
VIN < –0.5 • VREF 0000
Bits 28-5 are the 24-bit conversion result MSB first.
Bit 5 is the least significant bit (LSB).
Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0
may be included in averaging or discarded without loss
of resolution.
Data is shifted out of the SDO pin under control of the
serial clock (SCK), see Figure 3. Whenever CS is HIGH,
SDO remains high impedance and any externally gener-
ated SCK clock pulses are ignored by the internal data
out shift register.
In order to shift the conversion result out of the device,
CS must first be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
rising edge of SCK. Bit 30 is shifted out of the device on
the first falling edge of SCK. The final data bit (Bit 0) is
shifted out on the falling edge of the 31st SCK and may
be latched on the rising edge of the 32nd SCK pulse. On
the falling edge of the 32nd SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (Bit 31) for the next conversion cycle.
Table 2 summarizes the output data format.
Figure 3. Output Data Timing
Table 2. LTC2411/LTC2411-1 Output Data Format
Differential Input Voltage
VIN*
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
Bit 27 Bit 26 Bit 25 … Bit 0
VIN* ≥ 0.5 • VREF** 0011000…0
0.5 • VREF** – 1LSB 0 0 1 0 1 1 1 … 1
0.25 • VREF** 0010100…0
0.25 • VREF** – 1LSB 0 0 1 0 0 1 1 … 1
0 0010000…0
–1LSB 0 0 0 1 1 1 1 … 1
–0.25 • VREF** 0001100…0
–0.25 • VREF** – 1LSB 0 0 0 1 0 1 1 … 1
–0.5 • VREF** 0001000…0
VIN* < –0.5 • VREF** 0000111…1
*The differential Input voltage VIN = IN+ – IN–.
**The differential reference voltage VREF = REF+ – REF–.
MSBSIG“0”
1 2 3 4 5 26 27 32
BIT 0BIT 27 BIT 5
LSB24
BIT 28BIT 29BIT 30
SDO
SCK
CS
EOC
BIT 31
SLEEP DATA OUTPUT CONVERSION
2411 F03
Hi-Z
LTC2411/LTC2411-1
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APPLICATIONS INFORMATION
As long as the voltage on the IN+ and IN– pins is main-
tained within the –0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF to
+FS = 0.5 • VREF. For differential input voltages greater
than +FS, the conversion result is clamped to the value
corresponding to the +FS + 1LSB. For differential input
voltages below –FS, the conversion result is clamped to
the value corresponding to –FS – 1LSB.
Frequency Rejection Selection (FO) (LTC2411 Only)
The LTC2411 internal oscillator provides better than
110dB normal mode rejection at the line frequency and
all its harmonics for 50Hz ±2% or 60Hz ±2%. For 60Hz
rejection, FO should be connected to GND while for 50Hz
rejection the FO pin should be connected to VCC.
The selection of 50Hz or 60Hz rejection can also be made
by driving FO to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2411 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the FO pin and turns off the internal oscillator.
The frequency fEOSC of the external signal must be at least
2560Hz (1Hz notch frequency) to be detected. The external
clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and
low periods tHEO and tLEO are observed.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2411 provides better than 110dB
normal mode rejection in a frequency range fEOSC/2560
±4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/2560
is shown in Figure 4.
Whenever an external clock is not present at the FO pin,
the converter automatically activates its internal oscilla-
tor and enters the Internal Conversion Clock mode. The
LTC2411 operation will not be disturbed if the change of
conversion clock source occurs during the sleep state
or during the data output state while the converter uses
an external serial clock. If the change occurs during the
conversion state, the result of the conversion in progress
may be outside specifications but the following conver-
sions will not be affected. If the change occurs during the
data output state and the converter is in the Internal SCK
mode, the serial clock duty cycle may be affected but the
serial data stream will remain valid.
Table 3 summarizes the duration of each state and the
achievable output data rate as a function of FO.
Simultaneous Frequency Rejection (LTC2411-1 Only)
The LTC2411-1 internal oscillator provides better than
87dB normal mode rejection over the range of 49Hz to
61.2Hz. For this simultaneous 50/60Hz rejection, FO should
be connected to GND. The performance of the LTC2411-1
is the same as the LTC2411 when driven by an external
conversion clock at FO pin.
Serial Interface pins
The LTC2411/LTC2411-1 transmit the conversion results
and receive the start of conversion command through
a synchronous 3-wire interface. During the conversion
and sleep states, this interface can be used to assess the
Figure 4. LTC2411 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC
/2560(%)
–12 –8 –4 0 4 8 12
NORMAL MODE REJECTION (dB)
2411 F04
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
LTC2411/LTC2411-1
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APPLICATIONS INFORMATION
Table 3. LTC2411/LTC2411-1 State Duration
State Operating Mode Duration
CONVERT Internal Oscillator FO = LOW (LTC2411)
(60Hz Rejection)
133ms, Output Data Rate ≤ 7.5 Readings/s
FO = HIGH (LTC2411)
(50Hz Rejection)
160ms, Output Data Rate ≤ 6.2 Readings/s
FO = LOW (LTC2411-1)
(Simultaneous 50Hz/60Hz Rejection)
147ms, Output Data Rate ≤ 6.8 Readings/s
External Oscillator FO = External Oscillator
with Frequency fEOSC kHz
(fEOSC/2560 Rejection)
20510/fEOSCs, Output Data Rate ≤ fEOSC/20510 Readings/s
SLEEP As Long As CS = HIGH Until CS = LOW and SCK
DATA OUTPUT Internal Serial Clock FO = LOW/HIGH (LTC2411)
(Internal Oscillator)
As Long As CS = LOW But Not Longer Than 1.67ms
(32 SCK cycles)
FO = LOW (LTC2411-1)
(Internal Oscillator)
As Long As CS = LOW But Not Longer Than 1.83ms
(32 SCK cycles)
FO = External Oscillator with
Frequency fEOSC kHz
As Long As CS = LOW But Not Longer Than 256/fEOSCms
(32 SCK cycles)
External Serial Clock with
Frequency fSCK kHz
As Long As CS = LOW But Not Longer Than 32/fSCKms
(32 SCK cycles)
converter status and during the data output state it is used
to read the conversion result.
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 9) is used to
synchronize the data transfer. Each bit of data is shifted
out the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is
an output and the LTC2411/LTC2411-1 create their own
serial clock by dividing the internal conversion clock by
8. In the External SCK mode of operation, the SCK pin
is used as input. The internal or external SCK mode is
selected on power-up and then reselected every time a
HIGH-to-LOW transition is detected at the CS pin. If SCK
is HIGH or floating at power-up or during this transition,
the converter enters the internal SCK mode. If SCK is LOW
at power-up or during this transition, the converter enters
the external SCK mode.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 8), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO
pin is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 7) is HIGH, the SDO driver is switched to
a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 7), is used to test the
conversion status and to enable the data output transfer
as described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2411/LTC2411-1 will abort any
serial data transfer in progress and start a new conver-
sion cycle anytime a LOW-to-HIGH transition is detected
at the CS pin after the converter has entered the data
output state (i.e., after the first rising edge of SCK occurs
with CS=LOW).
LTC2411/LTC2411-1
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Figure 5. External Serial Clock, Single Cycle Operation
Table 4. LTC2411/LTC2411-1 Interface Timing Modes
Configuration
SCK
Source
Conversion
Cycle
Control
Data
Output
Control
Connection
and
Waveforms
External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 5, 6
External SCK, 2-Wire I/O External SCK SCK Figure 7
Internal SCK, Single Cycle Conversion Internal CS ↓CS ↓Figures 8, 9
Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 10
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by FO.
SERIAL INTERFACE TIMING MODES
The LTC2411/LTC2411-1’s 3-wire interface is SPI and
MICROWIRE compatible. This interface offers several
flexible modes of operation. These include internal/external
serial clock, 2- or 3-wire I/O, single cycle conversion. The
following sections describe each of these serial interface
timing modes in detail. In all these cases, the converter
can use the internal oscillator (FO = LOW or FO = HIGH)
or an external oscillator connected to the FO pin. Refer to
Table4 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift
out the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
The serial clock mode is selected on the falling edge of
CS. To select the external serial clock mode, the serial
clock pin (SCK) must be LOW during each CS falling edge.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC=1 while a conversion is in progress and EOC = 0
if the device is in the sleep state. Independent of CS, the
EOC
BIT 31
SDO
SCK
(EXTERNAL)
CS
TEST EOC
SUB LSBMSBSIG
BIT 0
LSB
BIT 5BIT 27 BIT 26BIT 28BIT 29BIT 30
SLEEP DATA OUTPUT CONVERSION
2411 F05
CONVERSION
Hi-ZHi-ZHi-Z
TEST EOCTEST EOC
VCC FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
1 10
2
3
9
4
5
8
6
7
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
= 50Hz REJECTION (LTC2411)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2411)
= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)
VCC
1µF
2.7V TO 5.5V
LTC2411/
LTC2411-1
3-WIRE
SPI INTERFACE
LTC2411/LTC2411-1
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device automatically enters the low power sleep state once
the conversion is complete.
When the device is in the sleep state (EOC = 0), its con-
version result is held in an internal static shift register.
The device remains in the sleep state until the first rising
edge of SCK is seen while CS is LOW. Data is shifted out
the SDO pin on each falling edge of SCK. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 32nd rising edge of SCK. On the 32nd falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time
in order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing CS HIGH anytime between the first rising edge and
the 32nd falling edge of SCK, see Figure 6. On the rising
edge of CS, the device aborts the data output state and
immediately initiates a new conversion. This is useful for
systems not requiring all 32 bits of output data, aborting
an invalid conversion cycle or synchronizing the start of
a conversion.
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface.
The conversion result is shifted out of the device by an
externally generated serial clock (SCK) signal, see Figure
7. CS may be permanently tied to ground, simplifying the
user interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 1.9V. The level ap-
plied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can
be continuously monitored at the SDO pin during the
convert and sleep states. EOC may be used as an interrupt
to an external controller indicating the conversion result
is ready. EOC = 1 while the conversion is in progress and
EOC=0 once the conversion enters the low power sleep
state. On the falling edge of EOC, the conversion result
is loaded into an internal static shift register. The device
Figure 6. External Serial Clock, Reduced Data Output Length
SDO
SCK
(EXTERNAL)
CS
DATA OUTPUT
CONVERSIONSLEEP SLEEP
TEST EOC TEST EOC
DATA OUTPUT
Hi-Z Hi-ZHi-Z
CONVERSION
2411 F06
MSBSIG
BIT 8BIT 27 BIT 9BIT 28BIT 29BIT 30
EOC
BIT 31BIT 0
EOC
Hi-Z
TEST EOC
VCC FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
1 10
2
3
9
4
5
8
6
7
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
3-WIRE
SPI INTERFACE
1µF
2.7V TO 5.5V
= 50Hz REJECTION (LTC2411)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2411)
= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)
VCC
LTC2411/
LTC2411-1
LTC2411/LTC2411-1
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Figure 7. External Serial Clock, CS = 0 Operation
Figure 8. Internal Serial Clock, Single Cycle Operation
remains in the sleep state until the first rising edge of SCK.
Data is shifted out the SDO pin on each falling edge of
SCK enabling external circuitry to latch data on the rising
edge of SCK. EOC can be latched on the first rising edge
of SCK. On the 32nd falling edge of SCK, SDO goes HIGH
(EOC=1) indicating a new conversion has begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift
out the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
EOC
BIT 31
SDO
SCK
(EXTERNAL)
CS
MSBSIG
BIT 0
LSB24
BIT 5BIT 27 BIT 26BIT 28BIT 29BIT 30
SLEEP DATA OUTPUT CONVERSION
2411 F07
CONVERSION
VCC FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
1 10
2
3
9
4
5
8
6
7
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
2-WIRE I/O
1µF
2.7V TO 5.5V
= 50Hz REJECTION (LTC2411)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2411)
= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)
VCC
LTC2411/
LTC2411-1
SDO
SCK
(INTERNAL)
CS
MSBSIG
BIT 0
LSB24
BIT 5 TEST EOC
BIT 27 BIT 26BIT 28BIT 29BIT 30
EOC
BIT 31
SLEEP DATA OUTPUT CONVERSIONCONVERSION
2411 F08
<tEOCtest
V
CC
10k
Hi-Z Hi-Z Hi-Z Hi-Z
TEST EOC
VCC FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
1 10
2
3
9
4
5
8
6
7
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
3-WIRE
SPI INTERFACE
1µF
2.7V TO 5.5V
= 50Hz REJECTION (LTC2411)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2411)
= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)
VCC
LTC2411/
LTC2411-1
LTC2411/LTC2411-1
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In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resis-
tor is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is automati-
cally selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time tEOCtest after the falling edge of CS
(if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of tEOCtest is 23µs
if the device is using its internal oscillator for the LTC2411
(FO = logic LOW or HIGH) and 26µs for the LTC2411-1
(FO = logic LOW). If FO is driven by an external oscillator of
frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled
HIGH before time tEOCtest, the device remains in the sleep
state. The conversion result is held in the internal static
shift register.
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins
on this first rising edge of SCK and concludes after the
32nd rising edge. Data is shifted out the SDO pin on each
falling edge of SCK. The internally generated serial clock
is output to the SCK pin. This signal may be used to shift
the conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result on the 32nd rising edge of SCK.
After the 32nd rising edge, SDO goes HIGH (EOC = 1),
SCK stays HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
Figure 9. Internal Serial Clock, Reduced Data Output Length
SDO
SCK
(INTERNAL)
CS
>tEOCtest
MSBSIG
BIT 8
TEST EOCTEST EOC BIT 27 BIT 26BIT 28BIT 29BIT 30
EOC
BIT 31
EOC
BIT 0
SLEEP DATA OUTPUT
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
DATA OUTPUT
CONVERSIONCONVERSIONSLEEP
2411 F09
<tEOCtest
V
CC
10k
TEST EOC
VCC FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
1 10
2
3
9
4
5
8
6
7
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
3-WIRE
SPI INTERFACE
2.7V TO 5.5V
1µF = 50Hz REJECTION (LTC2411)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2411)
= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)
VCC
LTC2411/
LTC2411-1
LTC2411/LTC2411-1
21
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APPLICATIONS INFORMATION
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to the
SCK pin or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2411/LTC2411-1’s inter-
nal pull-up at pin SCK is disabled. Normally, SCK is not
externally driven if the device is in the internal SCK timing
mode. However, certain applications may require an exter-
nal driver on SCK. If this driver goes Hi-Z after outputting
a LOW signal, the LTC2411/LTC2411-1’s internal pull-up
remains disabled. Hence, SCK remains LOW. On the next
falling edge of CS, the device is switched to the external SCK
timing mode. By adding an external 10k pull-up resistor
to SCK, this pin goes HIGH once the external driver goes
Hi-Z. On the next CS falling edge, the device will remain
in the internal SCK timing mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as tEOCtest), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin,
the internal pull-up may not be adequate to return SCK
to a HIGH level before CS goes low again. This is not a
concern under normal conditions where CS remains LOW
after detecting EOC = 0. This situation is easily overcome
by adding an external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, sim-
plifying the user interface or isolation barrier.
Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
SDO
SCK
(INTERNAL)
CS
LSB24
MSBSIG
BIT 5 BIT 0BIT 27 BIT 26BIT 28BIT 29BIT 30
EOC
BIT 31
SLEEP
DATA OUTPUT CONVERSIONCONVERSION
2411 F10
VCC FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
1 10
2
3
9
4
5
8
6
7
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1µF
2.7V TO 5.5V
2-WIRE I/O
= 50Hz REJECTION (LTC2411)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2411)
= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)
VCC
LTC2411/
LTC2411-1
LTC2411/LTC2411-1
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The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 1.9V. An internal
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting data. The data output
cycle begins on the first rising edge of SCK and ends after
the 32nd rising edge. Data is shifted out the SDO pin on
each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used to
shift the conversion result into external circuitry. EOC can
be latched on the first rising edge of SCK and the last bit
of the conversion result can be latched on the 32nd rising
edge of SCK. After the 32nd rising edge, SDO goes HIGH
(EOC = 1) indicating a new conversion is in progress. SCK
remains HIGH during the conversion.
PRESERVING THE CONVERTER ACCURACY
The LTC2411/LTC2411-1 are designed to reduce as much
as possible the conversion result sensitivity to device de-
coupling, PCB layout, anti-aliasing circuits, line frequency
perturbations and so on. Nevertheless, in order to preserve
the extreme accuracy capability of this part, some simple
precautions are desirable.
Digital Signal Levels
The LTC2411/LTC2411-1’s digital interface is easy to use.
Its digital inputs (FO, CS and SCK in External SCK mode
of operation) accept standard TTL/CMOS logic levels and
the internal hysteresis receivers can tolerate edge rates
as slow as 100µs. However, some considerations are
required to take advantage of the exceptional accuracy
and low supply current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(VCC–0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (FO, CS and SCK
in External SCK mode of operation) is within this range, the
LTC2411/LTC2411-1 power supply current may increase
even if the signal in question is at a valid logic level. For
micropower operation, it is recommended to drive all
digital input signals to full CMOS levels [VIL < 0.4V and
VOH > (VCC – 0.4V)].
During the conversion period, the undershoot and/or over-
shoot of a fast digital signal connected to the LTC2411/
LTC2411-1 pins may severely disturb the analog to digital
conversion process. Undershoot and overshoot can occur
because of the impedance mismatch at the converter pin
when the transition time of an external control signal is
less than twice the propagation delay from the driver to
LTC2411/LTC2411-1. For reference, on a regular FR-4
board, signal propagation velocity is approximately 183ps/
inch for internal traces and 170ps/inch for surface traces.
Thus, a driver generating a control signal with a minimum
transition time of 1ns must be connected to the converter
pin through a trace shorter than 2.5 inches. This problem
becomes particularly difficult when shared control lines are
used and multiple reflections may occur. The solution is
to carefully terminate all transmission lines close to their
characteristic impedance.
Parallel termination near the LTC2411/LTC2411-1 pin will
eliminate this problem but will increase the driver power
dissipation. A series resistor between 27Ω and 56Ω placed
near the driver or near the LTC2411/LTC2411-1 pin will
also eliminate this problem without additional power dis-
sipation. The actual resistor value depends upon the trace
impedance and connection topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The differential input and ref-
erence architecture reduce substantially the converter’s
sensitivity to ground currents.
LTC2411/LTC2411-1
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APPLICATIONS INFORMATION
Particular attention must be given to the connection of
the FO signal when the LTC2411/LTC2411-1 are used
with an external conversion clock. This clock is active
during the conversion time and the normal mode rejection
provided by the internal digital filter is not very high at
this frequency. A normal mode signal of this frequency at
the converter reference terminals may result into DC gain
and INL errors. A normal mode signal of this frequency at
the converter input terminals may result into a DC offset
error. Such perturbations may occur due to asymmetric
capacitive coupling between the FO signal trace and the
converter input and/or reference connection traces. An
immediate solution is to maintain maximum possible
separation between the FO signal trace and the input/ref-
erence signals. When the FO signal is parallel terminated
near the converter, substantial AC current is flowing in the
loop formed by the FO connection trace, the termination
and the ground return path. Thus, perturbation signals
may be inductively coupled into the converter input and/
or reference. In this situation, the user must reduce to a
minimum the loop area for the FO signal as well as the loop
area for the differential input and reference connections.
Driving the Input and Reference
The input and reference pins of the LTC2411/LTC2411-1
converter are directly connected to a network of sampling
capacitors. Depending upon the relation between the dif-
ferential input voltage and the differential reference voltage,
these capacitors are switching between these four pins
transferring small amounts of charge in the process. A
simplified equivalent circuit is shown in Figure 11.
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, REF+ or REF–) can
be considered to form, together with R
SW and CEQ (see
Figure 11), a first order passive network with a time
constant τ = (RS + RSW) • CEQ. The converter is able to
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant τ. The sampling process on
the four input analog pins is quasi-independent so each
time constant should be considered by itself and, under
worst-case circumstances, the errors may add.
When using the internal oscillator (FO = LOW or HIGH),
the LTC2411 (LTC2411-1)’s front-end switched-capacitor
network is clocked at 76800Hz (69900Hz) corresponding
Figure 11. LTC2411/LTC2411-1 Equivalent Analog Input Circuit
VREF+
VIN+
V
CC
RSW (TYP)
20k
ILEAK
ILEAK
VCC
ILEAK
ILEAK
VCC
RSW (TYP)
20k
CEQ
6pF
(TYP)
RSW (TYP)
20k
ILEAK
IIN+
VIN–
IIN–
IREF+
IREF–
2411 F11
ILEAK
VCC
ILEAK
ILEAK
SWITCHING FREQUENCY
fSW = 76800Hz INTERNAL OSCILLATOR (FO = LOW OR HIGH)
f
SW
= 0.5 • f
EOSC
EXTERNAL OSCILLATOR
VREF–
RSW (TYP)
20k
I IN+
( )
AVG =
V
IN
+V
INCM
−V
REFCM
0.5•REQ
I IN−
( )
AVG =−V
IN +V
INCM −V
REFCM
0.5•REQ
I REF+
( )
AVG =1.5•V
REF −V
INCM +V
REFCM
0.5•REQ
−V
IN
2
V
REF •REQ
I REF−
( )
AVG =−1.5•V
REF −V
INCM +V
REFCM
0.5•REQ
+V
IN
2
V
REF •REQ
where:
V
REF =REF+−REF−
V
REFCM =REF++REF−
2
V
IN =IN+−IN−
V
INCM =IN+−IN−
2
REQ =10.8MΩINTERNAL OSCILLATOR 60Hz Notch FO=LOW
( )
LTC2411
( )
REQ =13.0MΩINTERNAL OSCILLATOR 50Hz Notch FO=HIGH
( )
LTC2411
( )
REQ =11.9MΩINTERNAL OSCILLATOR FO=LOW
( )
LTC2411−1
( )
REQ =1.67•1012
( )
/ f
EOSC EXTERNAL OSCILLATOR
LTC2411/LTC2411-1
24
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APPLICATIONS INFORMATION
to a 13µs (14.2µs) sampling period. Thus, for settling
errors of less than 1ppm, the driving source impedance
should be chosen such that τ ≤ 13µs/14 = 920ns (1.02µs).
When an external oscillator of frequency fEOSC is used,
the sampling period is 2/fEOSC and, for a settling error of
less than 1ppm, τ ≤ 0.14/fEOSC.
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 11 shows the
mathematical expressions for the average bias currents
flowing through the IN+ and IN– pins as a result of the
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 12. The CPAR capacitor
includes the LTC2411/LTC2411-1 pin capacitance (5pF
typical) plus the capacitance of the test fixture used to
obtain the results shown in Figures 13 and 14. A careful
implementation can bring the total input capacitance (CIN
+ CPAR) closer to 5pF thus achieving better performance
than the one predicted by Figures 13 and 14. The effect
of the input dynamic current is almost the same for the
LTC2411 and the LTC2411-1 and measurements of the
LTC2411 with FO = GND are plotted out as a typical case.
For simplicity, two distinct situations can be considered.
For relatively small values of input capacitance (CIN <
0.01µF), the voltage on the sampling capacitor settles
almost completely and relatively large values for the source
impedance result in only small errors. Such values for CIN
will deteriorate the converter offset and gain performance
without significant benefits of signal filtering and the user
is advised to avoid them. Nevertheless, when small val-
ues of CIN are unavoidably present as parasitics of input
multiplexers, wires, connectors or sensors, the LTC2411/
LTC2411-1 can maintain their exceptional accuracy while
operating with relative large values of source resistance
as shown in Figures 13 and 14. These measured results
may be slightly different from the first order approxima-
tion suggested earlier because they include the effect of
the actual second order input network together with the
nonlinear settling process of the input amplifiers. For
small CIN values, the settling on IN+ and IN– occurs almost
independently and there is little benefit in trying to match
the source impedance for the two pins.
Figure 12. An RC Network at IN+ and IN–
Figure 13. +FS Error vs RSOURCE at IN+ or IN– (Small CIN)
Figure 14. –FS Error vs RSOURCE at IN+ or IN– (Small CIN)
CIN
2411 F12
V
INCM + 0.5VIN
R
SOURCE
CPAR
≅20pF
CIN
V
INCM – 0.5VIN
RSOURCE
CPAR
≅20pF
IN+
IN–
LTC2411/
LTC2411-1
RSOURCE (Ω)
1 10 100 1k 10k
100k
+FS ERROR (ppm OF V
REF
)
2411 F13
50
40
30
20
10
0
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 5V
IN– = 2.5V
FO = GND
TA = 25°C
CIN = 0.01µF
CIN = 0pF
CIN = 0.001µF
CIN = 100pF
RSOURCE (Ω)
1 10 100 1k 10k
100k
–FS ERROR (ppm OF V
REF
)
2411 F14
0
–10
–20
–30
–40
–50
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = GND
IN– = 2.5V
FO = GND
TA = 25°C
CIN = 0pF
CIN = 0.001µF
CIN = 100pF
CIN = 0.01µF
LTC2411/LTC2411-1
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APPLICATIONS INFORMATION
Larger values of input capacitors (CIN > 0.01µF) may be
required in certain configurations for anti-aliasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance. For
the LTC2411, when FO = LOW (internal oscillator and 60Hz
notch), the typical differential input resistance is 5.4MΩ
which will generate a gain error of approximately 0.093ppm
for each ohm of source resistance driving IN+ or IN–. When
FO = HIGH (internal oscillator and 50Hz notch), the typical
differential input resistance is 6.5MΩ which will generate
a gain error of approximately 0.077ppm for each ohm of
source resistance driving IN+ or IN–. For the LTC2411-1,
the typical differential input resistance is 6MΩ which
will generate a gain error of approximately 0.084ppm for
each ohm of source resistance driving IN+ or IN– (FO =
LOW). When FO is driven by an external oscillator with a
frequency fEOSC (external conversion clock operation), the
typical differential input resistance is 0.83 • 1012/fEOSCΩ
and each ohm of source resistance driving IN+ or IN– will
result in 0.59 • 10–6 • fEOSCppm gain error. The effect of
the source resistance on the two input pins is additive with
respect to this gain error. The typical +FS and –FS errors
as a function of the sum of the source resistance seen by
IN+ and IN– for large values of CIN are shown in Figure 15.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins IN+
and IN– and with the difference between the input and refer-
ence common mode voltages. While the input drive circuit
nonzero source impedance combined with the converter
average input current will not degrade the INL performance,
indirect distortion may result from the modulation of the
offset error by the common mode component of the input
signal. Thus, when using large CIN capacitor values, it is
advisable to carefully match the source impedance seen
by the IN+ and IN– pins. For the LTC2411, when FO = LOW
(internal oscillator and 60Hz notch), every 1Ω mismatch in
source impedance transforms a full-scale common mode
input signal into a differential mode input signal of 0.093ppm.
When FO = HIGH (internal oscillator and 50Hz notch), every
1Ω mismatch in source impedance transforms a full-scale
common mode input signal into a differential mode input
signal of 0.077ppm. For the LTC2411-1, when internal os-
cillator is used (FO = LOW), every 1Ω mismatch in source
impedance transforms a full-scale common mode input
signal into a differential mode input signal of 0.084ppm.
When FO is driven by an external oscillator with a frequency
fEOSC, every 1Ω mismatch in source impedance transforms a
full-scale common mode input signal into a differential mode
input signal of 0.59 • 10–6 • fEOSCppm. Figure 16 shows the
typical offset error due to input common mode voltage for
various values of source resistance imbalance between the
IN+ and IN– pins when large CIN values are used.
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
Figure 15a. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)Figure 15b. –FS Error vs RSOURCE at IN+ or IN– (Large CIN)
RSOURCE (Ω)
0100 200 300 400 500 600 700 800 900
1000
+FS ERROR (ppm OF V
REF
)
2411 F15a
120
100
80
60
40
20
0
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 3.75V
IN– = 1.25V
FO = GND
TA = 25°C CIN = 1µF
CIN = 0.1µF
CIN = 0.01µF
CIN = 10µF
RSOURCE (Ω)
0100 200 300 400 500 600 700 800 900
1000
–FS ERROR (ppm OF V
REF
)
2411 F15b
–120
–100
–80
–60
–40
–20
0
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 1.25V
IN– = 3.75V
FO = GND
TA = 25°C
CIN = 1µF
CIN = 0.1µF
CIN = 0.01µF
CIN = 10µF
LTC2411/LTC2411-1
26
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APPLICATIONS INFORMATION
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 1%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are used
for the external source impedance seen by IN+ and IN–,
the expected drift of the dynamic current, offset and gain
errors will be insignificant (about 1% of their respective
values over the entire temperature and voltage range). Even
for the most stringent applications, a one-time calibration
operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 100Ω source resistance will create
a 0.1µV typical and 1µV maximum offset voltage.
Reference Current
In a similar fashion, the LTC2411/LTC2411-1 sample the
differential reference pins REF+ and REF– transferring small
amount of charge to and from the external driving circuits
thus producing a dynamic reference current. This current
does not change the converter offset, but it may degrade
the gain and INL performance. The effect of this current
can be analyzed in the same two distinct situations.
For relatively small values of the external reference capaci-
tors (CREF < 0.01µF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 0.01µF) may
be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi constant
reference differential impedance. For the LTC2411, when
FO = LOW (internal oscillator and 60Hz notch), the typical
differential reference resistance is 3.9MΩ which will gener-
ate a gain error of approximately 0.13ppm for each ohm of
source resistance driving REF+ or REF–. When FO = HIGH
(internal oscillator and 50Hz notch), the typical differential
reference resistance is 4.68MΩ which will generate a gain
error of approximately 0.11ppm for each ohm of source
resistance driving REF+ or REF–. For the LTC2411-1, when
internal oscillator is used (FO = LOW), the typical differ-
ential reference resistance is 4.29MΩ which will generate
a gain error of approximately 0.12ppm for each ohm of
source resistance driving REF+ or REF–. When FO is driven
by an external oscillator with a frequency fEOSC (external
conversion clock operation), the typical differential refer-
ence resistance is 0.60 • 1012/fEOSCΩ and each ohm of
source resistance driving REF+ or REF– will result in 0.823 •
10–6 • fEOSCppm gain error. The effect of the source resis-
tance on the two reference pins is additive with respect to
this gain error. The typical FS errors for various combina-
tions of source resistance seen by the REF+ and REF– pins
and external capacitance CREF connected to these pins are
shown in Figures 17 and 18. Typical –FS errors are similar
to +FS errors with opposite polarity.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
For LTC2411, when FO = LOW (internal oscillator and
60Hz notch), every 100Ω of source resistance driving
REF+ or REF– translates into about 0.45ppm additional
INL error. When FO = HIGH (internal oscillator and 50Hz
Figure 16. Offset Error vs Common Mode Voltage
(VINCM = IN+ = IN–) and Input Source Resistance Imbalance
(∆RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1µF)
VINCM (V)
0
OFFSET ERROR (ppm OF V
REF
)
30
–30
40
–40
50
–50 4
2411 F16
20
–20
10
–10
0
1
C
D
F
0.5 21.5 3 3.5 4.5
2.5 5
FO = GND
TA = 25°C
RSOURCEIN– = 500Ω
CIN = 10µF
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = IN– = VINCM
A: ∆RIN = +400Ω
B: ∆RIN = +200Ω
C: ∆RIN = +100Ω
D: ∆RIN = 0Ω
E: ∆RIN = –100Ω
F: ∆RIN = –200Ω
G: ∆RIN = –400Ω
E
B
A
G
LTC2411/LTC2411-1
27
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APPLICATIONS INFORMATION
RSOURCE (Ω)
1 10 100 1k 10k
100k
+FS ERROR (ppm OF V
REF
)
2411 F17a
0
–10
–20
–30
–40
–50
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 3.75V
IN– = 1.25V
FO = GND
TA = 25°C
CREF = 0.01µF
CREF = 0.001µF
CREF = 100pF
CREF = 0pF
RSOURCE (Ω)
1 10 100 1k 10k
100k
–FS ERROR (ppm OF V
REF
)
2411 F17b
50
40
30
20
10
0
CREF = 0.01µF
CREF = 0.001µF
CREF = 100pF
CREF = 0pF
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 1.25V
IN– = 3.75V
FO = GND
TA = 25°C
RSOURCE (Ω)
0
+FS ERROR (ppm OF V
REF
)
0
–20
–40
–60
–80
–100
–120
–140
–160 800
2411 F18a
200 400 600
1000
700100 300 500 900
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 3.75V
IN– = 1.25V
FO = GND
TA = 25°C
CREF = 0.01µF
CREF = 1µF
CREF = 0.1µF
CREF = 10µF
RSOURCE (Ω)
0
–FS ERROR (ppm OF V
REF
)
160
140
120
100
80
60
40
20
0800
2411 F18b
200 400 600
1000
700100 300 500 900
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 1.25V
IN– = 3.75V
FO = GND
TA = 25°C
CREF = 0.01µF
CREF = 1µF
CREF = 0.1µF
CREF = 10µF
VINDIF/VREFDIF
–0.5–0.4– 0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5
INL (ppm OF V
REF
)
10
9
6
4
2
0
–2
–4
–6
–8
–10
VCC = 5V
REF+ = 5V
REF– = GND
V
INCM
= 0.5 • (IN+ + IN–) = 2.5V
FO = GND
CREF = 10µF
TA = 25°C
RSOURCE = 2k
RSOURCE = 1k
RSOURCE = 500Ω
2411 F19
notch), every 100Ω of source resistance driving REF+
or REF– translates into about 0.37ppm additional INL
error. For the LTC2411-1, when FO = LOW, every 100Ω
of source resistance driving REF+ or REF– translates into
about 0.41ppm additional INL error. When FO is driven
by an external oscillator with a frequency fEOSC, every
100Ω of source resistance driving REF+ or REF– translates
into about 2.91 • 10–6 • fEOSCppm additional INL error.
Figure19 shows the typical INL error due to the source
resistance driving the REF+ or REF– pins when large CREF
values are used. The effect of the source resistance on
the two reference pins is additive with respect to this INL
error. In general, matching of source impedance for the
REF+ and REF– pins does not help the gain or the INL er-
ror. The user is thus advised to minimize the combined
source impedance driving the REF+ and REF– pins rather
than to try to match it.
Figure 18a. +FS Error vs RSOURCE at REF+ or REF– (Large CIN)
Figure 17b. –FS Error vs RSOURCE at REF+ or REF– (Small CIN)
Figure 18b. –FS Error vs RSOURCE at REF+ or REF– (Large CIN)
Figure 19. INL vs Differential Input Voltage (VIN = IN+ = IN–)
and Reference Source Resistance (RSOURCE at REF+ and REF–)
for Large CREF Values (CREF ≥ 1µF)
Figure 17a. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)
LTC2411/LTC2411-1
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APPLICATIONS INFORMATION
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors
and upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 1%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by REF+
and REF–, the expected drift of the dynamic current gain
error will be insignificant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications, a one-time calibration operation
may be sufficient.
In addition to the reference sampling charge, the refer-
ence pins ESD protection diodes have a temperature de-
pendent leakage current. This leakage current, nominally
1nA (±10nA max), results in a small gain error. A 100Ω
source resistance will create a 0.05µV typical and 0.5µV
maximum full-scale error.
Output Data Rate
When using its internal oscillator, the LTC2411 can produce
up to 7.5 readings per second with a notch frequency of
60Hz (FO = LOW) and 6.25 readings per second with a
notch frequency of 50Hz (FO = HIGH) and the LTC2411-1
can produce up to 6.8 readings per second with FO = LOW.
The actual output data rate will depend upon the length of
the sleep and data output phases which are controlled by
the user and which can be made insignificantly short. When
operated with an external conversion clock (FO connected
to an external oscillator), the LTC2411/LTC2411-1 output
data rate can be increased as desired. The duration of the
conversion phase is 20510/fEOSC. If fEOSC = 153600Hz, the
converter behaves as if the internal oscillator is used and
the notch is set at 60Hz. There is no significant difference
in the LTC2411/LTC2411-1 performance between these
two operation modes.
An increase in fEOSC over the nominal 153600Hz will
translate into a proportional increase in the maximum
output data rate. This substantial advantage is neverthe-
less accompanied by three potential effects, which must
be carefully considered.
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line fre-
quency. In many applications, the subsequent performance
degradation can be substantially reduced by relying upon
the LTC2411/LTC2411-1’s exceptional common mode
rejection and by carefully eliminating common mode to
differential mode conversion sources in the input circuit.
The user should avoid single-ended input filters and should
maintain a very high degree of matching and symmetry
in the circuits driving the IN+ and IN– pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (CIN, CREF) are used, the
previous section provides formulae for evaluating the effect
of the source resistance upon the converter performance for
any value of fEOSC. If small external input and/or reference
capacitors (CIN, CREF) are used, the effect of the external
source resistance upon the LTC2411/LTC2411-1 typical
performance can be inferred from Figures 13, 14 and 17
in which the horizontal axis is scaled by 153600/fEOSC.
Third, an increase in the frequency of the external oscil-
lator above 460800Hz (a more than 3× increase in the
output data rate) will start to decrease the effectiveness
of the internal auto-calibration circuits. This will result
in a progressive degradation in the converter accuracy
and linearity. Typical measured performance curves for
output data rates up to 25 readings per second are shown
in Figures20 to 27. In order to obtain the highest pos-
sible level of accuracy from this converter at output data
rates above 7.5 readings per second, the user is advised
to maximize the power supply voltage used and to limit
the maximum ambient operating temperature. In certain
circumstances, a reduction of the differential reference
voltage may be beneficial.
Input Bandwidth
The combined effect of the internal sinc4 digital filter and
of the analog and digital auto-calibration circuits deter-
mines the LTC2411/LTC2411-1 input bandwidth. When
the internal oscillator is used, the 3dB input bandwidth
LTC2411/LTC2411-1
29
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APPLICATIONS INFORMATION
010
515 20
25
OUTPUT DATA RATE (READINGS/SEC)
–120
OFFSET ERROR (ppm OF V
REF
)
–80
–40
0
120
2411 F20
40
80
VCC = 5V
VREF = 5V
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
TA = 85°C
TA = 25°C
010
515 20 25
OUTPUT DATA RATE (READINGS/SEC)
–50
+FS ERROR (ppm OF V
REF
)
50
150
250
0
100
200
2411 F21
TA = 85°C
VCC = 5V
VREF = 5V
IN+ = 3.75V
IN– = 1.25V
FO = EXT OSC
TA = 25°C
OUTPUT DATA RATE (READINGS/SEC)
0
–FS ERROR (ppm OF V
REF
)
0
50
100
2411 F22
–50
–100
–150 10
515 20
25
TA = 85°C
VCC = 5V
VREF = 5V
IN+ = 1.25V
IN– = 3.75V
FO = EXT OSC
TA = 25°C
OUTPUT DATA RATE (READINGS/SEC)
16
RESOLUTION (BITS)
18
20
22
17
19
21
20
2411 F23
25100 155
TA = 85°C
VCC = 5V
VREF = 5V
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
RES = LOG2(VREF/NOISERMS)
TA = 25°C
OUTPUT DATA RATE (READINGS/SEC)
10
RESOLUTION (BITS)
14
18
22
12
16
20
2411 F24
TA = 85°C
VCC = 5V
VREF = 5V
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
RES = LOG2(VREF/INLMAX)
TA = 25°C
20
25
100 155
OUTPUT DATA RATE (READINGS/SEC)
–120
OFFSET ERROR (ppm OF V
REF
)
–60
–20
40
–80
–100
–40
20
0
2411 F25
VCC = 5V
REF– = GND
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
TA = 25°C
VREF = 2.5V
VREF = 5V
20
25
100 155
Figure 23. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 24. Resolution (INLRMS ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 21. +FS Error vs Output Data Rate and Temperature
Figure 22. –FS Error vs Output Data Rate and Temperature
Figure 20. Offset Error vs Output Data Rate and Temperature
Figure 25. Offset Error vs Output
Data Rate and Reference Voltage
LTC2411/LTC2411-1
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APPLICATIONS INFORMATION
of the LTC2411 is 3.63Hz for 60Hz notch frequency (FO =
LOW) and 3.02Hz for 50Hz notch frequency (FO = HIGH).
The 3dB input bandwidth for the LTC2411-1 is 3.30Hz
(FO = LOW). If an external conversion clock generator of
frequency fEOSC is connected to the FO pin, the 3dB input
bandwidth is 0.236 • 10–6 • fEOSC.
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a first order filter with the pole located
at the 3dB frequency. When the internal oscillator is used,
the shape of the LTC2411/LTC2411-1 input bandwidth is
shown in Figure28. When an external oscillator of frequency
fEOSC is used, the shape of the LTC2411/LTC2411-1 input
bandwidth can be derived from Figure28, FO = LOW curve
of the LTC2411 in which the horizontal axis is scaled by
fEOSC/153600.
The conversion noise (1.45µVRMS typical for VREF = 5V)
can be modeled as a white noise source connected to a
noise free converter. The noise spectral density is 70nV/√Hz
for an infinite bandwidth source and 126nV/√Hz for a
single 0.5MHz pole source. From these numbers, it is
clear that particular attention must be given to the design
of external amplification circuits. Such circuits face the
simultaneous requirements of very low bandwidth (just a
few Hz) in order to reduce the output referred noise and
relatively high bandwidth (at least 500kHz) necessary to
drive the input switched-capacitor network. A possible
Figure 27. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Reference Voltage
Figure 26. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Reference Voltage
Figure 28. Input Signal Bandwidth
Using the Internal Oscillator
solution is a high gain, low bandwidth amplifier stage
followed by a high bandwidth unity-gain buffer.
When external amplifiers are driving the LTC2411/
LTC2411-1, the ADC input referred system noise calculation
can be simplified by Figure 29. The noise of an amplifier
driving the LTC2411/LTC2411-1 input pin can be modeled
as a band-limited white noise source. Its bandwidth can be
approximated by the bandwidth of a single pole lowpass
filter with a corner frequency fi. The amplifier noise spectral
density is ni. From Figure29, using fi as the x-axis selector,
we can find on the y-axis the noise equivalent bandwidth
freqi of the input driving amplifier. This bandwidth includes
OUTPUT DATA RATE (READINGS/SEC)
0
RESOLUTION (BITS)
20
21
2411 F26
19
18 20
25
22
10
515
VCC = 5V
REF– = GND
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
RES = LOG2(VREF/NOISERMS)
TA = 25°C
VREF = 2.5V
VREF = 5V
OUTPUT DATA RATE (READINGS/SEC)
10
RESOLUTION (BITS)
14
18
22
12
16
20
2411 F27
VCC = 5V
REF– = GND
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
RES = LOG2(VREF/INLMAX)
TA = 25°C
VREF = 5V
VREF = 2.5V
020 25
10
515
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
INPUT SIGNAL ATTENUATION (dB)
2411 F28
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–6.0
FO = HIGH
(LTC2411)
FO = LOW
(LTC2411)
FO = LOW
(LTC2411-1)
LTC2411/LTC2411-1
31
2411fa
For more information www.linear.com/LTC2411
APPLICATIONS INFORMATION
the band limiting effects of the ADC internal calibration
and filtering. The noise of the driving amplifier referred
to the converter input and including all these effects can
be calculated as N= ni • √freqi. The total system noise
(referred to the LTC2411/LTC2411-1 input) can now be
obtained by summing as square root of sum of squares
the three ADC input referred noise sources: the LTC2411/
LTC2411-1 internal noise (1.45µV), the noise of the IN+
driving amplifier and the noise of the IN– driving amplifier.
If the FO pin is driven by an external oscillator of frequency
fEOSC, Figure 29 can still be used for noise calculation if
the x-axis is scaled by fEOSC/153600. For large values of
the ratio fEOSC/153600, the Figure 29 plot accuracy begins
to decrease, but in the same time the LTC2411/LTC2411-1
noise floor rises and the noise contribution of the driving
amplifiers lose significance.
Normal Mode Rejection and Anti-Aliasing
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital filtering. Combined
with a large oversampling ratio, the LTC2411/LTC2411-1
significantly simplifies anti-aliasing filter requirements.
The sinc4 digital filter provides greater than 120dB normal
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (fS). The
LTC2411/LTC2411-1’s auto-calibration circuits further
simplify the anti-aliasing requirements by additional normal
mode signal filtering both in the analog and digital domain.
Independent of the operating mode, fS = 256 • fN = 2048
• fOUTMAX where fN is the notch frequency and fOUTMAX is
the maximum output data rate. In the internal oscillator
mode, for the LTC2411, fS = 12800Hz with a 50Hz notch
setting and fS = 15360Hz with a 60Hz notch setting. For
the LTC2411-1, fS = 13980Hz (FO = LOW). In the external
oscillator mode, fS = fEOSC/10.
The combined normal mode rejection performance is
shown in Figure30 for the internal oscillator with 50Hz
notch setting (FO = HIGH) and in Figure31 for the internal
oscillator with FO = LOW and for the external oscillator
mode. The regions of low rejection occurring at integer
multiples of fS have a very narrow bandwidth. Magnified
details of the normal mode rejection curves are shown
Figure 30. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch (LTC2411)
Figure 31. Input Normal Mode Rejection, Internal
Oscillator and FO = LOW or External Oscillator
Figure 29. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz)
1
INPUT REFERRED NOISE
EQUIVALENT BANDWIDTH (Hz)
10
100
1000
10 100 1k 10k 100k
1M
2411 G29
0.10.1 1
FO = LOW
FO = HIGH
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0 fS2fS3fS4fS5fS6fS7fS8fS9fS10fS
11fS
12f
S
INPUT NORMAL MODE REJECTION (dB)
2411 F30
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
FO = HIGH FO = LOW OR
FO
= EXTERNAL OSCILLATOR,
fEOSC = 10 • fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0 fS
INPUT NORMAL MODE REJECTION (dB)
2411 F31
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 2fS3fS4fS5fS6fS7fS8fS9fS10fS
LTC2411/LTC2411-1
32
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APPLICATIONS INFORMATION
Figure 32. Input Normal Mode Rejection Figure 33. Input Normal Mode Rejection
Figure 34. Input Normal Mode Rejection
vs Input Frequency (LTC2411)
Figure 35. Input Normal Mode Rejection
vs Input Frequency (LTC2411)
in Figure32 (rejection near DC) and Figure33 (rejection
at fS = 256fN) where fN represents the notch frequency.
These curves have been derived for the external oscilla-
tor mode but they can be used in all operating modes by
appropriately selecting the fN value.
The user can expect to achieve in practice this level of
performance using the internal oscillator as it is demon-
strated by Figures 34 to 36. Typical measured values of
the normal mode rejection of the LTC2411 operating with
an internal oscillator and a 60Hz notch setting are shown
in Figure 34 superimposed over the theoretical calculated
curve. Similarly, typical measured values of the normal
mode rejection of the LTC2411 operating with an internal
oscillator and a 50Hz notch setting are shown in Figure
35 superimposed over the theoretical calculated curve.
As a result of these remarkable normal mode specifica-
tions, minimal (if any) anti-alias filtering is required in front
of the LTC2411/LTC2411-1. If passive RC components
are placed in front of the LTC2411/LTC2411-1, the input
dynamic current should be considered (see Input Current
section). In cases where large effective RC time constants
are used, an external buffer amplifier may be required to
minimize the effects of dynamic input current.
Traditional high order delta-sigma modulators, while
providing very good linearity and resolution, suffer from
potential instabilities at large input signal levels. The
proprietary architecture used for the LTC2411/LTC2411-1
third order modulator resolves this problem and guaran-
tees a predictable stable behavior at input signal levels of
INPUT SIGNAL FREQUENCY (Hz)
INPUT NORMAL MODE REJECTION (dB)
2411 F32
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 fN
0 2fN3fN4fN5fN6fN7fN8f
N
INPUT SIGNAL FREQUENCY (Hz)
250fN252fN254fN256fN258fN260fN262f
N
INPUT NORMAL MODE REJECTION (dB)
2411 F33
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
INPUT FREQUENCY (Hz)
0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225
240
NORMAL MODE REJECTION (dB)
2411 F34
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VINCM = 2.5V
VIN(P-P) = 5V
FO = GND
TA = 25°C
MEASURED DATA
CALCULATED DATA
INPUT FREQUENCY (Hz)
0 25 50 75 100 125 150 175
200
NORMAL MODE REJECTION (dB)
2411 F35
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VINCM = 2.5V
VIN(P-P) = 5V
FO = 5V
TA = 25°C
MEASURED DATA
CALCULATED DATA
LTC2411/LTC2411-1
33
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APPLICATIONS INFORMATION
Figure 36. Input Normal Mode Rejection
vs Input Frequency (LTC2411-1)
Figure 37. Measured Input Normal Mode Rejection
vs Input Frequency (LTC2411)
Figure 38. Measured Input Normal Mode Rejection
vs Input Frequency (LTC2411)
up to 150% of full scale. In many industrial applications,
it is not uncommon to have to measure microvolt level
signals superimposed over volt level perturbations and
LTC2411/LTC2411-1 are eminently suited for such tasks.
When the perturbation is differential, the specification of
interest is the normal mode rejection for large input signal
levels. With a reference voltage VREF=5V, the LTC2411/
LTC2411-1 have a full-scale differential input range of
5V peak-to-peak. Figures 37 and 38 show measurement
results for the LTC2411 normal mode rejection ratio with
a 7.5V peak-to-peak (150% of full scale) input signal
superimposed over the more traditional normal mode
rejection ratio results obtained with a 5V peak-to-peak
(full scale) input signal and Figure 39 shows the cor-
responding measurement result for the LTC2411-1. It is
clear that the LTC2411/LTC2411-1 rejection performance
is maintained with no compromises in this extreme situ-
ation. When operating with large input signal levels, the
user must observe that such signals do not violate the
device absolute maximum ratings.
BRIDGE APPLICATIONS
Typical strain gauge based bridges deliver only 2mV/Volt
of excitation. As the maximum reference voltage of the
LTC2411/LTC2411-1 is 5V, remote sensing of applied
excitation without additional circuitry requires that exci-
tation be limited to 5V. This gives only 10mV full scale,
which can be resolved to 1 part in 5000 without averaging.
For many solid state sensors, this is comparable to the Figure 39. Measured Input Normal Mode Rejection
vs Input Frequency (LTC2411-1)
INPUT FREQUENCY (Hz)
0 20 40 60 80 100 120 140 160 180 200
220
NORMAL MODE REJECTION (dB)
2411 F36
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
REF– = GND
VINCM = 2.5V
VIN(P-P) = 5V
FO = GND
TA = 25°C
MEASURED DATA
CALCULATED DATA
INPUT FREQUENCY (Hz)
0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225
240
NORMAL MODE REJECTION (dB)
2411 F37
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VINCM = 2.5V
FO = GND
TA = 25°C
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
INPUT FREQUENCY (Hz)
0
NORMAL MODE REJECTION (dB)
2411 F38
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VINCM = 2.5V
FO = 5V
TA = 25°C
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
25 50 75 100 125 150 175
200
INPUT FREQUENCY (Hz)
0 20 40 60 80 100 120 140 160 180 200
220
NORMAL MODE REJECTION (dB)
2411 F39
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
REF– = GND
VINCM = 2.5V
FO = GND
TA = 25°C
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
LTC2411/LTC2411-1
34
2411fa
For more information www.linear.com/LTC2411
APPLICATIONS INFORMATION
sensor. Averaging 64 samples however reduces the noise
level by a factor of eight, bringing the resolving power to
1 part in 40000, comparable to better weighing systems.
Hysteresis and creep effects in the load cells are typically
much greater than this. Most applications that require
strain measurements to this level of accuracy are measur-
ing slowly changing phenomena, hence the time required
to average a large number of readings is usually not an
issue. For those systems that require accurate measure-
ment of a small incremental change on a significant tare
weight, the lack of history effects in the LTC2400 family
is of great benefit.
For those applications that cannot be fulfilled by the
LTC2411/LTC2411-1 alone, compensating for error in
external amplification can be done effectively due to
the “no latency” feature of the LTC2411/LTC2411-1. No
latency operation allows samples of the amplifier offset
and gain to be interleaved with weighing measurements.
The use of correlated double sampling allows suppression
of 1/f noise, offset and thermocouple effects within the
bridge. Correlated double sampling involves alternating the
polarity of excitation and dealing with the reversal of input
polarity mathematically. Alternatively, bridge excitation can
be increased to as much as ±10V, if one of several preci-
sion attenuation techniques is used to produce a precision
divide operation on the reference signal. Another option
is the use of a reference within the 5V input range of the
LTC2411/LTC2411-1 and developing excitation via fixed
gain, or LTC1043 based voltage multiplication, along with
remote feedback in the excitation amplifiers, as shown in
Figures 45 and 46.
Figure 40 shows an example of a simple bridge connection.
Note that it is suitable for any bridge application where
measurement speed is not of the utmost importance.
For many applications where large vessels are weighed,
the average weight over an extended period of time is of
concern and short term weight is not readily determined
due to movement of contents, or mechanical resonance.
Often, large weighing applications involve load cells
located at each load bearing point, the output of which
can be summed passively prior to the signal processing
circuitry, actively with amplification prior to the ADC, or
can be digitized via multiple ADC channels and summed
mathematically. The mathematical summation of the output
of multiple LTC2411/LTC2411-1’s provide the benefit of a
root square reduction in noise. The low power consumption
of the LTC2411/LTC2411-1 make it attractive for multidrop
communication schemes where the ADC is located within
the load-cell housing.
A direct connection to a load cell is perhaps best incorpo-
rated into the load-cell body, as minimizing the distance
to the sensor largely eliminates the need for protection
devices, RFI suppression and wiring. The LTC2411/
Figure 40. Simple Bridge Connection
REF+
REF–
SDO
SCK
IN+
IN–
CS
GND
VCC
FO
2
R1
8
3350Ω
BRIDGE
9
4
5
2411 F40
7
6
1
10
+
R2
R1 AND R2 CAN BE USED TO INCREASE TOLERABLE AC COMPONENT ON REF SIGNALS
LT1019
LTC2411/
LTC2411-1
LTC2411/LTC2411-1
35
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For more information www.linear.com/LTC2411
APPLICATIONS INFORMATION
LTC2411-1 exhibit extremely low temperature dependent
drift. As a result, exposure to external ambient temperature
ranges does not compromise performance. The incorpora-
tion of any amplification considerably complicates thermal
stability, as input offset voltages and currents, temperature
coefficient of gain settling resistors all become factors.
The circuit in Figure 41 shows an example of a simple
amplification scheme. This example produces a differ-
ential output with a common mode voltage of 2.5V, as
determined by the bridge. The use of a true three ampli-
fier instrumentation amplifier is not necessary, as the
LTC2411/LTC2411-1 have common mode rejection far
beyond that of most amplifiers. The LTC1051 is a dual
autozero amplifier that can be used to produce a gain of
30 before its input referred noise dominates the LTC2411/
LTC2411-1 noise. This example shows a gain of 34, that
is determined by a feedback network built using a resistor
array containing eight individual resistors. The resistors
are organized to optimize temperature tracking in the pres-
ence of thermal gradients. The second LTC1051 buffers
Figure 41. Using Autozero Amplifiers to Reduce Input Referred Noise
the low noise input stage from the transient load steps
produced during conversion.
The gain stability and accuracy of this approach is very
good, due to a statistical improvement in resistor matching
due to individual error contribution being reduced. A gain
of 34 may seem low, when compared to common practice
in earlier generations of load-cell interfaces, however the
accuracy of the LTC2411/LTC2411-1 changes the rationale.
Achieving high gain accuracy and linearity at higher gains
may prove difficult, while providing little benefit in terms
of noise reduction.
At a gain of 100, the gain error that could result from
typical open-loop gain of 160dB is –1ppm, however,
worst-case is at the minimum gain of 116dB, giving a
gain error of –158ppm. Worst-case gain error at a gain
of 34, is –54ppm. The use of the LTC1051A reduces the
worst-case gain error to –33ppm. The advantage of gain
higher than 34, then becomes dubious, as the input re-
ferred noise sees little improvement1 and gain accuracy
is potentially compromised.
0.1µF
8
0.1µF 0.1µF
REF+
REF–
SDO
SCK
IN+
IN–
CS
GND
VCC
FO
2 8
5V
REF
3
350Ω
BRIDGE
9
4
5
2411 F41
7
6
1
10
RN1 = 5k × 8 RESISTOR ARRAY
U1A, U1B, U2A, U2B = 1/2 LTC1051
–
+
3
2
8
4
U1A
4
5V
+
–
6
5
RN1
1
16
15
2
6 11
7
1
14
3
7 10
4
13
8 9
5 12
U1B
–
+
2
3
U2A
5V
1
–
+
6
5
U2B 7
LTC2411/
LTC2411-1
1Input referred noise for AV = 34 is approximately 0.05µVRMS, whereas at a gain of 50, it would
be 0.048µVRMS.
LTC2411/LTC2411-1
36
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APPLICATIONS INFORMATION
Figure 42. Bridge Amplification Using a Single Amplifier
Note that this 4-amplifier topology has advantages over
the typical integrated 3-amplifier instrumentation amplifier
in that it does not have the high noise level common in
the output stage that usually dominates when an instru-
mentation amplifier is used at low gain. If this amplifier
is used at a gain of 10, the gain error is only 10ppm and
input referred noise is reduced to 0.15µVRMS. The buffer
stages can also be configured to provide gain of up to 50
with high gain stability and linearity.
Figure 42 shows an example of a single amplifier used
to produce single-ended gain. This topology is best used
in applications where the gain setting resistor can be
made to match the temperature coefficient of the strain
gauges. If the bridge is composed of precision resistors,
with only one or two variable elements, the reference arm
of the bridge can be made to act in conjunction with the
feedback resistor to determine the gain. If the feedback
resistor is incorporated into the design of the load cell,
using resistors which match the temperature coefficient
of the load-cell elements, good results can be achieved
without the need for resistors with a high degree of ab-
solute accuracy. The common mode voltage in this case,
is again a function of the bridge output. Differential gain
as used with a 350Ω bridge is:
AV=9.95 =
R1+R2
R1+175Ω
Common mode gain is half the differential gain. The
maximum differential signal that can be used is 1/4 VREF,
as opposed to 1/2 VREF in the 2-amplifier topology above.
Remote Half Bridge Interface
As opposed to full bridge applications, typical half bridge
applications must contend with nonlinearity in the bridge
output, as signal swing is often much greater. Applications
include RTD’s, thermistors and other resistive elements
that undergo significant changes over their span. For single
variable element bridges, the nonlinearity of the half bridge
Figure 43. Remote Half Bridge Interface
0.1µF
5V
REF+
REF–
IN+
IN–
GND
VCC
2
3
2
4
6
7
3
350Ω
BRIDGE
4
5
2411 F42
6
1
–
+
LTC1050S8
5V
0.1µV
R2
46.4k
20k
20k
175Ω
1µF
10µF
R1
4.99k
AV = 9.95 = R1 + R2
R1 + 175Ω
+
+
1µF
+
LTC2411/
LTC2411-1
2411 F43
REF–
IN+
IN–
GND
VCC
V
S
2.7V TO 5.5V
2
3
4
5
PLATINUM
100Ω
RTD
R1
25.5k
0.1%
6
1
4
3
2
1
REF+
LTC2411/
LTC2411-1
LTC2411/LTC2411-1
37
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For more information www.linear.com/LTC2411
output can be eliminated completely; if the reference arm
of the bridge is used as the reference to the ADC, as shown
in Figure 43. The LTC2411/LTC2411-1 can accept inputs
up to 1/2 VREF. Hence, the reference resistor R1 must be
at least 2× the highest value of the variable resistor.
In the case of 100Ω platinum RTD’s, this would suggest
a value of 800Ω for R1. Such a low value for R1 is not
advisable due to self-heating effects. A value of 25.5k is
shown for R1, reducing self-heating effects to acceptable
levels for most sensors.
The basic circuit shown in Figure 43 shows connections
for a full 4-wire connection to the sensor, which may be
located remotely. The differential input connections will
reject induced or coupled 60Hz interference, however, the
reference inputs do not have the same rejection. If 60Hz
or other noise is present on the RTD, a low pass filter is
recommended as shown in Figure 44. Note that you cannot
place a large capacitor directly at the junction of R1 and
R2, as it will store charge from the sampling process. A
better approach is to produce a low pass filter decoupled
from the input lines with a high value resistor (R3).
The use of a third resistor in the half bridge, between the
variable and fixed elements gives essentially the same
result as the two resistor version, but has a few benefits.
If, for example, a 25k reference resistor is used to set
the excitation current with a 100Ω RTD, the negative
reference input is sampling the same external node as
the positive input, but may result in errors if used with a
long cable. For short cable applications, the errors may
be acceptably low. If instead the single 25k resistor is
replaced with a 10k 5% and a 10k 0.1% reference resistor,
the noise level introduced at the reference, at least at higher
frequencies, will be reduced. A filter can be introduced into
the network, in the form of one or more capacitors, or ferrite
beads, as long as the sampling pulses are not translated
into an error. The reference voltage is also reduced, but
this is not undesirable, as it will decrease the value of the
LSB, although, not the input referred noise level.
The circuit shown in Figure 44 shows a more rigorous
example of Figure 43, with increased noise suppression
and more protection for remote applications.
Figure 45 shows an example of gain in the excitation cir-
cuit and remote feedback from the bridge. The LTC1043s
provide voltage multiplication, providing ±10V from a 5V
reference with only 1ppm error. The amplifiers are used at
unity-gain and, hence, introduce a very little error due to
Figure 44. Remote Half Bridge Sensing with Noise Suppression on Reference
REF+
REF–
IN–
GND
VCC
5V
2
3
5
2411 F44
6
1
–
+
LTC1050
5V
PLATINUM
100Ω
RTD
560Ω
R3
10k
5%
R1
10k, 5%
R2
10k
0.1%
1µF
IN+
4
10k
10k
4
3
2
1
LTC2411/
LTC2411-1
APPLICATIONS INFORMATION
LTC2411/LTC2411-1
38
2411fa
For more information www.linear.com/LTC2411
350Ω
BRIDGE
0.1µF
1µF
15V15V
–15V
3 8
14
7
4
13
12
11
10V 5V
15V
U1
LTC1043
6
2
7
4
7
4
–
+
REF+
REF–
IN+
IN–
GND
VCC
2
3
4
5
6
2411 F45
1
5V
47µF 0.1µF
10V
+ +
17
5
15
6
18
3
2
U2
LTC1043
1µF
FILM
8
14
7
4
13
12
11
*
*
*
5V
U2
LTC1043
17
–10V
–10V
LT1236-5
1k
33Ω
Q1
2N3904
0.1µF
15V
–15V
–15V
3
6
2
–
+
1k
33Ω
–10V
10V
Q2
2N3906
*FLYING CAPACITORS ARE
1µF FILM (MKP OR EQUIVALENT)
SEE LTC1043 DATA SHEET FOR
DETAILS ON UNUSED HALF OF U1
LTC1150
LTC1150
20Ω
200Ω
20Ω
200Ω
0.1µF
10µF
+
LTC2411/
LTC2411-1
APPLICATIONS INFORMATION
Figure 45. LTC1043 Provides Precise 4× Reference for Excitation Voltages
LTC2411/LTC2411-1
39
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For more information www.linear.com/LTC2411
APPLICATIONS INFORMATION
Figure 46. Use a Differential Multiplexer to Expand Channel Capability
gain error or due to offset voltages. A 1µV/°C offset voltage
drift translates into 0.05ppm/°C gain error. Simpler alter-
natives, with the amplifiers providing gain using resistor
arrays for feedback, can produce results that are similar
to bridge sensing schemes via attenuators. Note that the
amplifiers must have high open-loop gain or gain error
will be a source of error. The fact that input offset voltage
has relatively little effect on overall error may lead one to
use low performance amplifiers for this application. Note
that the gain of a device such as an LF156, (25V/mV over
temperature) will produce a worst-case error of –180ppm
at a noise gain of 3, such as would be encountered in an
inverting gain of 2, to produce –10V from a 5V reference.
The error associated with the 10V excitation would be
–80ppm. Hence, overall reference error could be as high
as 130ppm, the average of the two.
Figure 47 shows a similar scheme to provide excitation
using resistor arrays to produce precise gain. The circuit
is configured to provide 10V and –5V excitation to the
bridge, producing a common mode voltage at the input
to the LTC2411/LTC2411-1 of 2.5V, maximizing the AC
input range for applications where induced 60Hz could
reach amplitudes up to 2VRMS.
The circuits in Figures 45 and 47 could be used where
multiple bridge circuits are involved and bridge output can
be multiplexed onto a single LTC2411/LTC2411-1, via an
inexpensive multiplexer such as the 74HC4052.
Figure 46 shows the use of an LTC2411/LTC2411-1 with a
differential multiplexer. This is an inexpensive multiplexer
that will contribute some error due to leakage if used directly
with the output from the bridge, or if resistors are inserted
as a protection mechanism from overvoltage. Although the
bridge output may be within the input range of the A/D and
multiplexer in normal operation, some thought should be
given to fault conditions that could result in full excitation
voltage at the inputs to the multiplexer or ADC. The use of
amplification prior to the multiplexer will largely eliminate
errors associated with channel leakage developing error
voltages in the source impedance.
2411 F46
REF+
REF–
IN+
IN–
6
A0
A1
VCC
GND
13
3
6
12 47µF
14
1
5
10
16
5V
15
11
2
TO OTHER
DEVICES 4
98
5V
+
74HC4052
2
3
4
5
1
LTC2411/
LTC2411-1
LTC2411/LTC2411-1
40
2411fa
For more information www.linear.com/LTC2411
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSOP (MS) 0213 REV F
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
1234 5
4.90 ±0.152
(.193 ±.006)
0.497 ±0.076
(.0196 ±.003)
REF
8910 76
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ±0.038
(.0120 ±.0015)
TYP
0.50
(.0197)
BSC
0.1016 ±0.0508
(.004 ±.002)
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev F)
LTC2411/LTC2411-1
41
2411fa
For more information www.linear.com/LTC2411
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 08/15 Updated fEOSC maximum to 500kHz and all associated information. 5, 9, 28, 29,
30, 31
LTC2411/LTC2411-1
42
2411fa
For more information www.linear.com/LTC2411
LINEAR TECHNOLOGY CORPORATION 2000
LT 0815 REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2411
RELATED PARTS
TYPICAL APPLICATION
C1
0.1µF
15V
3
1
2
3
21
65
4
–
+
REF+
REF–
IN+
IN–
GND
VCC
2
3
4
5
6
2411 F47
1
LT1236-5
RN1
10k
22Ω
10V
350Ω BRIDGE
TWO ELEMENTS
VARYING
RN1
10k
Q1
2N3904
1/2
LT1112
C2
0.1µF
15V
–5V
–15V
–15V
6
7
5
8
7
+
–
RN1
10k
RN1 IS CADDOCK T914 10K-010-02
Q2, Q3
2N3906
×2
1/2
LT1112
RN1
10k
33Ω
×2
C3
47µF
C1
0.1µF
5V
5V
8
4
20Ω
20Ω
+
LTC2411/
LTC2411-1
PART NUMBER DESCRIPTION COMMENTS
LT1019 Precision Bandgap Reference, 2.5V, 5V 3ppm/°C Drift, 0.05% Max Initial Accuracy
LT1025 Micropower Thermocouple Cold Junction Compensator 80µA Supply Current, 0.5°C Initial Accuracy
LTC1050 Precision Chopper Stabilized Op Amp No External Components 5µV Offset, 1.6µVP-P Noise
LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max Initial Accuracy, 5ppm/°C Drift
LT1460 Micropower Series Reference 0.075% Max Initial Accuracy, 10ppm/°C Max Drift
LTC2400 24-Bit, No Latency ∆Σ ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2401/LTC2402 1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2404/LTC2408 4-/8-Channel, 24-Bit, No Latency ∆Σ ADC 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2410 24-Bit, Fully Differential, No Latency ∆Σ ADC 0.16ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2413 24-Bit, Fully Differential, No Latency ∆Σ ADC Simultaneous 50Hz and 60Hz Rejection, 800nVRMS Noise
LTC2415 24-Bit, No Latency ∆Σ ADC with 15Hz Output Rate Pin Compatible with the LTC2410
LTC2420 20-Bit, No Latency ∆Σ ADC in SO-8 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
LTC2424/LTC2428 4-/8-Channel, 20-Bit, No Latency ∆Σ ADC 1.2ppm Noise, Pin Compatible with LTC2404/LTC2408
Figure 47. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier
